From: Guodong Xu <guodong@riscstar.com>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Yixun Lan <dlan@gentoo.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Samuel Holland <samuel.holland@sifive.com>,
Anup Patel <anup@brainfault.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>,
Lubomir Rintel <lkundrak@v3.sk>, Yangyu Chen <cyy@cyyself.name>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Conor Dooley <conor@kernel.org>,
Heinrich Schuchardt <xypron.glpk@gmx.de>,
Kevin Meng Zhang <zhangmeng.kevin@linux.spacemit.com>,
Anup Patel <anup@brainfault.org>,
Andrew Jones <ajones@ventanamicro.com>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, spacemit@lists.linux.dev,
linux-serial@vger.kernel.org, Guodong Xu <guodong@riscstar.com>
Subject: [PATCH v3 07/11] dt-bindings: riscv: Add descriptions for Za64rs, Ziccamoa, Ziccif, and Zicclsm
Date: Thu, 08 Jan 2026 20:25:58 +0800 [thread overview]
Message-ID: <20260108-k3-basic-dt-v3-7-ed99eb4c3ad3@riscstar.com> (raw)
In-Reply-To: <20260108-k3-basic-dt-v3-0-ed99eb4c3ad3@riscstar.com>
Add descriptions for four extensions: Za64rs, Ziccamoa, Ziccif, and
Zicclsm. These extensions are ratified in RISC-V Profiles Version 1.0
(commit b1d806605f87 "Updated to ratified state.").
They are introduced as new extension names for existing features and
regulate implementation details for RISC-V Profile compliance. According
to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, they are
mandatory for the following profiles:
- za64rs: Mandatory in RVA22U64, RVA23U64
- ziccamoa: Mandatory in RVA20U64, RVA22U64, RVA23U64
- ziccif: Mandatory in RVA20U64, RVA22U64, RVA23U64
- zicclsm: Mandatory in RVA20U64, RVA22U64, RVA23U64
Ziccrse specifies the main memory must support "RsrvEventual", which is
one (totally there are four) of the support level for Load-Reserved/
Store-Conditional (LR/SC) atomic instructions. Thus it depends on Zalrsc.
Ziccamoa specifies the main memory must support AMOArithmetic, among the
four levels of PMA support defined for AMOs in the A extension. Thus it
depends on Zaamo.
Za64rs defines reservation sets are contiguous, naturally aligned, and a
maximum of 64 bytes. Za64rs is consumed by two extensions: Zalrsc and
Zawrs. Zawrs itself depends on Zalrsc too.
Based on the relationship that "A" = Zaamo + Zalrsc, add the following
dependencies checks:
Za64rs -> Zalrsc or A
Ziccrse -> Zalrsc or A
Ziccamoa -> Zaamo or A
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v3: Update the commit message to explain the relationship of Za64rs,
Ziccrse, Ziccamoa, Zalrsc and A.
Add dependency checks.
v2: New patch.
---
.../devicetree/bindings/riscv/extensions.yaml | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index e026b366c8f5dbe7d6988d3ed374183c165de35a..ee2cdd3856b91a5bbf486e8a2da0986269e82a2b 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -237,6 +237,12 @@ properties:
as ratified at commit 4a69197e5617 ("Update to ratified state") of
riscv-svvptc.
+ - const: za64rs
+ description:
+ The standard Za64rs extension for reservation set size of at most
+ 64 bytes, as ratified in RISC-V Profiles Version 1.0, with commit
+ b1d806605f87 ("Updated to ratified state.")
+
- const: zaamo
description: |
The standard Zaamo extension for atomic memory operations as
@@ -378,6 +384,27 @@ properties:
in commit 64074bc ("Update version numbers for Zfh/Zfinx") of
riscv-isa-manual.
+ - const: ziccamoa
+ description:
+ The standard Ziccamoa extension for main memory (cacheability and
+ coherence) must support all atomics in A, as ratified in RISC-V
+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to
+ ratified state.")
+
+ - const: ziccif
+ description:
+ The standard Ziccif extension for main memory (cacheability and
+ coherence) instruction fetch atomicity, as ratified in RISC-V
+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to
+ ratified state.")
+
+ - const: zicclsm
+ description:
+ The standard Zicclsm extension for main memory (cacheability and
+ coherence) must support misaligned loads and stores, as ratified
+ in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Updated
+ to ratified state.")
+
- const: ziccrse
description:
The standard Ziccrse extension which provides forward progress
@@ -780,6 +807,18 @@ properties:
then:
contains:
const: b
+ # Za64rs and Ziccrse depend on Zalrsc or A
+ - if:
+ contains:
+ anyOf:
+ - const: za64rs
+ - const: ziccrse
+ then:
+ oneOf:
+ - contains:
+ const: zalrsc
+ - contains:
+ const: a
# Zcb depends on Zca
- if:
contains:
@@ -821,6 +860,16 @@ properties:
then:
contains:
const: f
+ # Ziccamoa depends on Zaamo or A
+ - if:
+ contains:
+ const: ziccamoa
+ then:
+ oneOf:
+ - contains:
+ const: zaamo
+ - contains:
+ const: a
# Zvfbfmin depends on V or Zve32f
- if:
contains:
--
2.43.0
next prev parent reply other threads:[~2026-01-08 12:27 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-08 12:25 [PATCH v3 00/11] riscv: spacemit: Add SpacemiT K3 SoC and K3 Pico-ITX board Guodong Xu
2026-01-08 12:25 ` [PATCH v3 01/11] dt-bindings: riscv: add SpacemiT X100 CPU compatible Guodong Xu
2026-01-14 23:17 ` Paul Walmsley
2026-01-08 12:25 ` [PATCH v3 02/11] dt-bindings: timer: add SpacemiT K3 CLINT Guodong Xu
2026-01-08 12:25 ` [PATCH v3 03/11] dt-bindings: interrupt-controller: add SpacemiT K3 APLIC Guodong Xu
2026-01-08 12:25 ` [PATCH v3 04/11] dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC Guodong Xu
2026-01-08 12:25 ` [PATCH v3 05/11] dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings Guodong Xu
2026-01-09 3:36 ` Yixun Lan
2026-01-09 10:12 ` Guodong Xu
2026-01-08 12:25 ` [PATCH v3 06/11] dt-bindings: riscv: Add B ISA extension description Guodong Xu
2026-01-08 12:25 ` Guodong Xu [this message]
2026-01-08 12:25 ` [PATCH v3 08/11] dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl Guodong Xu
2026-01-08 12:26 ` [PATCH v3 09/11] dt-bindings: riscv: Add Sha and its comprised extensions Guodong Xu
2026-01-08 12:26 ` [PATCH v3 10/11] riscv: dts: spacemit: add initial device tree of SpacemiT K3 SoC Guodong Xu
2026-01-08 18:19 ` Samuel Holland
2026-01-09 9:58 ` Guodong Xu
2026-01-14 23:57 ` Samuel Holland
2026-01-15 6:19 ` Heinrich Schuchardt
2026-01-08 12:26 ` [PATCH v3 11/11] riscv: dts: spacemit: add SpacemiT K3 Pico-ITX board device tree Guodong Xu
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