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Wed, 10 Jun 2026 20:39:16 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d:7285:c2ff:fe45:8a32]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84337bb47eesm334548b3a.13.2026.06.10.20.39.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2026 20:39:16 -0700 (PDT) From: Rosen Penev To: linux-serial@vger.kernel.org Cc: Greg Kroah-Hartman , Jiri Slaby , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , linux-kernel@vger.kernel.org (open list:TTY LAYER AND SERIAL DRIVERS), imx@lists.linux.dev (open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE) Subject: [PATCHv3 2/6] serial: mxs-auart: rework clock handling in mxs_get_clks and probe Date: Wed, 10 Jun 2026 20:38:52 -0700 Message-ID: <20260611033856.6476-3-rosenp@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260611033856.6476-1-rosenp@gmail.com> References: <20260611033856.6476-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Use devm_clk_get_enabled for the AHB clock so its enable/disable lifetime is managed by the driver model. Move the mod clock (clk) prepare_enable out of mxs_get_clks and into probe so that clk_set_rate is called while the clock is still disabled, avoiding CLK_SET_RATE_GATE failures. Clean up the error labels accordingly. Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev --- drivers/tty/serial/mxs-auart.c | 47 ++++++++++++---------------------- 1 file changed, 17 insertions(+), 30 deletions(-) diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c index de97c0f74e7d..aa59a48bfad7 100644 --- a/drivers/tty/serial/mxs-auart.c +++ b/drivers/tty/serial/mxs-auart.c @@ -1470,34 +1470,22 @@ static int mxs_get_clks(struct mxs_auart_port *s, return PTR_ERR(s->clk); } - s->clk_ahb = devm_clk_get(s->dev, "ahb"); + s->clk_ahb = devm_clk_get_enabled(s->dev, "ahb"); if (IS_ERR(s->clk_ahb)) { dev_err(s->dev, "Failed to get \"ahb\" clk\n"); return PTR_ERR(s->clk_ahb); } - err = clk_prepare_enable(s->clk_ahb); - if (err) { - dev_err(s->dev, "Failed to enable ahb_clk!\n"); - return err; - } - + /* + * Set mod clock rate while it is still disabled so + * CLK_SET_RATE_GATE does not cause clk_set_rate to fail. + * The mod clock will be enabled in mxs_auart_startup() + * and in probe after mxs_get_clks returns. + */ err = clk_set_rate(s->clk, clk_get_rate(s->clk_ahb)); - if (err) { + if (err) dev_err(s->dev, "Failed to set rate!\n"); - goto disable_clk_ahb; - } - err = clk_prepare_enable(s->clk); - if (err) { - dev_err(s->dev, "Failed to enable clk!\n"); - goto disable_clk_ahb; - } - - return 0; - -disable_clk_ahb: - clk_disable_unprepare(s->clk_ahb); return err; } @@ -1604,17 +1592,21 @@ static int mxs_auart_probe(struct platform_device *pdev) if (ret) return ret; + ret = clk_prepare_enable(s->clk); + if (ret) + return ret; + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!r) { ret = -ENXIO; - goto out_disable_clks; + goto out_disable_clk; } s->port.mapbase = r->start; s->port.membase = ioremap(r->start, resource_size(r)); if (!s->port.membase) { ret = -ENOMEM; - goto out_disable_clks; + goto out_disable_clk; } s->port.ops = &mxs_auart_ops; s->port.iotype = UPIO_MEM; @@ -1681,11 +1673,8 @@ static int mxs_auart_probe(struct platform_device *pdev) out_iounmap: iounmap(s->port.membase); -out_disable_clks: - if (is_asm9260_auart(s)) { - clk_disable_unprepare(s->clk); - clk_disable_unprepare(s->clk_ahb); - } +out_disable_clk: + clk_disable_unprepare(s->clk); return ret; } @@ -1697,10 +1686,8 @@ static void mxs_auart_remove(struct platform_device *pdev) auart_port[pdev->id] = NULL; mxs_auart_free_gpio_irq(s); iounmap(s->port.membase); - if (is_asm9260_auart(s)) { + if (is_asm9260_auart(s)) clk_disable_unprepare(s->clk); - clk_disable_unprepare(s->clk_ahb); - } } static struct platform_driver mxs_auart_driver = { -- 2.54.0