Re: [PATCH v2 6/9] spi: qcom-geni: Use geni_se_set_rate() for setting source clock frequency

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] spi_geni_runtime_suspend() returns the error code from geni_se_set_rate() after already disabling hardware clocks, leaving the device powered off but marked as RPM_ACTIVE.
--

commit dac5e1011a1f48eebd4fa7951d45a6efb1aeeb9a
Author: Praveen Talari <praveen.talari@oss.qualcomm.com>

spi: qcom-geni: Use geni_se_set_rate() for setting source clock frequency

This commit switches the spi-geni-qcom driver to use geni_se_set_rate()
instead of dev_pm_opp_set_rate() for source clock programming, allowing
firmware-managed platforms to utilize geni_se_clk_freq_match().

> diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
> --- a/drivers/spi/spi-geni-qcom.c
> +++ b/drivers/spi/spi-geni-qcom.c

[ ... ]

> @@ -1161,9 +1159,14 @@ static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
>  {
>  	struct spi_controller *spi = dev_get_drvdata(dev);
>  	struct spi_geni_master *mas = spi_controller_get_devdata(spi);
> +	int ret;
> +
> +	ret = mas->dev_data->power_off ?
> +	      mas->dev_data->power_off(&mas->se) : 0;
> +	if (ret)
> +		return ret;
>  
> -	return mas->dev_data->power_off ?
> -	       mas->dev_data->power_off(&mas->se) : 0;
> +	return geni_se_set_rate(&mas->se, 0);

[Severity: High]
If geni_se_set_rate() fails and returns an error code here, won't the PM
core abort the suspend transition and leave the software state as RPM_ACTIVE?

Since mas->dev_data->power_off() was already called just above, the physical 
hardware (clocks, interconnects) is disabled.

When the next transfer is queued, pm_runtime_get_sync() would see the device 
as RPM_ACTIVE and skip runtime_resume(), leading to accesses of unclocked 
hardware registers. Could this cause a synchronous external abort when the 
registers are accessed?

>  }

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Sashiko AI review · https://sashiko.dev/#/patchset/20260827-derive_clk_perf_tbl_from_perf_domain_opp_table-v2-0-091697dbeb02@oss.qualcomm.com?part=6