From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDE2E495AC2; Thu, 1 Oct 2026 12:41:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790858461; cv=none; b=ikV0y481cnClnSEFl2z0Wvpp3kw4adbyiAQUXwTpd0I6Twelya8TL+4MDrWMqjA3/1T1X3PjyoBUzzGIwes4SXOycdR+WvAV1+c56AO27mBwZ76MPg4d0fMZ5sFLuTBH9gSV81tC8mgrGUQUAAA7QYJpV5jguwAfg/VVNmbD+zE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790858461; c=relaxed/simple; bh=iSN13jQzT5q3aGEtcq9pGlkB8alxyY2QXP+GvUaeNFQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ESkDfvJjFKydwVVXKqG6buz8wXNCCK6Dg9+30xNjao+lw9JT+tphUs3j0DVWjMyHI86k0fhXR69E+oZ1mzKVN9+oTQFxSjHty+tTFwytpP29ilUtBepJVGtytrwjISLRz2yG1VburbXF/EOxlechNhi5839Rhvewhl5044oK6ik= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LPpe3Cbo; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LPpe3Cbo" Received: by smtp.kernel.org (Postfix) with ESMTPS id 78DC3C4AF53; Thu, 1 Oct 2026 12:41:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1790858460; bh=iSN13jQzT5q3aGEtcq9pGlkB8alxyY2QXP+GvUaeNFQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=LPpe3CboE+BCBrVnREoFWauwCcUEc06j8DaHs08UoDVSWhFNwzEfdlIn/N8HNeXff 0bpzvuguxJBNTyluNLwmz64Lpq0aHFw+tRn3ez4EoAsLeKcblP5t3KFDn2c+bObNIV Qmq4loduY9IumDt869z3+3A/WOh6rvZVTOPYhG58ohjn/5SvIB33rQ30W95fTAFCSG 1Mv6iOsL4rws6gM8PhXLZk9mK2cAeMepVXx93nD3KcDKjKd+YBT8JQdzzyWvosmNGA WtTLyHEoMqrVXjEumahV+w3yWQ9/69EFzDTxNgtSzNuxdDtECwDOsTnF3xtJ9qhw35 sUMG5kjCDKnWA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6012CCA5FD5; Thu, 1 Oct 2026 12:41:00 +0000 (UTC) From: Long Zhao via B4 Relay Date: Thu, 01 Oct 2026 20:40:53 +0800 Subject: [PATCH v9 04/15] dt-bindings: gpio: pl061: add Ambarella CV75 variant Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261001-cv75-v5-v9-4-486cc289a4b8@ambarella.com> References: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> In-Reply-To: <20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Michael Walle , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790858457; l=2025; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=GVEIXtfx8rpLQa9TzFd09VjRop28rVpySsmXjUcyqZs=; b=Y8pd3ddXl8IoS7dP8eJy1gqZI5BES85+71MExgOd+u1qD/1c0VXaLRMz8aW0dqWVexEzuiblT +wWPeAhuRbtBRapWsXfa0VADQa2yri6b17o/4w5jcXuoxYe3FLk7NFG X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao The CV75 GPIO banks sit on the AMBA PrimeCell bus but are not register-compatible with the ARM PL061. Each bank is 32-bit and 32 lines, with extra mask/enable registers, so arm,pl061 must not be used as a fallback compatible. The AMBA core matches the PL061 driver by PrimeCell ID, not by the DT compatible string. These blocks do not implement the standard PL061 ID (0x00041061) in the ID registers, so arm,primecell-periphid is required and is fixed to 0x000e8061; the driver uses that ID to select the Ambarella layout. gpio-ranges is required because each bank is a slice of the SoC pinctrl pin space. Signed-off-by: Long Zhao --- .../devicetree/bindings/gpio/pl061-gpio.yaml | 25 +++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml b/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml index 4d970e55104b..c22dd8a1d2c1 100644 --- a/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml @@ -15,7 +15,9 @@ select: properties: compatible: contains: - const: arm,pl061 + enum: + - arm,pl061 + - ambarella,cv75-gpio required: - compatible @@ -25,7 +27,9 @@ properties: compatible: items: - - const: arm,pl061 + - enum: + - ambarella,cv75-gpio + - arm,pl061 - const: arm,primecell reg: @@ -64,6 +68,21 @@ required: - "#gpio-cells" - gpio-controller -additionalProperties: false +allOf: + - $ref: /schemas/arm/primecell.yaml# + - if: + properties: + compatible: + contains: + const: ambarella,cv75-gpio + then: + properties: + arm,primecell-periphid: + const: 0x000e8061 + required: + - arm,primecell-periphid + - gpio-ranges + +unevaluatedProperties: false ... -- 2.34.1