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Sat, 17 Oct 2026 00:45:32 -0700 (PDT) Received: from localhost.localdomain ([186.151.100.62]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-5ea9b53cfdfsm3701836e0c.15.2026.10.17.00.45.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2026 00:45:32 -0700 (PDT) From: Sebastian Alba Vives To: gregkh@linuxfoundation.org, jirislaby@kernel.org, pjw@kernel.org, samuel.holland@sifive.com Cc: linux-serial@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Sebastian Alba Subject: [PATCH 2/2] serial: sifive: avoid division by zero in the clock notifier Date: Sat, 17 Oct 2026 01:44:53 -0600 Message-ID: <20261017074453.62645-3-sebasjosue84@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261017074453.62645-1-sebasjosue84@gmail.com> References: <20261017074453.62645-1-sebasjosue84@gmail.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Sebastian Alba sifive_serial_probe() registers the clock rate-change notifier before it initialises the two fields that notifier divides by. ssp comes from devm_kzalloc(), so between clk_notifier_register() and the assignments a few lines below, both ssp->baud_rate and ssp->port.uartclk are zero. A rate change taken in that window reaches: PRE_RATE_CHANGE: udelay(DIV_ROUND_UP(12 * 1000 * 1000, ssp->baud_rate)) POST_RATE_CHANGE: __ssp_update_div() -> DIV_ROUND_UP(ssp->port.uartclk, ssp->baud_rate) - 1 On RISC-V an integer division by zero does not trap; the ISA defines the result as all bits set. DIV_ROUND_UP() therefore yields ULONG_MAX and udelay() busy-waits essentially forever, hanging the CPU, rather than producing a clean oops. The POST_RATE_CHANGE path additionally programs a bogus divisor into the hardware. On the FU740 the UART clock is derived from the CPU clock through a synchronous divide-by-two, as the notifier's own comment describes, so any CPU rate change during probe can hit this. Initialise uartclk and baud_rate before registering the notifier, and bail out early if the notifier is ever called with no baud rate set. Fixes: 45c054d0815b ("tty: serial: add driver for the SiFive UART") Signed-off-by: Sebastian Alba --- drivers/tty/serial/sifive.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/tty/serial/sifive.c b/drivers/tty/serial/sifive.c index 4a445d285..cd2925b6a 100644 --- a/drivers/tty/serial/sifive.c +++ b/drivers/tty/serial/sifive.c @@ -604,6 +604,9 @@ static int sifive_serial_clk_notifier(struct notifier_block *nb, struct clk_notifier_data *cnd = data; struct sifive_serial_port *ssp = notifier_to_sifive_serial_port(nb); + if (!ssp->baud_rate) + return NOTIFY_OK; + if (event == PRE_RATE_CHANGE) { /* * The TX watermark is always set to 1 by this driver, which @@ -1022,6 +1025,11 @@ static int sifive_serial_probe(struct platform_device *pdev) ssp->clk = clk; ssp->clk_notifier.notifier_call = sifive_serial_clk_notifier; + /* Set up clock divider before the notifier can observe this port */ + ssp->port.uartclk = clk_get_rate(ssp->clk); + ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE; + __ssp_update_div(ssp); + r = clk_notifier_register(ssp->clk, &ssp->clk_notifier); if (r) { dev_err(&pdev->dev, "could not register clock notifier: %d\n", @@ -1029,11 +1037,6 @@ static int sifive_serial_probe(struct platform_device *pdev) goto probe_out1; } - /* Set up clock divider */ - ssp->port.uartclk = clk_get_rate(ssp->clk); - ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE; - __ssp_update_div(ssp); - platform_set_drvdata(pdev, ssp); /* Enable transmits and set the watermark level to 1 */ -- 2.43.0