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Wed, 28 Oct 2026 22:07:11 -0700 (PDT) Received: from [127.0.1.1] ([169.211.140.146]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2eae6c9d2cesm28159685ad.65.2026.10.28.22.07.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Oct 2026 22:07:10 -0700 (PDT) From: Kwanghoon Son Date: Thu, 29 Oct 2026 01:05:50 -0400 Subject: [PATCH RFC 09/12] riscv: dts: bouffalolab: Add BL808 SoC X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261029-rust-bl808-console-v1-9-b736ee920078@gmail.com> References: <20261029-rust-bl808-console-v1-0-b736ee920078@gmail.com> In-Reply-To: <20261029-rust-bl808-console-v1-0-b736ee920078@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Miguel Ojeda , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Daniel Almeida , Tamir Duberstein , Alexandre Courbot , =?utf-8?q?Onur_=C3=96zkan?= , Thomas Gleixner , Radu Rendec , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Daniel Lezcano , Anup Patel , Kwanghoon Son , Albert Ou , Alexandre Ghiti , Greg Kroah-Hartman , Jiri Slaby Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, Paul Walmsley , linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org X-Mailer: b4 0.14.2 Add the BL808 D0 CPU, PLIC, CLINT and UART3. Leave UART3 disabled for boards to enable. UART3 connects directly to PLIC source 20; firmware sets up UART clocks and pins. Signed-off-by: Kwanghoon Son --- arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 70 ++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..c739c77960c4578b87fcf2bc096ef7c8cda089bd --- /dev/null +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include + +/ { + compatible = "bflb,bl808"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", + "zicsr", "zifencei", "zicntr", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + xtal: clock-xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&plic>; + dma-noncoherent; + + uart3: serial@30002000 { + compatible = "bflb,uart"; + reg = <0x30002000 0x1000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&xtal>; + clock-names = "baud"; + status = "disabled"; + }; + + plic: interrupt-controller@e0000000 { + compatible = "bflb,bl808-plic", "thead,c900-plic"; + reg = <0xe0000000 0x04000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <82>; + }; + + timer@e4000000 { + compatible = "bflb,bl808-clint", "thead,c900-clint"; + reg = <0xe4000000 0xc000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; + }; + }; +}; -- 2.47.3