From: Jiri Slaby <jirislaby@kernel.org>
To: Rengarajan S <rengarajan.s@microchip.com>,
kumaravel.thiagarajan@microchip.com,
tharunkumar.pasumarthi@microchip.com, gregkh@linuxfoundation.org,
linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org,
unglinuxdriver@microchip.com
Subject: Re: [PATCH v1 tty-next] 8250: microchip: pci1xxxx: Add PCIe Hot reset disable support for Rev C0 and later devices
Date: Wed, 23 Apr 2025 07:11:07 +0200 [thread overview]
Message-ID: <3292610b-acb0-4b72-8aa8-9eec491238c5@kernel.org> (raw)
In-Reply-To: <20250423033841.33758-1-rengarajan.s@microchip.com>
On 23. 04. 25, 5:38, Rengarajan S wrote:
> Systems that issue PCIe hot reset requests during a suspend/resume
> cycle cause PCI1XXXX device revisions prior to C0 to get its UART
> configuration registers reset to hardware default values. This results
> in device inaccessibility and data transfer failures. Starting with
> Revision C0, support was added in the device hardware (via the Hot
> Reset Disable Bit) to allow resetting only the PCIe interface and its
> associated logic, but preserving the UART configuration during a hot
> reset. This patch enables the hot reset disable feature during suspend/
> resume for C0 and later revisions of the device.
>
> Signed-off-by: Rengarajan S <rengarajan.s@microchip.com>
> ---
> drivers/tty/serial/8250/8250_pci1xxxx.c | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c
> index e9c51d4e447d..ec573327590f 100644
> --- a/drivers/tty/serial/8250/8250_pci1xxxx.c
> +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c
> @@ -115,6 +115,7 @@
>
> #define UART_RESET_REG 0x94
> #define UART_RESET_D3_RESET_DISABLE BIT(16)
> +#define UART_RESET_HOT_RESET_DISABLE BIT(17)
>
> #define UART_BURST_STATUS_REG 0x9C
> #define UART_TX_BURST_FIFO 0xA0
> @@ -620,7 +621,13 @@ static int pci1xxxx_suspend(struct device *dev)
> }
>
> data = readl(p + UART_RESET_REG);
> - writel(data | UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG);
> +
> + if (priv->dev_rev >= 0xC0)
> + writel(data | (UART_RESET_D3_RESET_DISABLE |
> + UART_RESET_HOT_RESET_DISABLE), p + UART_RESET_REG);
> + else
> + writel(data | UART_RESET_D3_RESET_DISABLE,
> + p + UART_RESET_REG);
Instead of this overly long lines, could you just:
data |= UART_RESET_HOT_RESET_DISABLE;
and keep the writel() as is?
thanks,
--
js
suse labs
next prev parent reply other threads:[~2025-04-23 5:11 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-23 3:38 [PATCH v1 tty-next] 8250: microchip: pci1xxxx: Add PCIe Hot reset disable support for Rev C0 and later devices Rengarajan S
2025-04-23 5:11 ` Jiri Slaby [this message]
2025-04-24 3:57 ` Rengarajan.S
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