From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66910186A; Wed, 23 Apr 2025 05:11:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745385071; cv=none; b=RtJeDu6kBfX2l5AGA2MZURmfdDDKnjVIwb6nQOUKYQx7cPRDA1MNfrBc3kPraTguOhZwFjMuI8xV7e1P5KU/e0bempapLXg6um7L547kLCW0557D7+bUZBzo3T0z/x4NrwRinP/XBGcb/Ugz096FTJwiRZi+cXrCxAMDnwRSUiU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745385071; c=relaxed/simple; bh=7keckhtABWhiyOtwpWQepxmD1/wWw9n3KVzmE5Vw61o=; h=Message-ID:Date:MIME-Version:Subject:To:References:From: In-Reply-To:Content-Type; b=EqxhQlnLkQpGATmHs8cMtZQJ2B1YpZPEsnmvQmc8gYmdtw2KfQqqsAKHa9xvpxqcxBsnP2WVjt6dsSk1sJ74W1sWCzHoF5PWLjqA0j+ETrNx09TAm6ePOuADViaQr196B7PY0y9XwbHjU9BDFQbl8YXkITF1BPZNA8Q937eIiyI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZmoDNxAz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZmoDNxAz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 63ACDC4CEE2; Wed, 23 Apr 2025 05:11:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745385070; bh=7keckhtABWhiyOtwpWQepxmD1/wWw9n3KVzmE5Vw61o=; h=Date:Subject:To:References:From:In-Reply-To:From; b=ZmoDNxAzipeScZRwQ7T9skXTKQ82nLgKZU4wXvwdi6yicNTneoDKwqCu0gXVksvx3 VHGp/VaOp5DFR7TpUXoLA2WxWQzs+1KNnPpcaXspC01leRceHhGnwCDiGX/Y9YcywF TtUc2dwUtLP4EBY0V2oWrFK+xoP5mNUp/TzsnVIi1xa2GRYtfN53HPS9/2FgI2FLEU 0i0HKN9rZv2+C7OqPPggRWeWy0DiZa7NA8zUrXqRx8Wx4YkgIlRJ7/LpPXMSJek1dK 5xNmZCjiWJcBs++Rjfm7IKD7iuyzhvfQ/GC9b81ri+PQwMBHNILBgNYiQUdMR2piNq BwTB27au4bjpg== Message-ID: <3292610b-acb0-4b72-8aa8-9eec491238c5@kernel.org> Date: Wed, 23 Apr 2025 07:11:07 +0200 Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 tty-next] 8250: microchip: pci1xxxx: Add PCIe Hot reset disable support for Rev C0 and later devices To: Rengarajan S , kumaravel.thiagarajan@microchip.com, tharunkumar.pasumarthi@microchip.com, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, unglinuxdriver@microchip.com References: <20250423033841.33758-1-rengarajan.s@microchip.com> Content-Language: en-US From: Jiri Slaby Autocrypt: addr=jirislaby@kernel.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 23. 04. 25, 5:38, Rengarajan S wrote: > Systems that issue PCIe hot reset requests during a suspend/resume > cycle cause PCI1XXXX device revisions prior to C0 to get its UART > configuration registers reset to hardware default values. This results > in device inaccessibility and data transfer failures. Starting with > Revision C0, support was added in the device hardware (via the Hot > Reset Disable Bit) to allow resetting only the PCIe interface and its > associated logic, but preserving the UART configuration during a hot > reset. This patch enables the hot reset disable feature during suspend/ > resume for C0 and later revisions of the device. > > Signed-off-by: Rengarajan S > --- > drivers/tty/serial/8250/8250_pci1xxxx.c | 18 ++++++++++++++++-- > 1 file changed, 16 insertions(+), 2 deletions(-) > > diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c > index e9c51d4e447d..ec573327590f 100644 > --- a/drivers/tty/serial/8250/8250_pci1xxxx.c > +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c > @@ -115,6 +115,7 @@ > > #define UART_RESET_REG 0x94 > #define UART_RESET_D3_RESET_DISABLE BIT(16) > +#define UART_RESET_HOT_RESET_DISABLE BIT(17) > > #define UART_BURST_STATUS_REG 0x9C > #define UART_TX_BURST_FIFO 0xA0 > @@ -620,7 +621,13 @@ static int pci1xxxx_suspend(struct device *dev) > } > > data = readl(p + UART_RESET_REG); > - writel(data | UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG); > + > + if (priv->dev_rev >= 0xC0) > + writel(data | (UART_RESET_D3_RESET_DISABLE | > + UART_RESET_HOT_RESET_DISABLE), p + UART_RESET_REG); > + else > + writel(data | UART_RESET_D3_RESET_DISABLE, > + p + UART_RESET_REG); Instead of this overly long lines, could you just: data |= UART_RESET_HOT_RESET_DISABLE; and keep the writel() as is? thanks, -- js suse labs