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Mon, 24 Aug 2026 04:52:25 -0700 (PDT) X-Received: by 2002:a05:6a21:888a:b0:3cd:3e77:1dcd with SMTP id adf61e73a8af0-3cd3e771df5mr36827697637.1.1787572344804; Mon, 24 Aug 2026 04:52:24 -0700 (PDT) Received: from [10.217.218.158] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cc199e4b1d6sm885985a12.15.2026.08.24.04.52.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Aug 2026 04:52:24 -0700 (PDT) Message-ID: <3eb3b7ed-88d1-4185-accf-c81c14b1d408@oss.qualcomm.com> Date: Mon, 24 Aug 2026 17:22:17 +0530 Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/7] spi: qcom-geni: Use geni_se_set_rate() for setting source clock frequency To: Praveen Talari , konrad.dybcio@oss.qualcomm.com, Sudeep Holla , Cristian Marussi , Ulf Hansson , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Jiri Slaby , Mark Brown , Viken Dadhaniya , Andi Shyti Cc: chandana.chiluveru@oss.qualcomm.com, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org References: <20260805-derive_clk_perf_tbl_from_perf_domain_opp_table-v1-0-61171ab1cdce@oss.qualcomm.com> <20260805-derive_clk_perf_tbl_from_perf_domain_opp_table-v1-5-61171ab1cdce@oss.qualcomm.com> Content-Language: en-US From: Mukesh Savaliya In-Reply-To: <20260805-derive_clk_perf_tbl_from_perf_domain_opp_table-v1-5-61171ab1cdce@oss.qualcomm.com> Content-Type: text/plain; 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To work around this, firmware instead exposes the > SE HW supported source clock frequencies as OPPs on the perf domain > device. > > geni_se_domain_attach() now populates se->clk_perf_tbl from this OPP > table at attach time, mirroring clk_perf_tbl on the Linux-clock-managed > path. This lets get_spi_clk_cfg() call geni_se_clk_freq_match() to pick > the closest supported source clock frequency and divider on SA8255P > exactly as it already does when a Linux clock is present, and fill in > the GSI CONFIG0 TRE accordingly. > > Switch get_spi_clk_cfg() and spi_geni_runtime_resume() from calling > dev_pm_opp_set_rate() directly to the new geni_se_set_rate() helper, so > the matched frequency is applied to the correct device (the perf > domain device on the firmware managed path, or se->dev otherwise) > without the SPI driver needing to know which resources_init variant is > in use. > let me suggest little compressed commit message removing some duplication. geni_se_domain_attach() now populates clk_perf_tbl from the performance-domain OPP table, allowing firmware-managed platforms to use geni_se_clk_freq_match(). Use geni_se_set_rate() instead of dev_pm_opp_set_rate() so clock programming is handled centrally by the GENI core, independent of the underlying clock-control mechanism. > Signed-off-by: Praveen Talari > --- > drivers/spi/spi-geni-qcom.c | 17 ++++++----------- > 1 file changed, 6 insertions(+), 11 deletions(-) > > diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c [...] > @@ -150,9 +148,9 @@ static int get_spi_clk_cfg(unsigned int speed_hz, > > dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, > actual_hz, sclk_freq, *clk_idx, *clk_div); > - ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); > + ret = geni_se_set_rate(&mas->se, sclk_freq); > if (ret) > - dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); > + dev_err(mas->dev, "geni_se_set_rate failed %d\n", ret); little verbose - "Failed to set source clock rate %d"> else > mas->cur_sclk_hz = sclk_freq; > > @@ -847,7 +845,7 @@ static int setup_se_xfer(struct spi_transfer *xfer, > } [...]