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* mxs-auart stop bit-RTS delay
@ 2014-04-27  9:28 Chris
  0 siblings, 0 replies; only message in thread
From: Chris @ 2014-04-27  9:28 UTC (permalink / raw)
  To: linux-serial

I want to use the AUART0 of the i.MX28 with the handshake signals. For 
this I am using the latest stable Linux Kernel 3.14.1.

The AUART0 part of the device tree:

	auart0: serial@8006a000 {
    	pinctrl-names = "default";
    	pinctrl-0 = <&auart0_pins_a>; //four pins RX,TX,CTS,RTS
    	fsl,uart-has-rtscts;
    	status = "okay";
     };

So the device tree uses all four pins of this UART. In Linux itself I 
configure the interface with:

stty -F /dev/ttyAPP0 raw 9600 -echo -echoe -echok -echoctl -echoke crtscts

The UART and the handshake signals are working in principle. But I've 
noticed a delay between the RTS signal and the stopbit as you can see in 
the attached figure. If I have understood the RTS/CTS system correctly 
the RTS signal should be toggled immediately after the stopbit is sent. 
So that 13 ms (from the logic analyzer image) are really unnecessary and 
I can not trace it back where they are from. With other baudrates it is 
no less and no more than the 13 ms (~2...18ms-spread inside of the same 
baudrate)

I tried this too:

stty -F /dev/ttyAPP0 raw 9600 -echo -echoe -echok -echoctl -echoke -crtscts

The bits CTSEN and RTSEN of the UARTAPP_CTRL2 register are toggled, but 
there is still a something similar on the RTS lines, but now it is no 
CTS needed.

So my questions are, where are this delays come from?

How can I be sure who is toggling the RTS line (Linux or the i.MX28 
hardware module) ?

image logic analyzer:
https://community.freescale.com/servlet/JiveServlet/download/398158-274040/auart0_rts.png

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2014-04-27  9:28 mxs-auart stop bit-RTS delay Chris

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