From: John Ogness <john.ogness@linutronix.de>
To: yunhui cui <cuiyunhui@bytedance.com>,
Douglas Anderson <dianders@chromium.org>
Cc: arnd@arndb.de, andriy.shevchenko@linux.intel.com,
benjamin.larsson@genexis.eu, gregkh@linuxfoundation.org,
heikki.krogerus@linux.intel.com, ilpo.jarvinen@linux.intel.com,
jirislaby@kernel.org, jkeeping@inmusicbrands.com,
linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org,
markus.mayer@linaro.org, matt.porter@linaro.org,
namcao@linutronix.de, paulmck@kernel.org, pmladek@suse.com,
schnelle@linux.ibm.com, sunilvl@ventanamicro.com,
tim.kryger@linaro.org, stable@vger.kernel.org
Subject: Re: [External] Re: [PATCH v9 2/4] serial: 8250_dw: fix PSLVERR on RX_TIMEOUT
Date: Thu, 17 Jul 2025 16:20:29 +0206 [thread overview]
Message-ID: <84ikjqaoqi.fsf@jogness.linutronix.de> (raw)
In-Reply-To: <CAEEQ3w==dO2i+ZSsRZG0L1S+ccHSJQ-aUa9KE638MwnBM4+Jvw@mail.gmail.com>
Added Douglas Anderson, author of commit 424d79183af0 ("serial: 8250_dw:
Avoid "too much work" from bogus rx timeout interrupt").
On 2025-07-11, yunhui cui <cuiyunhui@bytedance.com> wrote:
>> On 2025-06-23, yunhui cui <cuiyunhui@bytedance.com> wrote:
>> >> The DW UART may trigger the RX_TIMEOUT interrupt without data
>> >> present and remain stuck in this state indefinitely. The
>> >> dw8250_handle_irq() function detects this condition by checking
>> >> if the UART_LSR_DR bit is not set when RX_TIMEOUT occurs. When
>> >> detected, it performs a "dummy read" to recover the DW UART from
>> >> this state.
>> >>
>> >> When the PSLVERR_RESP_EN parameter is set to 1, reading the UART_RX
>> >> while the FIFO is enabled and UART_LSR_DR is not set will generate a
>> >> PSLVERR error, which may lead to a system panic. There are two methods
>> >> to prevent PSLVERR: one is to check if UART_LSR_DR is set before reading
>> >> UART_RX when the FIFO is enabled, and the other is to read UART_RX when
>> >> the FIFO is disabled.
>> >>
>> >> Given these two scenarios, the FIFO must be disabled before the
>> >> "dummy read" operation and re-enabled afterward to maintain normal
>> >> UART functionality.
>> >>
>> >> Fixes: 424d79183af0 ("serial: 8250_dw: Avoid "too much work" from bogus rx timeout interrupt")
>> >> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
>> >> Cc: stable@vger.kernel.org
>> >> ---
>> >> drivers/tty/serial/8250/8250_dw.c | 10 +++++++++-
>> >> 1 file changed, 9 insertions(+), 1 deletion(-)
>> >>
>> >> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
>> >> index 1902f29444a1c..082b7fcf251db 100644
>> >> --- a/drivers/tty/serial/8250/8250_dw.c
>> >> +++ b/drivers/tty/serial/8250/8250_dw.c
>> >> @@ -297,9 +297,17 @@ static int dw8250_handle_irq(struct uart_port *p)
>> >> uart_port_lock_irqsave(p, &flags);
>> >> status = serial_lsr_in(up);
>> >>
>> >> - if (!(status & (UART_LSR_DR | UART_LSR_BI)))
>> >> + if (!(status & (UART_LSR_DR | UART_LSR_BI))) {
>> >> + /* To avoid PSLVERR, disable the FIFO first. */
>> >> + if (up->fcr & UART_FCR_ENABLE_FIFO)
>> >> + serial_out(up, UART_FCR, 0);
>> >> +
>> >> serial_port_in(p, UART_RX);
>> >>
>> >> + if (up->fcr & UART_FCR_ENABLE_FIFO)
>> >> + serial_out(up, UART_FCR, up->fcr);
>> >> + }
>> >> +
>> >> uart_port_unlock_irqrestore(p, flags);
>> >> }
>>
>> I do not know enough about the hardware. Is a dummy read really the only
>> way to exit the RX_TIMEOUT state?
>>
>> What if there are bytes in the TX-FIFO. Are they in danger of being
>> cleared?
>>
>> From [0] I see:
>>
>> "Writing a "0" to bit 0 will disable the FIFOs, in essence turning the
>> UART into 8250 compatibility mode. In effect this also renders the rest
>> of the settings in this register to become useless. If you write a "0"
>> here it will also stop the FIFOs from sending or receiving data, so any
>> data that is sent through the serial data port may be scrambled after
>> this setting has been changed. It would be recommended to disable FIFOs
>> only if you are trying to reset the serial communication protocol and
>> clearing any working buffers you may have in your application
>> software. Some documentation suggests that setting this bit to "0" also
>> clears the FIFO buffers, but I would recommend explicit buffer clearing
>> instead using bits 1 and 2."
>>
>> Have you performed tests where you fill the TX-FIFO and then
>> disable/enable the FIFO to see if the TX-bytes survive?
>
> Sorry, I haven't conducted relevant tests. The reason I made this
> modification is that it clearly contradicts the logic of avoiding
> PSLVERR. Disabling the FIFO can at least prevent the Panic() caused by
> PSVERR.
I am just wondering if there is some other way to avoid this. But since
we are talking about a hardware quirk and it is only related to
suspend/resume, maybe it is acceptable to risk data corruption in this
case. (?)
I am hoping Douglas can chime in.
John Ogness
>> [0] https://en.wikibooks.org/wiki/Serial_Programming/8250_UART_Programming
next prev parent reply other threads:[~2025-07-17 14:14 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-10 9:21 [PATCH v9 0/4] Serial: 8250: Fix PSLVERR related issues Yunhui Cui
2025-06-10 9:21 ` [PATCH v9 1/4] serial: 8250: fix panic due to PSLVERR Yunhui Cui
2025-06-20 11:19 ` John Ogness
2025-07-17 12:19 ` [External] " yunhui cui
2025-07-17 12:32 ` Greg KH
2025-06-10 9:21 ` [PATCH v9 2/4] serial: 8250_dw: fix PSLVERR on RX_TIMEOUT Yunhui Cui
2025-06-23 6:50 ` yunhui cui
2025-06-23 8:32 ` John Ogness
2025-07-11 2:19 ` [External] " yunhui cui
2025-07-17 14:14 ` John Ogness [this message]
2025-07-18 15:20 ` Doug Anderson
2025-06-10 9:21 ` [PATCH v9 3/4] serial: 8250: avoid potential PSLVERR issue Yunhui Cui
2025-06-20 11:20 ` John Ogness
2025-06-10 9:21 ` [PATCH v9 4/4] serial: 8250_dw: assert port->lock is held in dw8250_force_idle() Yunhui Cui
2025-06-20 12:14 ` John Ogness
2025-06-23 6:44 ` [External] " yunhui cui
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