[PATCH] uartlite: move from byte accesses to word accesses

[PATCH] uartlite: move from byte accesses to word accesses

[John Linn]

From: XAQ IP Librarian <abq_iplib@xaqiptest40.(none)>

Byte accesses for I/O devices in Xilinx IP is going to be less
desired in the future such that the driver is being changed to
use 32 bit accesses.

Signed-off-by: John Linn <john.linn@xilinx.com>
---
 drivers/serial/uartlite.c |   36 ++++++++++++++++++------------------
 1 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/serial/uartlite.c b/drivers/serial/uartlite.c
index 377f271..9f83949 100644
--- a/drivers/serial/uartlite.c
+++ b/drivers/serial/uartlite.c
@@ -86,7 +86,7 @@ static int ulite_receive(struct uart_port *port, int stat)
 	/* stats */
 	if (stat & ULITE_STATUS_RXVALID) {
 		port->icount.rx++;
-		ch = readb(port->membase + ULITE_RX);
+		ch = (u8)in_be32(port->membase + ULITE_RX);
 
 		if (stat & ULITE_STATUS_PARITY)
 			port->icount.parity++;
@@ -131,7 +131,7 @@ static int ulite_transmit(struct uart_port *port, int stat)
 		return 0;
 
 	if (port->x_char) {
-		writeb(port->x_char, port->membase + ULITE_TX);
+		out_be32(port->membase + ULITE_TX, (u32)port->x_char);
 		port->x_char = 0;
 		port->icount.tx++;
 		return 1;
@@ -140,7 +140,7 @@ static int ulite_transmit(struct uart_port *port, int stat)
 	if (uart_circ_empty(xmit) || uart_tx_stopped(port))
 		return 0;
 
-	writeb(xmit->buf[xmit->tail], port->membase + ULITE_TX);
+	out_be32(port->membase + ULITE_TX, (u32)xmit->buf[xmit->tail]);
 	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
 	port->icount.tx++;
 
@@ -157,7 +157,7 @@ static irqreturn_t ulite_isr(int irq, void *dev_id)
 	int busy, n = 0;
 
 	do {
-		int stat = readb(port->membase + ULITE_STATUS);
+		int stat = in_be32(port->membase + ULITE_STATUS);
 		busy  = ulite_receive(port, stat);
 		busy |= ulite_transmit(port, stat);
 		n++;
@@ -178,7 +178,7 @@ static unsigned int ulite_tx_empty(struct uart_port *port)
 	unsigned int ret;
 
 	spin_lock_irqsave(&port->lock, flags);
-	ret = readb(port->membase + ULITE_STATUS);
+	ret = in_be32(port->membase + ULITE_STATUS);
 	spin_unlock_irqrestore(&port->lock, flags);
 
 	return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
@@ -201,7 +201,7 @@ static void ulite_stop_tx(struct uart_port *port)
 
 static void ulite_start_tx(struct uart_port *port)
 {
-	ulite_transmit(port, readb(port->membase + ULITE_STATUS));
+	ulite_transmit(port, (u8)in_be32(port->membase + ULITE_STATUS));
 }
 
 static void ulite_stop_rx(struct uart_port *port)
@@ -230,17 +230,17 @@ static int ulite_startup(struct uart_port *port)
 	if (ret)
 		return ret;
 
-	writeb(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
-	       port->membase + ULITE_CONTROL);
-	writeb(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
+	out_be32(port->membase + ULITE_CONTROL,
+			ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
+	out_be32(port->membase + ULITE_CONTROL, ULITE_CONTROL_IE);
 
 	return 0;
 }
 
 static void ulite_shutdown(struct uart_port *port)
 {
-	writeb(0, port->membase + ULITE_CONTROL);
-	readb(port->membase + ULITE_CONTROL); /* dummy */
+	out_be32(port->membase + ULITE_CONTROL, 0);
+	in_be32(port->membase + ULITE_CONTROL); /* dummy */
 	free_irq(port->irq, port);
 }
 
@@ -348,11 +348,11 @@ static struct uart_ops ulite_ops = {
 static void ulite_console_wait_tx(struct uart_port *port)
 {
 	int i;
-	u8 val;
+	u32 val;
 
 	/* Spin waiting for TX fifo to have space available */
 	for (i = 0; i < 100000; i++) {
-		val = readb(port->membase + ULITE_STATUS);
+		val = in_be32(port->membase + ULITE_STATUS);
 		if ((val & ULITE_STATUS_TXFULL) == 0)
 			break;
 		cpu_relax();
@@ -362,7 +362,7 @@ static void ulite_console_wait_tx(struct uart_port *port)
 static void ulite_console_putchar(struct uart_port *port, int ch)
 {
 	ulite_console_wait_tx(port);
-	writeb(ch, port->membase + ULITE_TX);
+	out_be32(port->membase + ULITE_TX, (u32)ch);
 }
 
 static void ulite_console_write(struct console *co, const char *s,
@@ -379,8 +379,8 @@ static void ulite_console_write(struct console *co, const char *s,
 		spin_lock_irqsave(&port->lock, flags);
 
 	/* save and disable interrupt */
-	ier = readb(port->membase + ULITE_STATUS) & ULITE_STATUS_IE;
-	writeb(0, port->membase + ULITE_CONTROL);
+	ier = in_be32(port->membase + ULITE_STATUS) & ULITE_STATUS_IE;
+	out_be32(port->membase + ULITE_CONTROL, 0);
 
 	uart_console_write(port, s, count, ulite_console_putchar);
 
@@ -388,7 +388,7 @@ static void ulite_console_write(struct console *co, const char *s,
 
 	/* restore interrupt state */
 	if (ier)
-		writeb(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
+		out_be32(port->membase + ULITE_CONTROL, ULITE_CONTROL_IE);
 
 	if (locked)
 		spin_unlock_irqrestore(&port->lock, flags);
@@ -601,7 +601,7 @@ ulite_of_probe(struct of_device *op, const struct of_device_id *match)
 
 	id = of_get_property(op->node, "port-number", NULL);
 
-	return ulite_assign(&op->dev, id ? *id : -1, res.start+3, irq);
+	return ulite_assign(&op->dev, id ? *id : -1, res.start, irq);
 }
 
 static int __devexit ulite_of_remove(struct of_device *op)
-- 
1.6.2.1



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Re: [PATCH] uartlite: move from byte accesses to word accesses

[Peter Korsgaard]

>>>>> "John" == John Linn <john.linn@xilinx.com> writes:

 John> From: XAQ IP Librarian <abq_iplib@xaqiptest40.(none)>
 John> Byte accesses for I/O devices in Xilinx IP is going to be less
 John> desired in the future such that the driver is being changed to
 John> use 32 bit accesses.

Why is it less desired?

Back when I wrote the driver, I used 8bit access on purpose to be
independent of register widths / endianess.

We have used the driver on systems where (something looking like) a
uartlite was behind a 16bit bus, so doing 32bit accesses would require
double the bus accesses.

Btw, the abq_iplib@xaqiptest40 address is (obviously) invalid.

-- 
Bye, Peter Korsgaard

RE: [PATCH] uartlite: move from byte accesses to word accesses

[John Linn]

> -----Original Message-----
> From: Peter Korsgaard [mailto:jacmet@gmail.com] On Behalf Of Peter
Korsgaard
> Sent: Wednesday, January 20, 2010 12:24 PM
> To: John Linn
> Cc: linux-serial@vger.kernel.org; grant.likely@secretlab.ca;
michal.simek@petalogix.com;
> john.williams@petalogix.com
> Subject: Re: [PATCH] uartlite: move from byte accesses to word
accesses
> 
> >>>>> "John" == John Linn <john.linn@xilinx.com> writes:
> 
>  John> From: XAQ IP Librarian <abq_iplib@xaqiptest40.(none)>
>  John> Byte accesses for I/O devices in Xilinx IP is going to be less
>  John> desired in the future such that the driver is being changed to
>  John> use 32 bit accesses.
> 
> Why is it less desired?

We are wanting to use our IP cores over a PCIe bus and it only allows 32
bit accesses.

> 
> Back when I wrote the driver, I used 8bit access on purpose to be
> independent of register widths / endianess.
> 
> We have used the driver on systems where (something looking like) a
> uartlite was behind a 16bit bus, so doing 32bit accesses would require
> double the bus accesses.

I understand.  Most of our customers are using a 32 bit bus so that this
wouldn't be a problem for most people.

We could do some kind of conditional compilation for the accesses, but
it's certainly less desired.  We could make 32 bit the default and then
allow a kernel config to change the access size.

> 
> Btw, the abq_iplib@xaqiptest40 address is (obviously) invalid.

Yes, I saw that after it went out, I'll have to find the source of that
weirdness.

Thanks, 
John

> 
> --
> Bye, Peter Korsgaard


This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

Re: [PATCH] uartlite: move from byte accesses to word accesses

[Peter Korsgaard]

>>>>> "John" == John Linn <John.Linn@xilinx.com> writes:

Hi,

 >> Why is it less desired?

 John> We are wanting to use our IP cores over a PCIe bus and it only
 John> allows 32 bit accesses.

Ok, that's valuable information for the commit messages.

 John> I understand.  Most of our customers are using a 32 bit bus so
 John> that this wouldn't be a problem for most people.

 John> We could do some kind of conditional compilation for the
 John> accesses, but it's certainly less desired.  We could make 32 bit
 John> the default and then allow a kernel config to change the access
 John> size.

Naah, the project where we needed 16bit access is _OLD_, and the
platform hasn't been ported from arch/ppc, so let's just move to 32bit
access.

If you send an updated patch with a more detailed commit message then
I'll ack it.

-- 
Bye, Peter Korsgaard

RE: [PATCH] uartlite: move from byte accesses to word accesses

[John Linn]

Hi,

> -----Original Message-----
> From: Peter Korsgaard [mailto:jacmet@gmail.com] On Behalf Of Peter
Korsgaard
> Sent: Wednesday, January 20, 2010 3:53 PM
> To: John Linn
> Cc: linux-serial@vger.kernel.org; grant.likely@secretlab.ca;
michal.simek@petalogix.com;
> john.williams@petalogix.com
> Subject: Re: [PATCH] uartlite: move from byte accesses to word
accesses
> 
> >>>>> "John" == John Linn <John.Linn@xilinx.com> writes:
> 
> Hi,
> 
>  >> Why is it less desired?
> 
>  John> We are wanting to use our IP cores over a PCIe bus and it only
>  John> allows 32 bit accesses.
> 
> Ok, that's valuable information for the commit messages.

Understood, should have given more details.

> 
>  John> I understand.  Most of our customers are using a 32 bit bus so
>  John> that this wouldn't be a problem for most people.
> 
>  John> We could do some kind of conditional compilation for the
>  John> accesses, but it's certainly less desired.  We could make 32
bit
>  John> the default and then allow a kernel config to change the access
>  John> size.
> 
> Naah, the project where we needed 16bit access is _OLD_, and the
> platform hasn't been ported from arch/ppc, so let's just move to 32bit
> access.
> 

Agreed.

> If you send an updated patch with a more detailed commit message then
> I'll ack it.
> 

Sounds great, I'll respin it and send it tomorrow.

Thanks for your help.

> --
> Bye, Peter Korsgaard


This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.