Re: Uartlite driver

[Peter Korsgaard <jacmet@sunsite.dk>]

>>>>> "David" == David H Lynch <dhlii@dlasys.net> writes:

Hi,

 David> I am also not happy with the register definitions hard coded
 David> as 0,4,8,12 I have not read the Xilinx UartLite docs recently,
 David> but there was older Xilinx code that implied the registers
 David> could be 8, 16 or 32 bits.  There is also atleast one
 David> implimentation out there that accesses the UartLite via DCR.

Can the Xilinx core be configured for anything else than 32bit offset?
I don't think so.

 David>      Can we just move all the in's and outs to something like:

 David> static unsigned int
 David> serial_in(struct uart_port *port, int offset) {
 David>     unsigned int value;

 David>     switch (port->iotype) {
 David>         case UPIO_PORT:
 David>             value = mfdcr(offset);
 David>             break;
 David>         default:
 David>             offset <<= port->regshift;
 David>             value = readb(port->membase + offset);
 David>     }
 David>     return value;
 David> }

 David> Then we can handle all the 8/16/32 BE/LE, DCR, .... in one place ?
 David> I think that is what is done in other drivers.

The only one that afaik does this is 8250.c because of the mindblowing
number of more-or-less compatible 8250 implementations. That's surely
not the case for the uartlite.

But ok, if the DCR access mode is supported by Xilinx - Why not?
Patches are welcome.

-- 
Bye, Peter Korsgaard