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On 24-08-2026 20:36, Konrad Dybcio wrote: > On 8/4/26 9:57 PM, Praveen Talari wrote: >> On the SA8255P platform there is no Linux clock handler for the SE source >> clock; resources are instead managed by firmware via a genpd performance >> domain. The I2C driver therefore relies on geni_se_set_rate() to apply the >> fixed 19.2 MHz source clock frequency expected by the SCL divider and >> counter values programmed by qcom_geni_i2c_conf(). > [...] > >> @@ -233,6 +233,10 @@ static int qcom_geni_i2c_conf(struct geni_se *se, unsigned long freq) >> itr->clk_div, itr->t_high_cnt, >> itr->t_low_cnt, itr->t_cycle_cnt); >> >> + ret = geni_se_set_rate(&gi2c->se, 19200000); >> + if (ret) >> + return ret; > This wasn't here before and the commit message only says something to the Yes, it was not there earlier. I have added because of Fast-mode Plus (1 MHz) cannot achieve the required timings with the default 19.2 MHz source clock. A higher source frequency (for example, 32.5 MHz or 37.5 MHz) is required, along with the associated voltage/performance vote. Thanks, Praveen Talari > amount of "it's necessary" - what's the difference? > > Konrad