From: Shane McDonald <mcdonald.shane@gmail.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: Jamie Iles <jamie@jamieiles.com>,
linux-serial@vger.kernel.org, Greg Kroah-Hartman <gregkh@suse.de>,
linux-mips@linux-mips.org, Marc St-Jean <bluezzer@gmail.com>,
Anoop P A <anoop.pa@gmail.com>
Subject: Re: [PATCH] tty: 8250: handle USR for DesignWare 8250 with correct accessors
Date: Tue, 14 Jun 2011 09:33:45 -0600 [thread overview]
Message-ID: <BANLkTi=0Pk-2YT=jLeBTNLYELfo+e-saZA@mail.gmail.com> (raw)
In-Reply-To: <20110610035817.GA6740@linux-mips.org>
On Thu, Jun 9, 2011 at 9:58 PM, Ralf Baechle <ralf@linux-mips.org> wrote:
> If you look at arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h there's
>
> #define MSP_UART0_BASE (MSP_SLP_BASE + 0x100)
> /* UART0 controller base */
> #define MSP_BCPY_CTRL_BASE (MSP_SLP_BASE + 0x120)
> /* Block Copy controller base */
>
> So there are just 0x20 of address space reserved for that UART. Me thinks
> that PMC-Sierra clamped the 256 byte address space of the DesignWare APB
> UART to what is standard for 16550 class UARTs, 8 registers which at a
> shift of 4 is 0x20 bytes and the status register being accesses is really
> something else. I'd guess PMC-Sierra just remapped the register to
> another address.
I have confirmed with a contact at PMC-Sierra that this is the case.
Shane
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next prev parent reply other threads:[~2011-06-14 15:33 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-06-09 10:48 [PATCH] tty: 8250: handle USR for DesignWare 8250 with correct accessors Jamie Iles
2011-06-10 3:58 ` Ralf Baechle
2011-06-10 7:54 ` Jamie Iles
2011-06-10 13:57 ` Alan Cox
2011-06-13 9:19 ` Jamie Iles
2011-06-13 9:29 ` Alan Cox
2011-06-10 18:58 ` Shane McDonald
2011-06-14 15:33 ` Shane McDonald [this message]
2011-06-15 8:49 ` Jamie Iles
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