From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8868C433F5 for ; Fri, 18 Mar 2022 14:25:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237011AbiCRO1M (ORCPT ); Fri, 18 Mar 2022 10:27:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236864AbiCRO1L (ORCPT ); Fri, 18 Mar 2022 10:27:11 -0400 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3596813667D; Fri, 18 Mar 2022 07:25:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1647613553; x=1679149553; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=HVGWQSN8Ko7B/4rAfzeNU+LVyHQtN/f29tiIE9kf1RE=; b=KmH+BbfbTBGYroCeueCUpsf5b/rbJ5iUhc9RHXYs7P9zRMCS0Pqd8+00 vJFFiBdXWOFlUccMx1cJSMiPXquGz7ldDUsDAbH57A559DjR0GlR0cRGP 7yOuUc2l18OhXE1xDIvMxk/qoKxOpuoUAE7uTzUJRWmeP7jCH/bBR//mu cQAzJVHJeAsaDhm4XpQbb5eK/i5DQ4VhCYcM5t29niqf/WRfIiLTb0sxf wPsZTOc3iIrg30O8Bg+rFjgxV4vIHrDeKcqgd2lYcrYNp/4nvfohBPAgc +GZdloD5FmHasyIT/wM9mA0Sd5pIkVZQHvUDyM902rGv1lgaXD5AjJBbZ g==; X-IronPort-AV: E=McAfee;i="6200,9189,10289"; a="257332515" X-IronPort-AV: E=Sophos;i="5.90,192,1643702400"; d="scan'208";a="257332515" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2022 07:25:34 -0700 X-IronPort-AV: E=Sophos;i="5.90,192,1643702400"; d="scan'208";a="513881332" Received: from smile.fi.intel.com ([10.237.72.59]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2022 07:25:30 -0700 Received: from andy by smile.fi.intel.com with local (Exim 4.95) (envelope-from ) id 1nVDX9-002GrW-EI; Fri, 18 Mar 2022 16:24:51 +0200 Date: Fri, 18 Mar 2022 16:24:51 +0200 From: Andy Shevchenko To: Miquel Raynal Cc: linux-renesas-soc@vger.kernel.org, Magnus Damm , Gareth Williams , Phil Edworthy , Geert Uytterhoeven , Greg Kroah-Hartman , Jiri Slaby , Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , linux-serial@vger.kernel.org Subject: Re: [PATCH v2 08/10] serial: 8250: dw: Add support for DMA flow controlling devices Message-ID: References: <20220317174627.360815-1-miquel.raynal@bootlin.com> <20220317174627.360815-9-miquel.raynal@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220317174627.360815-9-miquel.raynal@bootlin.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org On Thu, Mar 17, 2022 at 06:46:25PM +0100, Miquel Raynal wrote: > From: Phil Edworthy > > DW based controllers like the one on Renesas RZ/N1 must be programmed as > flow controllers when using DMA. > > * Table 11.45 of the system manual, "Flow Control Combinations", states > that using UART with DMA requires setting the DMA in the peripheral > flow controller mode regardless of the direction. > > * Chapter 11.6.1.3 of the system manual, "Basic Interface Definitions", > explains that the burst size in the above case must be configured in > the peripheral's register DEST/SRC_BURST_SIZE. > > Experiments shown that upon Rx timeout, the DMA transaction needed to be > manually cleared as well. ... > +#define DW_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */ > +#define DW_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */ These are not Synposys ones. ... > +static u32 dw8250_rzn1_get_dmacr_burst(int max_burst) > +{ > + if (max_burst >= 8) > + return DW_UART_xDMACR_8_WORD_BURST; > + else if (max_burst >= 4) > + return DW_UART_xDMACR_4_WORD_BURST; > + else > + return DW_UART_xDMACR_1_WORD_BURST; > +} Redundant 'else' in all cases. -- With Best Regards, Andy Shevchenko