[PATCH v2 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support

[PATCH v2 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support

[Phil Edworthy]

Hello,

RZ/V2M has a dual-core Cortex-A53 (1.0 GHz) CPU and built-in AI
accelerator "DRP-AI" for vision, which is Renesas' original technology.
It also has a 32-bit LPDDR4 interface and video codec (H.264).

The RZ/V2M is used with ISP firmware that runs on one of the Cortex-A53
cores. The firmware is an integral part of the SoC such that the HW
User's Manual documents which of the peripheral modules are used by the
firmware.

Initial patches enables minimal peripherals on Renesas RZ/V2M EVK board
and booted via nfs. Ethernet is broadly compatible with the
etheravb-rcar-gen3 driver, but interrupts need some work so it's not
been included in this patch set.

Below blocks are enabled on Renesas RZ/V2M EVK board:
- memory
- External input clock
- CPG
- UART

Links for SoC and EVK:
[*] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output


Sorry for cross posting the patches to multiple subsystems, as these are
just the dt-binding patches included as part of initial bringup patches.

v2:
 * Removed SYS dt-bindings patch and corresponding SoC identification
   as we only used the LSI version register. This can be dealt with
   later on.
 * Fixed em-uart dt-bindings.
 * Included reviewed-by tags.

Thanks
Phil

[PATCH v2 02/13] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings

[Phil Edworthy]

The Renesas RZ/V2M (r9a09g011) SoC uses a uart that is compatible with the
EMMA Mobile SoC.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2: Fix dtbs_check by adding missing alternative binding
---
 .../devicetree/bindings/serial/renesas,em-uart.yaml      | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
index e98ec48fee46..332c385618e1 100644
--- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
@@ -14,7 +14,14 @@ allOf:
 
 properties:
   compatible:
-    const: renesas,em-uart
+    oneOf:
+      - items:
+          - enum:
+              - renesas,r9a09g011-uart    # RZ/V2M
+          - const: renesas,em-uart        # generic EMMA Mobile compatible UART
+
+      - items:
+          - const: renesas,em-uart        # generic EMMA Mobile compatible UART
 
   reg:
     maxItems: 1
-- 
2.32.0

[PATCH v2 05/13] serial: 8250: Make SERIAL_8250_EM available for arm64 systems

[Phil Edworthy]

This is needed for the Renesas RZ/V2M (r9a09g011) SoC.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/tty/serial/8250/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig
index cd93ea6eed65..fdb6c4188695 100644
--- a/drivers/tty/serial/8250/Kconfig
+++ b/drivers/tty/serial/8250/Kconfig
@@ -380,7 +380,7 @@ config SERIAL_8250_DW
 config SERIAL_8250_EM
 	tristate "Support for Emma Mobile integrated serial port"
 	depends on SERIAL_8250 && HAVE_CLK
-	depends on (ARM && ARCH_RENESAS) || COMPILE_TEST
+	depends on ARCH_RENESAS || COMPILE_TEST
 	help
 	  Selecting this option will add support for the integrated serial
 	  port hardware found on the Emma Mobile line of processors.
-- 
2.32.0

Re: [PATCH v2 02/13] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings

[Rob Herring]

On Wed, 30 Mar 2022 16:40:13 +0100, Phil Edworthy wrote:
> The Renesas RZ/V2M (r9a09g011) SoC uses a uart that is compatible with the
> EMMA Mobile SoC.
> 
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2: Fix dtbs_check by adding missing alternative binding
> ---
>  .../devicetree/bindings/serial/renesas,em-uart.yaml      | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support

[Geert Uytterhoeven]

Hi Phil,

On Wed, Mar 30, 2022 at 5:40 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> RZ/V2M has a dual-core Cortex-A53 (1.0 GHz) CPU and built-in AI
> accelerator "DRP-AI" for vision, which is Renesas' original technology.
> It also has a 32-bit LPDDR4 interface and video codec (H.264).
>
> The RZ/V2M is used with ISP firmware that runs on one of the Cortex-A53
> cores. The firmware is an integral part of the SoC such that the HW
> User's Manual documents which of the peripheral modules are used by the
> firmware.
>
> Initial patches enables minimal peripherals on Renesas RZ/V2M EVK board
> and booted via nfs. Ethernet is broadly compatible with the
> etheravb-rcar-gen3 driver, but interrupts need some work so it's not
> been included in this patch set.
>
> Below blocks are enabled on Renesas RZ/V2M EVK board:
> - memory
> - External input clock
> - CPG
> - UART

Thanks for your series!

> v2:
>  * Removed SYS dt-bindings patch and corresponding SoC identification
>    as we only used the LSI version register. This can be dealt with
>    later on.

That patch[1] also introduced the ARCH_R9A09G011 config symbol,
without which none of the new code in this series is built.

[1] [PATCH 07/14] soc: renesas: Identify RZ/V2M SoC
    https://lore.kernel.org/all/20220321154232.56315-8-phil.edworthy@renesas.com/

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v2 00/14] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support

[Phil Edworthy]

Hi Geert,

On 20 April 2022 21:11 Geert Uytterhoeven wrote:
> Hi Phil,
> 
> On Wed, Mar 30, 2022 at 5:40 PM Phil Edworthy <phil.edworthy@renesas.com>
> wrote:
> > RZ/V2M has a dual-core Cortex-A53 (1.0 GHz) CPU and built-in AI
> > accelerator "DRP-AI" for vision, which is Renesas' original technology.
> > It also has a 32-bit LPDDR4 interface and video codec (H.264).
> >
> > The RZ/V2M is used with ISP firmware that runs on one of the Cortex-A53
> > cores. The firmware is an integral part of the SoC such that the HW
> > User's Manual documents which of the peripheral modules are used by the
> > firmware.
> >
> > Initial patches enables minimal peripherals on Renesas RZ/V2M EVK board
> > and booted via nfs. Ethernet is broadly compatible with the
> > etheravb-rcar-gen3 driver, but interrupts need some work so it's not
> > been included in this patch set.
> >
> > Below blocks are enabled on Renesas RZ/V2M EVK board:
> > - memory
> > - External input clock
> > - CPG
> > - UART
> 
> Thanks for your series!
> 
> > v2:
> >  * Removed SYS dt-bindings patch and corresponding SoC identification
> >    as we only used the LSI version register. This can be dealt with
> >    later on.
> 
> That patch[1] also introduced the ARCH_R9A09G011 config symbol,
> without which none of the new code in this series is built.
> 
> [1] [PATCH 07/14] soc: renesas: Identify RZ/V2M SoC
> 
> https://lore.kernel.org/all/20220321154232.56315-8-phil.edworthy@renesas.com/

Ah, right. I should have said that I replaced that patch with
"[PATCH v2 06/13] soc: renesas: Add RZ/V2M (R9A09G011) config option".
However, looking back I managed to send that patch only to myself.
Doh!

Thanks
Phil


> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But
> when I'm talking to journalists I just say "programmer" or something like
> that.
>                                 -- Linus Torvalds

Re: [PATCH v2 02/13] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings

[Geert Uytterhoeven]

Hi Phil,

On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> The Renesas RZ/V2M (r9a09g011) SoC uses a uart that is compatible with the
> EMMA Mobile SoC.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2: Fix dtbs_check by adding missing alternative binding

Thanks for your patch, which is now commit 7bb301812b628099
("dt-bindings: serial: renesas,em-uart: Document r9a09g011
bindings") in tty/tty-next.

> --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> @@ -14,7 +14,14 @@ allOf:
>
>  properties:
>    compatible:
> -    const: renesas,em-uart
> +    oneOf:
> +      - items:
> +          - enum:
> +              - renesas,r9a09g011-uart    # RZ/V2M
> +          - const: renesas,em-uart        # generic EMMA Mobile compatible UART
> +
> +      - items:
> +          - const: renesas,em-uart        # generic EMMA Mobile compatible UART

The above looks good to me.

>
>    reg:
>      maxItems: 1

However, unlike EMEV2, RZ/V2M defines two clocks: pclk and sclk.
Hence please update the clocks section to reflect that.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v2 02/13] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings

[Phil Edworthy]

Hi Geert,

(updated Krzysztof's email)

On 20 April 2022 22:26 Geert Uytterhoeven wrote:
> On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy <phil.edworthy@renesas.com>
> wrote:
> > The Renesas RZ/V2M (r9a09g011) SoC uses a uart that is compatible with
> the
> > EMMA Mobile SoC.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v2: Fix dtbs_check by adding missing alternative binding
> 
> Thanks for your patch, which is now commit 7bb301812b628099
> ("dt-bindings: serial: renesas,em-uart: Document r9a09g011
> bindings") in tty/tty-next.
> 
> > --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > @@ -14,7 +14,14 @@ allOf:
> >
> >  properties:
> >    compatible:
> > -    const: renesas,em-uart
> > +    oneOf:
> > +      - items:
> > +          - enum:
> > +              - renesas,r9a09g011-uart    # RZ/V2M
> > +          - const: renesas,em-uart        # generic EMMA Mobile
> compatible UART
> > +
> > +      - items:
> > +          - const: renesas,em-uart        # generic EMMA Mobile
> compatible UART
> 
> The above looks good to me.
> 
> >
> >    reg:
> >      maxItems: 1
> 
> However, unlike EMEV2, RZ/V2M defines two clocks: pclk and sclk.
> Hence please update the clocks section to reflect that.
You are right that the uart has two clocks.

Note though that pclk is shared by both uarts. The HW manual says:
"ch. 1 is for use with the ISP support package, so do not
use registers related to this channel.". Due to this, section
48.5.2.50 Clock ON/OFF Control Register 15 (CPG_CLK_ON15) says
that bit 20, CLK4_ONWEN (enable for URT_PCLK) should be written
as 0.

I took this to mean that the URT_PCLK is enabled by the ISP firmware
and software must not touch it. I am not sure if the DT bindings
should document a clock that is specified as do not touch in the
HW manual. This is a bit of a grey area.

Thanks
Phil

Re: [PATCH v2 02/13] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings

[Geert Uytterhoeven]

Hi Phil,

On Fri, Apr 22, 2022 at 10:28 AM Phil Edworthy
<phil.edworthy@renesas.com> wrote:
> On 20 April 2022 22:26 Geert Uytterhoeven wrote:
> > On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy <phil.edworthy@renesas.com>
> > wrote:
> > > The Renesas RZ/V2M (r9a09g011) SoC uses a uart that is compatible with
> > the
> > > EMMA Mobile SoC.
> > >
> > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > ---
> > > v2: Fix dtbs_check by adding missing alternative binding
> >
> > Thanks for your patch, which is now commit 7bb301812b628099
> > ("dt-bindings: serial: renesas,em-uart: Document r9a09g011
> > bindings") in tty/tty-next.
> >
> > > --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > > +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > > @@ -14,7 +14,14 @@ allOf:
> > >
> > >  properties:
> > >    compatible:
> > > -    const: renesas,em-uart
> > > +    oneOf:
> > > +      - items:
> > > +          - enum:
> > > +              - renesas,r9a09g011-uart    # RZ/V2M
> > > +          - const: renesas,em-uart        # generic EMMA Mobile
> > compatible UART
> > > +
> > > +      - items:
> > > +          - const: renesas,em-uart        # generic EMMA Mobile
> > compatible UART
> >
> > The above looks good to me.
> >
> > >
> > >    reg:
> > >      maxItems: 1
> >
> > However, unlike EMEV2, RZ/V2M defines two clocks: pclk and sclk.
> > Hence please update the clocks section to reflect that.
> You are right that the uart has two clocks.
>
> Note though that pclk is shared by both uarts. The HW manual says:
> "ch. 1 is for use with the ISP support package, so do not
> use registers related to this channel.". Due to this, section
> 48.5.2.50 Clock ON/OFF Control Register 15 (CPG_CLK_ON15) says
> that bit 20, CLK4_ONWEN (enable for URT_PCLK) should be written
> as 0.
>
> I took this to mean that the URT_PCLK is enabled by the ISP firmware
> and software must not touch it. I am not sure if the DT bindings
> should document a clock that is specified as do not touch in the
> HW manual. This is a bit of a grey area.

"DT describes hardware, not software policy".

But I agree this is a grey area.

One option would be to mark URT_PCLK critical, so it won't be disabled.
But that would still mean it's enabled by Linux, i.e. Linux would set
CLK4_ONWEN to 1 while enabling the clock.

Another option would be to create URT_PCLK as a non-gateable clock,
so Linux won't ever touch the register bits.

Or just ignore URT_PCLK and do nothing, like you did ;-)
Would it be possible for a user to not use the ISP firmware at all,
and go full Linux, hence using both UART channels and URT_PCLK?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v2 02/13] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings

[Phil Edworthy]

Hi Geert,

On 22 April 2022 09:45 Geert Uytterhoeven wrote:
> On Fri, Apr 22, 2022 at 10:28 AM Phil Edworthy wrote:
> > On 20 April 2022 22:26 Geert Uytterhoeven wrote:
> > > On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy wrote:
> > > > The Renesas RZ/V2M (r9a09g011) SoC uses a uart that is compatible
> with
> > > the
> > > > EMMA Mobile SoC.
> > > >
> > > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > ---
> > > > v2: Fix dtbs_check by adding missing alternative binding
> > >
> > > Thanks for your patch, which is now commit 7bb301812b628099
> > > ("dt-bindings: serial: renesas,em-uart: Document r9a09g011
> > > bindings") in tty/tty-next.
> > >
> > > > --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > > > +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > > > @@ -14,7 +14,14 @@ allOf:
> > > >
> > > >  properties:
> > > >    compatible:
> > > > -    const: renesas,em-uart
> > > > +    oneOf:
> > > > +      - items:
> > > > +          - enum:
> > > > +              - renesas,r9a09g011-uart    # RZ/V2M
> > > > +          - const: renesas,em-uart        # generic EMMA Mobile
> > > compatible UART
> > > > +
> > > > +      - items:
> > > > +          - const: renesas,em-uart        # generic EMMA Mobile
> > > compatible UART
> > >
> > > The above looks good to me.
> > >
> > > >
> > > >    reg:
> > > >      maxItems: 1
> > >
> > > However, unlike EMEV2, RZ/V2M defines two clocks: pclk and sclk.
> > > Hence please update the clocks section to reflect that.
> > You are right that the uart has two clocks.
> >
> > Note though that pclk is shared by both uarts. The HW manual says:
> > "ch. 1 is for use with the ISP support package, so do not
> > use registers related to this channel.". Due to this, section
> > 48.5.2.50 Clock ON/OFF Control Register 15 (CPG_CLK_ON15) says
> > that bit 20, CLK4_ONWEN (enable for URT_PCLK) should be written
> > as 0.
> >
> > I took this to mean that the URT_PCLK is enabled by the ISP firmware
> > and software must not touch it. I am not sure if the DT bindings
> > should document a clock that is specified as do not touch in the
> > HW manual. This is a bit of a grey area.
> 
> "DT describes hardware, not software policy".
> 
> But I agree this is a grey area.
I wish the HW manual either didn’t mention this clock that you should
not touch, or didn’t specify anything as "used by the ISP firmware" :)

> One option would be to mark URT_PCLK critical, so it won't be disabled.
> But that would still mean it's enabled by Linux, i.e. Linux would set
> CLK4_ONWEN to 1 while enabling the clock.
> 
> Another option would be to create URT_PCLK as a non-gateable clock,
> so Linux won't ever touch the register bits.
> 
> Or just ignore URT_PCLK and do nothing, like you did ;-)
> Would it be possible for a user to not use the ISP firmware at all,
> and go full Linux, hence using both UART channels and URT_PCLK?
It is possible to not use the ISP firmware, but them what do we do?
Ignore everything in the HW manual that says "ISP firmware"?

Ideally, we want to only enable a clock if it's not already enabled,
but not turn it off if it is enabled. Isn't that a critical clk?

Thanks
Phil

Re: [PATCH v2 02/13] dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings

[Geert Uytterhoeven]

Hi Phil,

On Fri, Apr 22, 2022 at 11:31 AM Phil Edworthy
<phil.edworthy@renesas.com> wrote:
> On 22 April 2022 09:45 Geert Uytterhoeven wrote:
> > On Fri, Apr 22, 2022 at 10:28 AM Phil Edworthy wrote:
> > > On 20 April 2022 22:26 Geert Uytterhoeven wrote:
> > > > On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy wrote:
> > > > > The Renesas RZ/V2M (r9a09g011) SoC uses a uart that is compatible
> > with
> > > > the
> > > > > EMMA Mobile SoC.
> > > > >
> > > > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > > > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > ---
> > > > > v2: Fix dtbs_check by adding missing alternative binding
> > > >
> > > > Thanks for your patch, which is now commit 7bb301812b628099
> > > > ("dt-bindings: serial: renesas,em-uart: Document r9a09g011
> > > > bindings") in tty/tty-next.
> > > >
> > > > > --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > > > > +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
> > > > However, unlike EMEV2, RZ/V2M defines two clocks: pclk and sclk.
> > > > Hence please update the clocks section to reflect that.
> > > You are right that the uart has two clocks.
> > >
> > > Note though that pclk is shared by both uarts. The HW manual says:
> > > "ch. 1 is for use with the ISP support package, so do not
> > > use registers related to this channel.". Due to this, section
> > > 48.5.2.50 Clock ON/OFF Control Register 15 (CPG_CLK_ON15) says
> > > that bit 20, CLK4_ONWEN (enable for URT_PCLK) should be written
> > > as 0.
> > >
> > > I took this to mean that the URT_PCLK is enabled by the ISP firmware
> > > and software must not touch it. I am not sure if the DT bindings
> > > should document a clock that is specified as do not touch in the
> > > HW manual. This is a bit of a grey area.
> >
> > "DT describes hardware, not software policy".
> >
> > But I agree this is a grey area.
> I wish the HW manual either didn’t mention this clock that you should
> not touch, or didn’t specify anything as "used by the ISP firmware" :)

Yeah, hardware manuals making too many assumptions about the software
that will run on it will lead to headaches...

> > One option would be to mark URT_PCLK critical, so it won't be disabled.
> > But that would still mean it's enabled by Linux, i.e. Linux would set
> > CLK4_ONWEN to 1 while enabling the clock.
> >
> > Another option would be to create URT_PCLK as a non-gateable clock,
> > so Linux won't ever touch the register bits.
> >
> > Or just ignore URT_PCLK and do nothing, like you did ;-)
> > Would it be possible for a user to not use the ISP firmware at all,
> > and go full Linux, hence using both UART channels and URT_PCLK?
> It is possible to not use the ISP firmware, but them what do we do?
> Ignore everything in the HW manual that says "ISP firmware"?
>
> Ideally, we want to only enable a clock if it's not already enabled,
> but not turn it off if it is enabled. Isn't that a critical clk?

__clk_core_init() explicitly enables clocks marked with
CLK_IS_CRITICAL.  I think it does so without checking the hardware
if the clock is already enabled or not, so probably it will access
the reserved hardware bits regardless.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 05/13] serial: 8250: Make SERIAL_8250_EM available for arm64 systems

[Geert Uytterhoeven]

On Wed, Mar 30, 2022 at 5:41 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> This is needed for the Renesas RZ/V2M (r9a09g011) SoC.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds