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Date:   Thu, 14 Jul 2022 17:24:02 +0200
From:   Greg KH <gregkh@linuxfoundation.org>
To:     Shenwei Wang <shenwei.wang@nxp.com>
Cc:     "linux-serial@vger.kernel.org" <linux-serial@vger.kernel.org>
Subject: Re: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit
 in CS7 mode
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On Thu, Jul 14, 2022 at 03:11:35PM +0000, Shenwei Wang wrote:
> 
> 
> > -----Original Message-----
> > From: Greg KH <gregkh@linuxfoundation.org>
> > Sent: Thursday, July 14, 2022 9:31 AM
> > To: Shenwei Wang <shenwei.wang@nxp.com>
> > Cc: linux-serial@vger.kernel.org
> > Subject: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7
> > mode
> > 
> > Caution: EXT Email
> > 
> > On Fri, Jul 08, 2022 at 02:58:00PM -0500, shenwei.wang@nxp.com wrote:
> > > The LPUART hardware doesn't zero out the parity bit on the received
> > > characters. This behavior won't impact the use cases of CS8 because
> > > the parity bit is the 9th bit which is not currently used by software.
> > > But the parity bit for CS7 must be zeroed out by software in order to
> > > get the correct raw data.
> > >
> > > Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
> > 
> > What commit id does this fix?
> 
> The issue should have been there since the driver was written. As the CS7 mode was rarely used, we didn't notice the problem in the driver before.

So should this be backported to older stable kernels?

thanks,

greg k-h