* Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree
2024-07-03 14:55 ` [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree Yixun Lan
@ 2024-07-04 1:17 ` Jesse Taube
2024-07-04 11:39 ` Yixun Lan
2024-07-04 13:46 ` Jisheng Zhang
2024-07-05 5:55 ` 张猛
2 siblings, 1 reply; 33+ messages in thread
From: Jesse Taube @ 2024-07-04 1:17 UTC (permalink / raw)
To: Yixun Lan, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel,
Greg Kroah-Hartman, Jiri Slaby, Lubomir Rintel
Cc: devicetree, linux-kernel, Yangyu Chen, Inochi Amaoto,
linux-serial, linux-riscv, Meng Zhang
On 7/3/24 10:55, Yixun Lan wrote:
> From: Yangyu Chen <cyy@cyyself.name>
>
> Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
>
> Key features:
> - 4 cores per cluster, 2 clusters on chip
> - UART IP is Intel XScale UART
>
> Some key considerations:
> - ISA string is inferred from vendor documentation[2]
> - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> - No coherent DMA on this board
> Inferred by taking vendor ethernet and MMC drivers to the mainline
> kernel. Without dma-noncoherent in soc node, the driver fails.
> - No cache nodes now
> The parameters from vendor dts are likely to be wrong. It has 512
> sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> When the size of the cache line is 64B, it is a directly mapped
> cache rather than a set-associative cache, the latter is commonly
> used. Thus, I didn't use the parameters from vendor dts.
>
> Currently only support booting into console with only uart, other
> features will be added soon later.
>
> Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> Signed-off-by: Yixun Lan <dlan@gentoo.org>
> ---
> arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> 1 file changed, 376 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> new file mode 100644
> index 0000000000000..a076e35855a2e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -0,0 +1,376 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +/dts-v1/;
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + model = "SpacemiT K1";
> + compatible = "spacemit,k1";
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart2;
> + serial2 = &uart3;
> + serial3 = &uart4;
> + serial4 = &uart5;
> + serial5 = &uart6;
> + serial6 = &uart7;
> + serial7 = &uart8;
> + serial8 = &uart9;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <24000000>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu_0>;
> + };
> + core1 {
> + cpu = <&cpu_1>;
> + };
> + core2 {
> + cpu = <&cpu_2>;
> + };
> + core3 {
> + cpu = <&cpu_3>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu_4>;
> + };
> + core1 {
> + cpu = <&cpu_5>;
> + };
> + core2 {
> + cpu = <&cpu_6>;
> + };
> + core3 {
> + cpu = <&cpu_7>;
> + };
> + };
> + };
> +
> + cpu_0: cpu@0 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
Is there a reson not to add the I and D cache sizes.
i-cache-block-size = <64>;
i-cache-size = <32768>;
i-cache-sets = <512>;
d-cache-block-size = <64>;
d-cache-size = <32768>;
d-cache-sets = <512>;
next-level-cache = <&cluster0_l2_cache>;
......
cluster0_l2_cache: l2-cache0 {
compatible = "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-size = <524288>;
cache-sets = <1024>;
cache-unified;
};
> + mmu-type = "riscv,sv39";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_1: cpu@1 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <1>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu1_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_2: cpu@2 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <2>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu2_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_3: cpu@3 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <3>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu3_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_4: cpu@4 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <4>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu4_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_5: cpu@5 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <5>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu5_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_6: cpu@6 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <6>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu6_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_7: cpu@7 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <7>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu7_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-noncoherent;
> + ranges;
> +
> + uart0: serial@d4017000 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017000 0x0 0x100>;
> + interrupts = <42>;
interrupt-parent = <&plic>;
Thanks,
Jesse Taube
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart2: serial@d4017100 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017100 0x0 0x100>;
> + interrupts = <44>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart3: serial@d4017200 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017200 0x0 0x100>;
> + interrupts = <45>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart4: serial@d4017300 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017300 0x0 0x100>;
> + interrupts = <46>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart5: serial@d4017400 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017400 0x0 0x100>;
> + interrupts = <47>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart6: serial@d4017500 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017500 0x0 0x100>;
> + interrupts = <48>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart7: serial@d4017600 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017600 0x0 0x100>;
> + interrupts = <49>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart8: serial@d4017700 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017700 0x0 0x100>;
> + interrupts = <50>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart9: serial@d4017800 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017800 0x0 0x100>;
> + interrupts = <51>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + plic: interrupt-controller@e0000000 {
> + compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
> + reg = <0x0 0xe0000000 0x0 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
> + <&cpu1_intc 11>, <&cpu1_intc 9>,
> + <&cpu2_intc 11>, <&cpu2_intc 9>,
> + <&cpu3_intc 11>, <&cpu3_intc 9>,
> + <&cpu4_intc 11>, <&cpu4_intc 9>,
> + <&cpu5_intc 11>, <&cpu5_intc 9>,
> + <&cpu6_intc 11>, <&cpu6_intc 9>,
> + <&cpu7_intc 11>, <&cpu7_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + riscv,ndev = <159>;
> + };
> +
> + clint: timer@e4000000 {
> + compatible = "spacemit,k1-clint", "sifive,clint0";
> + reg = <0x0 0xe4000000 0x0 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> + <&cpu1_intc 3>, <&cpu1_intc 7>,
> + <&cpu2_intc 3>, <&cpu2_intc 7>,
> + <&cpu3_intc 3>, <&cpu3_intc 7>,
> + <&cpu4_intc 3>, <&cpu4_intc 7>,
> + <&cpu5_intc 3>, <&cpu5_intc 7>,
> + <&cpu6_intc 3>, <&cpu6_intc 7>,
> + <&cpu7_intc 3>, <&cpu7_intc 7>;
> + };
> + };
> +};
>
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree
2024-07-04 1:17 ` Jesse Taube
@ 2024-07-04 11:39 ` Yixun Lan
0 siblings, 0 replies; 33+ messages in thread
From: Yixun Lan @ 2024-07-04 11:39 UTC (permalink / raw)
To: Jesse Taube
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Daniel Lezcano,
Thomas Gleixner, Samuel Holland, Anup Patel, Greg Kroah-Hartman,
Jiri Slaby, Lubomir Rintel, devicetree, linux-kernel, Yangyu Chen,
Inochi Amaoto, linux-serial, linux-riscv, Meng Zhang
Hi Jesse
On 21:17 Wed 03 Jul , Jesse Taube wrote:
> On 7/3/24 10:55, Yixun Lan wrote:
> > From: Yangyu Chen <cyy@cyyself.name>
> >
> > Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> >
> > Key features:
> > - 4 cores per cluster, 2 clusters on chip
> > - UART IP is Intel XScale UART
> >
> > Some key considerations:
> > - ISA string is inferred from vendor documentation[2]
> > - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> > - No coherent DMA on this board
> > Inferred by taking vendor ethernet and MMC drivers to the mainline
> > kernel. Without dma-noncoherent in soc node, the driver fails.
> > - No cache nodes now
> > The parameters from vendor dts are likely to be wrong. It has 512
> > sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> > When the size of the cache line is 64B, it is a directly mapped
> > cache rather than a set-associative cache, the latter is commonly
> > used. Thus, I didn't use the parameters from vendor dts.
> >
> > Currently only support booting into console with only uart, other
> > features will be added soon later.
> >
> > Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> > Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> > Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > ---
> > arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 376 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > new file mode 100644
> > index 0000000000000..a076e35855a2e
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > @@ -0,0 +1,376 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> > + */
> > +
> > +/dts-v1/;
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + model = "SpacemiT K1";
> > + compatible = "spacemit,k1";
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + serial1 = &uart2;
> > + serial2 = &uart3;
> > + serial3 = &uart4;
> > + serial4 = &uart5;
> > + serial5 = &uart6;
> > + serial6 = &uart7;
> > + serial7 = &uart8;
> > + serial8 = &uart9;
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = <24000000>;
> > +
> > + cpu-map {
> > + cluster0 {
> > + core0 {
> > + cpu = <&cpu_0>;
> > + };
> > + core1 {
> > + cpu = <&cpu_1>;
> > + };
> > + core2 {
> > + cpu = <&cpu_2>;
> > + };
> > + core3 {
> > + cpu = <&cpu_3>;
> > + };
> > + };
> > +
> > + cluster1 {
> > + core0 {
> > + cpu = <&cpu_4>;
> > + };
> > + core1 {
> > + cpu = <&cpu_5>;
> > + };
> > + core2 {
> > + cpu = <&cpu_6>;
> > + };
> > + core3 {
> > + cpu = <&cpu_7>;
> > + };
> > + };
> > + };
> > +
> > + cpu_0: cpu@0 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <0>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
>
> Is there a reson not to add the I and D cache sizes.
No specific reason..
For "not adding those properties", I think it's largely due to Yangyu is kind of
skeptical about the info from vendor dts, and he do want to test/verify before
adding them..
so, did you test all these info, and confirm they are correct?
>
> i-cache-block-size = <64>;
> i-cache-size = <32768>;
> i-cache-sets = <512>;
> d-cache-block-size = <64>;
> d-cache-size = <32768>;
> d-cache-sets = <512>;
> next-level-cache = <&cluster0_l2_cache>;
> ......
>
> cluster0_l2_cache: l2-cache0 {
> compatible = "cache";
> cache-block-size = <64>;
> cache-level = <2>;
> cache-size = <524288>;
> cache-sets = <1024>;
> cache-unified;
> };
>
I think we probably have two options, 1) including this info in next version bump
2) leave it alone, and sending via another independent patch
I do not have strong preference, but do want to confirm before adding them.
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu0_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_1: cpu@1 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <1>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu1_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_2: cpu@2 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <2>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu2_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_3: cpu@3 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <3>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu3_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_4: cpu@4 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <4>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu4_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_5: cpu@5 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <5>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu5_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_6: cpu@6 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <6>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu6_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_7: cpu@7 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <7>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu7_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + };
> > +
> > + soc {
> > + compatible = "simple-bus";
> > + interrupt-parent = <&plic>;
we have interrrupt-parent info here
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + dma-noncoherent;
> > + ranges;
> > +
> > + uart0: serial@d4017000 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > + reg = <0x0 0xd4017000 0x0 0x100>;
> > + interrupts = <42>;
>
> interrupt-parent = <&plic>;
I think if we omit this info, then this node's interrupt parent property will
inherit from its device tree parent?
But I'm not sure if this is the right way to do from dt maintainer's
perspective? or should we specify interrupt-parent explicitly?
thanks for raising this question
>
> Thanks,
> Jesse Taube
>
> > + clock-frequency = <14857000>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart2: serial@d4017100 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > + reg = <0x0 0xd4017100 0x0 0x100>;
> > + interrupts = <44>;
> > + clock-frequency = <14857000>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart3: serial@d4017200 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > + reg = <0x0 0xd4017200 0x0 0x100>;
> > + interrupts = <45>;
> > + clock-frequency = <14857000>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart4: serial@d4017300 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > + reg = <0x0 0xd4017300 0x0 0x100>;
> > + interrupts = <46>;
> > + clock-frequency = <14857000>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart5: serial@d4017400 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > + reg = <0x0 0xd4017400 0x0 0x100>;
> > + interrupts = <47>;
> > + clock-frequency = <14857000>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart6: serial@d4017500 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > + reg = <0x0 0xd4017500 0x0 0x100>;
> > + interrupts = <48>;
> > + clock-frequency = <14857000>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart7: serial@d4017600 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > + reg = <0x0 0xd4017600 0x0 0x100>;
> > + interrupts = <49>;
> > + clock-frequency = <14857000>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart8: serial@d4017700 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > + reg = <0x0 0xd4017700 0x0 0x100>;
> > + interrupts = <50>;
> > + clock-frequency = <14857000>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart9: serial@d4017800 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > + reg = <0x0 0xd4017800 0x0 0x100>;
> > + interrupts = <51>;
> > + clock-frequency = <14857000>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + plic: interrupt-controller@e0000000 {
> > + compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
> > + reg = <0x0 0xe0000000 0x0 0x4000000>;
> > + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
> > + <&cpu1_intc 11>, <&cpu1_intc 9>,
> > + <&cpu2_intc 11>, <&cpu2_intc 9>,
> > + <&cpu3_intc 11>, <&cpu3_intc 9>,
> > + <&cpu4_intc 11>, <&cpu4_intc 9>,
> > + <&cpu5_intc 11>, <&cpu5_intc 9>,
> > + <&cpu6_intc 11>, <&cpu6_intc 9>,
> > + <&cpu7_intc 11>, <&cpu7_intc 9>;
> > + interrupt-controller;
> > + #address-cells = <0>;
> > + #interrupt-cells = <1>;
> > + riscv,ndev = <159>;
> > + };
> > +
> > + clint: timer@e4000000 {
> > + compatible = "spacemit,k1-clint", "sifive,clint0";
> > + reg = <0x0 0xe4000000 0x0 0x10000>;
> > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> > + <&cpu1_intc 3>, <&cpu1_intc 7>,
> > + <&cpu2_intc 3>, <&cpu2_intc 7>,
> > + <&cpu3_intc 3>, <&cpu3_intc 7>,
> > + <&cpu4_intc 3>, <&cpu4_intc 7>,
> > + <&cpu5_intc 3>, <&cpu5_intc 7>,
> > + <&cpu6_intc 3>, <&cpu6_intc 7>,
> > + <&cpu7_intc 3>, <&cpu7_intc 7>;
> > + };
> > + };
> > +};
> >
--
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree
2024-07-03 14:55 ` [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree Yixun Lan
2024-07-04 1:17 ` Jesse Taube
@ 2024-07-04 13:46 ` Jisheng Zhang
2024-07-04 14:18 ` Jisheng Zhang
2024-07-05 6:38 ` Yixun Lan
2024-07-05 5:55 ` 张猛
2 siblings, 2 replies; 33+ messages in thread
From: Jisheng Zhang @ 2024-07-04 13:46 UTC (permalink / raw)
To: Yixun Lan
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Daniel Lezcano,
Thomas Gleixner, Samuel Holland, Anup Patel, Greg Kroah-Hartman,
Jiri Slaby, Lubomir Rintel, devicetree, linux-kernel, Yangyu Chen,
Inochi Amaoto, linux-serial, linux-riscv, Meng Zhang
On Wed, Jul 03, 2024 at 02:55:11PM +0000, Yixun Lan wrote:
> From: Yangyu Chen <cyy@cyyself.name>
>
> Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
>
> Key features:
> - 4 cores per cluster, 2 clusters on chip
> - UART IP is Intel XScale UART
>
> Some key considerations:
> - ISA string is inferred from vendor documentation[2]
> - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> - No coherent DMA on this board
> Inferred by taking vendor ethernet and MMC drivers to the mainline
> kernel. Without dma-noncoherent in soc node, the driver fails.
> - No cache nodes now
> The parameters from vendor dts are likely to be wrong. It has 512
> sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> When the size of the cache line is 64B, it is a directly mapped
> cache rather than a set-associative cache, the latter is commonly
> used. Thus, I didn't use the parameters from vendor dts.
>
> Currently only support booting into console with only uart, other
> features will be added soon later.
>
> Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> Signed-off-by: Yixun Lan <dlan@gentoo.org>
> ---
> arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> 1 file changed, 376 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> new file mode 100644
> index 0000000000000..a076e35855a2e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -0,0 +1,376 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +/dts-v1/;
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + model = "SpacemiT K1";
> + compatible = "spacemit,k1";
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart2;
> + serial2 = &uart3;
> + serial3 = &uart4;
> + serial4 = &uart5;
> + serial5 = &uart6;
> + serial6 = &uart7;
> + serial7 = &uart8;
> + serial8 = &uart9;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <24000000>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu_0>;
> + };
> + core1 {
> + cpu = <&cpu_1>;
> + };
> + core2 {
> + cpu = <&cpu_2>;
> + };
> + core3 {
> + cpu = <&cpu_3>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu_4>;
> + };
> + core1 {
> + cpu = <&cpu_5>;
> + };
> + core2 {
> + cpu = <&cpu_6>;
> + };
> + core3 {
> + cpu = <&cpu_7>;
> + };
> + };
> + };
> +
> + cpu_0: cpu@0 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_1: cpu@1 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <1>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu1_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_2: cpu@2 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <2>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu2_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_3: cpu@3 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <3>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu3_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_4: cpu@4 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <4>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu4_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_5: cpu@5 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <5>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu5_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_6: cpu@6 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <6>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu6_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_7: cpu@7 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <7>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu7_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-noncoherent;
> + ranges;
> +
> + uart0: serial@d4017000 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
no, this is not a correct hw modeling. The doc on spacemit says
all the uart support 64 bytes FIFO, declaring xscale only makes
use of 32 bytes FIFO.
IIRC, 8250_pxa is a xscale uart with 64 bytes FIFO, so this should be
"mrvl,pxa-uart" or "mrvl,mmp-uart"
> + reg = <0x0 0xd4017000 0x0 0x100>;
> + interrupts = <42>;
> + clock-frequency = <14857000>;
once clk is ready, you will remove this property and add clk phandles,
so why not bring clk, pinctrl, reset before hand?
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart2: serial@d4017100 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017100 0x0 0x100>;
> + interrupts = <44>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart3: serial@d4017200 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017200 0x0 0x100>;
> + interrupts = <45>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart4: serial@d4017300 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017300 0x0 0x100>;
> + interrupts = <46>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart5: serial@d4017400 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017400 0x0 0x100>;
> + interrupts = <47>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart6: serial@d4017500 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017500 0x0 0x100>;
> + interrupts = <48>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart7: serial@d4017600 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017600 0x0 0x100>;
> + interrupts = <49>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart8: serial@d4017700 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017700 0x0 0x100>;
> + interrupts = <50>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart9: serial@d4017800 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017800 0x0 0x100>;
> + interrupts = <51>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + plic: interrupt-controller@e0000000 {
> + compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
> + reg = <0x0 0xe0000000 0x0 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
> + <&cpu1_intc 11>, <&cpu1_intc 9>,
> + <&cpu2_intc 11>, <&cpu2_intc 9>,
> + <&cpu3_intc 11>, <&cpu3_intc 9>,
> + <&cpu4_intc 11>, <&cpu4_intc 9>,
> + <&cpu5_intc 11>, <&cpu5_intc 9>,
> + <&cpu6_intc 11>, <&cpu6_intc 9>,
> + <&cpu7_intc 11>, <&cpu7_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + riscv,ndev = <159>;
> + };
> +
> + clint: timer@e4000000 {
> + compatible = "spacemit,k1-clint", "sifive,clint0";
> + reg = <0x0 0xe4000000 0x0 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> + <&cpu1_intc 3>, <&cpu1_intc 7>,
> + <&cpu2_intc 3>, <&cpu2_intc 7>,
> + <&cpu3_intc 3>, <&cpu3_intc 7>,
> + <&cpu4_intc 3>, <&cpu4_intc 7>,
> + <&cpu5_intc 3>, <&cpu5_intc 7>,
> + <&cpu6_intc 3>, <&cpu6_intc 7>,
> + <&cpu7_intc 3>, <&cpu7_intc 7>;
> + };
> + };
> +};
>
> --
> 2.45.2
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree
2024-07-04 13:46 ` Jisheng Zhang
@ 2024-07-04 14:18 ` Jisheng Zhang
2024-07-05 6:38 ` Yixun Lan
1 sibling, 0 replies; 33+ messages in thread
From: Jisheng Zhang @ 2024-07-04 14:18 UTC (permalink / raw)
To: Yixun Lan
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Daniel Lezcano,
Thomas Gleixner, Samuel Holland, Anup Patel, Greg Kroah-Hartman,
Jiri Slaby, Lubomir Rintel, devicetree, linux-kernel, Yangyu Chen,
Inochi Amaoto, linux-serial, linux-riscv, Meng Zhang
On Thu, Jul 04, 2024 at 09:48:01PM +0800, Jisheng Zhang wrote:
> On Wed, Jul 03, 2024 at 02:55:11PM +0000, Yixun Lan wrote:
> > From: Yangyu Chen <cyy@cyyself.name>
> >
> > Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> >
> > Key features:
> > - 4 cores per cluster, 2 clusters on chip
> > - UART IP is Intel XScale UART
> >
> > Some key considerations:
> > - ISA string is inferred from vendor documentation[2]
> > - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> > - No coherent DMA on this board
> > Inferred by taking vendor ethernet and MMC drivers to the mainline
> > kernel. Without dma-noncoherent in soc node, the driver fails.
> > - No cache nodes now
> > The parameters from vendor dts are likely to be wrong. It has 512
> > sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> > When the size of the cache line is 64B, it is a directly mapped
> > cache rather than a set-associative cache, the latter is commonly
> > used. Thus, I didn't use the parameters from vendor dts.
> >
> > Currently only support booting into console with only uart, other
> > features will be added soon later.
> >
> > Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> > Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> > Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > ---
> > arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 376 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > new file mode 100644
> > index 0000000000000..a076e35855a2e
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > @@ -0,0 +1,376 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> > + */
> > +
> > +/dts-v1/;
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + model = "SpacemiT K1";
> > + compatible = "spacemit,k1";
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + serial1 = &uart2;
> > + serial2 = &uart3;
> > + serial3 = &uart4;
> > + serial4 = &uart5;
> > + serial5 = &uart6;
> > + serial6 = &uart7;
> > + serial7 = &uart8;
> > + serial8 = &uart9;
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = <24000000>;
> > +
> > + cpu-map {
> > + cluster0 {
> > + core0 {
> > + cpu = <&cpu_0>;
> > + };
> > + core1 {
> > + cpu = <&cpu_1>;
> > + };
> > + core2 {
> > + cpu = <&cpu_2>;
> > + };
> > + core3 {
> > + cpu = <&cpu_3>;
> > + };
> > + };
> > +
> > + cluster1 {
> > + core0 {
> > + cpu = <&cpu_4>;
> > + };
> > + core1 {
> > + cpu = <&cpu_5>;
> > + };
> > + core2 {
> > + cpu = <&cpu_6>;
> > + };
> > + core3 {
> > + cpu = <&cpu_7>;
> > + };
> > + };
> > + };
> > +
> > + cpu_0: cpu@0 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <0>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu0_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_1: cpu@1 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <1>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu1_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_2: cpu@2 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <2>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu2_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_3: cpu@3 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <3>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu3_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_4: cpu@4 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <4>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu4_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_5: cpu@5 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <5>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu5_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_6: cpu@6 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <6>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu6_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_7: cpu@7 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <7>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu7_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + };
> > +
> > + soc {
> > + compatible = "simple-bus";
> > + interrupt-parent = <&plic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + dma-noncoherent;
> > + ranges;
> > +
> > + uart0: serial@d4017000 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
>
> no, this is not a correct hw modeling.
Vendor's linux kernel source code also clearly indicates the FIFO size
is 64B.
>
> IIRC, 8250_pxa is a xscale uart with 64 bytes FIFO, so this should be
> "mrvl,pxa-uart" or "mrvl,mmp-uart"
>
> > + reg = <0x0 0xd4017000 0x0 0x100>;
> > + interrupts = <42>;
> > + clock-frequency = <14857000>;
>
> once clk is ready, you will remove this property and add clk phandles,
> so why not bring clk, pinctrl, reset before hand?
>
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree
2024-07-04 13:46 ` Jisheng Zhang
2024-07-04 14:18 ` Jisheng Zhang
@ 2024-07-05 6:38 ` Yixun Lan
2024-07-06 4:12 ` Jisheng Zhang
1 sibling, 1 reply; 33+ messages in thread
From: Yixun Lan @ 2024-07-05 6:38 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Daniel Lezcano,
Thomas Gleixner, Samuel Holland, Anup Patel, Greg Kroah-Hartman,
Jiri Slaby, Lubomir Rintel, devicetree, linux-kernel, Yangyu Chen,
Inochi Amaoto, linux-serial, linux-riscv, Meng Zhang
On 21:46 Thu 04 Jul , Jisheng Zhang wrote:
> On Wed, Jul 03, 2024 at 02:55:11PM +0000, Yixun Lan wrote:
> > From: Yangyu Chen <cyy@cyyself.name>
> >
> > Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> >
> > Key features:
> > - 4 cores per cluster, 2 clusters on chip
> > - UART IP is Intel XScale UART
> >
> > Some key considerations:
> > - ISA string is inferred from vendor documentation[2]
> > - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> > - No coherent DMA on this board
> > Inferred by taking vendor ethernet and MMC drivers to the mainline
> > kernel. Without dma-noncoherent in soc node, the driver fails.
> > - No cache nodes now
> > The parameters from vendor dts are likely to be wrong. It has 512
> > sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> > When the size of the cache line is 64B, it is a directly mapped
> > cache rather than a set-associative cache, the latter is commonly
> > used. Thus, I didn't use the parameters from vendor dts.
> >
> > Currently only support booting into console with only uart, other
> > features will be added soon later.
> >
> > Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> > Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> > Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > ---
> > arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 376 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > new file mode 100644
> > index 0000000000000..a076e35855a2e
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > @@ -0,0 +1,376 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> > + */
> > +
> > +/dts-v1/;
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + model = "SpacemiT K1";
> > + compatible = "spacemit,k1";
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + serial1 = &uart2;
> > + serial2 = &uart3;
> > + serial3 = &uart4;
> > + serial4 = &uart5;
> > + serial5 = &uart6;
> > + serial6 = &uart7;
> > + serial7 = &uart8;
> > + serial8 = &uart9;
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = <24000000>;
> > +
> > + cpu-map {
> > + cluster0 {
> > + core0 {
> > + cpu = <&cpu_0>;
> > + };
> > + core1 {
> > + cpu = <&cpu_1>;
> > + };
> > + core2 {
> > + cpu = <&cpu_2>;
> > + };
> > + core3 {
> > + cpu = <&cpu_3>;
> > + };
> > + };
> > +
> > + cluster1 {
> > + core0 {
> > + cpu = <&cpu_4>;
> > + };
> > + core1 {
> > + cpu = <&cpu_5>;
> > + };
> > + core2 {
> > + cpu = <&cpu_6>;
> > + };
> > + core3 {
> > + cpu = <&cpu_7>;
> > + };
> > + };
> > + };
> > +
> > + cpu_0: cpu@0 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <0>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu0_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_1: cpu@1 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <1>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu1_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_2: cpu@2 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <2>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu2_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_3: cpu@3 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <3>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu3_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_4: cpu@4 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <4>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu4_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_5: cpu@5 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <5>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu5_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_6: cpu@6 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <6>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu6_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + cpu_7: cpu@7 {
> > + compatible = "spacemit,x60", "riscv";
> > + device_type = "cpu";
> > + reg = <7>;
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > + riscv,cbom-block-size = <64>;
> > + riscv,cbop-block-size = <64>;
> > + riscv,cboz-block-size = <64>;
> > + mmu-type = "riscv,sv39";
> > +
> > + cpu7_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > +
> > + };
> > +
> > + soc {
> > + compatible = "simple-bus";
> > + interrupt-parent = <&plic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + dma-noncoherent;
> > + ranges;
> > +
> > + uart0: serial@d4017000 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
>
> no, this is not a correct hw modeling. The doc on spacemit says
> all the uart support 64 bytes FIFO, declaring xscale only makes
> use of 32 bytes FIFO.
yes, I also noticed it's 64 bytes FIFO
>
> IIRC, 8250_pxa is a xscale uart with 64 bytes FIFO, so this should be
> "mrvl,pxa-uart" or "mrvl,mmp-uart"
for mrvl,pxa-uart, I think you imply to use drivers/tty/serial/8250/8250_pxa.c,
which turn out doesn't work on k1 SoC, for the record, we need to adjust
drivers/tty/serial/8250/Kconfig to enable the driver for ARCH_SPACEMIT,
and change uart compatible to "spacemit,k1-uart", "mrvl,pxa-uart"
for mrvl,mmp-uart, I see two choices, one using 8250_pxa.c which has same result
as mrvl,pxa-uart, another choice would using the driver of 8250_of.c
and it work as same as "intel,xscale-uart", I don't see any difference..
P.S: there is possibly a side problem that "mrvl,mmp-uart" from 8250_of.c doesn't
really compatile with "mrvl,mmp-uart" from 8250_pxa.c, but I think it's another story
>
> > + reg = <0x0 0xd4017000 0x0 0x100>;
> > + interrupts = <42>;
> > + clock-frequency = <14857000>;
>
> once clk is ready, you will remove this property and add clk phandles,
yes, this is exactly the plan
> so why not bring clk, pinctrl, reset before hand?
>
No, we want to have an initial minimal working environment with initramfs + console,
and start from there to work with clk, pinctrl, reset, it will help us to debug and
work in parallel
Note, I have no objection, if maintainer consider to merge this patch series on condition that
clk, pinctrl, reset are also ready..
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart2: serial@d4017100 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > + reg = <0x0 0xd4017100 0x0 0x100>;
> > + interrupts = <44>;
> > + clock-frequency = <14857000>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart3: serial@d4017200 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > + reg = <0x0 0xd4017200 0x0 0x100>;
> > + interrupts = <45>;
> > + clock-frequency = <14857000>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart4: serial@d4017300 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > + reg = <0x0 0xd4017300 0x0 0x100>;
> > + interrupts = <46>;
> > + clock-frequency = <14857000>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart5: serial@d4017400 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > + reg = <0x0 0xd4017400 0x0 0x100>;
> > + interrupts = <47>;
> > + clock-frequency = <14857000>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart6: serial@d4017500 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > + reg = <0x0 0xd4017500 0x0 0x100>;
> > + interrupts = <48>;
> > + clock-frequency = <14857000>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart7: serial@d4017600 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > + reg = <0x0 0xd4017600 0x0 0x100>;
> > + interrupts = <49>;
> > + clock-frequency = <14857000>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart8: serial@d4017700 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > + reg = <0x0 0xd4017700 0x0 0x100>;
> > + interrupts = <50>;
> > + clock-frequency = <14857000>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart9: serial@d4017800 {
> > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > + reg = <0x0 0xd4017800 0x0 0x100>;
> > + interrupts = <51>;
> > + clock-frequency = <14857000>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + plic: interrupt-controller@e0000000 {
> > + compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
> > + reg = <0x0 0xe0000000 0x0 0x4000000>;
> > + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
> > + <&cpu1_intc 11>, <&cpu1_intc 9>,
> > + <&cpu2_intc 11>, <&cpu2_intc 9>,
> > + <&cpu3_intc 11>, <&cpu3_intc 9>,
> > + <&cpu4_intc 11>, <&cpu4_intc 9>,
> > + <&cpu5_intc 11>, <&cpu5_intc 9>,
> > + <&cpu6_intc 11>, <&cpu6_intc 9>,
> > + <&cpu7_intc 11>, <&cpu7_intc 9>;
> > + interrupt-controller;
> > + #address-cells = <0>;
> > + #interrupt-cells = <1>;
> > + riscv,ndev = <159>;
> > + };
> > +
> > + clint: timer@e4000000 {
> > + compatible = "spacemit,k1-clint", "sifive,clint0";
> > + reg = <0x0 0xe4000000 0x0 0x10000>;
> > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> > + <&cpu1_intc 3>, <&cpu1_intc 7>,
> > + <&cpu2_intc 3>, <&cpu2_intc 7>,
> > + <&cpu3_intc 3>, <&cpu3_intc 7>,
> > + <&cpu4_intc 3>, <&cpu4_intc 7>,
> > + <&cpu5_intc 3>, <&cpu5_intc 7>,
> > + <&cpu6_intc 3>, <&cpu6_intc 7>,
> > + <&cpu7_intc 3>, <&cpu7_intc 7>;
> > + };
> > + };
> > +};
> >
> > --
> > 2.45.2
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
--
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree
2024-07-05 6:38 ` Yixun Lan
@ 2024-07-06 4:12 ` Jisheng Zhang
2024-07-06 5:05 ` Yixun Lan
0 siblings, 1 reply; 33+ messages in thread
From: Jisheng Zhang @ 2024-07-06 4:12 UTC (permalink / raw)
To: Yixun Lan
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Daniel Lezcano,
Thomas Gleixner, Samuel Holland, Anup Patel, Greg Kroah-Hartman,
Jiri Slaby, Lubomir Rintel, devicetree, linux-kernel, Yangyu Chen,
Inochi Amaoto, linux-serial, linux-riscv, Meng Zhang
On Fri, Jul 05, 2024 at 06:38:39AM +0000, Yixun Lan wrote:
>
> On 21:46 Thu 04 Jul , Jisheng Zhang wrote:
> > On Wed, Jul 03, 2024 at 02:55:11PM +0000, Yixun Lan wrote:
> > > From: Yangyu Chen <cyy@cyyself.name>
> > >
> > > Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> > >
> > > Key features:
> > > - 4 cores per cluster, 2 clusters on chip
> > > - UART IP is Intel XScale UART
> > >
> > > Some key considerations:
> > > - ISA string is inferred from vendor documentation[2]
> > > - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> > > - No coherent DMA on this board
> > > Inferred by taking vendor ethernet and MMC drivers to the mainline
> > > kernel. Without dma-noncoherent in soc node, the driver fails.
> > > - No cache nodes now
> > > The parameters from vendor dts are likely to be wrong. It has 512
> > > sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> > > When the size of the cache line is 64B, it is a directly mapped
> > > cache rather than a set-associative cache, the latter is commonly
> > > used. Thus, I didn't use the parameters from vendor dts.
> > >
> > > Currently only support booting into console with only uart, other
> > > features will be added soon later.
> > >
> > > Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> > > Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> > > Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> > > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> > > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > > ---
> > > arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> > > 1 file changed, 376 insertions(+)
> > >
> > > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > new file mode 100644
> > > index 0000000000000..a076e35855a2e
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > @@ -0,0 +1,376 @@
> > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > +/*
> > > + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> > > + */
> > > +
> > > +/dts-v1/;
> > > +/ {
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > + model = "SpacemiT K1";
> > > + compatible = "spacemit,k1";
> > > +
> > > + aliases {
> > > + serial0 = &uart0;
> > > + serial1 = &uart2;
> > > + serial2 = &uart3;
> > > + serial3 = &uart4;
> > > + serial4 = &uart5;
> > > + serial5 = &uart6;
> > > + serial6 = &uart7;
> > > + serial7 = &uart8;
> > > + serial8 = &uart9;
> > > + };
> > > +
> > > + cpus {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + timebase-frequency = <24000000>;
> > > +
> > > + cpu-map {
> > > + cluster0 {
> > > + core0 {
> > > + cpu = <&cpu_0>;
> > > + };
> > > + core1 {
> > > + cpu = <&cpu_1>;
> > > + };
> > > + core2 {
> > > + cpu = <&cpu_2>;
> > > + };
> > > + core3 {
> > > + cpu = <&cpu_3>;
> > > + };
> > > + };
> > > +
> > > + cluster1 {
> > > + core0 {
> > > + cpu = <&cpu_4>;
> > > + };
> > > + core1 {
> > > + cpu = <&cpu_5>;
> > > + };
> > > + core2 {
> > > + cpu = <&cpu_6>;
> > > + };
> > > + core3 {
> > > + cpu = <&cpu_7>;
> > > + };
> > > + };
> > > + };
> > > +
> > > + cpu_0: cpu@0 {
> > > + compatible = "spacemit,x60", "riscv";
> > > + device_type = "cpu";
> > > + reg = <0>;
> > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > + riscv,isa-base = "rv64i";
> > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > + riscv,cbom-block-size = <64>;
> > > + riscv,cbop-block-size = <64>;
> > > + riscv,cboz-block-size = <64>;
> > > + mmu-type = "riscv,sv39";
> > > +
> > > + cpu0_intc: interrupt-controller {
> > > + compatible = "riscv,cpu-intc";
> > > + interrupt-controller;
> > > + #interrupt-cells = <1>;
> > > + };
> > > + };
> > > +
> > > + cpu_1: cpu@1 {
> > > + compatible = "spacemit,x60", "riscv";
> > > + device_type = "cpu";
> > > + reg = <1>;
> > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > + riscv,isa-base = "rv64i";
> > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > + riscv,cbom-block-size = <64>;
> > > + riscv,cbop-block-size = <64>;
> > > + riscv,cboz-block-size = <64>;
> > > + mmu-type = "riscv,sv39";
> > > +
> > > + cpu1_intc: interrupt-controller {
> > > + compatible = "riscv,cpu-intc";
> > > + interrupt-controller;
> > > + #interrupt-cells = <1>;
> > > + };
> > > + };
> > > +
> > > + cpu_2: cpu@2 {
> > > + compatible = "spacemit,x60", "riscv";
> > > + device_type = "cpu";
> > > + reg = <2>;
> > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > + riscv,isa-base = "rv64i";
> > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > + riscv,cbom-block-size = <64>;
> > > + riscv,cbop-block-size = <64>;
> > > + riscv,cboz-block-size = <64>;
> > > + mmu-type = "riscv,sv39";
> > > +
> > > + cpu2_intc: interrupt-controller {
> > > + compatible = "riscv,cpu-intc";
> > > + interrupt-controller;
> > > + #interrupt-cells = <1>;
> > > + };
> > > + };
> > > +
> > > + cpu_3: cpu@3 {
> > > + compatible = "spacemit,x60", "riscv";
> > > + device_type = "cpu";
> > > + reg = <3>;
> > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > + riscv,isa-base = "rv64i";
> > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > + riscv,cbom-block-size = <64>;
> > > + riscv,cbop-block-size = <64>;
> > > + riscv,cboz-block-size = <64>;
> > > + mmu-type = "riscv,sv39";
> > > +
> > > + cpu3_intc: interrupt-controller {
> > > + compatible = "riscv,cpu-intc";
> > > + interrupt-controller;
> > > + #interrupt-cells = <1>;
> > > + };
> > > + };
> > > +
> > > + cpu_4: cpu@4 {
> > > + compatible = "spacemit,x60", "riscv";
> > > + device_type = "cpu";
> > > + reg = <4>;
> > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > + riscv,isa-base = "rv64i";
> > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > + riscv,cbom-block-size = <64>;
> > > + riscv,cbop-block-size = <64>;
> > > + riscv,cboz-block-size = <64>;
> > > + mmu-type = "riscv,sv39";
> > > +
> > > + cpu4_intc: interrupt-controller {
> > > + compatible = "riscv,cpu-intc";
> > > + interrupt-controller;
> > > + #interrupt-cells = <1>;
> > > + };
> > > + };
> > > +
> > > + cpu_5: cpu@5 {
> > > + compatible = "spacemit,x60", "riscv";
> > > + device_type = "cpu";
> > > + reg = <5>;
> > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > + riscv,isa-base = "rv64i";
> > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > + riscv,cbom-block-size = <64>;
> > > + riscv,cbop-block-size = <64>;
> > > + riscv,cboz-block-size = <64>;
> > > + mmu-type = "riscv,sv39";
> > > +
> > > + cpu5_intc: interrupt-controller {
> > > + compatible = "riscv,cpu-intc";
> > > + interrupt-controller;
> > > + #interrupt-cells = <1>;
> > > + };
> > > + };
> > > +
> > > + cpu_6: cpu@6 {
> > > + compatible = "spacemit,x60", "riscv";
> > > + device_type = "cpu";
> > > + reg = <6>;
> > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > + riscv,isa-base = "rv64i";
> > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > + riscv,cbom-block-size = <64>;
> > > + riscv,cbop-block-size = <64>;
> > > + riscv,cboz-block-size = <64>;
> > > + mmu-type = "riscv,sv39";
> > > +
> > > + cpu6_intc: interrupt-controller {
> > > + compatible = "riscv,cpu-intc";
> > > + interrupt-controller;
> > > + #interrupt-cells = <1>;
> > > + };
> > > + };
> > > +
> > > + cpu_7: cpu@7 {
> > > + compatible = "spacemit,x60", "riscv";
> > > + device_type = "cpu";
> > > + reg = <7>;
> > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > + riscv,isa-base = "rv64i";
> > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > + riscv,cbom-block-size = <64>;
> > > + riscv,cbop-block-size = <64>;
> > > + riscv,cboz-block-size = <64>;
> > > + mmu-type = "riscv,sv39";
> > > +
> > > + cpu7_intc: interrupt-controller {
> > > + compatible = "riscv,cpu-intc";
> > > + interrupt-controller;
> > > + #interrupt-cells = <1>;
> > > + };
> > > + };
> > > +
> > > + };
> > > +
> > > + soc {
> > > + compatible = "simple-bus";
> > > + interrupt-parent = <&plic>;
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > + dma-noncoherent;
> > > + ranges;
> > > +
> > > + uart0: serial@d4017000 {
> > > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> >
> > no, this is not a correct hw modeling. The doc on spacemit says
> > all the uart support 64 bytes FIFO, declaring xscale only makes
> > use of 32 bytes FIFO.
> yes, I also noticed it's 64 bytes FIFO
>
> >
> > IIRC, 8250_pxa is a xscale uart with 64 bytes FIFO, so this should be
> > "mrvl,pxa-uart" or "mrvl,mmp-uart"
>
>
> for mrvl,pxa-uart, I think you imply to use drivers/tty/serial/8250/8250_pxa.c,
> which turn out doesn't work on k1 SoC, for the record, we need to adjust
Really? I just tried "mrvl,pxa-uart" with rc6, it works perfectly, and the FIFO
in the driver logic is 64bytes now. Am I misssing something or you never tried it?
> drivers/tty/serial/8250/Kconfig to enable the driver for ARCH_SPACEMIT,
> and change uart compatible to "spacemit,k1-uart", "mrvl,pxa-uart"
>
> for mrvl,mmp-uart, I see two choices, one using 8250_pxa.c which has same result
> as mrvl,pxa-uart, another choice would using the driver of 8250_of.c
> and it work as same as "intel,xscale-uart", I don't see any difference..
>
> P.S: there is possibly a side problem that "mrvl,mmp-uart" from 8250_of.c doesn't
> really compatile with "mrvl,mmp-uart" from 8250_pxa.c, but I think it's another story
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree
2024-07-06 4:12 ` Jisheng Zhang
@ 2024-07-06 5:05 ` Yixun Lan
2024-07-06 10:40 ` Jisheng Zhang
0 siblings, 1 reply; 33+ messages in thread
From: Yixun Lan @ 2024-07-06 5:05 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Daniel Lezcano,
Thomas Gleixner, Samuel Holland, Anup Patel, Greg Kroah-Hartman,
Jiri Slaby, Lubomir Rintel, devicetree, linux-kernel, Yangyu Chen,
Inochi Amaoto, linux-serial, linux-riscv, Meng Zhang
On 12:12 Sat 06 Jul , Jisheng Zhang wrote:
> On Fri, Jul 05, 2024 at 06:38:39AM +0000, Yixun Lan wrote:
> >
> > On 21:46 Thu 04 Jul , Jisheng Zhang wrote:
> > > On Wed, Jul 03, 2024 at 02:55:11PM +0000, Yixun Lan wrote:
> > > > From: Yangyu Chen <cyy@cyyself.name>
> > > >
> > > > Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> > > >
> > > > Key features:
> > > > - 4 cores per cluster, 2 clusters on chip
> > > > - UART IP is Intel XScale UART
> > > >
> > > > Some key considerations:
> > > > - ISA string is inferred from vendor documentation[2]
> > > > - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> > > > - No coherent DMA on this board
> > > > Inferred by taking vendor ethernet and MMC drivers to the mainline
> > > > kernel. Without dma-noncoherent in soc node, the driver fails.
> > > > - No cache nodes now
> > > > The parameters from vendor dts are likely to be wrong. It has 512
> > > > sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> > > > When the size of the cache line is 64B, it is a directly mapped
> > > > cache rather than a set-associative cache, the latter is commonly
> > > > used. Thus, I didn't use the parameters from vendor dts.
> > > >
> > > > Currently only support booting into console with only uart, other
> > > > features will be added soon later.
> > > >
> > > > Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> > > > Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> > > > Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> > > > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> > > > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > > > ---
> > > > arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> > > > 1 file changed, 376 insertions(+)
> > > >
> > > > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > > new file mode 100644
> > > > index 0000000000000..a076e35855a2e
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > > @@ -0,0 +1,376 @@
> > > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > > +/*
> > > > + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> > > > + */
> > > > +
> > > > +/dts-v1/;
> > > > +/ {
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > + model = "SpacemiT K1";
> > > > + compatible = "spacemit,k1";
> > > > +
> > > > + aliases {
> > > > + serial0 = &uart0;
> > > > + serial1 = &uart2;
> > > > + serial2 = &uart3;
> > > > + serial3 = &uart4;
> > > > + serial4 = &uart5;
> > > > + serial5 = &uart6;
> > > > + serial6 = &uart7;
> > > > + serial7 = &uart8;
> > > > + serial8 = &uart9;
> > > > + };
> > > > +
> > > > + cpus {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + timebase-frequency = <24000000>;
> > > > +
> > > > + cpu-map {
> > > > + cluster0 {
> > > > + core0 {
> > > > + cpu = <&cpu_0>;
> > > > + };
> > > > + core1 {
> > > > + cpu = <&cpu_1>;
> > > > + };
> > > > + core2 {
> > > > + cpu = <&cpu_2>;
> > > > + };
> > > > + core3 {
> > > > + cpu = <&cpu_3>;
> > > > + };
> > > > + };
> > > > +
> > > > + cluster1 {
> > > > + core0 {
> > > > + cpu = <&cpu_4>;
> > > > + };
> > > > + core1 {
> > > > + cpu = <&cpu_5>;
> > > > + };
> > > > + core2 {
> > > > + cpu = <&cpu_6>;
> > > > + };
> > > > + core3 {
> > > > + cpu = <&cpu_7>;
> > > > + };
> > > > + };
> > > > + };
> > > > +
> > > > + cpu_0: cpu@0 {
> > > > + compatible = "spacemit,x60", "riscv";
> > > > + device_type = "cpu";
> > > > + reg = <0>;
> > > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > > + riscv,isa-base = "rv64i";
> > > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > > + riscv,cbom-block-size = <64>;
> > > > + riscv,cbop-block-size = <64>;
> > > > + riscv,cboz-block-size = <64>;
> > > > + mmu-type = "riscv,sv39";
> > > > +
> > > > + cpu0_intc: interrupt-controller {
> > > > + compatible = "riscv,cpu-intc";
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <1>;
> > > > + };
> > > > + };
> > > > +
> > > > + cpu_1: cpu@1 {
> > > > + compatible = "spacemit,x60", "riscv";
> > > > + device_type = "cpu";
> > > > + reg = <1>;
> > > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > > + riscv,isa-base = "rv64i";
> > > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > > + riscv,cbom-block-size = <64>;
> > > > + riscv,cbop-block-size = <64>;
> > > > + riscv,cboz-block-size = <64>;
> > > > + mmu-type = "riscv,sv39";
> > > > +
> > > > + cpu1_intc: interrupt-controller {
> > > > + compatible = "riscv,cpu-intc";
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <1>;
> > > > + };
> > > > + };
> > > > +
> > > > + cpu_2: cpu@2 {
> > > > + compatible = "spacemit,x60", "riscv";
> > > > + device_type = "cpu";
> > > > + reg = <2>;
> > > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > > + riscv,isa-base = "rv64i";
> > > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > > + riscv,cbom-block-size = <64>;
> > > > + riscv,cbop-block-size = <64>;
> > > > + riscv,cboz-block-size = <64>;
> > > > + mmu-type = "riscv,sv39";
> > > > +
> > > > + cpu2_intc: interrupt-controller {
> > > > + compatible = "riscv,cpu-intc";
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <1>;
> > > > + };
> > > > + };
> > > > +
> > > > + cpu_3: cpu@3 {
> > > > + compatible = "spacemit,x60", "riscv";
> > > > + device_type = "cpu";
> > > > + reg = <3>;
> > > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > > + riscv,isa-base = "rv64i";
> > > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > > + riscv,cbom-block-size = <64>;
> > > > + riscv,cbop-block-size = <64>;
> > > > + riscv,cboz-block-size = <64>;
> > > > + mmu-type = "riscv,sv39";
> > > > +
> > > > + cpu3_intc: interrupt-controller {
> > > > + compatible = "riscv,cpu-intc";
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <1>;
> > > > + };
> > > > + };
> > > > +
> > > > + cpu_4: cpu@4 {
> > > > + compatible = "spacemit,x60", "riscv";
> > > > + device_type = "cpu";
> > > > + reg = <4>;
> > > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > > + riscv,isa-base = "rv64i";
> > > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > > + riscv,cbom-block-size = <64>;
> > > > + riscv,cbop-block-size = <64>;
> > > > + riscv,cboz-block-size = <64>;
> > > > + mmu-type = "riscv,sv39";
> > > > +
> > > > + cpu4_intc: interrupt-controller {
> > > > + compatible = "riscv,cpu-intc";
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <1>;
> > > > + };
> > > > + };
> > > > +
> > > > + cpu_5: cpu@5 {
> > > > + compatible = "spacemit,x60", "riscv";
> > > > + device_type = "cpu";
> > > > + reg = <5>;
> > > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > > + riscv,isa-base = "rv64i";
> > > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > > + riscv,cbom-block-size = <64>;
> > > > + riscv,cbop-block-size = <64>;
> > > > + riscv,cboz-block-size = <64>;
> > > > + mmu-type = "riscv,sv39";
> > > > +
> > > > + cpu5_intc: interrupt-controller {
> > > > + compatible = "riscv,cpu-intc";
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <1>;
> > > > + };
> > > > + };
> > > > +
> > > > + cpu_6: cpu@6 {
> > > > + compatible = "spacemit,x60", "riscv";
> > > > + device_type = "cpu";
> > > > + reg = <6>;
> > > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > > + riscv,isa-base = "rv64i";
> > > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > > + riscv,cbom-block-size = <64>;
> > > > + riscv,cbop-block-size = <64>;
> > > > + riscv,cboz-block-size = <64>;
> > > > + mmu-type = "riscv,sv39";
> > > > +
> > > > + cpu6_intc: interrupt-controller {
> > > > + compatible = "riscv,cpu-intc";
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <1>;
> > > > + };
> > > > + };
> > > > +
> > > > + cpu_7: cpu@7 {
> > > > + compatible = "spacemit,x60", "riscv";
> > > > + device_type = "cpu";
> > > > + reg = <7>;
> > > > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> > > > + riscv,isa-base = "rv64i";
> > > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> > > > + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> > > > + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> > > > + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> > > > + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> > > > + riscv,cbom-block-size = <64>;
> > > > + riscv,cbop-block-size = <64>;
> > > > + riscv,cboz-block-size = <64>;
> > > > + mmu-type = "riscv,sv39";
> > > > +
> > > > + cpu7_intc: interrupt-controller {
> > > > + compatible = "riscv,cpu-intc";
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <1>;
> > > > + };
> > > > + };
> > > > +
> > > > + };
> > > > +
> > > > + soc {
> > > > + compatible = "simple-bus";
> > > > + interrupt-parent = <&plic>;
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > + dma-noncoherent;
> > > > + ranges;
> > > > +
> > > > + uart0: serial@d4017000 {
> > > > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > >
> > > no, this is not a correct hw modeling. The doc on spacemit says
> > > all the uart support 64 bytes FIFO, declaring xscale only makes
> > > use of 32 bytes FIFO.
> > yes, I also noticed it's 64 bytes FIFO
> >
> > >
> > > IIRC, 8250_pxa is a xscale uart with 64 bytes FIFO, so this should be
> > > "mrvl,pxa-uart" or "mrvl,mmp-uart"
> >
> >
> > for mrvl,pxa-uart, I think you imply to use drivers/tty/serial/8250/8250_pxa.c,
> > which turn out doesn't work on k1 SoC, for the record, we need to adjust
>
> Really? I just tried "mrvl,pxa-uart" with rc6, it works perfectly, and the FIFO
> in the driver logic is 64bytes now. Am I misssing something or you never tried it?
>
Ok, I realised it's the clock issue
still, I'm not fully convinced about using "mrvl,pxa-uart",
e.g this driver hardcoded tz_loadsz to 32, not sure if K1 suffer same problem
5208e7ced520 ("serial: 8250_pxa: Configure tx_loadsz to match FIFO IRQ level")
also, what's the preference when choosing driver between 8250_pxa.c vs 8250_of.c?
it occur to me that 8250_pxa.c is more specially tailored for pxa hardware, while
8250_of.c is more generic.. besides, should we consider one more step if we want to
support DMA mode in the future (vendor uart driver has DMA support)?
> > drivers/tty/serial/8250/Kconfig to enable the driver for ARCH_SPACEMIT,
> > and change uart compatible to "spacemit,k1-uart", "mrvl,pxa-uart"
> >
> > for mrvl,mmp-uart, I see two choices, one using 8250_pxa.c which has same result
> > as mrvl,pxa-uart, another choice would using the driver of 8250_of.c
> > and it work as same as "intel,xscale-uart", I don't see any difference..
> >
> > P.S: there is possibly a side problem that "mrvl,mmp-uart" from 8250_of.c doesn't
> > really compatile with "mrvl,mmp-uart" from 8250_pxa.c, but I think it's another story
--
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree
2024-07-06 5:05 ` Yixun Lan
@ 2024-07-06 10:40 ` Jisheng Zhang
2024-07-06 14:24 ` Yixun Lan
0 siblings, 1 reply; 33+ messages in thread
From: Jisheng Zhang @ 2024-07-06 10:40 UTC (permalink / raw)
To: Yixun Lan
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Daniel Lezcano,
Thomas Gleixner, Samuel Holland, Anup Patel, Greg Kroah-Hartman,
Jiri Slaby, Lubomir Rintel, devicetree, linux-kernel, Yangyu Chen,
Inochi Amaoto, linux-serial, linux-riscv, Meng Zhang
On Sat, Jul 06, 2024 at 05:05:56AM +0000, Yixun Lan wrote:
>
> On 12:12 Sat 06 Jul , Jisheng Zhang wrote:
> > On Fri, Jul 05, 2024 at 06:38:39AM +0000, Yixun Lan wrote:
> > >
> > > On 21:46 Thu 04 Jul , Jisheng Zhang wrote:
> > > > On Wed, Jul 03, 2024 at 02:55:11PM +0000, Yixun Lan wrote:
> > > > > From: Yangyu Chen <cyy@cyyself.name>
> > > > >
> > > > > Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> > > > >
> > > > > Key features:
> > > > > - 4 cores per cluster, 2 clusters on chip
> > > > > - UART IP is Intel XScale UART
> > > > >
> > > > > Some key considerations:
> > > > > - ISA string is inferred from vendor documentation[2]
> > > > > - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> > > > > - No coherent DMA on this board
> > > > > Inferred by taking vendor ethernet and MMC drivers to the mainline
> > > > > kernel. Without dma-noncoherent in soc node, the driver fails.
> > > > > - No cache nodes now
> > > > > The parameters from vendor dts are likely to be wrong. It has 512
> > > > > sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> > > > > When the size of the cache line is 64B, it is a directly mapped
> > > > > cache rather than a set-associative cache, the latter is commonly
> > > > > used. Thus, I didn't use the parameters from vendor dts.
> > > > >
> > > > > Currently only support booting into console with only uart, other
> > > > > features will be added soon later.
> > > > >
> > > > > Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> > > > > Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> > > > > Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> > > > > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> > > > > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > > > > ---
> > > > > arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> > > > > 1 file changed, 376 insertions(+)
> > > > >
> > > > > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > > > new file mode 100644
> > > > > index 0000000000000..a076e35855a2e
> > > > > --- /dev/null
> > > > > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > > > @@ -0,0 +1,376 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > > > +/*
> > > > > + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> > > > > + */
> > > > > +
> > > > > +/dts-v1/;
> > > > > +/ {
> > > > > + #address-cells = <2>;
> > > > > + #size-cells = <2>;
> > > > > + model = "SpacemiT K1";
> > > > > + compatible = "spacemit,k1";
> > > > > +
> > > > > +
...
> > > > > + soc {
> > > > > + compatible = "simple-bus";
> > > > > + interrupt-parent = <&plic>;
> > > > > + #address-cells = <2>;
> > > > > + #size-cells = <2>;
> > > > > + dma-noncoherent;
> > > > > + ranges;
> > > > > +
> > > > > + uart0: serial@d4017000 {
> > > > > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > > >
> > > > no, this is not a correct hw modeling. The doc on spacemit says
> > > > all the uart support 64 bytes FIFO, declaring xscale only makes
> > > > use of 32 bytes FIFO.
> > > yes, I also noticed it's 64 bytes FIFO
> > >
> > > >
> > > > IIRC, 8250_pxa is a xscale uart with 64 bytes FIFO, so this should be
> > > > "mrvl,pxa-uart" or "mrvl,mmp-uart"
> > >
> > >
> > > for mrvl,pxa-uart, I think you imply to use drivers/tty/serial/8250/8250_pxa.c,
> > > which turn out doesn't work on k1 SoC, for the record, we need to adjust
> >
> > Really? I just tried "mrvl,pxa-uart" with rc6, it works perfectly, and the FIFO
> > in the driver logic is 64bytes now. Am I misssing something or you never tried it?
> >
> Ok, I realised it's the clock issue
>
> still, I'm not fully convinced about using "mrvl,pxa-uart",
> e.g this driver hardcoded tz_loadsz to 32, not sure if K1 suffer same problem
> 5208e7ced520 ("serial: 8250_pxa: Configure tx_loadsz to match FIFO IRQ level")
I believe the problem commit 5208e7ced520 tries to solve is: the
mmp|pxa-uart only support threshold up to 32Bytes, tz_loadsz will be
fifo size by default, this will cause probleme with 64Bytes FIFO.
>
> also, what's the preference when choosing driver between 8250_pxa.c vs 8250_of.c?
Good question. I have no preference. But there are two problems with
8250_of, I have sent out patches[1][2] to address them.
After these two patches, both the earlycon and uart FIFO logic work too
with below dts properties:
uart0: serial@d4017000 {
compatible = "mrvl,mmp-uart";
...
reg-shift = <2>;
reg-io-width = <4>;
tx-threshold = <32>;
fifo-size = <64>;
no-loopback-test;
...
}
Link: https://lore.kernel.org/linux-riscv/20240706082928.2238-1-jszhang@kernel.org/ [1]
Link: https://lore.kernel.org/linux-riscv/20240706101856.3077-1-jszhang@kernel.org/ [2]
> it occur to me that 8250_pxa.c is more specially tailored for pxa hardware, while
> 8250_of.c is more generic.. besides, should we consider one more step if we want to
there's a work around for Erratum #74 in 8250_pxa, while I believe the
Errata doesn't exisit in K1, so from this PoV it seems 8250_of is
better, no?
> support DMA mode in the future (vendor uart driver has DMA support)?
Adding dma engine support to 8250_of is doable.
>
>
> > > drivers/tty/serial/8250/Kconfig to enable the driver for ARCH_SPACEMIT,
> > > and change uart compatible to "spacemit,k1-uart", "mrvl,pxa-uart"
> > >
> > > for mrvl,mmp-uart, I see two choices, one using 8250_pxa.c which has same result
> > > as mrvl,pxa-uart, another choice would using the driver of 8250_of.c
> > > and it work as same as "intel,xscale-uart", I don't see any difference..
> > >
> > > P.S: there is possibly a side problem that "mrvl,mmp-uart" from 8250_of.c doesn't
> > > really compatile with "mrvl,mmp-uart" from 8250_pxa.c, but I think it's another story
>
> --
> Yixun Lan (dlan)
> Gentoo Linux Developer
> GPG Key ID AABEFD55
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree
2024-07-06 10:40 ` Jisheng Zhang
@ 2024-07-06 14:24 ` Yixun Lan
2024-07-08 12:31 ` Jisheng Zhang
0 siblings, 1 reply; 33+ messages in thread
From: Yixun Lan @ 2024-07-06 14:24 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Daniel Lezcano,
Thomas Gleixner, Samuel Holland, Anup Patel, Greg Kroah-Hartman,
Jiri Slaby, Lubomir Rintel, devicetree, linux-kernel, Yangyu Chen,
Inochi Amaoto, linux-serial, linux-riscv, Meng Zhang
On 18:40 Sat 06 Jul , Jisheng Zhang wrote:
> On Sat, Jul 06, 2024 at 05:05:56AM +0000, Yixun Lan wrote:
> >
> > On 12:12 Sat 06 Jul , Jisheng Zhang wrote:
> > > On Fri, Jul 05, 2024 at 06:38:39AM +0000, Yixun Lan wrote:
> > > >
> > > > On 21:46 Thu 04 Jul , Jisheng Zhang wrote:
> > > > > On Wed, Jul 03, 2024 at 02:55:11PM +0000, Yixun Lan wrote:
> > > > > > From: Yangyu Chen <cyy@cyyself.name>
> > > > > >
> > > > > > Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> > > > > >
> > > > > > Key features:
> > > > > > - 4 cores per cluster, 2 clusters on chip
> > > > > > - UART IP is Intel XScale UART
> > > > > >
> > > > > > Some key considerations:
> > > > > > - ISA string is inferred from vendor documentation[2]
> > > > > > - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> > > > > > - No coherent DMA on this board
> > > > > > Inferred by taking vendor ethernet and MMC drivers to the mainline
> > > > > > kernel. Without dma-noncoherent in soc node, the driver fails.
> > > > > > - No cache nodes now
> > > > > > The parameters from vendor dts are likely to be wrong. It has 512
> > > > > > sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> > > > > > When the size of the cache line is 64B, it is a directly mapped
> > > > > > cache rather than a set-associative cache, the latter is commonly
> > > > > > used. Thus, I didn't use the parameters from vendor dts.
> > > > > >
> > > > > > Currently only support booting into console with only uart, other
> > > > > > features will be added soon later.
> > > > > >
> > > > > > Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> > > > > > Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> > > > > > Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> > > > > > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> > > > > > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > > > > > ---
> > > > > > arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> > > > > > 1 file changed, 376 insertions(+)
> > > > > >
> > > > > > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > > > > new file mode 100644
> > > > > > index 0000000000000..a076e35855a2e
> > > > > > --- /dev/null
> > > > > > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > > > > @@ -0,0 +1,376 @@
> > > > > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > > > > +/*
> > > > > > + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> > > > > > + */
> > > > > > +
> > > > > > +/dts-v1/;
> > > > > > +/ {
> > > > > > + #address-cells = <2>;
> > > > > > + #size-cells = <2>;
> > > > > > + model = "SpacemiT K1";
> > > > > > + compatible = "spacemit,k1";
> > > > > > +
> > > > > > +
> ...
> > > > > > + soc {
> > > > > > + compatible = "simple-bus";
> > > > > > + interrupt-parent = <&plic>;
> > > > > > + #address-cells = <2>;
> > > > > > + #size-cells = <2>;
> > > > > > + dma-noncoherent;
> > > > > > + ranges;
> > > > > > +
> > > > > > + uart0: serial@d4017000 {
> > > > > > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > > > >
> > > > > no, this is not a correct hw modeling. The doc on spacemit says
> > > > > all the uart support 64 bytes FIFO, declaring xscale only makes
> > > > > use of 32 bytes FIFO.
> > > > yes, I also noticed it's 64 bytes FIFO
> > > >
> > > > >
> > > > > IIRC, 8250_pxa is a xscale uart with 64 bytes FIFO, so this should be
> > > > > "mrvl,pxa-uart" or "mrvl,mmp-uart"
> > > >
> > > >
> > > > for mrvl,pxa-uart, I think you imply to use drivers/tty/serial/8250/8250_pxa.c,
> > > > which turn out doesn't work on k1 SoC, for the record, we need to adjust
> > >
> > > Really? I just tried "mrvl,pxa-uart" with rc6, it works perfectly, and the FIFO
> > > in the driver logic is 64bytes now. Am I misssing something or you never tried it?
> > >
> > Ok, I realised it's the clock issue
> >
> > still, I'm not fully convinced about using "mrvl,pxa-uart",
> > e.g this driver hardcoded tz_loadsz to 32, not sure if K1 suffer same problem
> > 5208e7ced520 ("serial: 8250_pxa: Configure tx_loadsz to match FIFO IRQ level")
>
> I believe the problem commit 5208e7ced520 tries to solve is: the
> mmp|pxa-uart only support threshold up to 32Bytes, tz_loadsz will be
> fifo size by default, this will cause probleme with 64Bytes FIFO.
>
yes, exactly
> >
> > also, what's the preference when choosing driver between 8250_pxa.c vs 8250_of.c?
>
> Good question. I have no preference. But there are two problems with
> 8250_of, I have sent out patches[1][2] to address them.
>
> After these two patches, both the earlycon and uart FIFO logic work too
> with below dts properties:
> uart0: serial@d4017000 {
> compatible = "mrvl,mmp-uart";
to be precise, I think here should be compatible = "mrvl,mmp-uart", "intel,xscale-uart"
but can you check this patch below? it should be ok with your two proposed patches applied
https://lore.kernel.org/all/20240703-k1-01-basic-dt-v3-6-12f73b47461e@gentoo.org/
> ...
> reg-shift = <2>;
> reg-io-width = <4>;
> tx-threshold = <32>;
> fifo-size = <64>;
..
> no-loopback-test;
need to check, from vendor docs, there is a loopback mode
see 16.2.4.1 SSCR register description, bit12
https://developer.spacemit.com/#/documentation?token=Rn9Kw3iFHirAMgkIpTAcV2Arnkf
> ...
> }
>
> Link: https://lore.kernel.org/linux-riscv/20240706082928.2238-1-jszhang@kernel.org/ [1]
I have some comments for this patch, and I believe it's a valid fix,
without this patch, K1 will also have problem duo to "UART_CAP_UUE | UART_CAP_RTOIE" lost
> Link: https://lore.kernel.org/linux-riscv/20240706101856.3077-1-jszhang@kernel.org/ [2]
>
> > it occur to me that 8250_pxa.c is more specially tailored for pxa hardware, while
> > 8250_of.c is more generic.. besides, should we consider one more step if we want to
>
> there's a work around for Erratum #74 in 8250_pxa, while I believe the
do you have any link for this Erratum? let's double check it..
> Errata doesn't exisit in K1, so from this PoV it seems 8250_of is
> better, no?
>
> > support DMA mode in the future (vendor uart driver has DMA support)?
>
> Adding dma engine support to 8250_of is doable.
Ok, sounds good to me
>
> >
> >
> > > > drivers/tty/serial/8250/Kconfig to enable the driver for ARCH_SPACEMIT,
> > > > and change uart compatible to "spacemit,k1-uart", "mrvl,pxa-uart"
> > > >
> > > > for mrvl,mmp-uart, I see two choices, one using 8250_pxa.c which has same result
> > > > as mrvl,pxa-uart, another choice would using the driver of 8250_of.c
> > > > and it work as same as "intel,xscale-uart", I don't see any difference..
> > > >
> > > > P.S: there is possibly a side problem that "mrvl,mmp-uart" from 8250_of.c doesn't
> > > > really compatile with "mrvl,mmp-uart" from 8250_pxa.c, but I think it's another story
> >
> > --
> > Yixun Lan (dlan)
> > Gentoo Linux Developer
> > GPG Key ID AABEFD55
--
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree
2024-07-06 14:24 ` Yixun Lan
@ 2024-07-08 12:31 ` Jisheng Zhang
0 siblings, 0 replies; 33+ messages in thread
From: Jisheng Zhang @ 2024-07-08 12:31 UTC (permalink / raw)
To: Yixun Lan
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Daniel Lezcano,
Thomas Gleixner, Samuel Holland, Anup Patel, Greg Kroah-Hartman,
Jiri Slaby, Lubomir Rintel, devicetree, linux-kernel, Yangyu Chen,
Inochi Amaoto, linux-serial, linux-riscv, Meng Zhang
On Sat, Jul 06, 2024 at 02:24:03PM +0000, Yixun Lan wrote:
> On 18:40 Sat 06 Jul , Jisheng Zhang wrote:
> > On Sat, Jul 06, 2024 at 05:05:56AM +0000, Yixun Lan wrote:
> > >
> > > On 12:12 Sat 06 Jul , Jisheng Zhang wrote:
> > > > On Fri, Jul 05, 2024 at 06:38:39AM +0000, Yixun Lan wrote:
> > > > >
> > > > > On 21:46 Thu 04 Jul , Jisheng Zhang wrote:
> > > > > > On Wed, Jul 03, 2024 at 02:55:11PM +0000, Yixun Lan wrote:
> > > > > > > From: Yangyu Chen <cyy@cyyself.name>
> > > > > > >
> > > > > > > Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
> > > > > > >
> > > > > > > Key features:
> > > > > > > - 4 cores per cluster, 2 clusters on chip
> > > > > > > - UART IP is Intel XScale UART
> > > > > > >
> > > > > > > Some key considerations:
> > > > > > > - ISA string is inferred from vendor documentation[2]
> > > > > > > - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> > > > > > > - No coherent DMA on this board
> > > > > > > Inferred by taking vendor ethernet and MMC drivers to the mainline
> > > > > > > kernel. Without dma-noncoherent in soc node, the driver fails.
> > > > > > > - No cache nodes now
> > > > > > > The parameters from vendor dts are likely to be wrong. It has 512
> > > > > > > sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> > > > > > > When the size of the cache line is 64B, it is a directly mapped
> > > > > > > cache rather than a set-associative cache, the latter is commonly
> > > > > > > used. Thus, I didn't use the parameters from vendor dts.
> > > > > > >
> > > > > > > Currently only support booting into console with only uart, other
> > > > > > > features will be added soon later.
> > > > > > >
> > > > > > > Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> > > > > > > Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> > > > > > > Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> > > > > > > Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> > > > > > > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > > > > > > ---
> > > > > > > arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> > > > > > > 1 file changed, 376 insertions(+)
> > > > > > >
> > > > > > > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > > > > > new file mode 100644
> > > > > > > index 0000000000000..a076e35855a2e
> > > > > > > --- /dev/null
> > > > > > > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > > > > > > @@ -0,0 +1,376 @@
> > > > > > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > > > > > +/*
> > > > > > > + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> > > > > > > + */
> > > > > > > +
> > > > > > > +/dts-v1/;
> > > > > > > +/ {
> > > > > > > + #address-cells = <2>;
> > > > > > > + #size-cells = <2>;
> > > > > > > + model = "SpacemiT K1";
> > > > > > > + compatible = "spacemit,k1";
> > > > > > > +
> > > > > > > +
> > ...
> > > > > > > + soc {
> > > > > > > + compatible = "simple-bus";
> > > > > > > + interrupt-parent = <&plic>;
> > > > > > > + #address-cells = <2>;
> > > > > > > + #size-cells = <2>;
> > > > > > > + dma-noncoherent;
> > > > > > > + ranges;
> > > > > > > +
> > > > > > > + uart0: serial@d4017000 {
> > > > > > > + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> > > > > >
> > > > > > no, this is not a correct hw modeling. The doc on spacemit says
> > > > > > all the uart support 64 bytes FIFO, declaring xscale only makes
> > > > > > use of 32 bytes FIFO.
> > > > > yes, I also noticed it's 64 bytes FIFO
> > > > >
> > > > > >
> > > > > > IIRC, 8250_pxa is a xscale uart with 64 bytes FIFO, so this should be
> > > > > > "mrvl,pxa-uart" or "mrvl,mmp-uart"
> > > > >
> > > > >
> > > > > for mrvl,pxa-uart, I think you imply to use drivers/tty/serial/8250/8250_pxa.c,
> > > > > which turn out doesn't work on k1 SoC, for the record, we need to adjust
> > > >
> > > > Really? I just tried "mrvl,pxa-uart" with rc6, it works perfectly, and the FIFO
> > > > in the driver logic is 64bytes now. Am I misssing something or you never tried it?
> > > >
> > > Ok, I realised it's the clock issue
> > >
> > > still, I'm not fully convinced about using "mrvl,pxa-uart",
> > > e.g this driver hardcoded tz_loadsz to 32, not sure if K1 suffer same problem
> > > 5208e7ced520 ("serial: 8250_pxa: Configure tx_loadsz to match FIFO IRQ level")
> >
> > I believe the problem commit 5208e7ced520 tries to solve is: the
> > mmp|pxa-uart only support threshold up to 32Bytes, tz_loadsz will be
> > fifo size by default, this will cause probleme with 64Bytes FIFO.
> >
> yes, exactly
>
> > >
> > > also, what's the preference when choosing driver between 8250_pxa.c vs 8250_of.c?
> >
> > Good question. I have no preference. But there are two problems with
> > 8250_of, I have sent out patches[1][2] to address them.
> >
> > After these two patches, both the earlycon and uart FIFO logic work too
> > with below dts properties:
> > uart0: serial@d4017000 {
> > compatible = "mrvl,mmp-uart";
> to be precise, I think here should be compatible = "mrvl,mmp-uart", "intel,xscale-uart"
see below.
>
> but can you check this patch below? it should be ok with your two proposed patches applied
> https://lore.kernel.org/all/20240703-k1-01-basic-dt-v3-6-12f73b47461e@gentoo.org/
>
> > ...
> > reg-shift = <2>;
> > reg-io-width = <4>;
> > tx-threshold = <32>;
> > fifo-size = <64>;
I just tried, the previous "spacemit,k1-uart", "intel,xscale-uart"; with above properties
work too, and the fifo size in driver logic seems correct as well.
> ..
> > no-loopback-test;
> need to check, from vendor docs, there is a loopback mode
oh, this property is from the UPF_SKIP_TEST of 8250_pxa.c. This
property can be removed.
> see 16.2.4.1 SSCR register description, bit12
>
> https://developer.spacemit.com/#/documentation?token=Rn9Kw3iFHirAMgkIpTAcV2Arnkf
> > ...
> > }
> >
> > Link: https://lore.kernel.org/linux-riscv/20240706082928.2238-1-jszhang@kernel.org/ [1]
> I have some comments for this patch, and I believe it's a valid fix,
> without this patch, K1 will also have problem duo to "UART_CAP_UUE | UART_CAP_RTOIE" lost
>
> > Link: https://lore.kernel.org/linux-riscv/20240706101856.3077-1-jszhang@kernel.org/ [2]
> >
> > > it occur to me that 8250_pxa.c is more specially tailored for pxa hardware, while
> > > 8250_of.c is more generic.. besides, should we consider one more step if we want to
> >
> > there's a work around for Erratum #74 in 8250_pxa, while I believe the
> do you have any link for this Erratum? let's double check it..
I can't find any link now :(
>
> > Errata doesn't exisit in K1, so from this PoV it seems 8250_of is
> > better, no?
> >
> > > support DMA mode in the future (vendor uart driver has DMA support)?
> >
> > Adding dma engine support to 8250_of is doable.
> Ok, sounds good to me
> >
> > >
> > >
> > > > > drivers/tty/serial/8250/Kconfig to enable the driver for ARCH_SPACEMIT,
> > > > > and change uart compatible to "spacemit,k1-uart", "mrvl,pxa-uart"
> > > > >
> > > > > for mrvl,mmp-uart, I see two choices, one using 8250_pxa.c which has same result
> > > > > as mrvl,pxa-uart, another choice would using the driver of 8250_of.c
> > > > > and it work as same as "intel,xscale-uart", I don't see any difference..
> > > > >
> > > > > P.S: there is possibly a side problem that "mrvl,mmp-uart" from 8250_of.c doesn't
> > > > > really compatile with "mrvl,mmp-uart" from 8250_pxa.c, but I think it's another story
> > >
> > > --
> > > Yixun Lan (dlan)
> > > Gentoo Linux Developer
> > > GPG Key ID AABEFD55
>
> --
> Yixun Lan (dlan)
> Gentoo Linux Developer
> GPG Key ID AABEFD55
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree
2024-07-03 14:55 ` [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree Yixun Lan
2024-07-04 1:17 ` Jesse Taube
2024-07-04 13:46 ` Jisheng Zhang
@ 2024-07-05 5:55 ` 张猛
2024-07-05 6:28 ` Conor Dooley
2 siblings, 1 reply; 33+ messages in thread
From: 张猛 @ 2024-07-05 5:55 UTC (permalink / raw)
To: Yixun Lan
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Daniel Lezcano,
Thomas Gleixner, Samuel Holland, Anup Patel, Greg Kroah-Hartman,
Jiri Slaby, Lubomir Rintel, devicetree, linux-kernel, linux-riscv,
linux-serial, Inochi Amaoto, Icenowy Zheng, Yangyu Chen,
Yixun Lan
Hi, Yixun Lan,
> From: "Yixun Lan"<dlan@gentoo.org>
> Date: Wed, Jul 3, 2024, 22:57
> Subject: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree
> To: "Rob Herring"<robh@kernel.org>, "Krzysztof Kozlowski"<krzk+dt@kernel.org>, "Conor Dooley"<conor+dt@kernel.org>, "Conor Dooley"<conor@kernel.org>, "Paul Walmsley"<paul.walmsley@sifive.com>, "Palmer Dabbelt"<palmer@dabbelt.com>, "Albert Ou"<aou@eecs.berkeley.edu>, "Daniel Lezcano"<daniel.lezcano@linaro.org>, "Thomas Gleixner"<tglx@linutronix.de>, "Samuel Holland"<samuel.holland@sifive.com>, "Anup Patel"<anup@brainfault.org>, "Greg Kroah-Hartman"<gregkh@linuxfoundation.org>, "Jiri Slaby"<jirislaby@kernel.org>, "Lubomir Rintel"<lkundrak@v3.sk>
> Cc: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-serial@vger.kernel.org>, "Inochi Amaoto"<inochiama@outlook.com>, "Icenowy Zheng"<uwu@icenowy.me>, "Meng Zhang"<zhangmeng.kevin@spacemit.com>, "Yangyu Chen"<cyy@cyyself.name>, "Yixun Lan"<dlan@gentoo.org>
> From: Yangyu Chen <cyy@cyyself.name>
>
> Banana Pi BPI-F3 motherboard is powered by SpacemiT K1[1].
>
> Key features:
> - 4 cores per cluster, 2 clusters on chip
> - UART IP is Intel XScale UART
>
> Some key considerations:
> - ISA string is inferred from vendor documentation[2]
> - Cluster topology is inferred from datasheet[1] and L2 in vendor dts[3]
> - No coherent DMA on this board
> Inferred by taking vendor ethernet and MMC drivers to the mainline
> kernel. Without dma-noncoherent in soc node, the driver fails.
> - No cache nodes now
> The parameters from vendor dts are likely to be wrong. It has 512
> sets for a 32KiB L1 Cache. In this case, each set is 64B in size.
> When the size of the cache line is 64B, it is a directly mapped
> cache rather than a set-associative cache, the latter is commonly
> used. Thus, I didn't use the parameters from vendor dts.
>
> Currently only support booting into console with only uart, other
> features will be added soon later.
>
> Link: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet [1]
> Link: https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb [2]
> Link: https://gitee.com/bianbu-linux/linux-6.1/blob/bl-v1.0.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi [3]
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> Signed-off-by: Yixun Lan <dlan@gentoo.org>
> ---
> arch/riscv/boot/dts/spacemit/k1.dtsi | 376 +++++++++++++++++++++++++++++++++++
> 1 file changed, 376 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> new file mode 100644
> index 0000000000000..a076e35855a2e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -0,0 +1,376 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
> + */
> +
> +/dts-v1/;
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + model = "SpacemiT K1";
> + compatible = "spacemit,k1";
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart2;
> + serial2 = &uart3;
> + serial3 = &uart4;
> + serial4 = &uart5;
> + serial5 = &uart6;
> + serial6 = &uart7;
> + serial7 = &uart8;
> + serial8 = &uart9;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <24000000>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu_0>;
> + };
> + core1 {
> + cpu = <&cpu_1>;
> + };
> + core2 {
> + cpu = <&cpu_2>;
> + };
> + core3 {
> + cpu = <&cpu_3>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu_4>;
> + };
> + core1 {
> + cpu = <&cpu_5>;
> + };
> + core2 {
> + cpu = <&cpu_6>;
> + };
> + core3 {
> + cpu = <&cpu_7>;
> + };
> + };
> + };
> +
> + cpu_0: cpu@0 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
Linux 6.7 kernel modifies the definition of the "riscv, isa" property, and describes the extended features in the "riscv, isa-extensions". So, can the definition of "riscv, isa" be simplified here?
Defined as ： riscv,isa = "rv64imafdcv";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_1: cpu@1 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <1>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu1_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_2: cpu@2 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <2>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu2_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_3: cpu@3 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <3>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu3_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_4: cpu@4 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <4>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu4_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_5: cpu@5 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <5>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu5_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_6: cpu@6 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <6>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu6_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu_7: cpu@7 {
> + compatible = "spacemit,x60", "riscv";
> + device_type = "cpu";
> + reg = <7>;
> + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
> + "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
> + "zifencei", "zihintpause", "zihpm", "zfh", "zba",
> + "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
> + "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + mmu-type = "riscv,sv39";
> +
> + cpu7_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-noncoherent;
> + ranges;
> +
> + uart0: serial@d4017000 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017000 0x0 0x100>;
> + interrupts = <42>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart2: serial@d4017100 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017100 0x0 0x100>;
> + interrupts = <44>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart3: serial@d4017200 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017200 0x0 0x100>;
> + interrupts = <45>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart4: serial@d4017300 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017300 0x0 0x100>;
> + interrupts = <46>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart5: serial@d4017400 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017400 0x0 0x100>;
> + interrupts = <47>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart6: serial@d4017500 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017500 0x0 0x100>;
> + interrupts = <48>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart7: serial@d4017600 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017600 0x0 0x100>;
> + interrupts = <49>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart8: serial@d4017700 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017700 0x0 0x100>;
> + interrupts = <50>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart9: serial@d4017800 {
> + compatible = "spacemit,k1-uart", "intel,xscale-uart";
> + reg = <0x0 0xd4017800 0x0 0x100>;
> + interrupts = <51>;
> + clock-frequency = <14857000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + plic: interrupt-controller@e0000000 {
> + compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
> + reg = <0x0 0xe0000000 0x0 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
> + <&cpu1_intc 11>, <&cpu1_intc 9>,
> + <&cpu2_intc 11>, <&cpu2_intc 9>,
> + <&cpu3_intc 11>, <&cpu3_intc 9>,
> + <&cpu4_intc 11>, <&cpu4_intc 9>,
> + <&cpu5_intc 11>, <&cpu5_intc 9>,
> + <&cpu6_intc 11>, <&cpu6_intc 9>,
> + <&cpu7_intc 11>, <&cpu7_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + riscv,ndev = <159>;
> + };
> +
> + clint: timer@e4000000 {
> + compatible = "spacemit,k1-clint", "sifive,clint0";
> + reg = <0x0 0xe4000000 0x0 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> + <&cpu1_intc 3>, <&cpu1_intc 7>,
> + <&cpu2_intc 3>, <&cpu2_intc 7>,
> + <&cpu3_intc 3>, <&cpu3_intc 7>,
> + <&cpu4_intc 3>, <&cpu4_intc 7>,
> + <&cpu5_intc 3>, <&cpu5_intc 7>,
> + <&cpu6_intc 3>, <&cpu6_intc 7>,
> + <&cpu7_intc 3>, <&cpu7_intc 7>;
> + };
> + };
> +};
>
> --
> 2.45.2
This message and any attachment are confidential and may be privileged or otherwise protected from disclosure. If you are not an intended recipient of this message, please delete it and any attachment from your system and notify the sender immediately by reply e-mail. Unintended recipients should not use, copy, disclose or take any action based on this message or any information contained in this message. Emails cannot be guaranteed to be secure or error free as they can be intercepted, amended, lost or destroyed, and you should take full responsibility for security checking.
本邮件及其任何附件具有保密性质，并可能受其他保护或不允许被披露给第三方。如阁下误收到本邮件，敬请立即以回复电子邮件的方式通知发件人，并将本邮件及其任何附件从阁下系统中予以删除。如阁下并非本邮件写明之收件人，敬请切勿使用、复制、披露本邮件或其任何内容，亦请切勿依本邮件或其任何内容而采取任何行动。电子邮件无法保证是一种安全和不会出现任何差错的通信方式，可能会被拦截、修改、丢失或损坏，收件人需自行负责做好安全检查。
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PATCH v3 08/11] riscv: dts: add initial SpacemiT K1 SoC device tree
2024-07-05 5:55 ` 张猛
@ 2024-07-05 6:28 ` Conor Dooley
0 siblings, 0 replies; 33+ messages in thread
From: Conor Dooley @ 2024-07-05 6:28 UTC (permalink / raw)
To: 张猛
Cc: Yixun Lan, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel,
Greg Kroah-Hartman, Jiri Slaby, Lubomir Rintel, devicetree,
linux-kernel, linux-riscv, linux-serial, Inochi Amaoto,
Icenowy Zheng, Yangyu Chen
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On Fri, Jul 05, 2024 at 01:55:43PM +0800, 张猛 wrote:
> > + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
> Linux 6.7 kernel modifies the definition of the "riscv, isa" property, and describes the extended features in the "riscv, isa-extensions". So, can the definition of "riscv, isa" be simplified here?
> Defined as ： riscv,isa = "rv64imafdcv";
No, they should match, other than vendor extensions. Not every project
supports the new property.
> This message and any attachment are confidential and may be privileged or otherwise protected from disclosure. If you are not an intended recipient of this message, please delete it and any attachment from your system and notify the sender immediately by reply e-mail. Unintended recipients should not use, copy, disclose or take any action based on this message or any information contained in this message. Emails cannot be guaranteed to be secure or error free as they can be intercepted, amended, lost or destroyed, and you should take full responsibility for security checking.
>
> 本邮件及其任何附件具有保密性质，并可能受其他保护或不允许被披露给第三方。如阁下误收到本邮件，敬请立即以回复电子邮件的方式通知发件人，并将本邮件及其任何附件从阁下系统中予以删除。如阁下并非本邮件写明之收件人，敬请切勿使用、复制、披露本邮件或其任何内容，亦请切勿依本邮件或其任何内容而采取任何行动。电子邮件无法保证是一种安全和不会出现任何差错的通信方式，可能会被拦截、修改、丢失或损坏，收件人需自行负责做好安全检查。
Please fix your mail client/system to not append this. Such footers are
incompatible with kernel development.
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 33+ messages in thread