From: Jiri Slaby <jirislaby@kernel.org>
To: "Sathish Kumar Balasubramaniam -ERS,
HCL Tech" <b-sathishkumar@hcl.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: "linux-serial@vger.kernel.org" <linux-serial@vger.kernel.org>
Subject: Re: [PATCH] tty: serial: UART driver for RISC-V based Chromite SoC family
Date: Sun, 29 Aug 2021 09:09:58 +0200 [thread overview]
Message-ID: <a473e415-1cb2-a6bf-829b-c91777856a12@kernel.org> (raw)
In-Reply-To: <SG2PR04MB3820E80B2501990F1B906E8581C99@SG2PR04MB3820.apcprd04.prod.outlook.com>
On 28. 08. 21, 19:16, Sathish Kumar Balasubramaniam -ERS, HCL Tech wrote:
> Classification: Public
>
> Hi JS,
>
> Got the function opening change and will do it.
> But could not understand the meaning which you are referring by mangled lines.
> Please can you explain the issue for one place so that I will do for all
>
> Thank you.
>
>
> On 27. 08. 21, 18:32, Sathish Kumar Balasubramaniam -ERS, HCL Tech wrote:
>> +static void chromite_serial_set_termios(struct uart_port *port,
>> + struct ktermios *termios,
>> + struct ktermios *old) {
>> + struct chromite_serial_port *csp = port_to_chromite_serial_port(port);
>> + unsigned long flags;
>> + int rate;
>> +
>> + if ((termios->c_cflag & CSIZE) != CS8)
>> + dev_err_once(csp->port.dev, "only 8-bit words supported\n");
>> + if (termios->c_cflag & CSTOPB)
>> + dev_err_once(csp->port.dev, "only 1 stop-bit is supported\n");
>> + if (termios->c_iflag & (INPCK | PARMRK))
>> + dev_err_once(csp->port.dev, "parity checking not supported\n");
>> + if (termios->c_iflag & BRKINT)
>> + dev_err_once(csp->port.dev, "BREAK detection not
>> + supported\n");
>
> Many mangled lines like this. Please fix these up in v2. And also use checkpatch. The function-opening { above should be on a separate line (on many locations).
Note the
supported\n");
on a separate line above.
--
js
suse labs
prev parent reply other threads:[~2021-08-29 7:10 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-27 16:23 [PATCH] tty: serial: UART driver for RISC-V based Chromite SoC family Sathish Kumar Balasubramaniam -ERS, HCL Tech
2021-08-27 16:30 ` Greg Kroah-Hartman
2021-08-27 16:32 ` Sathish Kumar Balasubramaniam -ERS, HCL Tech
2021-08-27 17:26 ` Greg Kroah-Hartman
2021-08-28 16:54 ` Sathish Kumar Balasubramaniam -ERS, HCL Tech
2021-08-28 7:55 ` Jiri Slaby
2021-08-28 16:59 ` Sathish Kumar Balasubramaniam -ERS, HCL Tech
2021-08-28 17:16 ` Sathish Kumar Balasubramaniam -ERS, HCL Tech
2021-08-29 7:09 ` Jiri Slaby [this message]
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