From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: Yicong Yang <yang.yicong@picoheart.com>,
linux-serial <linux-serial@vger.kernel.org>,
LKML <linux-kernel@vger.kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>,
geshijian@picoheart.com, yangyang.8776@picoheart.com,
yanligen@picoheart.com
Subject: Re: [PATCH] serial: 8250_dw: Prefer SRBR in bogus RX timeout workaround if available
Date: Mon, 29 Jun 2026 18:16:10 +0300 [thread overview]
Message-ID: <akKMOlRjl3R-uR3b@ashevche-desk.local> (raw)
In-Reply-To: <60c05ab5-c805-dd78-1b6b-9c78ee7d7148@linux.intel.com>
On Mon, Jun 29, 2026 at 06:14:02PM +0300, Ilpo Järvinen wrote:
> On Mon, 29 Jun 2026, Andy Shevchenko wrote:
> > On Mon, Jun 29, 2026 at 03:55:10PM +0800, Yicong Yang wrote:
...
> > > /* Offsets for the DesignWare specific registers */
> > > +#define DW_UART_SRBR_0 0x0c /* Shadow Receive Buffer Register */
> >
> > Is this a name per DesignWare databook for UART? I mean that _0 part.
>
> They have 16 consecutive registers for it. There isn't underscore in the
> databook but n is apparently part of the name.
Oh, okay.
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2026-06-29 15:16 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-29 7:55 [PATCH] serial: 8250_dw: Prefer SRBR in bogus RX timeout workaround if available Yicong Yang
2026-06-29 14:56 ` Andy Shevchenko
2026-06-29 15:14 ` Ilpo Järvinen
2026-06-29 15:16 ` Andy Shevchenko [this message]
2026-06-29 15:56 ` Ilpo Järvinen
2026-06-29 16:07 ` Andy Shevchenko
2026-06-30 17:51 ` Yicong Yang
2026-06-30 18:18 ` Ilpo Järvinen
2026-06-30 18:42 ` Yicong Yang
2026-07-01 8:45 ` Ilpo Järvinen
2026-07-01 16:13 ` Yicong Yang
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