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Wed, 17 Jan 2024 07:08:30 -0800 (PST) Received: from [192.168.2.107] ([79.115.63.202]) by smtp.gmail.com with ESMTPSA id o19-20020a17090608d300b00a2adc93e308sm7838583eje.222.2024.01.17.07.08.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Jan 2024 07:08:29 -0800 (PST) Message-ID: Date: Wed, 17 Jan 2024 15:08:27 +0000 Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 11/12] arm64: dts: exynos: gs101: define USI8 with I2C configuration Content-Language: en-US To: Sam Protsenko Cc: peter.griffin@linaro.org, krzysztof.kozlowski+dt@linaro.org, gregkh@linuxfoundation.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, conor+dt@kernel.org, andi.shyti@kernel.org, alim.akhtar@samsung.com, jirislaby@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com References: <20240109125814.3691033-1-tudor.ambarus@linaro.org> <20240109125814.3691033-12-tudor.ambarus@linaro.org> From: Tudor Ambarus In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/16/24 18:03, Sam Protsenko wrote: >> USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8 >> doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the >> selection of the protocol is intentionally left for the board dts file. >> >> Signed-off-by: Tudor Ambarus >> --- >> v3: reorder usi8 clock order (thanks Andre'!). Did not make any >> difference at testing as the usi driver treats the clocks in bulk. >> v2: >> - identify and use gate clocks instead of dividers >> - move cells and pinctrl properties from dts to dtsi >> - move IRQ type constant on the previous line >> >> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 29 ++++++++++++++++++++ >> 1 file changed, 29 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi >> index 6aa25cc4676e..f14a24628d04 100644 >> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi >> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi >> @@ -352,6 +352,35 @@ pinctrl_peric0: pinctrl@10840000 { >> interrupts = ; >> }; >> >> + usi8: usi@109700c0 { >> + compatible = "google,gs101-usi", >> + "samsung,exynos850-usi"; >> + reg = <0x109700c0 0x20>; >> + ranges; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>, >> + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; >> + clock-names = "pclk", "ipclk"; >> + samsung,sysreg = <&sysreg_peric0 0x101c>; > I'd also add samsung,mode for the "default" USI mode here, just to > avoid providing it later in the board's dts. But that's a matter of > taste I guess. > USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8 doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the selection of the protocol is intentionally left for the board dts file. I wanted to emphasize that USI8 doesn't have any HW defaults and its mode must be chosen by each particular board. I mentioned the same in the commit message, please tell if you feel it needs updating. Cheers, ta