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Wed, 11 Sep 2024 17:19:11 -0700 (PDT) Received: from [10.67.48.245] ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7db1fba421dsm578767a12.5.2024.09.11.17.19.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Sep 2024 17:19:10 -0700 (PDT) Message-ID: Date: Wed, 11 Sep 2024 17:19:08 -0700 Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] tty: rp2: Fix reset with non forgiving PCIe host bridges To: Jim Quinlan Cc: linux-serial@vger.kernel.org, Kevin Cernekee , Greg Kroah-Hartman , Jiri Slaby , John Ogness , =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= , Thomas Gleixner , "open list:TTY LAYER AND SERIAL DRIVERS" References: <20240906225435.707837-1-florian.fainelli@broadcom.com> <2bb3a405-cb6b-4033-99f4-ecd25ffc095d@broadcom.com> Content-Language: en-US From: Florian Fainelli Autocrypt: addr=florian.fainelli@broadcom.com; keydata= xsBNBFPAG8ABCAC3EO02urEwipgbUNJ1r6oI2Vr/+uE389lSEShN2PmL3MVnzhViSAtrYxeT M0Txqn1tOWoIc4QUl6Ggqf5KP6FoRkCrgMMTnUAINsINYXK+3OLe7HjP10h2jDRX4Ajs4Ghs JrZOBru6rH0YrgAhr6O5gG7NE1jhly+EsOa2MpwOiXO4DE/YKZGuVe6Bh87WqmILs9KvnNrQ PcycQnYKTVpqE95d4M824M5cuRB6D1GrYovCsjA9uxo22kPdOoQRAu5gBBn3AdtALFyQj9DQ KQuc39/i/Kt6XLZ/RsBc6qLs+p+JnEuPJngTSfWvzGjpx0nkwCMi4yBb+xk7Hki4kEslABEB AAHNMEZsb3JpYW4gRmFpbmVsbGkgPGZsb3JpYW4uZmFpbmVsbGlAYnJvYWRjb20uY29tPsLB IQQQAQgAywUCZWl41AUJI+Jo+hcKAAG/SMv+fS3xUQWa0NryPuoRGjsA3SAUAAAAAAAWAAFr ZXktdXNhZ2UtbWFza0BwZ3AuY29tjDAUgAAAAAAgAAdwcmVmZXJyZWQtZW1haWwtZW5jb2Rp bmdAcGdwLmNvbXBncG1pbWUICwkIBwMCAQoFF4AAAAAZGGxkYXA6Ly9rZXlzLmJyb2FkY29t Lm5ldAUbAwAAAAMWAgEFHgEAAAAEFQgJChYhBNXZKpfnkVze1+R8aIExtcQpvGagAAoJEIEx tcQpvGagWPEH/2l0DNr9QkTwJUxOoP9wgHfmVhqc0ZlDsBFv91I3BbhGKI5UATbipKNqG13Z TsBrJHcrnCqnTRS+8n9/myOF0ng2A4YT0EJnayzHugXm+hrkO5O9UEPJ8a+0553VqyoFhHqA zjxj8fUu1px5cbb4R9G4UAySqyeLLeqnYLCKb4+GklGSBGsLMYvLmIDNYlkhMdnnzsSUAS61 WJYW6jjnzMwuKJ0ZHv7xZvSHyhIsFRiYiEs44kiYjbUUMcXor/uLEuTIazGrE3MahuGdjpT2 IOjoMiTsbMc0yfhHp6G/2E769oDXMVxCCbMVpA+LUtVIQEA+8Zr6mX0Yk4nDS7OiBlvOwE0E U8AbwQEIAKxr71oqe+0+MYCc7WafWEcpQHFUwvYLcdBoOnmJPxDwDRpvU5LhqSPvk/yJdh9k 4xUDQu3rm1qIW2I9Puk5n/Jz/lZsqGw8T13DKyu8eMcvaA/irm9lX9El27DPHy/0qsxmxVmU pu9y9S+BmaMb2CM9IuyxMWEl9ruWFS2jAWh/R8CrdnL6+zLk60R7XGzmSJqF09vYNlJ6Bdbs MWDXkYWWP5Ub1ZJGNJQ4qT7g8IN0qXxzLQsmz6tbgLMEHYBGx80bBF8AkdThd6SLhreCN7Uh IR/5NXGqotAZao2xlDpJLuOMQtoH9WVNuuxQQZHVd8if+yp6yRJ5DAmIUt5CCPcAEQEAAcLB gQQYAQIBKwUCU8AbwgUbDAAAAMBdIAQZAQgABgUCU8AbwQAKCRCTYAaomC8PVQ0VCACWk3n+ obFABEp5Rg6Qvspi9kWXcwCcfZV41OIYWhXMoc57ssjCand5noZi8bKg0bxw4qsg+9cNgZ3P N/DFWcNKcAT3Z2/4fTnJqdJS//YcEhlr8uGs+ZWFcqAPbteFCM4dGDRruo69IrHfyyQGx16s CcFlrN8vD066RKevFepb/ml7eYEdN5SRALyEdQMKeCSf3mectdoECEqdF/MWpfWIYQ1hEfdm C2Kztm+h3Nkt9ZQLqc3wsPJZmbD9T0c9Rphfypgw/SfTf2/CHoYVkKqwUIzI59itl5Lze+R5 wDByhWHx2Ud2R7SudmT9XK1e0x7W7a5z11Q6vrzuED5nQvkhAAoJEIExtcQpvGagugcIAJd5 EYe6KM6Y6RvI6TvHp+QgbU5dxvjqSiSvam0Ms3QrLidCtantcGT2Wz/2PlbZqkoJxMQc40rb fXa4xQSvJYj0GWpadrDJUvUu3LEsunDCxdWrmbmwGRKqZraV2oG7YEddmDqOe0Xm/NxeSobc MIlnaE6V0U8f5zNHB7Y46yJjjYT/Ds1TJo3pvwevDWPvv6rdBeV07D9s43frUS6xYd1uFxHC 7dZYWJjZmyUf5evr1W1gCgwLXG0PEi9n3qmz1lelQ8lSocmvxBKtMbX/OKhAfuP/iIwnTsww 95A2SaPiQZA51NywV8OFgsN0ITl2PlZ4Tp9hHERDe6nQCsNI/Us= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 9/11/24 15:44, Jim Quinlan wrote: > On Wed, Sep 11, 2024 at 6:19 PM Florian Fainelli > wrote: >> >> On 9/11/24 15:16, Jim Quinlan wrote: >>> On Wed, Sep 11, 2024 at 6:01 PM Florian Fainelli >>> wrote: >>>> >>>> On 9/11/24 14:47, Jim Quinlan wrote: >>>>> On Fri, Sep 6, 2024 at 6:54 PM Florian Fainelli >>>>> wrote: >>>>>> >>>>>> The write to RP2_GLOBAL_CMD followed by an immediate read of >>>>>> RP2_GLOBAL_CMD in rp2_reset_asic() is intented to flush out the write, >>>>>> however by then the device is already in reset and cannot respond to a >>>>>> memory cycle access. >>>>>> >>>>>> On platforms such as the Raspberry Pi 4 and others using the >>>>>> pcie-brcmstb.c driver, any memory access to a device that cannot respond >>>>>> is met with a fatal system error, rather than being substituted with all >>>>>> 1s as is usually the case on PC platforms. >>>>>> >>>>>> Swapping the delay and the read ensures that the device has finished >>>>>> resetting before we attempt to read from it. >>>>>> >>>>>> Fixes: 7d9f49afa451 ("serial: rp2: New driver for Comtrol RocketPort 2 cards") >>>>>> Suggested-by: Jim Quinlan >>>>>> Signed-off-by: Florian Fainelli >>>>>> --- >>>>>> drivers/tty/serial/rp2.c | 2 +- >>>>>> 1 file changed, 1 insertion(+), 1 deletion(-) >>>>>> >>>>>> diff --git a/drivers/tty/serial/rp2.c b/drivers/tty/serial/rp2.c >>>>>> index 4132fcff7d4e..8bab2aedc499 100644 >>>>>> --- a/drivers/tty/serial/rp2.c >>>>>> +++ b/drivers/tty/serial/rp2.c >>>>>> @@ -577,8 +577,8 @@ static void rp2_reset_asic(struct rp2_card *card, unsigned int asic_id) >>>>>> u32 clk_cfg; >>>>>> >>>>>> writew(1, base + RP2_GLOBAL_CMD); >>>>>> - readw(base + RP2_GLOBAL_CMD); >>>>>> msleep(100); >>>>>> + readw(base + RP2_GLOBAL_CMD); >>>>> >>>>> Since the assumed purpose of the readw() was to flush the writew(), >>>>> would it make sense to add a barrier after the writew()? >>>> >>>> AFAICT there is one which is implied within the name, as it is not a >>>> _relaxed() variant. Did you mean a different sort of barrier to be used? >>> >>> Not sure. The __raw_writew() is followed by __io_aw(), which is a >>> no-op on arm64. I don't know arm64 well enough to know if a follow-up >>> barrier is needed. >> >> By definition all of the {read,write}{b,w,l,q} do include an adequate >> barrier > I do see this in the kernel, e.g. altera_edac.c, pci-hyperv.c, > oxu210hp-hcd.c, etc: > > write[lw](..); > wmb(); > > All I am saying is that the definition of writew() for arm64 has no > explicit barrier *after* it makes the __raw_writew() call, since its > __io_aw() call is a no-op. I really don't know if this matters, just > wanted to mention it. Not having the documentation for this peripheral, not sure TBH. As far as the drivers you quoted given the __io_bw() does include a barrier, it would appear that the barrier after is possibly redundant, or is based upon a misunderstanding of which side of the write the barrier must be on, or maybe they are actually necessary, but undocumented as such.. -- Florian