* Re: [RFC PATCH] pch_uart: Add eg20t_port lock field, avoid recursive spinlocks
From: Tomoya MORINAGA @ 2012-06-01 8:30 UTC (permalink / raw)
To: Darren Hart
Cc: Linux Kernel Mailing List, Feng Tang, Alexander Stein,
Greg Kroah-Hartman, Alan Cox, linux-serial
In-Reply-To: <8854635ac5471f8671b93c65e3663eb1cb204c9d.1338454156.git.dvhart@linux.intel.com>
On Thu, May 31, 2012 at 5:54 PM, Darren Hart <dvhart@linux.intel.com> wrote:
> @@ -1376,7 +1379,8 @@ static void pch_uart_set_termios(struct uart_port *port,
>
> baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
>
> - spin_lock_irqsave(&port->lock, flags);
> + spin_lock_irqsave(&priv->lock, flags);
> + spin_lock(&port->lock);
>
> uart_update_timeout(port, termios->c_cflag, baud);
> rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
> @@ -1389,7 +1393,8 @@ static void pch_uart_set_termios(struct uart_port *port,
> tty_termios_encode_baud_rate(termios, baud, baud);
>
> out:
> - spin_unlock_irqrestore(&port->lock, flags);
> + spin_unlock(&port->lock);
> + spin_unlock_irqrestore(&priv->lock, flags);
> }
Are both port->lock and priv->lock really necessary ?
> @@ -1572,7 +1578,9 @@ pch_console_write(struct console *co, const char *s, unsigned int count)
>
> if (locked)
> spin_unlock(&priv->port.lock);
> + spin_unlock(&priv->lock);
> local_irq_restore(flags);
> +
> }
Looks spare blank line.
thanks.
--
ROHM Co., Ltd.
tomoya
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^ permalink raw reply
* [RFC PATCH] pch_uart: Add eg20t_port lock field, avoid recursive spinlocks
From: Darren Hart @ 2012-05-31 8:54 UTC (permalink / raw)
To: Linux Kernel Mailing List
Cc: Darren Hart, Tomoya MORINAGA, Feng Tang, Alexander Stein,
Greg Kroah-Hartman, Alan Cox, linux-serial
pch_uart_interrupt() takes priv->port.lock which leads to two recursive
spinlock calls if low_latency==1 or CONFIG_PREEMPT_RT_FULL=y (one
otherwise):
pch_uart_interrupt
spin_lock_irqsave(priv->port.lock, flags)
case PCH_UART_IID_RDR_TO (data ready)
handle_rx_to
push_rx
tty_port_tty_get
spin_lock_irqsave(&port->lock, flags) <--- already hold this lock
...
tty_flip_buffer_push
...
flush_to_ldisc
spin_lock_irqsave(&tty->buf.lock)
spin_lock_irqsave(&tty->buf.lock)
disc->ops->receive_buf(tty, char_buf)
n_tty_receive_buf
tty->ops->flush_chars()
uart_flush_chars
uart_start
spin_lock_irqsave(&port->lock) <--- already hold this lock
Avoid this by using a dedicated lock to protect the eg20t_port structure
and IO access to its membase. This is more consistent with the 8250
driver. Ensure priv->lock is always take prior to priv->port.lock when
taken at the same time.
Tomoya, I have attempted to protect the eg20t_port structure and the membase
with the new eg20t_port.lock field, however I believe the current locking to be
a bit coarse. I imagine the priv->lock could be held a bit less. What are your
thoughts?
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
CC: Tomoya MORINAGA <tomoya.rohm@gmail.com>
CC: Feng Tang <feng.tang@intel.com>
CC: Alexander Stein <alexander.stein@systec-electronic.com>
CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CC: Alan Cox <alan@linux.intel.com>
CC: linux-serial@vger.kernel.org
---
drivers/tty/serial/pch_uart.c | 22 ++++++++++++++++------
1 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/tty/serial/pch_uart.c b/drivers/tty/serial/pch_uart.c
index 4fdec6a..c90a8cd 100644
--- a/drivers/tty/serial/pch_uart.c
+++ b/drivers/tty/serial/pch_uart.c
@@ -253,6 +253,9 @@ struct eg20t_port {
dma_addr_t rx_buf_dma;
struct dentry *debugfs;
+
+ /* protect the eg20t_port private structure and io access to membase */
+ spinlock_t lock;
};
/**
@@ -1058,7 +1061,7 @@ static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
int next = 1;
u8 msr;
- spin_lock_irqsave(&priv->port.lock, flags);
+ spin_lock_irqsave(&priv->lock, flags);
handled = 0;
while (next) {
iid = pch_uart_hal_get_iid(priv);
@@ -1116,7 +1119,7 @@ static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
handled |= (unsigned int)ret;
}
- spin_unlock_irqrestore(&priv->port.lock, flags);
+ spin_unlock_irqrestore(&priv->lock, flags);
return IRQ_RETVAL(handled);
}
@@ -1226,9 +1229,9 @@ static void pch_uart_break_ctl(struct uart_port *port, int ctl)
unsigned long flags;
priv = container_of(port, struct eg20t_port, port);
- spin_lock_irqsave(&port->lock, flags);
+ spin_lock_irqsave(&priv->lock, flags);
pch_uart_hal_set_break(priv, ctl);
- spin_unlock_irqrestore(&port->lock, flags);
+ spin_unlock_irqrestore(&priv->lock, flags);
}
/* Grab any interrupt resources and initialise any low level driver state. */
@@ -1376,7 +1379,8 @@ static void pch_uart_set_termios(struct uart_port *port,
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
- spin_lock_irqsave(&port->lock, flags);
+ spin_lock_irqsave(&priv->lock, flags);
+ spin_lock(&port->lock);
uart_update_timeout(port, termios->c_cflag, baud);
rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
@@ -1389,7 +1393,8 @@ static void pch_uart_set_termios(struct uart_port *port,
tty_termios_encode_baud_rate(termios, baud, baud);
out:
- spin_unlock_irqrestore(&port->lock, flags);
+ spin_unlock(&port->lock);
+ spin_unlock_irqrestore(&priv->lock, flags);
}
static const char *pch_uart_type(struct uart_port *port)
@@ -1546,6 +1551,7 @@ pch_console_write(struct console *co, const char *s, unsigned int count)
touch_nmi_watchdog();
local_irq_save(flags);
+ spin_lock(&priv->lock);
if (priv->port.sysrq) {
/* serial8250_handle_port() already took the lock */
locked = 0;
@@ -1572,7 +1578,9 @@ pch_console_write(struct console *co, const char *s, unsigned int count)
if (locked)
spin_unlock(&priv->port.lock);
+ spin_unlock(&priv->lock);
local_irq_restore(flags);
+
}
static int __init pch_console_setup(struct console *co, char *options)
@@ -1669,6 +1677,8 @@ static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
pci_enable_msi(pdev);
pci_set_master(pdev);
+ spin_lock_init(&priv->lock);
+
iobase = pci_resource_start(pdev, 0);
mapbase = pci_resource_start(pdev, 1);
priv->mapbase = mapbase;
--
1.7.5.4
^ permalink raw reply related
* Re: [PATCH] serial: Add driver for LPC32xx High Speed UARTs
From: Alan Cox @ 2012-05-30 15:31 UTC (permalink / raw)
To: Roland Stigge
Cc: alan, gregkh, linux-serial, linux-kernel, kevin.wells,
srinivas.bakki, linux-arm-kernel
In-Reply-To: <1338389751-16022-1-git-send-email-stigge@antcom.de>
> +#define LPC32XX_TTY_MINOR_START 196
> +#define LPC32XX_TTY_MAJOR 204
NAK - please use dynamic allocations.
> + /* Read data from FIFO and push into terminal */
> + tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
> + while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
> + flag = TTY_NORMAL;
> + port->icount.rx++;
> +
> + if (tmp & LPC32XX_HSU_ERROR_DATA) {
> + /* Framing error */
> + writel(LPC32XX_HSU_FE_INT,
> + LPC32XX_HSUART_IIR(port->membase));
> + port->icount.frame++;
> + flag = TTY_FRAME;
> + tty_insert_flip_char(port->state->port.tty, 0,
> + TTY_FRAME);
> + tty_schedule_flip(port->state->port.tty);
> + }
> +
> + tty_insert_flip_char(port->state->port.tty, (tmp & 0xFF), flag);
> +
> + tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
This seems odd - you don't need to schedule the flip of the framing error
separately. It all just ends up in the queue and can be kicked in one go.
Also if the last byte is a normal char - who ensures the buffer is pushed
and not wedged until a future I/O ?
Second problem is port->state->port.tty can be or go to NULL. Take a look
how drivers use tty_port_tty_get(), and tty_kref_put.
> + /* Data received? */
> + if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT)) {
> + __serial_lpc32xx_rx(port);
> + spin_unlock(&port->lock);
> + tty_flip_buffer_push(port->state->port.tty);
> + spin_lock(&port->lock);
> + }
Not sure what the locking is about here - you shouldn't need to fiddle
with locks unless you are using low latency and you can't use low latency
safely from an IRQ handler...
(Also again tty and NULL - you may want to grab it once at the start of
the handler)
> +static void serial_lpc32xx_set_termios(struct uart_port *port,
> + struct ktermios *termios,
> + struct ktermios *old)
> +{
> + unsigned long flags;
> + unsigned int baud, quot;
> + u32 tmp;
> +
> + /* Always 8-bit, no parity, 1 stop bit */
> + termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
> + termios->c_cflag |= CS8;
> +
> + termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
> +
> + baud = uart_get_baud_rate(port, termios, old, 0,
> + port->uartclk / 14);
You want to set the resulting baud rate back into the struct - see 8250.c
for an example.
Alan
^ permalink raw reply
* [PATCH] serial: Add driver for LPC32xx High Speed UARTs
From: Roland Stigge @ 2012-05-30 14:55 UTC (permalink / raw)
To: alan, gregkh, linux-serial, linux-kernel, kevin.wells,
srinivas.bakki, linux-arm-kernel
Cc: Roland Stigge
This patch adds a driver for the 3 High Speed UARTs of the LPC32xx SoC that
support up to 900kbps. These UARTs are different from the 4 "Standard" UARTs
of the LPC32xx.
Signed-off-by: Roland Stigge <stigge@antcom.de>
---
Applies to v3.4
Documentation/devicetree/bindings/tty/serial/nxp-lpc32xx-hsuart.txt | 14
drivers/tty/serial/Kconfig | 19
drivers/tty/serial/Makefile | 1
drivers/tty/serial/lpc32xx_hs.c | 810 ++++++++++
4 files changed, 844 insertions(+)
--- /dev/null
+++ linux-2.6/Documentation/devicetree/bindings/tty/serial/nxp-lpc32xx-hsuart.txt
@@ -0,0 +1,14 @@
+* NXP LPC32xx SoC High Speed UART
+
+Required properties:
+- compatible: Should be "nxp,lpc3220-hsuart"
+- reg: Should contain registers location and length
+- interrupts: Should contain interrupt
+
+Example:
+
+ uart1: serial@40014000 {
+ compatible = "nxp,lpc3220-hsuart";
+ reg = <0x40014000 0x1000>;
+ interrupts = <26 0>;
+ };
--- linux-2.6.orig/drivers/tty/serial/Kconfig
+++ linux-2.6/drivers/tty/serial/Kconfig
@@ -704,6 +704,25 @@ config SERIAL_PNX8XXX_CONSOLE
If you have a MIPS-based Philips SoC such as PNX8550 or PNX8330
and you want to use serial console, say Y. Otherwise, say N.
+config SERIAL_HS_LPC32XX
+ tristate "LPC32XX high speed serial port support"
+ depends on ARCH_LPC32XX && OF
+ select SERIAL_CORE
+ help
+ Support for the LPC32XX high speed serial ports (up to 900kbps).
+ Those are UARTs completely different from the Standard UARTs on the
+ LPC32XX SoC.
+ Choose M or Y here to build this driver.
+
+config SERIAL_HS_LPC32XX_CONSOLE
+ bool "Enable LPC32XX high speed UART serial console"
+ depends on SERIAL_HS_LPC32XX
+ select SERIAL_CORE_CONSOLE
+ help
+ If you would like to be able to use one of the high speed serial
+ ports on the LPC32XX as the console, you can do so by answering
+ Y to this option.
+
config SERIAL_CORE
tristate
--- linux-2.6.orig/drivers/tty/serial/Makefile
+++ linux-2.6/drivers/tty/serial/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_SERIAL_MUX) += mux.o
obj-$(CONFIG_SERIAL_68328) += 68328serial.o
obj-$(CONFIG_SERIAL_MCF) += mcf.o
obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o
+obj-$(CONFIG_SERIAL_HS_LPC32XX) += lpc32xx_hs.o
obj-$(CONFIG_SERIAL_DZ) += dz.o
obj-$(CONFIG_SERIAL_ZS) += zs.o
obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o
--- /dev/null
+++ linux-2.6/drivers/tty/serial/lpc32xx_hs.c
@@ -0,0 +1,810 @@
+/*
+ * High Speed Serial Ports on NXP LPC32xx SoC
+ *
+ * Authors: Kevin Wells <kevin.wells@nxp.com>
+ * Roland Stigge <stigge@antcom.de>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ * Copyright (C) 2012 Roland Stigge
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/sysrq.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/nmi.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/of.h>
+#include <mach/platform.h>
+#include <mach/hardware.h>
+
+/*
+ * High Speed UART register offsets
+ */
+#define LPC32XX_HSUART_FIFO(x) ((x) + 0x00)
+#define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04)
+#define LPC32XX_HSUART_IIR(x) ((x) + 0x08)
+#define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C)
+#define LPC32XX_HSUART_RATE(x) ((x) + 0x10)
+
+#define LPC32XX_HSU_BREAK_DATA (1 << 10)
+#define LPC32XX_HSU_ERROR_DATA (1 << 9)
+#define LPC32XX_HSU_RX_EMPTY (1 << 8)
+
+#define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF)
+#define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF)
+
+#define LPC32XX_HSU_TX_INT_SET (1 << 6)
+#define LPC32XX_HSU_RX_OE_INT (1 << 5)
+#define LPC32XX_HSU_BRK_INT (1 << 4)
+#define LPC32XX_HSU_FE_INT (1 << 3)
+#define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2)
+#define LPC32XX_HSU_RX_TRIG_INT (1 << 1)
+#define LPC32XX_HSU_TX_INT (1 << 0)
+
+#define LPC32XX_HSU_HRTS_INV (1 << 21)
+#define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19)
+#define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19)
+#define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19)
+#define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19)
+#define LPC32XX_HSU_HRTS_EN (1 << 18)
+#define LPC32XX_HSU_TMO_DISABLED (0x0 << 16)
+#define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16)
+#define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16)
+#define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16)
+#define LPC32XX_HSU_HCTS_INV (1 << 15)
+#define LPC32XX_HSU_HCTS_EN (1 << 14)
+#define LPC32XX_HSU_OFFSET(n) ((n) << 9)
+#define LPC32XX_HSU_BREAK (1 << 8)
+#define LPC32XX_HSU_ERR_INT_EN (1 << 7)
+#define LPC32XX_HSU_RX_INT_EN (1 << 6)
+#define LPC32XX_HSU_TX_INT_EN (1 << 5)
+#define LPC32XX_HSU_RX_TL1B (0x0 << 2)
+#define LPC32XX_HSU_RX_TL4B (0x1 << 2)
+#define LPC32XX_HSU_RX_TL8B (0x2 << 2)
+#define LPC32XX_HSU_RX_TL16B (0x3 << 2)
+#define LPC32XX_HSU_RX_TL32B (0x4 << 2)
+#define LPC32XX_HSU_RX_TL48B (0x5 << 2)
+#define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0)
+#define LPC32XX_HSU_TX_TL0B (0x0 << 0)
+#define LPC32XX_HSU_TX_TL4B (0x1 << 0)
+#define LPC32XX_HSU_TX_TL8B (0x2 << 0)
+#define LPC32XX_HSU_TX_TL16B (0x3 << 0)
+
+#define MODNAME "lpc32xx_hsuart"
+
+struct lpc32xx_hsuart_port {
+ struct uart_port port;
+};
+
+#define FIFO_READ_LIMIT 128
+#define MAX_PORTS 3
+#define LPC32XX_TTY_NAME "ttyTX"
+#define LPC32XX_TTY_MINOR_START 196
+#define LPC32XX_TTY_MAJOR 204
+static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
+
+#ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
+static void wait_for_xmit_empty(struct uart_port *port)
+{
+ unsigned int timeout = 10000;
+
+ do {
+ if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
+ port->membase))) == 0)
+ break;
+ if (--timeout == 0)
+ break;
+ udelay(1);
+ } while (1);
+}
+
+static void wait_for_xmit_ready(struct uart_port *port)
+{
+ unsigned int timeout = 10000;
+
+ while (1) {
+ if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
+ port->membase))) < 32)
+ break;
+ if (--timeout == 0)
+ break;
+ udelay(1);
+ }
+}
+
+static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch)
+{
+ wait_for_xmit_ready(port);
+ writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
+}
+
+static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
+ unsigned int count)
+{
+ struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
+ unsigned long flags;
+ int locked = 1;
+
+ touch_nmi_watchdog();
+ local_irq_save(flags);
+ if (up->port.sysrq)
+ locked = 0;
+ else if (oops_in_progress)
+ locked = spin_trylock(&up->port.lock);
+ else
+ spin_lock(&up->port.lock);
+
+ uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar);
+ wait_for_xmit_empty(&up->port);
+
+ if (locked)
+ spin_unlock(&up->port.lock);
+ local_irq_restore(flags);
+}
+
+static int __init lpc32xx_hsuart_console_setup(struct console *co,
+ char *options)
+{
+ struct uart_port *port;
+ int baud = 115200;
+ int bits = 8;
+ int parity = 'n';
+ int flow = 'n';
+
+ if (co->index >= MAX_PORTS)
+ co->index = 0;
+
+ port = &lpc32xx_hs_ports[co->index].port;
+ if (!port->membase)
+ return -ENODEV;
+
+ if (options)
+ uart_parse_options(options, &baud, &parity, &bits, &flow);
+
+ return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+static struct uart_driver lpc32xx_hsuart_reg;
+static struct console lpc32xx_hsuart_console = {
+ .name = LPC32XX_TTY_NAME,
+ .write = lpc32xx_hsuart_console_write,
+ .device = uart_console_device,
+ .setup = lpc32xx_hsuart_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+ .data = &lpc32xx_hsuart_reg,
+};
+
+static int __init lpc32xx_hsuart_console_init(void)
+{
+ register_console(&lpc32xx_hsuart_console);
+ return 0;
+}
+console_initcall(lpc32xx_hsuart_console_init);
+
+#define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console)
+#else
+#define LPC32XX_HSUART_CONSOLE NULL
+#endif
+
+static struct uart_driver lpc32xx_hs_reg = {
+ .owner = THIS_MODULE,
+ .driver_name = MODNAME,
+ .dev_name = LPC32XX_TTY_NAME,
+ .major = LPC32XX_TTY_MAJOR,
+ .minor = LPC32XX_TTY_MINOR_START,
+ .nr = MAX_PORTS,
+ .cons = LPC32XX_HSUART_CONSOLE,
+};
+static int uarts_registered;
+
+static unsigned int __serial_get_clock_div(unsigned long uartclk,
+ unsigned long rate)
+{
+ u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
+ u32 rate_diff;
+
+ /* Find the closest divider to get the desired clock rate */
+ div = uartclk / rate;
+ goodrate = hsu_rate = (div / 14) - 1;
+ if (hsu_rate != 0)
+ hsu_rate--;
+
+ /* Tweak divider */
+ l_hsu_rate = hsu_rate + 3;
+ rate_diff = 0xFFFFFFFF;
+
+ while (hsu_rate < l_hsu_rate) {
+ comprate = uartclk / ((hsu_rate + 1) * 14);
+ if (abs(comprate - rate) < rate_diff) {
+ goodrate = hsu_rate;
+ rate_diff = abs(comprate - rate);
+ }
+
+ hsu_rate++;
+ }
+ if (hsu_rate > 0xFF)
+ hsu_rate = 0xFF;
+
+ return goodrate;
+}
+
+static void __serial_uart_flush(struct uart_port *port)
+{
+ u32 tmp;
+ int cnt = 0;
+
+ while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
+ (cnt++ < FIFO_READ_LIMIT))
+ tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
+}
+
+static void __serial_lpc32xx_rx(struct uart_port *port)
+{
+ unsigned int tmp, flag;
+
+ /* Read data from FIFO and push into terminal */
+ tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
+ while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
+ flag = TTY_NORMAL;
+ port->icount.rx++;
+
+ if (tmp & LPC32XX_HSU_ERROR_DATA) {
+ /* Framing error */
+ writel(LPC32XX_HSU_FE_INT,
+ LPC32XX_HSUART_IIR(port->membase));
+ port->icount.frame++;
+ flag = TTY_FRAME;
+ tty_insert_flip_char(port->state->port.tty, 0,
+ TTY_FRAME);
+ tty_schedule_flip(port->state->port.tty);
+ }
+
+ tty_insert_flip_char(port->state->port.tty, (tmp & 0xFF), flag);
+
+ tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
+ }
+}
+
+static void __serial_lpc32xx_tx(struct uart_port *port)
+{
+ struct circ_buf *xmit = &port->state->xmit;
+ unsigned int tmp;
+
+ if (port->x_char) {
+ writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase));
+ port->icount.tx++;
+ port->x_char = 0;
+ return;
+ }
+
+ if (uart_circ_empty(xmit) || uart_tx_stopped(port))
+ goto exit_tx;
+
+ /* Transfer data */
+ while (LPC32XX_HSU_TX_LEV(readl(
+ LPC32XX_HSUART_LEVEL(port->membase))) < 64) {
+ writel((u32) xmit->buf[xmit->tail],
+ LPC32XX_HSUART_FIFO(port->membase));
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ port->icount.tx++;
+ if (uart_circ_empty(xmit))
+ break;
+ }
+
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ uart_write_wakeup(port);
+
+exit_tx:
+ if (uart_circ_empty(xmit)) {
+ tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
+ tmp &= ~LPC32XX_HSU_TX_INT_EN;
+ writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
+ }
+}
+
+static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
+{
+ struct uart_port *port = dev_id;
+ u32 status;
+
+ spin_lock(&port->lock);
+
+ /* Read UART status and clear latched interrupts */
+ status = readl(LPC32XX_HSUART_IIR(port->membase));
+
+ if (status & LPC32XX_HSU_BRK_INT) {
+ /* Break received */
+ writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase));
+ port->icount.brk++;
+ uart_handle_break(port);
+ }
+
+ /* Framing error */
+ if (status & LPC32XX_HSU_FE_INT)
+ writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase));
+
+ if (status & LPC32XX_HSU_RX_OE_INT) {
+ /* Receive FIFO overrun */
+ writel(LPC32XX_HSU_RX_OE_INT,
+ LPC32XX_HSUART_IIR(port->membase));
+ port->icount.overrun++;
+ tty_insert_flip_char(port->state->port.tty, 0, TTY_OVERRUN);
+ tty_schedule_flip(port->state->port.tty);
+ }
+
+ /* Data received? */
+ if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT)) {
+ __serial_lpc32xx_rx(port);
+ spin_unlock(&port->lock);
+ tty_flip_buffer_push(port->state->port.tty);
+ spin_lock(&port->lock);
+ }
+
+ /* Transmit data request? */
+ if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
+ writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase));
+ __serial_lpc32xx_tx(port);
+ }
+
+ spin_unlock(&port->lock);
+
+ return IRQ_HANDLED;
+}
+
+/* port->lock is not held. */
+static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
+{
+ unsigned int ret = 0;
+
+ if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0)
+ ret = TIOCSER_TEMT;
+
+ return ret;
+}
+
+/* port->lock held by caller. */
+static void serial_lpc32xx_set_mctrl(struct uart_port *port,
+ unsigned int mctrl)
+{
+ /* No signals are supported on HS UARTs */
+}
+
+/* port->lock is held by caller and interrupts are disabled. */
+static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
+{
+ /* No signals are supported on HS UARTs */
+ return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
+}
+
+/* port->lock held by caller. */
+static void serial_lpc32xx_stop_tx(struct uart_port *port)
+{
+ u32 tmp;
+
+ tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
+ tmp &= ~LPC32XX_HSU_TX_INT_EN;
+ writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
+}
+
+/* port->lock held by caller. */
+static void serial_lpc32xx_start_tx(struct uart_port *port)
+{
+ u32 tmp;
+
+ __serial_lpc32xx_tx(port);
+ tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
+ tmp |= LPC32XX_HSU_TX_INT_EN;
+ writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
+}
+
+/* port->lock held by caller. */
+static void serial_lpc32xx_stop_rx(struct uart_port *port)
+{
+ u32 tmp;
+
+ tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
+ tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
+ writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
+
+ writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
+ LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
+}
+
+/* port->lock held by caller. */
+static void serial_lpc32xx_enable_ms(struct uart_port *port)
+{
+ /* Modem status is not supported */
+}
+
+/* port->lock is not held. */
+static void serial_lpc32xx_break_ctl(struct uart_port *port,
+ int break_state)
+{
+ unsigned long flags;
+ u32 tmp;
+
+ spin_lock_irqsave(&port->lock, flags);
+ tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
+ if (break_state != 0)
+ tmp |= LPC32XX_HSU_BREAK;
+ else
+ tmp &= ~LPC32XX_HSU_BREAK;
+ writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
+static void lpc32xx_loopback_set(resource_size_t mapbase, int state)
+{
+ int bit;
+ u32 tmp;
+
+ switch (mapbase) {
+ case LPC32XX_HS_UART1_BASE:
+ bit = 0;
+ break;
+ case LPC32XX_HS_UART2_BASE:
+ bit = 1;
+ break;
+ case LPC32XX_HS_UART7_BASE:
+ bit = 6;
+ break;
+ default:
+ WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
+ return;
+ }
+
+ tmp = readl(LPC32XX_UARTCTL_CLOOP);
+ if (state)
+ tmp |= (1 << bit);
+ else
+ tmp &= ~(1 << bit);
+ writel(tmp, LPC32XX_UARTCTL_CLOOP);
+}
+
+/* port->lock is not held. */
+static int serial_lpc32xx_startup(struct uart_port *port)
+{
+ int retval;
+ unsigned long flags;
+ u32 tmp;
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ __serial_uart_flush(port);
+
+ writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
+ LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
+ LPC32XX_HSUART_IIR(port->membase));
+
+ writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
+
+ /*
+ * Set receiver timeout, HSU offset of 20, no break, no interrupts,
+ * and default FIFO trigger levels
+ */
+ tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
+ LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
+ writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
+
+ lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
+
+ spin_unlock_irqrestore(&port->lock, flags);
+
+ retval = request_irq(port->irq, serial_lpc32xx_interrupt,
+ 0, MODNAME, port);
+ if (!retval)
+ writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
+ LPC32XX_HSUART_CTRL(port->membase));
+
+ return retval;
+}
+
+/* port->lock is not held. */
+static void serial_lpc32xx_shutdown(struct uart_port *port)
+{
+ u32 tmp;
+ unsigned long flags;
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
+ LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
+ writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
+
+ lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */
+
+ spin_unlock_irqrestore(&port->lock, flags);
+
+ free_irq(port->irq, port);
+}
+
+/* port->lock is not held. */
+static void serial_lpc32xx_set_termios(struct uart_port *port,
+ struct ktermios *termios,
+ struct ktermios *old)
+{
+ unsigned long flags;
+ unsigned int baud, quot;
+ u32 tmp;
+
+ /* Always 8-bit, no parity, 1 stop bit */
+ termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
+ termios->c_cflag |= CS8;
+
+ termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
+
+ baud = uart_get_baud_rate(port, termios, old, 0,
+ port->uartclk / 14);
+
+ quot = __serial_get_clock_div(port->uartclk, baud);
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ /* Ignore characters? */
+ tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
+ if ((termios->c_cflag & CREAD) == 0)
+ tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
+ else
+ tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
+ writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
+
+ writel(quot, LPC32XX_HSUART_RATE(port->membase));
+
+ uart_update_timeout(port, termios->c_cflag, baud);
+
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static const char *serial_lpc32xx_type(struct uart_port *port)
+{
+ return MODNAME;
+}
+
+static void serial_lpc32xx_release_port(struct uart_port *port)
+{
+ if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
+ if (port->flags & UPF_IOREMAP) {
+ iounmap(port->membase);
+ port->membase = NULL;
+ }
+
+ release_mem_region(port->mapbase, SZ_4K);
+ }
+}
+
+static int serial_lpc32xx_request_port(struct uart_port *port)
+{
+ int ret = -ENODEV;
+
+ if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
+ ret = 0;
+
+ if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
+ ret = -EBUSY;
+ else if (port->flags & UPF_IOREMAP) {
+ port->membase = ioremap(port->mapbase, SZ_4K);
+ if (!port->membase) {
+ release_mem_region(port->mapbase, SZ_4K);
+ ret = -ENOMEM;
+ }
+ }
+ }
+
+ return ret;
+}
+
+static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
+{
+ int ret;
+
+ ret = serial_lpc32xx_request_port(port);
+ if (ret < 0)
+ return;
+ port->type = PORT_UART00;
+ port->fifosize = 64;
+
+ __serial_uart_flush(port);
+
+ writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
+ LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
+ LPC32XX_HSUART_IIR(port->membase));
+
+ writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
+
+ /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
+ and default FIFO trigger levels */
+ writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
+ LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
+ LPC32XX_HSUART_CTRL(port->membase));
+}
+
+static int serial_lpc32xx_verify_port(struct uart_port *port,
+ struct serial_struct *ser)
+{
+ int ret = 0;
+
+ if (ser->type != PORT_UART00)
+ ret = -EINVAL;
+
+ return ret;
+}
+
+static struct uart_ops serial_lpc32xx_pops = {
+ .tx_empty = serial_lpc32xx_tx_empty,
+ .set_mctrl = serial_lpc32xx_set_mctrl,
+ .get_mctrl = serial_lpc32xx_get_mctrl,
+ .stop_tx = serial_lpc32xx_stop_tx,
+ .start_tx = serial_lpc32xx_start_tx,
+ .stop_rx = serial_lpc32xx_stop_rx,
+ .enable_ms = serial_lpc32xx_enable_ms,
+ .break_ctl = serial_lpc32xx_break_ctl,
+ .startup = serial_lpc32xx_startup,
+ .shutdown = serial_lpc32xx_shutdown,
+ .set_termios = serial_lpc32xx_set_termios,
+ .type = serial_lpc32xx_type,
+ .release_port = serial_lpc32xx_release_port,
+ .request_port = serial_lpc32xx_request_port,
+ .config_port = serial_lpc32xx_config_port,
+ .verify_port = serial_lpc32xx_verify_port,
+};
+
+/*
+ * Register a set of serial devices attached to a platform device
+ */
+static int __devinit serial_hs_lpc32xx_probe(struct platform_device *pdev)
+{
+ struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered];
+ int ret = 0;
+ struct resource *res;
+
+ if (uarts_registered >= MAX_PORTS) {
+ dev_err(&pdev->dev,
+ "Error: Number of possible ports exceeded (%d)!\n",
+ uarts_registered + 1);
+ return -ENXIO;
+ }
+
+ memset(p, 0, sizeof(*p));
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev,
+ "Error getting mem resource for HS UART port %d\n",
+ uarts_registered);
+ return -ENXIO;
+ }
+ p->port.mapbase = res->start;
+ p->port.membase = NULL;
+
+ p->port.irq = platform_get_irq(pdev, 0);
+ if (p->port.irq < 0) {
+ dev_err(&pdev->dev, "Error getting irq for HS UART port %d\n",
+ uarts_registered);
+ return p->port.irq;
+ }
+
+ p->port.iotype = UPIO_MEM32;
+ p->port.uartclk = LPC32XX_MAIN_OSC_FREQ;
+ p->port.regshift = 2;
+ p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP;
+ p->port.dev = &pdev->dev;
+ p->port.ops = &serial_lpc32xx_pops;
+ p->port.line = uarts_registered++;
+ spin_lock_init(&p->port.lock);
+
+ /* send port to loopback mode by default */
+ lpc32xx_loopback_set(p->port.mapbase, 1);
+
+ ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port);
+
+ platform_set_drvdata(pdev, p);
+
+ return ret;
+}
+
+/*
+ * Remove serial ports registered against a platform device.
+ */
+static int __devexit serial_hs_lpc32xx_remove(struct platform_device *pdev)
+{
+ struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
+
+ uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
+
+ return 0;
+}
+
+
+#ifdef CONFIG_PM
+static int serial_hs_lpc32xx_suspend(struct platform_device *pdev,
+ pm_message_t state)
+{
+ struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
+
+ uart_suspend_port(&lpc32xx_hs_reg, &p->port);
+
+ return 0;
+}
+
+static int serial_hs_lpc32xx_resume(struct platform_device *pdev)
+{
+ struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
+
+ uart_resume_port(&lpc32xx_hs_reg, &p->port);
+
+ return 0;
+}
+#else
+#define serial_hs_lpc32xx_suspend NULL
+#define serial_hs_lpc32xx_resume NULL
+#endif
+
+static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = {
+ { .compatible = "nxp,lpc3220-hsuart" },
+ { /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids);
+
+static struct platform_driver serial_hs_lpc32xx_driver = {
+ .probe = serial_hs_lpc32xx_probe,
+ .remove = __devexit_p(serial_hs_lpc32xx_remove),
+ .suspend = serial_hs_lpc32xx_suspend,
+ .resume = serial_hs_lpc32xx_resume,
+ .driver = {
+ .name = MODNAME,
+ .owner = THIS_MODULE,
+ .of_match_table = serial_hs_lpc32xx_dt_ids,
+ },
+};
+
+static int __init lpc32xx_hsuart_init(void)
+{
+ int ret;
+
+ ret = uart_register_driver(&lpc32xx_hs_reg);
+ if (ret)
+ return ret;
+
+ ret = platform_driver_register(&serial_hs_lpc32xx_driver);
+ if (ret)
+ uart_unregister_driver(&lpc32xx_hs_reg);
+
+ return ret;
+}
+
+static void __exit lpc32xx_hsuart_exit(void)
+{
+ platform_driver_unregister(&serial_hs_lpc32xx_driver);
+ uart_unregister_driver(&lpc32xx_hs_reg);
+}
+
+module_init(lpc32xx_hsuart_init);
+module_exit(lpc32xx_hsuart_exit);
+
+MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
+MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
+MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver");
+MODULE_LICENSE("GPL");
^ permalink raw reply
* RE: [PATCH] serial: samsung: protect NULL dereference of clock name
From: Kyoungil Kim @ 2012-05-30 9:28 UTC (permalink / raw)
To: 'Shubhrajyoti Datta'
Cc: linux-arm-kernel, linux-samsung-soc, linux-serial,
'Kukjin Kim', 'Alan Cox', 'KeyYoung Park',
'Huisung Kang'
In-Reply-To: <CAM=Q2csPTE=5sc+kxnW6d+trf04OknFtRoxq4NGu8PkoAhOOxg@mail.gmail.com>
Shubhrajyoti Datta wrote:
> Hi Kim,
> On Wed, May 30, 2012 at 1:59 PM, Kyoungil Kim <ki0351.kim@samsung.com> wrote:
> > From: KeyYoung Park <keyyoung.park@samsung.com>
> >
> > When priting the serial clock source, if clock source name is null,
> > kernel reference NULL point.
> >
> Could you help me understand why is that NULL ? Or the crash that you saw.
When you want to see the serial clock source name like using cat command before you open the tty,
You can see the kernel crash.
I know this is not normal scenario.
This patch just prevents the kernel panic.
^ permalink raw reply
* Re: [PATCH] serial: samsung: protect NULL dereference of clock name
From: Shubhrajyoti Datta @ 2012-05-30 9:07 UTC (permalink / raw)
To: Kyoungil Kim
Cc: linux-arm-kernel, linux-samsung-soc, linux-serial, Kukjin Kim,
Alan Cox, KeyYoung Park, Huisung Kang
In-Reply-To: <001401cd3e3e$644fd3a0$2cef7ae0$%kim@samsung.com>
Hi Kim,
On Wed, May 30, 2012 at 1:59 PM, Kyoungil Kim <ki0351.kim@samsung.com> wrote:
> From: KeyYoung Park <keyyoung.park@samsung.com>
>
> When priting the serial clock source, if clock source name is null,
> kernel reference NULL point.
>
Could you help me understand why is that NULL ? Or the crash that you saw.
^ permalink raw reply
* [PATCH] serial: samsung: protect NULL dereference of clock name
From: Kyoungil Kim @ 2012-05-30 8:29 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc, linux-serial
Cc: 'Kukjin Kim', 'Alan Cox', 'Kyoungil Kim',
'KeyYoung Park', 'Huisung Kang'
From: KeyYoung Park <keyyoung.park@samsung.com>
When priting the serial clock source, if clock source name is null,
kernel reference NULL point.
Signed-off-by: KeyYoung Park <keyyoung.park@samsung.com>
Signed-off-by: Huisung Kang <hs1218.kang@samsung.com>
Signed-off-by: Kyoungil Kim <ki0351.kim@samsung.com>
---
drivers/tty/serial/samsung.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index ea76b40..77484e0 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1160,7 +1160,8 @@ static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
struct uart_port *port = s3c24xx_dev_to_port(dev);
struct s3c24xx_uart_port *ourport = to_ourport(port);
- return snprintf(buf, PAGE_SIZE, "* %s\n", ourport->baudclk->name);
+ return snprintf(buf, PAGE_SIZE, "* %s\n",
+ ourport->baudclk->name ?: "(null)");
}
static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
--
1.7.1
^ permalink raw reply related
* Re: Using the MAX3107
From: Alan Cox @ 2012-05-29 15:55 UTC (permalink / raw)
To: Ubdfu; +Cc: linux-serial
In-Reply-To: <4FC4E511.7010501@student.kit.edu>
On Tue, 29 May 2012 17:02:41 +0200
Ubdfu <ubdfu@student.kit.edu> wrote:
> Hello,
>
> Please excuse my and be aware that I'm quite new to kernel hacking :-)
>
> I'm currently trying to enable the RS485 support on the MAX3107 and
> continuously getting the error:
> "max3107 spi2.0: interrup isn't serviced normally!"
> Assuming it means interrupt it nevertheless does not help me to find the
> cause of the problem.
>
> Added some patches form:
> http://marc.info/?l=linux-serial&w=2&r=1&s=max3107&q=b
>
> And changed the baudrate to the appropriate, set bit for rs458 mode.
>
> Has anyone tried working with the MAX3107?
Not in rs485 mode and not for a while. The base code in drivers/tty/serial
should work for RS232 mode at least.
The trigger you are hitting implies that it got an event during
suspend/freezing or somehow tried to queue work when work was already
queued.
The current code doesn't cope with the device being on a shared interrupt
line, so my first guess would be that might be the problem ?
Alan
^ permalink raw reply
* Re: [PATCH 1/2] serial/8250: Add LPC3220 standard UART type
From: Arnd Bergmann @ 2012-05-29 15:39 UTC (permalink / raw)
To: Roland Stigge
Cc: alan, gregkh, linux-serial, linux-kernel, kevin.wells,
srinivas.bakki, linux-arm-kernel, linux
In-Reply-To: <1338282570-19799-1-git-send-email-stigge@antcom.de>
On Tuesday 29 May 2012, Roland Stigge wrote:
>
> LPC32xx has "Standard" UARTs that are actually 16550A compatible but have
> bigger FIFOs. Since the already supported 16X50 line still doesn't match here,
> we agreed on adding a new type.
>
> Signed-off-by: Roland Stigge <stigge@antcom.de>
>
Acked-by: Arnd Bergmann <arnd@arndb.de>
^ permalink raw reply
* Using the MAX3107
From: Ubdfu @ 2012-05-29 15:02 UTC (permalink / raw)
To: linux-serial
Hello,
Please excuse my and be aware that I'm quite new to kernel hacking :-)
I'm currently trying to enable the RS485 support on the MAX3107 and
continuously getting the error:
"max3107 spi2.0: interrup isn't serviced normally!"
Assuming it means interrupt it nevertheless does not help me to find the
cause of the problem.
Added some patches form:
http://marc.info/?l=linux-serial&w=2&r=1&s=max3107&q=b
And changed the baudrate to the appropriate, set bit for rs458 mode.
Has anyone tried working with the MAX3107?
Thanks in advance
Marcel
^ permalink raw reply
* Re: struct tty_flip_buffer replacement in newer kernels
From: Alan Cox @ 2012-05-29 10:41 UTC (permalink / raw)
To: Dmitriy Alekseev
Cc: linux-serial@vger.kernel.org,
Юрий Зверев
In-Reply-To: <1338273996.59244.YahooMailNeo@web44910.mail.sp1.yahoo.com>
On Mon, 28 May 2012 23:46:36 -0700 (PDT)
Dmitriy Alekseev <alexeev6@yahoo.com> wrote:
> Sorry, that means, most probably I don't understand something. The IC ST16C554D combines the package interface modes of the 16C554 and 68C554 series on a single integrated chip. Earlier, I assumed, 8250.c is supporting both modes of the circuit.
> Unfortunately I didn't understand the code of 8250.c enough to realise is 68 mode supported or not.
Thats an electrical signal difference not an interface one as I understand
it (beyond the fact it might change the register offsets depending how
the board was wired)
I don't think it matters therefore.
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^ permalink raw reply
* Re: [PATCH 1/2] serial/8250: Add LPC3220 standard UART type
From: Alan Cox @ 2012-05-29 10:04 UTC (permalink / raw)
To: Roland Stigge
Cc: alan, gregkh, linux-serial, linux-kernel, kevin.wells,
srinivas.bakki, linux-arm-kernel, arnd, linux
In-Reply-To: <1338282570-19799-1-git-send-email-stigge@antcom.de>
On Tue, 29 May 2012 11:09:29 +0200
Roland Stigge <stigge@antcom.de> wrote:
> LPC32xx has "Standard" UARTs that are actually 16550A compatible but have
> bigger FIFOs. Since the already supported 16X50 line still doesn't match here,
> we agreed on adding a new type.
>
> Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Alan Cox <alan@linux.intel.com>
^ permalink raw reply
* [PATCH 1/2] serial/8250: Add LPC3220 standard UART type
From: Roland Stigge @ 2012-05-29 9:09 UTC (permalink / raw)
To: alan, gregkh, linux-serial, linux-kernel, kevin.wells,
srinivas.bakki, linux-arm-kernel, arnd, linux
Cc: Roland Stigge
LPC32xx has "Standard" UARTs that are actually 16550A compatible but have
bigger FIFOs. Since the already supported 16X50 line still doesn't match here,
we agreed on adding a new type.
Signed-off-by: Roland Stigge <stigge@antcom.de>
---
Applies to v3.4
drivers/tty/serial/8250/8250.c | 8 ++++++++
include/linux/serial_core.h | 3 ++-
2 files changed, 10 insertions(+), 1 deletion(-)
--- linux-2.6.orig/drivers/tty/serial/8250/8250.c
+++ linux-2.6/drivers/tty/serial/8250/8250.c
@@ -282,6 +282,14 @@ static const struct serial8250_config ua
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
},
+ [PORT_LPC3220] = {
+ .name = "LPC3220",
+ .fifo_size = 64,
+ .tx_loadsz = 32,
+ .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
+ UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
+ .flags = UART_CAP_FIFO,
+ },
};
#if defined(CONFIG_MIPS_ALCHEMY)
--- linux-2.6.orig/include/linux/serial_core.h
+++ linux-2.6/include/linux/serial_core.h
@@ -47,7 +47,8 @@
#define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
#define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
#define PORT_XR17D15X 21 /* Exar XR17D15x UART */
-#define PORT_MAX_8250 21 /* max port ID */
+#define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */
+#define PORT_MAX_8250 22 /* max port ID */
/*
* ARM specific type numbers. These are not currently guaranteed
^ permalink raw reply
* [PATCH 2/2] serial/of-serial: Add LPC3220 standard UART compatible string
From: Roland Stigge @ 2012-05-29 9:09 UTC (permalink / raw)
To: alan, gregkh, linux-serial, linux-kernel, kevin.wells,
srinivas.bakki, linux-arm-kernel, arnd, linux
Cc: Roland Stigge
In-Reply-To: <1338282570-19799-1-git-send-email-stigge@antcom.de>
This patch adds a "compatible" string for the new 8250 UART type PORT_LPC3220.
Signed-off-by: Roland Stigge <stigge@antcom.de>
---
Applies to v 3.4
Documentation/devicetree/bindings/tty/serial/of-serial.txt | 1 +
drivers/tty/serial/of_serial.c | 1 +
2 files changed, 2 insertions(+)
--- linux-2.6.orig/Documentation/devicetree/bindings/tty/serial/of-serial.txt
+++ linux-2.6/Documentation/devicetree/bindings/tty/serial/of-serial.txt
@@ -9,6 +9,7 @@ Required properties:
- "ns16750"
- "ns16850"
- "nvidia,tegra20-uart"
+ - "nxp,lpc3220-uart"
- "ibm,qpace-nwp-serial"
- "serial" if the port type is unknown.
- reg : offset and length of the register set for the device.
--- linux-2.6.orig/drivers/tty/serial/of_serial.c
+++ linux-2.6/drivers/tty/serial/of_serial.c
@@ -182,6 +182,7 @@ static struct of_device_id __devinitdata
{ .compatible = "ns16750", .data = (void *)PORT_16750, },
{ .compatible = "ns16850", .data = (void *)PORT_16850, },
{ .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },
+ { .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL
{ .compatible = "ibm,qpace-nwp-serial",
.data = (void *)PORT_NWPSERIAL, },
^ permalink raw reply
* RE: Questions regarding adding a patch in linux/drivers/char/8250.c
From: Donald @ 2012-05-29 8:37 UTC (permalink / raw)
To: 'Alan Cox'; +Cc: linux-serial
In-Reply-To: <20120521102848.7bfb49e0@pyramind.ukuu.org.uk>
Hi Alan,
Sorry for my late reply. Below are my answers for your questions in previous emails:
1. Regarding how to detect the presence of the UART devices with this erratum, it's feasible to check the device's vendor
identification, which can be acquired by using " container_of" macro.
2. Regarding doing parity check by software, it's not feasible mainly because that the parity bit will be stripped off by the
hardware, the software can only get the data portion; hence no chance to do parity check.
3. Regarding the performance concern of the proposed software workaround, we had been verified this workaround and didn't see any
performance issue. For example, in a file transfer test at 115200 bps, the performance and CPU utilization rate are almost the same
between test drivers with and without this workaround.
4. Below is the complete patch for your preview, upon your approve, I will submit the formal patch by another email. Thank you for
your help.
drivers/tty/serial/8250/8250.c | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/drivers/tty/serial/8250/8250.c b/drivers/tty/serial/8250/8250.c
index 5c27f7e..be493b0 100644
--- a/drivers/tty/serial/8250/8250.c
+++ b/drivers/tty/serial/8250/8250.c
@@ -38,6 +38,7 @@
#include <linux/nmi.h>
#include <linux/mutex.h>
#include <linux/slab.h>
+#include <linux/pci.h>
#ifdef CONFIG_SPARC
#include <linux/sunserialcore.h>
#endif
@@ -2238,6 +2239,8 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
unsigned long flags;
unsigned int baud, quot;
+ struct pci_dev *pdev = container_of(port->dev, struct pci_dev, dev);
+
switch (termios->c_cflag & CSIZE) {
case CS5:
cval = UART_LCR_WLEN5;
@@ -2351,6 +2354,13 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
if (up->capabilities & UART_CAP_RTOIE)
up->ier |= UART_IER_RTOIE;
+ if ((termios->c_cflag & PARENB) && (pdev->vendor == 0x9710)) {
+ fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
+ up->ier &= ~UART_IER_RLSI;
+ } else {
+ up->ier |= UART_IER_RLSI;
+ }
+
serial_port_out(port, UART_IER, up->ier);
if (up->capabilities & UART_CAP_EFR) {
--
1.7.7.6
Regards,
Donald
-----Original Message-----
From: Alan Cox [mailto:alan@lxorguk.ukuu.org.uk]
Sent: Monday, May 21, 2012 5:29 PM
To: Donald
Cc: linux-serial@vger.kernel.org
Subject: Re: Questions regarding adding a patch in linux/drivers/char/8250.c
On Mon, 21 May 2012 14:19:34 +0800
"Donald" <donald@asix.com.tw> wrote:
> Hi,
>
> This is Donald from ASIX Electronics Corp. My company has three PCI to Serial controllers, including MCS9845, MCS9835, and
MCS9820.
> Currently those serial devices using these three chips can directly
> use the Linux kernel's serial driver in linux/drivers/char/8250.c.
> Recently we find these three chips have a hardware bug relating to parity error count function. We have a software workaround for
this issue. Below for reference is a pseudo code for this workaround.
>
> serial8250_do_set_termios() {
> If ((PID == MCS9845 || PID == MCS935 || PID == MCS9820) && ((termios->c_cflag & PARENB))) {
> port->fifosize = 1; /* Change RX FIFO size to 1 byte */
> up->ier &= ~UART_IER_RLSI; /* Disable RLSI interrupt */
> }
> }
>
> Is it possible to add a patch into linux/drivers/char/8250.c for our chips' hardware issue?
Sure.
The only question I would have is how do we reliably detect the presence of the UART devices with this erratum. Can we do it from
the PCI identifier ?
Alan
^ permalink raw reply related
* Re: struct tty_flip_buffer replacement in newer kernels
From: Dmitriy Alekseev @ 2012-05-29 6:46 UTC (permalink / raw)
To: Alan Cox
Cc: linux-serial@vger.kernel.org,
Юрий Зверев
In-Reply-To: <20120528181251.7d5e6d9b@pyramind.ukuu.org.uk>
Sorry, that means, most probably I don't understand something. The IC ST16C554D combines the package interface modes of the 16C554 and 68C554 series on a single integrated chip. Earlier, I assumed, 8250.c is supporting both modes of the circuit.
Unfortunately I didn't understand the code of 8250.c enough to realise is 68 mode supported or not.
Best regards,
Dmitriy Alekseev
----- Original Message -----
From: Alan Cox <alan@lxorguk.ukuu.org.uk>
To: Dmitriy Alekseev <alexeev6@yahoo.com>
Cc: "linux-serial@vger.kernel.org" <linux-serial@vger.kernel.org>; Юрий Зверев <yury.zverev@gmail.com>
Sent: Monday, May 28, 2012 9:12 PM
Subject: Re: struct tty_flip_buffer replacement in newer kernels
On Mon, 28 May 2012 05:40:15 -0700 (PDT)
Dmitriy Alekseev <alexeev6@yahoo.com> wrote:
> Hi,
>
> My st16c554 chip is connected with cpu (at91rm9200) in 68 (Motorola) mode, and formally works as 68c554.
> Is 8250 driver supports the 68 mode?
> I thought the driver maintains whole 16c554 IC, or it means only mode 16 is supported?
Not sure I understand the question
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^ permalink raw reply
* [PATCH] 8250_pci: Remove duplicate struct pciserial_board
From: Shawn Bohrer @ 2012-05-28 20:20 UTC (permalink / raw)
To: Alan Cox; +Cc: Greg Kroah-Hartman, linux-serial, linux-kernel, Shawn Bohrer
pbn_exsys_4055 is the same thing as pbn_b2_4_115200 so replace it with
the standard pattern.
Signed-off-by: Shawn Bohrer <shawn.bohrer@gmail.com>
---
drivers/tty/serial/8250/8250_pci.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c
index 28e7c7c..66e5909 100644
--- a/drivers/tty/serial/8250/8250_pci.c
+++ b/drivers/tty/serial/8250/8250_pci.c
@@ -1887,7 +1887,6 @@ enum pci_board_num_t {
pbn_panacom,
pbn_panacom2,
pbn_panacom4,
- pbn_exsys_4055,
pbn_plx_romulus,
pbn_oxsemi,
pbn_oxsemi_1_4000000,
@@ -2393,13 +2392,6 @@ static struct pciserial_board pci_boards[] __devinitdata = {
.reg_shift = 7,
},
- [pbn_exsys_4055] = {
- .flags = FL_BASE2,
- .num_ports = 4,
- .base_baud = 115200,
- .uart_offset = 8,
- },
-
/* I think this entry is broken - the first_offset looks wrong --rmk */
[pbn_plx_romulus] = {
.flags = FL_BASE2,
@@ -3193,7 +3185,7 @@ static struct pci_device_id serial_pci_tbl[] = {
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
PCI_SUBVENDOR_ID_EXSYS,
PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
- pbn_exsys_4055 },
+ pbn_b2_4_115200 },
/*
* Megawolf Romulus PCI Serial Card, from Mike Hudson
* (Exoray@isys.ca)
--
1.7.10.2
^ permalink raw reply related
* Re: [PATCH] serial/of-serial: Add 16654 chip to compatible string list
From: Russell King - ARM Linux @ 2012-05-28 18:39 UTC (permalink / raw)
To: Roland Stigge
Cc: alan, gregkh, linux-serial, linux-kernel, kevin.wells,
srinivas.bakki, linux-arm-kernel, arnd
In-Reply-To: <4FC3C156.5040609@antcom.de>
On Mon, May 28, 2012 at 08:17:58PM +0200, Roland Stigge wrote:
> On 28/05/12 20:01, Russell King - ARM Linux wrote:
> >> Now, introducing a new type, can I add to 8250.c's uart_config[] by
> >> introducing a new type (no. 22) after PORT_XR17D15X? Unfortunately,
> >> there are the "ARM specific type numbers" after current PORT_MAX_8250
> >> (21), but those are not listed in 8250.c's uart_config[]. Or how am I
> >> supposed to add a new type?
> >
> > If it's 8250, stick it in with the group, otherwise the array will
> > become stupidly large. That's why there's a separation of the two.
>
> Do you mean adding one element to uart_config[] and increasing
> PORT_MAX_8250 (actually, the size of uart_config[]) by one? I would also
> need to increase the indices of all the following "ARM specific type
> numbers" by one (the second group).
#define PORT_XR17D15X 21 /* Exar XR17D15x UART */
#define PORT_MAX_8250 21 /* max port ID */
#define PORT_PXA 31
There's space between 21 and 31...
^ permalink raw reply
* Re: [PATCH] serial/of-serial: Add 16654 chip to compatible string list
From: Roland Stigge @ 2012-05-28 18:17 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: srinivas.bakki, arnd, gregkh, linux-kernel, kevin.wells,
linux-serial, linux-arm-kernel, alan
In-Reply-To: <20120528180139.GC28290@n2100.arm.linux.org.uk>
On 28/05/12 20:01, Russell King - ARM Linux wrote:
>> Now, introducing a new type, can I add to 8250.c's uart_config[] by
>> introducing a new type (no. 22) after PORT_XR17D15X? Unfortunately,
>> there are the "ARM specific type numbers" after current PORT_MAX_8250
>> (21), but those are not listed in 8250.c's uart_config[]. Or how am I
>> supposed to add a new type?
>
> If it's 8250, stick it in with the group, otherwise the array will
> become stupidly large. That's why there's a separation of the two.
Do you mean adding one element to uart_config[] and increasing
PORT_MAX_8250 (actually, the size of uart_config[]) by one? I would also
need to increase the indices of all the following "ARM specific type
numbers" by one (the second group).
Or did I get sth. wrong here?
Thanks in advance,
Roland
^ permalink raw reply
* Re: [PATCH] serial/of-serial: Add 16654 chip to compatible string list
From: Russell King - ARM Linux @ 2012-05-28 18:01 UTC (permalink / raw)
To: Roland Stigge
Cc: alan, gregkh, linux-serial, linux-kernel, kevin.wells,
srinivas.bakki, linux-arm-kernel, arnd
In-Reply-To: <4FC3BA89.4060804@antcom.de>
On Mon, May 28, 2012 at 07:48:57PM +0200, Roland Stigge wrote:
> On 28/05/12 18:31, Russell King - ARM Linux wrote:
> >>>> So maybe 16750 is the better choice for me, anyway. Already supported in
> >>>> of-serial. Works for now, but need more testing. Another hint is that
> >>>> 16750 is advertised as "IP core for Soc" which matches the case of LPC32xx.
> >>>
> >>> 16750 also has automatic hardware flow control support, selectable through
> >>> bit 5 in the MCR register. If your UART has that, then it's probably a
> >>> 16750 derivative rather than a 16550 or 16650 derivative.
> >>>
> >>> 16650s have an EFR register at offset 2, selectable by writing 0xBF into
> >>> the LCR register, which the 16750 doesn't have. 16650 also has automatic
> >>> hardware flow control, bit this is selected through a couple of bits in
> >>> the EFR.
> >>
> >> The 4 LPC32xx's "Standard" UARTs have neither of those.
> >>
> >> Is it ok to use "ns16650", i.e. PORT_16650, or do I need to introduce a
> >> FIFO depth configuration?
> >
> > I think you need a new type, because as I said above, 16650s have that
> > additional EFR, and we will attempt to access that register which
> > isn't present in yours.
>
> I actually meant 16750 instead of 16650, sorry, but this basically means
> the same - I would refer to extensions that are actually not there...
>
> Now, introducing a new type, can I add to 8250.c's uart_config[] by
> introducing a new type (no. 22) after PORT_XR17D15X? Unfortunately,
> there are the "ARM specific type numbers" after current PORT_MAX_8250
> (21), but those are not listed in 8250.c's uart_config[]. Or how am I
> supposed to add a new type?
If it's 8250, stick it in with the group, otherwise the array will
become stupidly large. That's why there's a separation of the two.
^ permalink raw reply
* Re: [PATCH] serial/of-serial: Add 16654 chip to compatible string list
From: Roland Stigge @ 2012-05-28 17:48 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: alan, gregkh, linux-serial, linux-kernel, kevin.wells,
srinivas.bakki, linux-arm-kernel, arnd
In-Reply-To: <20120528163151.GB28290@n2100.arm.linux.org.uk>
On 28/05/12 18:31, Russell King - ARM Linux wrote:
>>>> So maybe 16750 is the better choice for me, anyway. Already supported in
>>>> of-serial. Works for now, but need more testing. Another hint is that
>>>> 16750 is advertised as "IP core for Soc" which matches the case of LPC32xx.
>>>
>>> 16750 also has automatic hardware flow control support, selectable through
>>> bit 5 in the MCR register. If your UART has that, then it's probably a
>>> 16750 derivative rather than a 16550 or 16650 derivative.
>>>
>>> 16650s have an EFR register at offset 2, selectable by writing 0xBF into
>>> the LCR register, which the 16750 doesn't have. 16650 also has automatic
>>> hardware flow control, bit this is selected through a couple of bits in
>>> the EFR.
>>
>> The 4 LPC32xx's "Standard" UARTs have neither of those.
>>
>> Is it ok to use "ns16650", i.e. PORT_16650, or do I need to introduce a
>> FIFO depth configuration?
>
> I think you need a new type, because as I said above, 16650s have that
> additional EFR, and we will attempt to access that register which
> isn't present in yours.
I actually meant 16750 instead of 16650, sorry, but this basically means
the same - I would refer to extensions that are actually not there...
Now, introducing a new type, can I add to 8250.c's uart_config[] by
introducing a new type (no. 22) after PORT_XR17D15X? Unfortunately,
there are the "ARM specific type numbers" after current PORT_MAX_8250
(21), but those are not listed in 8250.c's uart_config[]. Or how am I
supposed to add a new type?
Thanks in advance,
Roland
^ permalink raw reply
* Re: struct tty_flip_buffer replacement in newer kernels
From: Alan Cox @ 2012-05-28 17:12 UTC (permalink / raw)
To: Dmitriy Alekseev
Cc: linux-serial@vger.kernel.org,
Юрий Зверев
In-Reply-To: <1338208815.57140.YahooMailNeo@web44914.mail.sp1.yahoo.com>
On Mon, 28 May 2012 05:40:15 -0700 (PDT)
Dmitriy Alekseev <alexeev6@yahoo.com> wrote:
> Hi,
>
> My st16c554 chip is connected with cpu (at91rm9200) in 68 (Motorola) mode, and formally works as 68c554.
> Is 8250 driver supports the 68 mode?
> I thought the driver maintains whole 16c554 IC, or it means only mode 16 is supported?
Not sure I understand the question
^ permalink raw reply
* [PATCH V2 6/6] drivers/amba: add support for a PCI bridge
From: Alessandro Rubini @ 2012-05-28 16:38 UTC (permalink / raw)
To: linux-kernel
Cc: Giancarlo Asnaghi, Alan Cox, Russell King, x86,
Greg Kroah-Hartman, Arnd Bergmann, linux-arm-kernel, linux-serial,
linux-arch
In-Reply-To: <cover.1338222460.git.rubini@gnudd.com>
This is a PCI driver that registers AMBA devices for the range of
supported devices. It is currently used by STA2X11, which exports
AMBA peripherals under PCIe. The original AMBA drivers work with no
changes or minimal ones.
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Alan Cox <alan@linux.intel.com>
---
drivers/Kconfig | 2 +
drivers/amba/Kconfig | 10 +++++
drivers/amba/Makefile | 1 +
drivers/amba/pci-amba.c | 95 +++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 108 insertions(+), 0 deletions(-)
create mode 100644 drivers/amba/Kconfig
create mode 100644 drivers/amba/pci-amba.c
diff --git a/drivers/Kconfig b/drivers/Kconfig
index c2b0cd2..72d5145 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -150,4 +150,6 @@ source "drivers/vme/Kconfig"
source "drivers/modem_shm/Kconfig"
+source "drivers/amba/Kconfig"
+
endmenu
diff --git a/drivers/amba/Kconfig b/drivers/amba/Kconfig
new file mode 100644
index 0000000..b5b5aca
--- /dev/null
+++ b/drivers/amba/Kconfig
@@ -0,0 +1,10 @@
+
+config PCI_AMBA
+ tristate "PCI-to-AMBA bridge"
+ depends on ARM_AMBA && PCI
+ ---help---
+ This compiles a PCI driver that registers AMBA devices, so
+ the respective AMBA driver can be used unchanged if you have
+ a PCI to amba bridge. This is required for STA2X11 support.
+
+ If uncertain, choose N.
diff --git a/drivers/amba/Makefile b/drivers/amba/Makefile
index 66e81c2..d30e947 100644
--- a/drivers/amba/Makefile
+++ b/drivers/amba/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_ARM_AMBA) += bus.o
+obj-$(CONFIG_PCI_AMBA) += pci-amba.o
obj-$(CONFIG_TEGRA_AHB) += tegra-ahb.o
diff --git a/drivers/amba/pci-amba.c b/drivers/amba/pci-amba.c
new file mode 100644
index 0000000..12e7a7e
--- /dev/null
+++ b/drivers/amba/pci-amba.c
@@ -0,0 +1,95 @@
+/*
+ * Support for AMBA devices (both APB and AHB) behind a PCI bridge
+ * Copyright 2012 ST Microelectronics (Alessandro Rubini)
+ * GNU GPL version 2.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/amba/bus.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/slab.h>
+#include <linux/irq.h>
+#include <linux/sizes.h>
+
+static int __devinit pci_amba_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ struct amba_device *adev;
+ char *name;
+ int ret;
+
+ pci_enable_msi(pdev);
+ ret = pci_enable_device(pdev);
+ if (ret)
+ return ret;
+
+ /* Create a name: each of them must be different */
+ name = devm_kzalloc(&pdev->dev, strlen(dev_name(&pdev->dev)) + 6,
+ GFP_KERNEL);
+ sprintf(name, "amba-%s", dev_name(&pdev->dev));
+
+ /* Simply build an amba device and register it */
+ adev = amba_device_alloc(name, pdev->resource[0].start, SZ_4K);
+ if (!adev)
+ return -ENOMEM;
+ adev->irq[0] = pdev->irq;
+
+ /* This bridge can host both APB and AHB devices, so set master */
+ pci_set_master(pdev);
+ if (pdev->vendor == PCI_VENDOR_ID_STMICRO) {
+ /* Under sta2x11, DMA is there but limited to 512M */
+ adev->dma_mask = SZ_512M - 1;
+ adev->dev.coherent_dma_mask = SZ_512M - 1;
+ }
+
+ adev->dev.platform_data = pdev->dev.platform_data;
+ pci_set_drvdata(pdev, adev);
+
+ if ((ret = amba_device_add(adev, &pdev->resource[0])) < 0)
+ return ret;
+ return 0;
+};
+
+static void __devexit pci_amba_remove(struct pci_dev *pdev)
+{
+ struct amba_device *adev = pci_get_drvdata(pdev);
+ amba_device_unregister(adev);
+ pci_disable_msi(pdev);
+}
+
+static DEFINE_PCI_DEVICE_TABLE(pci_amba_table) = {
+ {PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_UART_HWFC)},
+ {PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_UART_NO_HWFC)},
+ {PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_SOC_DMA)},
+ {PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_I2C)},
+ {PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_SPI_HS)},
+ {PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_SDIO_EMMC)},
+ {PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_SDIO)},
+ {PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_DMA)},
+ {PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_MSPS)},
+ {0,}
+};
+
+static struct pci_driver pci_amba_driver = {
+ .name = "pci-amba",
+ .id_table = pci_amba_table,
+ .probe = pci_amba_probe,
+ .remove = __devexit_p(pci_amba_remove),
+};
+
+static int __init pci_amba_init(void)
+{
+ return pci_register_driver(&pci_amba_driver);
+}
+
+static void __exit pci_amba_exit(void)
+{
+ pci_unregister_driver(&pci_amba_driver);
+}
+
+module_init(pci_amba_init);
+module_exit(pci_amba_exit);
+
+MODULE_LICENSE("GPL");
--
1.7.7.2
^ permalink raw reply related
* [PATCH V2 5/6] x86: add CONFIG_ARM_AMBA, selected by STA2X11
From: Alessandro Rubini @ 2012-05-28 16:37 UTC (permalink / raw)
To: linux-kernel
Cc: Giancarlo Asnaghi, Alan Cox, Russell King, x86,
Greg Kroah-Hartman, Arnd Bergmann, linux-arm-kernel, linux-serial,
linux-arch
In-Reply-To: <cover.1338222460.git.rubini@gnudd.com>
The sta2x11 I/O Hub is a bridge from PCIe to AMBA. It reuses a number
of amba drivers and needs to activate core bus support.
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com>
---
arch/x86/Kconfig | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 91dea918..112718f 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -500,6 +500,7 @@ config STA2X11
select SWIOTLB
select MFD_STA2X11
select ARCH_REQUIRE_GPIOLIB
+ select ARM_AMBA
default n
---help---
This adds support for boards based on the STA2X11 IO-Hub,
@@ -2173,6 +2174,9 @@ config GEOS
endif # X86_32
+config ARM_AMBA
+ bool
+
config AMD_NB
def_bool y
depends on CPU_SUP_AMD && PCI
--
1.7.7.2
^ permalink raw reply related
* [PATCH V2 4/6] serial: use the new linux/sizes.h
From: Alessandro Rubini @ 2012-05-28 16:37 UTC (permalink / raw)
To: linux-kernel
Cc: Giancarlo Asnaghi, Alan Cox, Russell King, x86,
Greg Kroah-Hartman, Arnd Bergmann, linux-arm-kernel, linux-serial,
linux-arch
In-Reply-To: <cover.1338222460.git.rubini@gnudd.com>
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com>
Cc: Russell King <linux@arm.linux.org.uk>
---
drivers/tty/serial/amba-pl011.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 4ad721f..d394b93 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -53,9 +53,9 @@
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/pinctrl/consumer.h>
+#include <linux/sizes.h>
#include <asm/io.h>
-#include <asm/sizes.h>
#define UART_NR 14
--
1.7.7.2
^ permalink raw reply related
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