* [PATCH v5 07/39] nds32: Exception handling
From: Greentime Hu @ 2018-01-02 8:24 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial,
geert.uytterhoeven, linus.walleij, mark.rutland, greg, ren_guo,
rdunlap, davem, jonas, stefan.kristiansson, shorne
Cc: green.hu, Vincent Chen
In-Reply-To: <cover.1514874857.git.green.hu@gmail.com>
From: Greentime Hu <greentime@andestech.com>
This patch includes the exception/interrupt entries, pt_reg structure and
related accessors.
Signed-off-by: Vincent Chen <vincentc@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
---
arch/nds32/include/asm/ptrace.h | 66 +++++
arch/nds32/kernel/ex-entry.S | 157 ++++++++++
arch/nds32/kernel/ex-exit.S | 193 +++++++++++++
arch/nds32/kernel/stacktrace.c | 47 +++
arch/nds32/kernel/traps.c | 428 +++++++++++++++++++++++++++
arch/nds32/mm/alignment.c | 609 +++++++++++++++++++++++++++++++++++++++
6 files changed, 1500 insertions(+)
create mode 100644 arch/nds32/include/asm/ptrace.h
create mode 100644 arch/nds32/kernel/ex-entry.S
create mode 100644 arch/nds32/kernel/ex-exit.S
create mode 100644 arch/nds32/kernel/stacktrace.c
create mode 100644 arch/nds32/kernel/traps.c
create mode 100644 arch/nds32/mm/alignment.c
diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
new file mode 100644
index 0000000..db7856c
--- /dev/null
+++ b/arch/nds32/include/asm/ptrace.h
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_PTRACE_H
+#define __ASM_NDS32_PTRACE_H
+
+#define PTRACE_GETREGS 12
+#define PTRACE_SETREGS 13
+#define PTRACE_GETFPREGS 14
+#define PTRACE_SETFPREGS 15
+
+#include <uapi/asm/ptrace.h>
+
+#ifndef __ASSEMBLY__
+
+struct pt_regs {
+ union {
+ struct user_pt_regs user_regs;
+ struct {
+ long uregs[26];
+ long fp;
+ long gp;
+ long lp;
+ long sp;
+ long ipc;
+#if defined(CONFIG_HWZOL)
+ long lb;
+ long le;
+ long lc;
+#else
+ long dummy[3];
+#endif
+ long syscallno;
+ };
+ };
+ long orig_r0;
+ long ir0;
+ long ipsw;
+ long pipsw;
+ long pipc;
+ long pp0;
+ long pp1;
+ long fucop_ctl;
+ long osp;
+};
+
+#include <asm/bitfield.h>
+extern void show_regs(struct pt_regs *);
+/* Avoid circular header include via sched.h */
+struct task_struct;
+extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs,
+ int error_code, int si_code);
+
+#define arch_has_single_step() (1)
+#define user_mode(regs) (((regs)->ipsw & PSW_mskPOM) == 0)
+#define interrupts_enabled(regs) (!!((regs)->ipsw & PSW_mskGIE))
+#define valid_user_regs(regs) (user_mode(regs) && interrupts_enabled(regs))
+#define regs_return_value(regs) ((regs)->uregs[0])
+#define instruction_pointer(regs) ((regs)->ipc)
+#define user_stack_pointer(regs) ((regs)->sp)
+#define profile_pc(regs) instruction_pointer(regs)
+
+#define ARCH_HAS_USER_SINGLE_STEP_INFO
+
+#endif /* __ASSEMBLY__ */
+#endif
diff --git a/arch/nds32/kernel/ex-entry.S b/arch/nds32/kernel/ex-entry.S
new file mode 100644
index 0000000..a72e83d
--- /dev/null
+++ b/arch/nds32/kernel/ex-entry.S
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/linkage.h>
+#include <asm/memory.h>
+#include <asm/nds32.h>
+#include <asm/errno.h>
+#include <asm/asm-offsets.h>
+#include <asm/page.h>
+
+#ifdef CONFIG_HWZOL
+ .macro push_zol
+ mfusr $r14, $LB
+ mfusr $r15, $LE
+ mfusr $r16, $LC
+ .endm
+#endif
+
+ .macro save_user_regs
+
+ smw.adm $sp, [$sp], $sp, #0x1
+ /* move $SP to the bottom of pt_regs */
+ addi $sp, $sp, -OSP_OFFSET
+
+ /* push $r0 ~ $r25 */
+ smw.bim $r0, [$sp], $r25
+ /* push $fp, $gp, $lp */
+ smw.bim $sp, [$sp], $sp, #0xe
+
+ mfsr $r12, $SP_USR
+ mfsr $r13, $IPC
+#ifdef CONFIG_HWZOL
+ push_zol
+#endif
+ movi $r17, -1
+ move $r18, $r0
+ mfsr $r19, $PSW
+ mfsr $r20, $IPSW
+ mfsr $r21, $P_IPSW
+ mfsr $r22, $P_IPC
+ mfsr $r23, $P_P0
+ mfsr $r24, $P_P1
+ smw.bim $r12, [$sp], $r24, #0
+ addi $sp, $sp, -FUCOP_CTL_OFFSET
+
+ /* Initialize kernel space $fp */
+ andi $p0, $r20, #PSW_mskPOM
+ movi $p1, #0x0
+ cmovz $fp, $p1, $p0
+
+ andi $r16, $r19, #PSW_mskINTL
+ slti $r17, $r16, #4
+ bnez $r17, 1f
+ addi $r17, $r19, #-2
+ mtsr $r17, $PSW
+ isb
+1:
+ /* If it was superuser mode, we don't need to update $r25 */
+ bnez $p0, 2f
+ la $p0, __entry_task
+ lw $r25, [$p0]
+2:
+ .endm
+
+ .text
+
+/*
+ * Exception Vector
+ */
+exception_handlers:
+ .long unhandled_exceptions !Reset/NMI
+ .long unhandled_exceptions !TLB fill
+ .long do_page_fault !PTE not present
+ .long do_dispatch_tlb_misc !TLB misc
+ .long unhandled_exceptions !TLB VLPT
+ .long unhandled_exceptions !Machine Error
+ .long do_debug_trap !Debug related
+ .long do_dispatch_general !General exception
+ .long eh_syscall !Syscall
+ .long asm_do_IRQ !IRQ
+
+common_exception_handler:
+ save_user_regs
+ mfsr $p0, $ITYPE
+ andi $p0, $p0, #ITYPE_mskVECTOR
+ srli $p0, $p0, #ITYPE_offVECTOR
+ andi $p1, $p0, #NDS32_VECTOR_mskNONEXCEPTION
+ bnez $p1, 1f
+ sethi $lp, hi20(ret_from_exception)
+ ori $lp, $lp, lo12(ret_from_exception)
+ sethi $p1, hi20(exception_handlers)
+ ori $p1, $p1, lo12(exception_handlers)
+ lw $p1, [$p1+$p0<<2]
+ move $r0, $p0
+ mfsr $r1, $EVA
+ mfsr $r2, $ITYPE
+ move $r3, $sp
+ mfsr $r4, $OIPC
+ /* enable gie if it is enabled in IPSW. */
+ mfsr $r21, $PSW
+ andi $r20, $r20, #PSW_mskGIE /* r20 is $IPSW*/
+ or $r21, $r21, $r20
+ mtsr $r21, $PSW
+ dsb
+ jr $p1
+
+ /* syscall */
+1:
+ addi $p1, $p0, #-NDS32_VECTOR_offEXCEPTION
+ bnez $p1, 2f
+ sethi $lp, hi20(ret_from_exception)
+ ori $lp, $lp, lo12(ret_from_exception)
+ sethi $p1, hi20(exception_handlers)
+ ori $p1, $p1, lo12(exception_handlers)
+ lwi $p1, [$p1+#NDS32_VECTOR_offEXCEPTION<<2]
+ jr $p1
+
+ /* interrupt */
+2:
+#ifdef CONFIG_TRACE_IRQFLAGS
+ jal arch_trace_hardirqs_off
+#endif
+ move $r0, $sp
+ sethi $lp, hi20(ret_from_intr)
+ ori $lp, $lp, lo12(ret_from_intr)
+ sethi $p0, hi20(exception_handlers)
+ ori $p0, $p0, lo12(exception_handlers)
+ lwi $p0, [$p0+#NDS32_VECTOR_offINTERRUPT<<2]
+ jr $p0
+
+ .macro EXCEPTION_VECTOR_DEBUG
+ .align 4
+ mfsr $p0, $EDM_CTL
+ andi $p0, $p0, EDM_CTL_mskV3_EDM_MODE
+ tnez $p0, SWID_RAISE_INTERRUPT_LEVEL
+ .endm
+
+ .macro EXCEPTION_VECTOR
+ .align 4
+ sethi $p0, hi20(common_exception_handler)
+ ori $p0, $p0, lo12(common_exception_handler)
+ jral.ton $p0, $p0
+ .endm
+
+ .section ".text.init", #alloc, #execinstr
+ .global exception_vector
+exception_vector:
+.rept 6
+ EXCEPTION_VECTOR
+.endr
+ EXCEPTION_VECTOR_DEBUG
+.rept 121
+ EXCEPTION_VECTOR
+.endr
+ .align 4
+ .global exception_vector_end
+exception_vector_end:
diff --git a/arch/nds32/kernel/ex-exit.S b/arch/nds32/kernel/ex-exit.S
new file mode 100644
index 0000000..98e1e33
--- /dev/null
+++ b/arch/nds32/kernel/ex-exit.S
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/linkage.h>
+#include <asm/unistd.h>
+#include <asm/assembler.h>
+#include <asm/nds32.h>
+#include <asm/asm-offsets.h>
+#include <asm/thread_info.h>
+#include <asm/current.h>
+
+
+
+#ifdef CONFIG_HWZOL
+ .macro pop_zol
+ mtusr $r14, $LB
+ mtusr $r15, $LE
+ mtusr $r16, $LC
+ .endm
+#endif
+
+ .macro restore_user_regs_first
+ setgie.d
+ isb
+
+ addi $sp, $sp, FUCOP_CTL_OFFSET
+
+ lmw.adm $r12, [$sp], $r24, #0x0
+ mtsr $r12, $SP_USR
+ mtsr $r13, $IPC
+#ifdef CONFIG_HWZOL
+ pop_zol
+#endif
+ mtsr $r19, $PSW
+ mtsr $r20, $IPSW
+ mtsr $r21, $P_IPSW
+ mtsr $r22, $P_IPC
+ mtsr $r23, $P_P0
+ mtsr $r24, $P_P1
+ lmw.adm $sp, [$sp], $sp, #0xe
+ .endm
+
+ .macro restore_user_regs_last
+ pop $p0
+ cmovn $sp, $p0, $p0
+
+ iret
+ nop
+
+ .endm
+
+ .macro restore_user_regs
+ restore_user_regs_first
+ lmw.adm $r0, [$sp], $r25, #0x0
+ addi $sp, $sp, OSP_OFFSET
+ restore_user_regs_last
+ .endm
+
+ .macro fast_restore_user_regs
+ restore_user_regs_first
+ lmw.adm $r1, [$sp], $r25, #0x0
+ addi $sp, $sp, OSP_OFFSET-4
+ restore_user_regs_last
+ .endm
+
+#ifdef CONFIG_PREEMPT
+ .macro preempt_stop
+ .endm
+#else
+ .macro preempt_stop
+ setgie.d
+ isb
+ .endm
+#define resume_kernel no_work_pending
+#endif
+
+ENTRY(ret_from_exception)
+ preempt_stop
+ENTRY(ret_from_intr)
+ move why, #0 ! not system call
+
+/*
+ * judge Kernel or user mode
+ *
+ */
+ lwi $p0, [$sp+(#IPSW_OFFSET)] ! Check if in nested interrupt
+ andi $p0, $p0, #PSW_mskINTL
+ bnez $p0, resume_kernel ! done with iret
+ j resume_userspace
+
+
+/*
+ * This is the fast syscall return path. We do as little as
+ * possible here, and this includes saving $r0 back into the SVC
+ * stack.
+ * fixed: tsk - $r25, why - $r8, $r7 - syscall #, $r8 - syscall table pointer
+ */
+ENTRY(ret_fast_syscall)
+ gie_disable
+ lwi $r1, [tsk+#TSK_TI_FLAGS]
+ andi $p1, $r1, #_TIF_WORK_MASK
+ bnez $p1, fast_work_pending
+ fast_restore_user_regs ! iret
+
+/*
+ * Ok, we need to do extra processing,
+ * enter the slow path returning from syscall, while pending work.
+ */
+fast_work_pending:
+ swi $r0, [$sp+(#R0_OFFSET)] ! what is different from ret_from_exception
+work_pending:
+ andi $p1, $r1, #_TIF_NEED_RESCHED
+ bnez $p1, work_resched
+
+ andi $p1, $r1, #_TIF_SIGPENDING|#_TIF_NOTIFY_RESUME
+ beqz $p1, no_work_pending
+
+ move $r0, $sp ! 'regs'
+ move $r2, why
+ gie_enable
+ bal do_notify_resume
+ beqz $r0, ret_slow_syscall
+ bgtz $r0, 1f
+ movi $r7, #__NR_restart_syscall
+1:
+ lmw.bi $r0, [sp], $r5
+ b eh_syscall_phase_2
+work_resched:
+ bal schedule ! path, return to user mode
+
+/*
+ * "slow" syscall return path.
+ * "why" tells us if this was a real syscall.
+ */
+ENTRY(resume_userspace)
+ENTRY(ret_slow_syscall)
+ gie_disable
+ lwi $p0, [$sp+(#IPSW_OFFSET)] ! Check if in nested interrupt
+ andi $p0, $p0, #PSW_mskINTL
+ bnez $p0, no_work_pending ! done with iret
+ lwi $r1, [tsk+#TSK_TI_FLAGS]
+ andi $p1, $r1, #_TIF_WORK_MASK
+ bnez $p1, work_pending ! handle work_resched, sig_pend
+
+no_work_pending:
+#ifdef CONFIG_TRACE_IRQFLAGS
+ lwi $p0, [$sp+(#IPSW_OFFSET)]
+ andi $p0, $p0, #0x1
+ la $r10, trace_hardirqs_off
+ la $r9, trace_hardirqs_on
+ cmovz $r9, $p0, $r10
+ jral $r9
+#endif
+ restore_user_regs ! return from iret
+
+
+/*
+ * preemptive kernel
+ */
+#ifdef CONFIG_PREEMPT
+resume_kernel:
+ gie_disable
+ lwi $t0, [tsk+#TSK_TI_PREEMPT]
+ bnez $t0, no_work_pending
+need_resched:
+ lwi $t0, [tsk+#TSK_TI_FLAGS]
+ andi $p1, $t0, #_TIF_NEED_RESCHED
+ beqz $p1, no_work_pending
+
+ lwi $t0, [$sp+(#IPSW_OFFSET)] ! Interrupts off?
+ andi $t0, $t0, #1
+ beqz $t0, no_work_pending
+
+ jal preempt_schedule_irq
+ b need_resched
+#endif
+
+/*
+ * This is how we return from a fork.
+ */
+ENTRY(ret_from_fork)
+ bal schedule_tail
+ beqz $r6, 1f ! r6 stores fn for kernel thread
+ move $r0, $r7 ! prepare kernel thread arg
+ jral $r6
+1:
+ lwi $r1, [tsk+#TSK_TI_FLAGS] ! check for syscall tracing
+ move why, #1
+ andi $p1, $r1, #_TIF_WORK_SYSCALL_LEAVE ! are we tracing syscalls?
+ beqz $p1, ret_slow_syscall
+ move $r0, $sp
+ bal syscall_trace_leave
+ b ret_slow_syscall
diff --git a/arch/nds32/kernel/stacktrace.c b/arch/nds32/kernel/stacktrace.c
new file mode 100644
index 0000000..bc70113
--- /dev/null
+++ b/arch/nds32/kernel/stacktrace.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/sched/debug.h>
+#include <linux/sched/task_stack.h>
+#include <linux/stacktrace.h>
+
+void save_stack_trace(struct stack_trace *trace)
+{
+ save_stack_trace_tsk(current, trace);
+}
+
+void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
+{
+ unsigned long *fpn;
+ int skip = trace->skip;
+ int savesched;
+
+ if (tsk == current) {
+ __asm__ __volatile__("\tori\t%0, $fp, #0\n":"=r"(fpn));
+ savesched = 1;
+ } else {
+ fpn = (unsigned long *)thread_saved_fp(tsk);
+ savesched = 0;
+ }
+
+ while (!kstack_end(fpn) && !((unsigned long)fpn & 0x3)
+ && (fpn >= (unsigned long *)TASK_SIZE)) {
+ unsigned long lpp, fpp;
+
+ lpp = fpn[-1];
+ fpp = fpn[FP_OFFSET];
+ if (!__kernel_text_address(lpp))
+ break;
+
+ if (savesched || !in_sched_functions(lpp)) {
+ if (skip) {
+ skip--;
+ } else {
+ trace->entries[trace->nr_entries++] = lpp;
+ if (trace->nr_entries >= trace->max_entries)
+ break;
+ }
+ }
+ fpn = (unsigned long *)fpp;
+ }
+}
diff --git a/arch/nds32/kernel/traps.c b/arch/nds32/kernel/traps.c
new file mode 100644
index 0000000..bb162a9
--- /dev/null
+++ b/arch/nds32/kernel/traps.c
@@ -0,0 +1,428 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/module.h>
+#include <linux/personality.h>
+#include <linux/kallsyms.h>
+#include <linux/hardirq.h>
+#include <linux/kdebug.h>
+#include <linux/sched/task_stack.h>
+#include <linux/uaccess.h>
+
+#include <asm/proc-fns.h>
+#include <asm/unistd.h>
+
+#include <linux/ptrace.h>
+#include <nds32_intrinsic.h>
+
+extern void show_pte(struct mm_struct *mm, unsigned long addr);
+
+/*
+ * Dump out the contents of some memory nicely...
+ */
+void dump_mem(const char *lvl, unsigned long bottom, unsigned long top)
+{
+ unsigned long first;
+ mm_segment_t fs;
+ int i;
+
+ /*
+ * We need to switch to kernel mode so that we can use __get_user
+ * to safely read from kernel space. Note that we now dump the
+ * code first, just in case the backtrace kills us.
+ */
+ fs = get_fs();
+ set_fs(KERNEL_DS);
+
+ pr_emerg("%s(0x%08lx to 0x%08lx)\n", lvl, bottom, top);
+
+ for (first = bottom & ~31; first < top; first += 32) {
+ unsigned long p;
+ char str[sizeof(" 12345678") * 8 + 1];
+
+ memset(str, ' ', sizeof(str));
+ str[sizeof(str) - 1] = '\0';
+
+ for (p = first, i = 0; i < 8 && p < top; i++, p += 4) {
+ if (p >= bottom && p < top) {
+ unsigned long val;
+ if (__get_user(val, (unsigned long *)p) == 0)
+ sprintf(str + i * 9, " %08lx", val);
+ else
+ sprintf(str + i * 9, " ????????");
+ }
+ }
+ pr_emerg("%s%04lx:%s\n", lvl, first & 0xffff, str);
+ }
+
+ set_fs(fs);
+}
+
+EXPORT_SYMBOL(dump_mem);
+
+static void dump_instr(struct pt_regs *regs)
+{
+ unsigned long addr = instruction_pointer(regs);
+ mm_segment_t fs;
+ char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
+ int i;
+
+ return;
+ /*
+ * We need to switch to kernel mode so that we can use __get_user
+ * to safely read from kernel space. Note that we now dump the
+ * code first, just in case the backtrace kills us.
+ */
+ fs = get_fs();
+ set_fs(KERNEL_DS);
+
+ pr_emerg("Code: ");
+ for (i = -4; i < 1; i++) {
+ unsigned int val, bad;
+
+ bad = __get_user(val, &((u32 *) addr)[i]);
+
+ if (!bad) {
+ p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val);
+ } else {
+ p += sprintf(p, "bad PC value");
+ break;
+ }
+ }
+ pr_emerg("Code: %s\n", str);
+
+ set_fs(fs);
+}
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+#include <linux/ftrace.h>
+static void
+get_real_ret_addr(unsigned long *addr, struct task_struct *tsk, int *graph)
+{
+ if (*addr == (unsigned long)return_to_handler) {
+ int index = tsk->curr_ret_stack;
+
+ if (tsk->ret_stack && index >= *graph) {
+ index -= *graph;
+ *addr = tsk->ret_stack[index].ret;
+ (*graph)++;
+ }
+ }
+}
+#else
+static inline void
+get_real_ret_addr(unsigned long *addr, struct task_struct *tsk, int *graph)
+{
+}
+#endif
+
+#define LOOP_TIMES (100)
+static void __dump(struct task_struct *tsk, unsigned long *base_reg)
+{
+ unsigned long ret_addr;
+ int cnt = LOOP_TIMES, graph = 0;
+ pr_emerg("Call Trace:\n");
+ if (!IS_ENABLED(CONFIG_FRAME_POINTER)) {
+ while (!kstack_end(base_reg)) {
+ ret_addr = *base_reg++;
+ if (__kernel_text_address(ret_addr)) {
+ get_real_ret_addr(&ret_addr, tsk, &graph);
+ print_ip_sym(ret_addr);
+ }
+ if (--cnt < 0)
+ break;
+ }
+ } else {
+ while (!kstack_end((void *)base_reg) &&
+ !((unsigned long)base_reg & 0x3) &&
+ ((unsigned long)base_reg >= TASK_SIZE)) {
+ unsigned long next_fp;
+#if !defined(NDS32_ABI_2)
+ ret_addr = base_reg[0];
+ next_fp = base_reg[1];
+#else
+ ret_addr = base_reg[-1];
+ next_fp = base_reg[FP_OFFSET];
+#endif
+ if (__kernel_text_address(ret_addr)) {
+ get_real_ret_addr(&ret_addr, tsk, &graph);
+ print_ip_sym(ret_addr);
+ }
+ if (--cnt < 0)
+ break;
+ base_reg = (unsigned long *)next_fp;
+ }
+ }
+ pr_emerg("\n");
+}
+
+void dump_stack(void)
+{
+ unsigned long *base_reg;
+ if (!IS_ENABLED(CONFIG_FRAME_POINTER))
+ __asm__ __volatile__("\tori\t%0, $sp, #0\n":"=r"(base_reg));
+ else
+ __asm__ __volatile__("\tori\t%0, $fp, #0\n":"=r"(base_reg));
+ __dump(NULL, base_reg);
+}
+
+EXPORT_SYMBOL(dump_stack);
+
+void show_stack(struct task_struct *tsk, unsigned long *sp)
+{
+ unsigned long *base_reg;
+
+ if (!tsk)
+ tsk = current;
+ if (!IS_ENABLED(CONFIG_FRAME_POINTER)) {
+ if (tsk != current)
+ base_reg = (unsigned long *)(tsk->thread.cpu_context.sp);
+ else
+ __asm__ __volatile__("\tori\t%0, $sp, #0\n":"=r"(base_reg));
+ } else {
+ if (tsk != current)
+ base_reg = (unsigned long *)(tsk->thread.cpu_context.fp);
+ else
+ __asm__ __volatile__("\tori\t%0, $fp, #0\n":"=r"(base_reg));
+ }
+ __dump(tsk, base_reg);
+ barrier();
+}
+
+DEFINE_SPINLOCK(die_lock);
+
+/*
+ * This function is protected against re-entrancy.
+ */
+void die(const char *str, struct pt_regs *regs, int err)
+{
+ struct task_struct *tsk = current;
+ static int die_counter;
+
+ console_verbose();
+ spin_lock_irq(&die_lock);
+ bust_spinlocks(1);
+
+ pr_emerg("Internal error: %s: %x [#%d]\n", str, err, ++die_counter);
+ print_modules();
+ pr_emerg("CPU: %i\n", smp_processor_id());
+ show_regs(regs);
+ pr_emerg("Process %s (pid: %d, stack limit = 0x%p)\n",
+ tsk->comm, tsk->pid, task_thread_info(tsk) + 1);
+
+ if (!user_mode(regs) || in_interrupt()) {
+ dump_mem("Stack: ", regs->sp,
+ THREAD_SIZE + (unsigned long)task_thread_info(tsk));
+ dump_instr(regs);
+ dump_stack();
+ }
+
+ bust_spinlocks(0);
+ spin_unlock_irq(&die_lock);
+ do_exit(SIGSEGV);
+}
+
+EXPORT_SYMBOL(die);
+
+void die_if_kernel(const char *str, struct pt_regs *regs, int err)
+{
+ if (user_mode(regs))
+ return;
+
+ die(str, regs, err);
+}
+
+int bad_syscall(int n, struct pt_regs *regs)
+{
+ siginfo_t info;
+
+ if (current->personality != PER_LINUX) {
+ send_sig(SIGSEGV, current, 1);
+ return regs->uregs[0];
+ }
+
+ info.si_signo = SIGILL;
+ info.si_errno = 0;
+ info.si_code = ILL_ILLTRP;
+ info.si_addr = (void __user *)instruction_pointer(regs) - 4;
+
+ force_sig_info(SIGILL, &info, current);
+ die_if_kernel("Oops - bad syscall", regs, n);
+ return regs->uregs[0];
+}
+
+void __pte_error(const char *file, int line, unsigned long val)
+{
+ pr_emerg("%s:%d: bad pte %08lx.\n", file, line, val);
+}
+
+void __pmd_error(const char *file, int line, unsigned long val)
+{
+ pr_emerg("%s:%d: bad pmd %08lx.\n", file, line, val);
+}
+
+void __pgd_error(const char *file, int line, unsigned long val)
+{
+ pr_emerg("%s:%d: bad pgd %08lx.\n", file, line, val);
+}
+
+extern char *exception_vector, *exception_vector_end;
+void __init trap_init(void)
+{
+ return;
+}
+
+void __init early_trap_init(void)
+{
+ unsigned long ivb = 0;
+ unsigned long base = PAGE_OFFSET;
+
+ memcpy((unsigned long *)base, (unsigned long *)&exception_vector,
+ ((unsigned long)&exception_vector_end -
+ (unsigned long)&exception_vector));
+ ivb = __nds32__mfsr(NDS32_SR_IVB);
+ /* Check platform support. */
+ if (((ivb & IVB_mskNIVIC) >> IVB_offNIVIC) < 2)
+ panic
+ ("IVIC mode is not allowed on the platform with interrupt controller\n");
+ __nds32__mtsr((ivb & ~IVB_mskESZ) | (IVB_valESZ16 << IVB_offESZ) |
+ IVB_BASE, NDS32_SR_IVB);
+ __nds32__mtsr(INT_MASK_INITAIAL_VAL, NDS32_SR_INT_MASK);
+
+ /*
+ * 0x800 = 128 vectors * 16byte.
+ * It should be enough to flush a page.
+ */
+ cpu_cache_wbinval_page(base, true);
+}
+
+void do_debug_trap(unsigned long entry, unsigned long addr,
+ unsigned long type, struct pt_regs *regs)
+{
+ if (notify_die(DIE_OOPS, "Oops", regs, addr, type, SIGTRAP)
+ == NOTIFY_STOP)
+ return;
+
+ if (user_mode(regs)) {
+ /* trap_signal */
+ send_sigtrap(current, regs, 0, TRAP_BRKPT);
+ } else {
+ /* kernel_trap */
+ if (!fixup_exception(regs))
+ die("unexpected kernel_trap", regs, 0);
+ }
+}
+
+void unhandled_interruption(struct pt_regs *regs)
+{
+ siginfo_t si;
+ pr_emerg("unhandled_interruption\n");
+ show_regs(regs);
+ if (!user_mode(regs))
+ do_exit(SIGKILL);
+ si.si_signo = SIGKILL;
+ si.si_errno = 0;
+ force_sig_info(SIGKILL, &si, current);
+}
+
+void unhandled_exceptions(unsigned long entry, unsigned long addr,
+ unsigned long type, struct pt_regs *regs)
+{
+ siginfo_t si;
+ pr_emerg("Unhandled Exception: entry: %lx addr:%lx itype:%lx\n", entry,
+ addr, type);
+ show_regs(regs);
+ if (!user_mode(regs))
+ do_exit(SIGKILL);
+ si.si_signo = SIGKILL;
+ si.si_errno = 0;
+ si.si_addr = (void *)addr;
+ force_sig_info(SIGKILL, &si, current);
+}
+
+extern int do_page_fault(unsigned long entry, unsigned long addr,
+ unsigned int error_code, struct pt_regs *regs);
+
+/*
+ * 2:DEF dispatch for TLB MISC exception handler
+*/
+
+void do_dispatch_tlb_misc(unsigned long entry, unsigned long addr,
+ unsigned long type, struct pt_regs *regs)
+{
+ type = type & (ITYPE_mskINST | ITYPE_mskETYPE);
+ if ((type & ITYPE_mskETYPE) < 5) {
+ /* Permission exceptions */
+ do_page_fault(entry, addr, type, regs);
+ } else
+ unhandled_exceptions(entry, addr, type, regs);
+}
+
+void do_revinsn(struct pt_regs *regs)
+{
+ siginfo_t si;
+ pr_emerg("Reserved Instruction\n");
+ show_regs(regs);
+ if (!user_mode(regs))
+ do_exit(SIGILL);
+ si.si_signo = SIGILL;
+ si.si_errno = 0;
+ force_sig_info(SIGILL, &si, current);
+}
+
+#ifdef CONFIG_ALIGNMENT_TRAP
+extern int unalign_access_mode;
+extern int do_unaligned_access(unsigned long entry, unsigned long addr,
+ unsigned long type, struct pt_regs *regs);
+#endif
+void do_dispatch_general(unsigned long entry, unsigned long addr,
+ unsigned long itype, struct pt_regs *regs,
+ unsigned long oipc)
+{
+ unsigned int swid = itype >> ITYPE_offSWID;
+ unsigned long type = itype & (ITYPE_mskINST | ITYPE_mskETYPE);
+ if (type == ETYPE_ALIGNMENT_CHECK) {
+#ifdef CONFIG_ALIGNMENT_TRAP
+ /* Alignment check */
+ if (unalign_access_mode & 0x3) {
+ int ret;
+ ret = do_unaligned_access(entry, addr, type, regs);
+
+ if (ret == 0)
+ return;
+
+ if (ret == -EFAULT)
+ pr_emerg
+ ("Unhandled unaligned access exception\n");
+ }
+#endif
+ do_page_fault(entry, addr, type, regs);
+ } else if (type == ETYPE_RESERVED_INSTRUCTION) {
+ /* Reserved instruction */
+ do_revinsn(regs);
+ } else if (type == ETYPE_TRAP && swid == SWID_RAISE_INTERRUPT_LEVEL) {
+ /* trap, used on v3 EDM target debugging workaround */
+ /*
+ * DIPC(OIPC) is passed as parameter before
+ * interrupt is enabled, so the DIPC will not be corrupted
+ * even though interrupts are coming in
+ */
+ /*
+ * 1. update ipc
+ * 2. update pt_regs ipc with oipc
+ * 3. update pt_regs ipsw (clear DEX)
+ */
+ __asm__ volatile ("mtsr %0, $IPC\n\t"::"r" (oipc));
+ regs->ipc = oipc;
+ if (regs->pipsw & PSW_mskDEX) {
+ pr_emerg
+ ("Nested Debug exception is possibly happened\n");
+ pr_emerg("ipc:%08x pipc:%08x\n",
+ (unsigned int)regs->ipc,
+ (unsigned int)regs->pipc);
+ }
+ do_debug_trap(entry, addr, itype, regs);
+ regs->ipsw &= ~PSW_mskDEX;
+ } else
+ unhandled_exceptions(entry, addr, type, regs);
+}
diff --git a/arch/nds32/mm/alignment.c b/arch/nds32/mm/alignment.c
new file mode 100644
index 0000000..653b89b
--- /dev/null
+++ b/arch/nds32/mm/alignment.c
@@ -0,0 +1,609 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/proc_fs.h>
+#include <linux/uaccess.h>
+#include <linux/sysctl.h>
+#include <asm/unaligned.h>
+
+#define DEBUG(enable, tagged, ...) \
+ do{ \
+ if (enable) { \
+ if (tagged) \
+ pr_warn("[ %30s() ] ", __func__); \
+ pr_warn(__VA_ARGS__); \
+ } \
+ } while (0)
+
+#define RT(inst) (((inst) >> 20) & 0x1FUL)
+#define RA(inst) (((inst) >> 15) & 0x1FUL)
+#define RB(inst) (((inst) >> 10) & 0x1FUL)
+#define SV(inst) (((inst) >> 8) & 0x3UL)
+#define IMM(inst) (((inst) >> 0) & 0x3FFFUL)
+
+#define RA3(inst) (((inst) >> 3) & 0x7UL)
+#define RT3(inst) (((inst) >> 6) & 0x7UL)
+#define IMM3U(inst) (((inst) >> 0) & 0x7UL)
+
+#define RA5(inst) (((inst) >> 0) & 0x1FUL)
+#define RT4(inst) (((inst) >> 5) & 0xFUL)
+
+#define __get8_data(val,addr,err) \
+ __asm__( \
+ "1: lbi.bi %1, [%2], #1\n" \
+ "2:\n" \
+ " .pushsection .text.fixup,\"ax\"\n" \
+ " .align 2\n" \
+ "3: movi %0, #1\n" \
+ " j 2b\n" \
+ " .popsection\n" \
+ " .pushsection __ex_table,\"a\"\n" \
+ " .align 3\n" \
+ " .long 1b, 3b\n" \
+ " .popsection\n" \
+ : "=r" (err), "=&r" (val), "=r" (addr) \
+ : "0" (err), "2" (addr))
+
+#define get16_data(addr, val_ptr) \
+ do { \
+ unsigned int err = 0, v, a = addr; \
+ __get8_data(v,a,err); \
+ *val_ptr = v << 0; \
+ __get8_data(v,a,err); \
+ *val_ptr |= v << 8; \
+ if (err) \
+ goto fault; \
+ *val_ptr = le16_to_cpu(*val_ptr); \
+ } while(0)
+
+#define get32_data(addr, val_ptr) \
+ do { \
+ unsigned int err = 0, v, a = addr; \
+ __get8_data(v,a,err); \
+ *val_ptr = v << 0; \
+ __get8_data(v,a,err); \
+ *val_ptr |= v << 8; \
+ __get8_data(v,a,err); \
+ *val_ptr |= v << 16; \
+ __get8_data(v,a,err); \
+ *val_ptr |= v << 24; \
+ if (err) \
+ goto fault; \
+ *val_ptr = le32_to_cpu(*val_ptr); \
+ } while(0)
+
+#define get_data(addr, val_ptr, len) \
+ if (len == 2) \
+ get16_data(addr, val_ptr); \
+ else \
+ get32_data(addr, val_ptr);
+
+
+#define set16_data(addr, val) \
+ do { \
+ unsigned int err = 0, *ptr = addr ; \
+ val = le32_to_cpu(val); \
+ __asm__( \
+ "1: sbi.bi %2, [%1], #1\n" \
+ " srli %2, %2, #8\n" \
+ "2: sbi %2, [%1]\n" \
+ "3:\n" \
+ " .pushsection .text.fixup,\"ax\"\n" \
+ " .align 2\n" \
+ "4: movi %0, #1\n" \
+ " j 3b\n" \
+ " .popsection\n" \
+ " .pushsection __ex_table,\"a\"\n" \
+ " .align 3\n" \
+ " .long 1b, 4b\n" \
+ " .long 2b, 4b\n" \
+ " .popsection\n" \
+ : "=r" (err), "+r" (ptr), "+r" (val) \
+ : "0" (err) \
+ ); \
+ if (err) \
+ goto fault; \
+ } while(0)
+
+#define set32_data(addr, val) \
+ do { \
+ unsigned int err = 0, *ptr = addr ; \
+ val = le32_to_cpu(val); \
+ __asm__( \
+ "1: sbi.bi %2, [%1], #1\n" \
+ " srli %2, %2, #8\n" \
+ "2: sbi.bi %2, [%1], #1\n" \
+ " srli %2, %2, #8\n" \
+ "3: sbi.bi %2, [%1], #1\n" \
+ " srli %2, %2, #8\n" \
+ "4: sbi %2, [%1]\n" \
+ "5:\n" \
+ " .pushsection .text.fixup,\"ax\"\n" \
+ " .align 2\n" \
+ "6: movi %0, #1\n" \
+ " j 5b\n" \
+ " .popsection\n" \
+ " .pushsection __ex_table,\"a\"\n" \
+ " .align 3\n" \
+ " .long 1b, 6b\n" \
+ " .long 2b, 6b\n" \
+ " .long 3b, 6b\n" \
+ " .long 4b, 6b\n" \
+ " .popsection\n" \
+ : "=r" (err), "+r" (ptr), "+r" (val) \
+ : "0" (err) \
+ ); \
+ if (err) \
+ goto fault; \
+ } while(0)
+#define set_data(addr, val, len) \
+ if (len == 2) \
+ set16_data(addr, val); \
+ else \
+ set32_data(addr, val);
+extern pte_t va_present(struct mm_struct *mm, unsigned long addr);
+extern pte_t va_kernel_present(unsigned long addr);
+extern int va_readable(struct pt_regs *regs, unsigned long addr);
+extern int va_writable(struct pt_regs *regs, unsigned long addr);
+
+int unalign_access_mode = 0, unalign_access_debug = 0;
+
+static inline unsigned long *idx_to_addr(struct pt_regs *regs, int idx)
+{
+ /* this should be consistent with ptrace.h */
+ if (idx >= 0 && idx <= 25) /* R0-R25 */
+ return ®s->uregs[0] + idx;
+ else if (idx >= 28 && idx <= 30) /* FP, GP, LP */
+ return ®s->fp + (idx - 28);
+ else if (idx == 31) /* SP */
+ return ®s->sp;
+ else
+ return NULL; /* cause a segfault */
+}
+
+static inline unsigned long get_inst(unsigned long addr)
+{
+ return be32_to_cpu(get_unaligned((u32 *) addr));
+}
+
+
+static inline unsigned long sign_extend(unsigned long val, int len)
+{
+ unsigned long ret = 0;
+ unsigned char *s, *t;
+ int i = 0;
+
+ val = cpu_to_le32(val);
+
+ s = (void *)&val;
+ t = (void *)&ret;
+
+ while (i++ < len)
+ *t++ = *s++;
+
+ if (((*(t - 1)) & 0x80) && (i < 4)) {
+
+ while (i++ <= 4)
+ *t++ = 0xff;
+ }
+
+ return le32_to_cpu(ret);
+}
+
+static inline int do_16(unsigned long inst, struct pt_regs *regs)
+{
+ int imm, regular, load, len, addr_mode, idx_mode;
+ unsigned long unaligned_addr, target_val, source_idx, target_idx,
+ shift = 0;
+ switch ((inst >> 9) & 0x3F) {
+
+ case 0x12: /* LHI333 */
+ imm = 1;
+ regular = 1;
+ load = 1;
+ len = 2;
+ addr_mode = 3;
+ idx_mode = 3;
+ break;
+ case 0x10: /* LWI333 */
+ imm = 1;
+ regular = 1;
+ load = 1;
+ len = 4;
+ addr_mode = 3;
+ idx_mode = 3;
+ break;
+ case 0x11: /* LWI333.bi */
+ imm = 1;
+ regular = 0;
+ load = 1;
+ len = 4;
+ addr_mode = 3;
+ idx_mode = 3;
+ break;
+ case 0x1A: /* LWI450 */
+ imm = 0;
+ regular = 1;
+ load = 1;
+ len = 4;
+ addr_mode = 5;
+ idx_mode = 4;
+ break;
+ case 0x16: /* SHI333 */
+ imm = 1;
+ regular = 1;
+ load = 0;
+ len = 2;
+ addr_mode = 3;
+ idx_mode = 3;
+ break;
+ case 0x14: /* SWI333 */
+ imm = 1;
+ regular = 1;
+ load = 0;
+ len = 4;
+ addr_mode = 3;
+ idx_mode = 3;
+ break;
+ case 0x15: /* SWI333.bi */
+ imm = 1;
+ regular = 0;
+ load = 0;
+ len = 4;
+ addr_mode = 3;
+ idx_mode = 3;
+ break;
+ case 0x1B: /* SWI450 */
+ imm = 0;
+ regular = 1;
+ load = 0;
+ len = 4;
+ addr_mode = 5;
+ idx_mode = 4;
+ break;
+
+ default:
+ return -EFAULT;
+ }
+
+ if (addr_mode == 3) {
+ unaligned_addr = *idx_to_addr(regs, RA3(inst));
+ source_idx = RA3(inst);
+ } else {
+ unaligned_addr = *idx_to_addr(regs, RA5(inst));
+ source_idx = RA5(inst);
+ }
+
+ if (idx_mode == 3)
+ target_idx = RT3(inst);
+ else
+ target_idx = RT4(inst);
+
+ if (imm)
+ shift = IMM3U(inst) * len;
+
+ if (regular)
+ unaligned_addr += shift;
+
+ if (load) {
+ if (!access_ok(VERIFY_READ, (void *)unaligned_addr, len))
+ return -EACCES;
+
+ get_data(unaligned_addr,&target_val,len);
+ *idx_to_addr(regs, target_idx) = target_val;
+ } else {
+ if (!access_ok(VERIFY_WRITE, (void *)unaligned_addr, len))
+ return -EACCES;
+ target_val = *idx_to_addr(regs, target_idx);
+ set_data((void *)unaligned_addr, target_val, len);
+ }
+
+ if(!regular)
+ *idx_to_addr(regs, source_idx) = unaligned_addr + shift;
+ regs->ipc += 2;
+
+ return 0;
+fault:
+ return -EACCES;
+}
+
+static inline int do_32(unsigned long inst, struct pt_regs *regs)
+{
+ int imm, regular, load, len, sign_ext;
+ unsigned long unaligned_addr, target_val, shift;
+
+ unaligned_addr = *idx_to_addr(regs, RA(inst));
+
+ switch ((inst >> 25) << 1) {
+
+ case 0x02: /* LHI */
+ imm = 1;
+ regular = 1;
+ load = 1;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x0A: /* LHI.bi */
+ imm = 1;
+ regular = 0;
+ load = 1;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x22: /* LHSI */
+ imm = 1;
+ regular = 1;
+ load = 1;
+ len = 2;
+ sign_ext = 1;
+ break;
+ case 0x2A: /* LHSI.bi */
+ imm = 1;
+ regular = 0;
+ load = 1;
+ len = 2;
+ sign_ext = 1;
+ break;
+ case 0x04: /* LWI */
+ imm = 1;
+ regular = 1;
+ load = 1;
+ len = 4;
+ sign_ext = 0;
+ break;
+ case 0x0C: /* LWI.bi */
+ imm = 1;
+ regular = 0;
+ load = 1;
+ len = 4;
+ sign_ext = 0;
+ break;
+ case 0x12: /* SHI */
+ imm = 1;
+ regular = 1;
+ load = 0;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x1A: /* SHI.bi */
+ imm = 1;
+ regular = 0;
+ load = 0;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x14: /* SWI */
+ imm = 1;
+ regular = 1;
+ load = 0;
+ len = 4;
+ sign_ext = 0;
+ break;
+ case 0x1C: /* SWI.bi */
+ imm = 1;
+ regular = 0;
+ load = 0;
+ len = 4;
+ sign_ext = 0;
+ break;
+
+ default:
+ switch (inst & 0xff) {
+
+ case 0x01: /* LH */
+ imm = 0;
+ regular = 1;
+ load = 1;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x05: /* LH.bi */
+ imm = 0;
+ regular = 0;
+ load = 1;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x11: /* LHS */
+ imm = 0;
+ regular = 1;
+ load = 1;
+ len = 2;
+ sign_ext = 1;
+ break;
+ case 0x15: /* LHS.bi */
+ imm = 0;
+ regular = 0;
+ load = 1;
+ len = 2;
+ sign_ext = 1;
+ break;
+ case 0x02: /* LW */
+ imm = 0;
+ regular = 1;
+ load = 1;
+ len = 4;
+ sign_ext = 0;
+ break;
+ case 0x06: /* LW.bi */
+ imm = 0;
+ regular = 0;
+ load = 1;
+ len = 4;
+ sign_ext = 0;
+ break;
+ case 0x09: /* SH */
+ imm = 0;
+ regular = 1;
+ load = 0;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x0D: /* SH.bi */
+ imm = 0;
+ regular = 0;
+ load = 0;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x0A: /* SW */
+ imm = 0;
+ regular = 1;
+ load = 0;
+ len = 4;
+ sign_ext = 0;
+ break;
+ case 0x0E: /* SW.bi */
+ imm = 0;
+ regular = 0;
+ load = 0;
+ len = 4;
+ sign_ext = 0;
+ break;
+
+ default:
+ return -EFAULT;
+ }
+ }
+
+ if (imm)
+ shift = IMM(inst) * len;
+ else
+ shift = *idx_to_addr(regs, RB(inst)) << SV(inst);
+
+
+ if (regular)
+ unaligned_addr += shift;
+
+ if (load) {
+
+ if (!access_ok(VERIFY_READ, (void *)unaligned_addr, len))
+ return -EACCES;
+
+ get_data(unaligned_addr,&target_val,len);
+
+ if (sign_ext)
+ *idx_to_addr(regs, RT(inst)) =
+ sign_extend(target_val, len);
+ else
+ *idx_to_addr(regs, RT(inst)) = target_val;
+ } else {
+
+ if (!access_ok(VERIFY_WRITE, (void *)unaligned_addr, len))
+ return -EACCES;
+
+ target_val = *idx_to_addr(regs, RT(inst));
+ set_data((void *)unaligned_addr, target_val, len);
+ }
+
+ if(!regular)
+ *idx_to_addr(regs, RA(inst)) = unaligned_addr + shift;
+
+ regs->ipc += 4;
+
+ return 0;
+fault:
+ return -EACCES;
+}
+
+int do_unaligned_access(unsigned long entry, unsigned long addr,
+ unsigned long type, struct pt_regs *regs)
+{
+ unsigned long inst;
+ int ret = -EFAULT;
+
+ inst = get_inst(regs->ipc);
+
+ DEBUG((unalign_access_debug > 0), 1,
+ "Faulting addr: 0x%08lx, pc: 0x%08lx [inst: 0x%08lx ]\n"
+ "unalign_access_mode: %x\n"
+ , addr,regs->ipc, inst, unalign_access_mode);
+
+ if ((user_mode(regs) && (unalign_access_mode & 0x01))
+ || (!user_mode(regs) && (unalign_access_mode & 0x02))) {
+
+ mm_segment_t seg = get_fs();
+
+ user_mode(regs)?set_fs(USER_DS):set_fs(KERNEL_DS);
+
+ if (inst & 0x80000000)
+ {
+ ret = do_16((inst >> 16) & 0xffff, regs);
+ }
+ else
+ {
+ ret = do_32(inst, regs);
+ }
+ set_fs(seg);
+ }
+
+ return ret;
+}
+
+#ifdef CONFIG_PROC_FS
+
+static
+int unalign_access_policy(struct ctl_table *ctl, int write,
+ void __user * buffer, size_t * lenp, loff_t * ppos)
+{
+ int val = *(int *)(ctl->data);
+ loff_t pos = *ppos;
+ struct ctl_table lctl;
+ int ret;
+
+ lctl = *ctl;
+ lctl.data = &val;
+ ret = proc_dointvec(&lctl, write, buffer, lenp, ppos);
+
+ if (ret)
+ *ppos = pos;
+ else {
+ *(int *)ctl->data = val;
+ if (val > 3)
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+static struct ctl_table alignment_tbl[3] = {
+ {
+ .procname = "enable_mode",
+ .data = &unalign_access_mode,
+ .maxlen = sizeof(unalign_access_mode),
+ .mode = 0666,
+ .proc_handler = unalign_access_policy,
+ },
+ {
+ .procname = "debug",
+ .data = &unalign_access_debug,
+ .maxlen = sizeof(unalign_access_mode),
+ .mode = 0644,
+ .proc_handler = &proc_dointvec
+ },
+ {}
+};
+
+static struct ctl_table nds32_sysctl_table[2] = {
+ {
+ .procname = "unaligned_acess",
+ .mode = 0555,
+ .child = alignment_tbl},
+ {}
+};
+static struct ctl_path nds32_path[2] = {
+ {.procname = "nds32" },
+ {}
+};
+
+/*
+ * Initialize nds32 alignment-correction interface
+ */
+static int __init nds32_sysctl_init(void)
+{
+ register_sysctl_paths(nds32_path, nds32_sysctl_table);
+ return 0;
+}
+
+__initcall(nds32_sysctl_init);
+#endif /* CONFIG_PROC_FS */
--
1.7.9.5
^ permalink raw reply related
* [PATCH v5 06/39] nds32: Kernel booting and initialization
From: Greentime Hu @ 2018-01-02 8:24 UTC (permalink / raw)
To: greentime-MUIXKm3Oiri1Z/+hSey0Gg,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
linux-arch-u79uwXL29TY76Z2rM5mHXA, tglx-hfZtesqFncYOwBW4kG4KsQ,
jason-NLaQJdtUoK4Be96aLqz0jA, marc.zyngier-5wv7dgnIgG8,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, netdev-u79uwXL29TY76Z2rM5mHXA,
deanbo422-Re5JQEeQqe8AvxtiuMwx3w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
viro-RmSDqhL/yNMiFSDQTTA3OLVCufUGDwFn,
dhowells-H+wXaHxf7aLQT0dZR+AlfA, will.deacon-5wv7dgnIgG8,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
linux-serial-u79uwXL29TY76Z2rM5mHXA,
geert.uytterhoeven-Re5JQEeQqe8AvxtiuMwx3w,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
greg-U8xfFu+wG4EAvxtiuMwx3w, ren_guo-Y+KPrCd2zL4AvxtiuMwx3w,
rdunlap-wEGCiKHe2LqWVfeAwA7xHQ, davem-fT/PcQaiUtIeIZ0/mPfg9Q,
jonas-A9uVI2HLR7kOP4wsBPIw7w,
stefan.kristiansson-MbMCFXIvDHJFcC0YU169RA,
shorne-Re5JQEeQqe8AvxtiuMwx3w
Cc: green.hu-Re5JQEeQqe8AvxtiuMwx3w, Vincent Chen
In-Reply-To: <cover.1514874857.git.green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Greentime Hu <greentime-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org>
This patch includes the kernel startup code. It can get dtb pointer
passed from bootloader. It will create a temp mapping by tlb
instructions at beginning and goto start_kernel.
Signed-off-by: Vincent Chen <vincentc-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org>
Signed-off-by: Greentime Hu <greentime-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org>
---
arch/nds32/kernel/head.S | 188 ++++++++++++++++++++++
arch/nds32/kernel/setup.c | 387 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 575 insertions(+)
create mode 100644 arch/nds32/kernel/head.S
create mode 100644 arch/nds32/kernel/setup.c
diff --git a/arch/nds32/kernel/head.S b/arch/nds32/kernel/head.S
new file mode 100644
index 0000000..71f57bd
--- /dev/null
+++ b/arch/nds32/kernel/head.S
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/ptrace.h>
+#include <asm/asm-offsets.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/sizes.h>
+#include <asm/thread_info.h>
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define OF_DT_MAGIC 0xd00dfeed
+#else
+#define OF_DT_MAGIC 0xedfe0dd0
+#endif
+
+ .globl swapper_pg_dir
+ .equ swapper_pg_dir, TEXTADDR - 0x4000
+
+/*
+ * Kernel startup entry point.
+ */
+ .section ".head.text", "ax"
+ .type _stext, %function
+ENTRY(_stext)
+ setgie.d ! Disable interrupt
+ isb
+/*
+ * Disable I/D-cache and enable it at a proper time
+ */
+ mfsr $r0, $mr8
+ li $r1, #~(CACHE_CTL_mskIC_EN|CACHE_CTL_mskDC_EN)
+ and $r0, $r0, $r1
+ mtsr $r0, $mr8
+
+/*
+ * Process device tree blob
+ */
+ andi $r0,$r2,#0x3
+ li $r10, 0
+ bne $r0, $r10, _nodtb
+ lwi $r0, [$r2]
+ li $r1, OF_DT_MAGIC
+ bne $r0, $r1, _nodtb
+ move $r10, $r2
+_nodtb:
+
+/*
+ * Create a temporary mapping area for booting, before start_kernel
+ */
+ sethi $r4, hi20(swapper_pg_dir)
+ li $p0, (PAGE_OFFSET - PHYS_OFFSET)
+ sub $r4, $r4, $p0
+ tlbop FlushAll ! invalidate TLB\n"
+ isb
+ mtsr $r4, $L1_PPTB ! load page table pointer\n"
+
+/* set NTC0 cacheable/writeback, mutliple page size in use */
+ mfsr $r3, $MMU_CTL
+ li $r0, #~MMU_CTL_mskNTC0
+ and $r3, $r3, $r0
+#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
+ ori $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << MMU_CTL_offNTC0))
+#else
+ ori $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << MMU_CTL_offNTC0)|MMU_CTL_D8KB)
+#endif
+#ifdef CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS
+ li $r0, #MMU_CTL_UNA
+ or $r3, $r3, $r0
+#endif
+ mtsr $r3, $MMU_CTL
+ isb
+
+/* set page size and size of kernel image */
+ mfsr $r0, $MMU_CFG
+ srli $r3, $r0, MMU_CFG_offfEPSZ
+ zeb $r3, $r3
+ bnez $r3, _extra_page_size_support
+#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
+ li $r5, #SZ_4K ! Use 4KB page size
+#else
+ li $r5, #SZ_8K ! Use 8KB page size
+ li $r3, #1
+#endif
+ mtsr $r3, $TLB_MISC
+ b _image_size_check
+
+_extra_page_size_support: ! Use epzs pages size
+ clz $r6, $r3
+ subri $r2, $r6, #31
+ li $r3, #1
+ sll $r3, $r3, $r2
+ /* MMU_CFG.EPSZ value -> meaning */
+ mul $r5, $r3, $r3
+ slli $r5, $r5, #14
+ /* MMU_CFG.EPSZ -> TLB_MISC.ACC_PSZ */
+ addi $r3, $r2, #0x2
+ mtsr $r3, $TLB_MISC
+
+_image_size_check:
+ /* calculate the image maximum size accepted by TLB config */
+ andi $r6, $r0, MMU_CFG_mskTBW
+ andi $r0, $r0, MMU_CFG_mskTBS
+ srli $r6, $r6, MMU_CFG_offTBW
+ srli $r0, $r0, MMU_CFG_offTBS
+ /*
+ * we just map the kernel to the maximum way - 1 of tlb
+ * reserver one way for UART VA mapping
+ * it will cause page fault if UART mapping cover the kernel mapping
+ *
+ * direct mapping is not supported now.
+ */
+ li $r2, 't'
+ beqz $r6, __error ! MMU_CFG.TBW = 0 is direct mappin
+ addi $r0, $r0, #0x2 ! MMU_CFG.TBS value -> meaning
+ sll $r0, $r6, $r0 ! entries = k-way * n-set
+ mul $r6, $r0, $r5 ! max size = entries * page size
+ /* check kernel image size */
+ la $r3, (_end - PAGE_OFFSET)
+ li $r2, 's'
+ bgt $r3, $r6, __error
+
+ li $r2, #(PHYS_OFFSET + TLB_DATA_kernel_text_attr)
+ li $r3, PAGE_OFFSET
+ add $r6, $r6, $r3
+
+_tlb:
+ mtsr $r3, $TLB_VPN
+ dsb
+ tlbop $r2, RWR
+ isb
+ add $r3, $r3, $r5
+ add $r2, $r2, $r5
+ bgt $r6, $r3, _tlb
+ mfsr $r3, $TLB_MISC ! setup access page size
+ li $r2, #~0xf
+ and $r3, $r3, $r2
+#ifdef CONFIG_ANDES_PAGE_SIZE_8KB
+ ori $r3, $r3, #0x1
+#endif
+ mtsr $r3, $TLB_MISC
+
+ mfsr $r0, $MISC_CTL ! Enable BTB and RTP and shadow sp
+ ori $r0, $r0, #MISC_init
+ mtsr $r0, $MISC_CTL
+
+ mfsr $p1, $PSW
+ li $r15, #~PSW_clr ! clear WBNA|DME|IME|DT|IT|POM|INTL|GIE
+ and $p1, $p1, $r15
+ ori $p1, $p1, #PSW_init
+ mtsr $p1, $IPSW ! when iret, it will automatically enable MMU
+ la $lp, __mmap_switched
+ mtsr $lp, $IPC
+ iret
+ nop
+
+ .type __switch_data, %object
+__switch_data:
+ .long __bss_start ! $r6
+ .long _end ! $r7
+ .long __atags_pointer ! $atag_pointer
+ .long init_task ! $r9, move to $r25
+ .long init_thread_union + THREAD_SIZE ! $sp
+
+
+/*
+ * The following fragment of code is executed with the MMU on in MMU mode,
+ * and uses absolute addresses; this is not position independent.
+ */
+ .align
+ .type __mmap_switched, %function
+__mmap_switched:
+ la $r3, __switch_data
+ lmw.bim $r6, [$r3], $r9, #0b0001
+ move $r25, $r9
+ move $fp, #0 ! Clear BSS (and zero $fp)
+ beq $r7, $r6, _RRT
+1: swi.bi $fp, [$r6], #4
+ bne $r7, $r6, 1b
+ swi $r10, [$r8]
+
+_RRT:
+ b start_kernel
+
+__error:
+ b __error
diff --git a/arch/nds32/kernel/setup.c b/arch/nds32/kernel/setup.c
new file mode 100644
index 0000000..01f2654d7
--- /dev/null
+++ b/arch/nds32/kernel/setup.c
@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/cpu.h>
+#include <linux/bootmem.h>
+#include <linux/seq_file.h>
+#include <linux/memblock.h>
+#include <linux/console.h>
+#include <linux/screen_info.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
+#include <asm/setup.h>
+#include <asm/sections.h>
+#include <asm/proc-fns.h>
+#include <asm/cache_info.h>
+#include <asm/elf.h>
+#include <nds32_intrinsic.h>
+
+#define HWCAP_MFUSR_PC 0x000001
+#define HWCAP_EXT 0x000002
+#define HWCAP_EXT2 0x000004
+#define HWCAP_FPU 0x000008
+#define HWCAP_AUDIO 0x000010
+#define HWCAP_BASE16 0x000020
+#define HWCAP_STRING 0x000040
+#define HWCAP_REDUCED_REGS 0x000080
+#define HWCAP_VIDEO 0x000100
+#define HWCAP_ENCRYPT 0x000200
+#define HWCAP_EDM 0x000400
+#define HWCAP_LMDMA 0x000800
+#define HWCAP_PFM 0x001000
+#define HWCAP_HSMP 0x002000
+#define HWCAP_TRACE 0x004000
+#define HWCAP_DIV 0x008000
+#define HWCAP_MAC 0x010000
+#define HWCAP_L2C 0x020000
+#define HWCAP_FPU_DP 0x040000
+#define HWCAP_V2 0x080000
+#define HWCAP_DX_REGS 0x100000
+
+#ifdef CONFIG_VGA_CONSOLE
+struct screen_info screen_info;
+#endif
+
+extern struct mm_struct init_mm;
+unsigned long cpu_id, cpu_rev, cpu_cfgid;
+char cpu_series;
+char *endianness = NULL;
+
+unsigned int __atags_pointer __initdata;
+unsigned int elf_hwcap;
+EXPORT_SYMBOL(elf_hwcap);
+
+extern void __init early_init_devtree(void *params);
+extern void __init early_trap_init(void);
+/*
+ * The following string table, must sync with HWCAP_xx bitmask,
+ * which is defined in <asm/procinfo.h>
+ */
+static const char *hwcap_str[] = {
+ "mfusr_pc",
+ "perf1",
+ "perf2",
+ "fpu",
+ "audio",
+ "16b",
+ "string",
+ "reduced_regs",
+ "video",
+ "encrypt",
+ "edm",
+ "lmdma",
+ "pfm",
+ "hsmp",
+ "trace",
+ "div",
+ "mac",
+ "l2c",
+ "dx_regs",
+ "v2",
+ NULL,
+};
+
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+#define WRITE_METHOD "write through"
+#else
+#define WRITE_METHOD "write back"
+#endif
+
+struct cache_info L1_cache_info[2];
+static void __init dump_cpu_info(int cpu)
+{
+ int i, p = 0;
+ char str[sizeof(hwcap_str) + 16];
+
+ for (i = 0; hwcap_str[i]; i++) {
+ if (elf_hwcap & (1 << i)) {
+ sprintf(str + p, "%s ", hwcap_str[i]);
+ p += strlen(hwcap_str[i]) + 1;
+ }
+ }
+
+ pr_info("CPU%d Features: %s\n", cpu, str);
+
+ L1_cache_info[ICACHE].ways = CACHE_WAY(ICACHE);
+ L1_cache_info[ICACHE].line_size = CACHE_LINE_SIZE(ICACHE);
+ L1_cache_info[ICACHE].sets = CACHE_SET(ICACHE);
+ L1_cache_info[ICACHE].size =
+ L1_cache_info[ICACHE].ways * L1_cache_info[ICACHE].line_size *
+ L1_cache_info[ICACHE].sets / 1024;
+ pr_info("L1I:%dKB/%dS/%dW/%dB\n", L1_cache_info[ICACHE].size,
+ L1_cache_info[ICACHE].sets, L1_cache_info[ICACHE].ways,
+ L1_cache_info[ICACHE].line_size);
+ L1_cache_info[DCACHE].ways = CACHE_WAY(DCACHE);
+ L1_cache_info[DCACHE].line_size = CACHE_LINE_SIZE(DCACHE);
+ L1_cache_info[DCACHE].sets = CACHE_SET(DCACHE);
+ L1_cache_info[DCACHE].size =
+ L1_cache_info[DCACHE].ways * L1_cache_info[DCACHE].line_size *
+ L1_cache_info[DCACHE].sets / 1024;
+ pr_info("L1D:%dKB/%dS/%dW/%dB\n", L1_cache_info[DCACHE].size,
+ L1_cache_info[DCACHE].sets, L1_cache_info[DCACHE].ways,
+ L1_cache_info[DCACHE].line_size);
+ pr_info("L1 D-Cache is %s\n", WRITE_METHOD);
+ if (L1_cache_info[DCACHE].size != L1_CACHE_BYTES)
+ pr_crit
+ ("The cache line size(%d) of this processor is not the same as L1_CACHE_BYTES(%d).\n",
+ L1_cache_info[DCACHE].size, L1_CACHE_BYTES);
+#ifdef CONFIG_CPU_CACHE_ALIASING
+ {
+ int aliasing_num;
+ aliasing_num =
+ L1_cache_info[ICACHE].size * 1024 / PAGE_SIZE /
+ L1_cache_info[ICACHE].ways;
+ L1_cache_info[ICACHE].aliasing_num = aliasing_num;
+ L1_cache_info[ICACHE].aliasing_mask =
+ (aliasing_num - 1) << PAGE_SHIFT;
+ aliasing_num =
+ L1_cache_info[DCACHE].size * 1024 / PAGE_SIZE /
+ L1_cache_info[DCACHE].ways;
+ L1_cache_info[DCACHE].aliasing_num = aliasing_num;
+ L1_cache_info[DCACHE].aliasing_mask =
+ (aliasing_num - 1) << PAGE_SHIFT;
+ }
+#endif
+}
+
+static void __init setup_cpuinfo(void)
+{
+ unsigned long tmp = 0, cpu_name;
+
+ cpu_dcache_inval_all();
+ cpu_icache_inval_all();
+ __nds32__isb();
+
+ cpu_id = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskCPUID) >> CPU_VER_offCPUID;
+ cpu_name = ((cpu_id) & 0xf0) >> 4;
+ cpu_series = cpu_name ? cpu_name - 10 + 'A' : 'N';
+ cpu_id = cpu_id & 0xf;
+ cpu_rev = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskREV) >> CPU_VER_offREV;
+ cpu_cfgid = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskCFGID) >> CPU_VER_offCFGID;
+
+ pr_info("CPU:%c%ld, CPU_VER 0x%08x(id %lu, rev %lu, cfg %lu)\n",
+ cpu_series, cpu_id, __nds32__mfsr(NDS32_SR_CPU_VER), cpu_id, cpu_rev, cpu_cfgid);
+
+ elf_hwcap |= HWCAP_MFUSR_PC;
+
+ if (((__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskBASEV) >> MSC_CFG_offBASEV) == 0) {
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskDIV)
+ elf_hwcap |= HWCAP_DIV;
+
+ if ((__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskMAC)
+ || (cpu_id == 12 && cpu_rev < 4))
+ elf_hwcap |= HWCAP_MAC;
+ } else {
+ elf_hwcap |= HWCAP_V2;
+ elf_hwcap |= HWCAP_DIV;
+ elf_hwcap |= HWCAP_MAC;
+ }
+
+ if (cpu_cfgid & 0x0001)
+ elf_hwcap |= HWCAP_EXT;
+
+ if (cpu_cfgid & 0x0002)
+ elf_hwcap |= HWCAP_BASE16;
+
+ if (cpu_cfgid & 0x0004)
+ elf_hwcap |= HWCAP_EXT2;
+
+ if (cpu_cfgid & 0x0008)
+ elf_hwcap |= HWCAP_FPU;
+
+ if (cpu_cfgid & 0x0010)
+ elf_hwcap |= HWCAP_STRING;
+
+ if (__nds32__mfsr(NDS32_SR_MMU_CFG) & MMU_CFG_mskDE)
+ endianness = "MSB";
+ else
+ endianness = "LSB";
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskEDM)
+ elf_hwcap |= HWCAP_EDM;
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskLMDMA)
+ elf_hwcap |= HWCAP_LMDMA;
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskPFM)
+ elf_hwcap |= HWCAP_PFM;
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskHSMP)
+ elf_hwcap |= HWCAP_HSMP;
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskTRACE)
+ elf_hwcap |= HWCAP_TRACE;
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskAUDIO)
+ elf_hwcap |= HWCAP_AUDIO;
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskL2C)
+ elf_hwcap |= HWCAP_L2C;
+
+ tmp = __nds32__mfsr(NDS32_SR_CACHE_CTL);
+ if (!IS_ENABLED(CONFIG_CPU_DCACHE_DISABLE))
+ tmp |= CACHE_CTL_mskDC_EN;
+
+ if (!IS_ENABLED(CONFIG_CPU_ICACHE_DISABLE))
+ tmp |= CACHE_CTL_mskIC_EN;
+ __nds32__mtsr_isb(tmp, NDS32_SR_CACHE_CTL);
+
+ dump_cpu_info(smp_processor_id());
+}
+
+static void __init setup_memory(void)
+{
+ unsigned long ram_start_pfn;
+ unsigned long free_ram_start_pfn;
+ phys_addr_t memory_start, memory_end;
+ struct memblock_region *region;
+
+ memory_end = memory_start = 0;
+
+ /* Find main memory where is the kernel */
+ for_each_memblock(memory, region) {
+ memory_start = region->base;
+ memory_end = region->base + region->size;
+ pr_info("%s: Memory: 0x%x-0x%x\n", __func__,
+ memory_start, memory_end);
+ }
+
+ if (!memory_end) {
+ panic("No memory!");
+ }
+
+ ram_start_pfn = PFN_UP(memblock_start_of_DRAM());
+ /* free_ram_start_pfn is first page after kernel */
+ free_ram_start_pfn = PFN_UP(__pa(&_end));
+ max_pfn = PFN_DOWN(memblock_end_of_DRAM());
+ /* it could update max_pfn */
+ if (max_pfn - ram_start_pfn <= MAXMEM_PFN)
+ max_low_pfn = max_pfn;
+ else {
+ max_low_pfn = MAXMEM_PFN + ram_start_pfn;
+ if (!IS_ENABLED(CONFIG_HIGHMEM))
+ max_pfn = MAXMEM_PFN + ram_start_pfn;
+ }
+ /* high_memory is related with VMALLOC */
+ high_memory = (void *)__va(max_low_pfn * PAGE_SIZE);
+ min_low_pfn = free_ram_start_pfn;
+
+ /*
+ * initialize the boot-time allocator (with low memory only).
+ *
+ * This makes the memory from the end of the kernel to the end of
+ * RAM usable.
+ */
+ memblock_set_bottom_up(true);
+ memblock_reserve(PFN_PHYS(ram_start_pfn), PFN_PHYS(free_ram_start_pfn - ram_start_pfn));
+
+ early_init_fdt_reserve_self();
+ early_init_fdt_scan_reserved_mem();
+
+ memblock_dump_all();
+}
+
+void __init setup_arch(char **cmdline_p)
+{
+ early_init_devtree(__atags_pointer ?
+ phys_to_virt(__atags_pointer) : __dtb_start);
+
+ setup_cpuinfo();
+
+ init_mm.start_code = (unsigned long)&_stext;
+ init_mm.end_code = (unsigned long)&_etext;
+ init_mm.end_data = (unsigned long)&_edata;
+ init_mm.brk = (unsigned long)&_end;
+
+ /* setup bootmem allocator */
+ setup_memory();
+
+ /* paging_init() sets up the MMU and marks all pages as reserved */
+ paging_init();
+
+ /* use generic way to parse */
+ parse_early_param();
+
+ unflatten_and_copy_device_tree();
+
+ if(IS_ENABLED(CONFIG_VT)) {
+ if(IS_ENABLED(CONFIG_VGA_CONSOLE))
+ conswitchp = &vga_con;
+ else if(IS_ENABLED(CONFIG_DUMMY_CONSOLE))
+ conswitchp = &dummy_con;
+ }
+
+ *cmdline_p = boot_command_line;
+ early_trap_init();
+}
+
+void calibrate_delay(void)
+{
+ const int *val;
+ struct device_node *cpu = NULL;
+ cpu = of_find_compatible_node(NULL, NULL, "andestech,nds32v3");
+ val = of_get_property(cpu, "clock-frequency", NULL);
+ if (!val || !*val)
+ panic("no cpu 'clock-frequency' parameter in device tree");
+ loops_per_jiffy = be32_to_cpup(val) / HZ;
+ pr_cont("%lu.%02lu BogoMIPS (lpj=%lu)\n",
+ loops_per_jiffy / (500000 / HZ),
+ (loops_per_jiffy / (5000 / HZ)) % 100, loops_per_jiffy);
+}
+
+static int c_show(struct seq_file *m, void *v)
+{
+ int i;
+
+ seq_printf(m, "Processor\t: %c%ld (id %lu, rev %lu, cfg %lu)\n",
+ cpu_series, cpu_id, cpu_id, cpu_rev, cpu_cfgid);
+
+ seq_printf(m, "L1I\t\t: %luKB/%luS/%luW/%luB\n",
+ CACHE_SET(ICACHE) * CACHE_WAY(ICACHE) *
+ CACHE_LINE_SIZE(ICACHE) / 1024, CACHE_SET(ICACHE),
+ CACHE_WAY(ICACHE), CACHE_LINE_SIZE(ICACHE));
+
+ seq_printf(m, "L1D\t\t: %luKB/%luS/%luW/%luB\n",
+ CACHE_SET(DCACHE) * CACHE_WAY(DCACHE) *
+ CACHE_LINE_SIZE(DCACHE) / 1024, CACHE_SET(DCACHE),
+ CACHE_WAY(DCACHE), CACHE_LINE_SIZE(DCACHE));
+
+ seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
+ loops_per_jiffy / (500000 / HZ),
+ (loops_per_jiffy / (5000 / HZ)) % 100);
+
+ /* dump out the processor features */
+ seq_puts(m, "Features\t: ");
+
+ for (i = 0; hwcap_str[i]; i++)
+ if (elf_hwcap & (1 << i))
+ seq_printf(m, "%s ", hwcap_str[i]);
+
+ seq_puts(m, "\n\n");
+
+ return 0;
+}
+
+static void *c_start(struct seq_file *m, loff_t * pos)
+{
+ return *pos < 1 ? (void *)1 : NULL;
+}
+
+static void *c_next(struct seq_file *m, void *v, loff_t * pos)
+{
+ ++*pos;
+ return NULL;
+}
+
+static void c_stop(struct seq_file *m, void *v)
+{
+}
+
+struct seq_operations cpuinfo_op = {
+ .start = c_start,
+ .next = c_next,
+ .stop = c_stop,
+ .show = c_show
+};
--
1.7.9.5
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^ permalink raw reply related
* [PATCH v5 05/39] nds32: Assembly macros and definitions
From: Greentime Hu @ 2018-01-02 8:24 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial,
geert.uytterhoeven, linus.walleij, mark.rutland, greg, ren_guo,
rdunlap, davem, jonas, stefan.kristiansson, shorne
Cc: green.hu, Vincent Chen
In-Reply-To: <cover.1514874857.git.green.hu@gmail.com>
From: Greentime Hu <greentime@andestech.com>
This patch includes assembly macros, bit field definitions used in .S
files across arch/nds32/.
Signed-off-by: Vincent Chen <vincentc@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
---
arch/nds32/include/asm/assembler.h | 39 ++
arch/nds32/include/asm/bitfield.h | 963 ++++++++++++++++++++++++++++++++++++
arch/nds32/include/asm/nds32.h | 83 ++++
arch/nds32/kernel/asm-offsets.c | 28 ++
4 files changed, 1113 insertions(+)
create mode 100644 arch/nds32/include/asm/assembler.h
create mode 100644 arch/nds32/include/asm/bitfield.h
create mode 100644 arch/nds32/include/asm/nds32.h
create mode 100644 arch/nds32/kernel/asm-offsets.c
diff --git a/arch/nds32/include/asm/assembler.h b/arch/nds32/include/asm/assembler.h
new file mode 100644
index 0000000..c385578
--- /dev/null
+++ b/arch/nds32/include/asm/assembler.h
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_ASSEMBLER_H__
+#define __NDS32_ASSEMBLER_H__
+
+.macro gie_disable
+ setgie.d
+ dsb
+.endm
+
+.macro gie_enable
+ setgie.e
+ dsb
+.endm
+
+.macro gie_save oldpsw
+ mfsr \oldpsw, $ir0
+ setgie.d
+ dsb
+.endm
+
+.macro gie_restore oldpsw
+ andi \oldpsw, \oldpsw, #0x1
+ beqz \oldpsw, 7001f
+ setgie.e
+ dsb
+7001:
+.endm
+
+
+#define USER(insn, reg, addr, opr) \
+9999: insn reg, addr, opr; \
+ .section __ex_table,"a"; \
+ .align 3; \
+ .long 9999b, 9001f; \
+ .previous
+
+#endif /* __NDS32_ASSEMBLER_H__ */
diff --git a/arch/nds32/include/asm/bitfield.h b/arch/nds32/include/asm/bitfield.h
new file mode 100644
index 0000000..c73f71d
--- /dev/null
+++ b/arch/nds32/include/asm/bitfield.h
@@ -0,0 +1,963 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_BITFIELD_H__
+#define __NDS32_BITFIELD_H__
+/******************************************************************************
+ * cr0: CPU_VER (CPU Version Register)
+ *****************************************************************************/
+#define CPU_VER_offCFGID 0 /* Minor configuration */
+#define CPU_VER_offREV 16 /* Revision of the CPU version */
+#define CPU_VER_offCPUID 24 /* Major CPU versions */
+
+#define CPU_VER_mskCFGID ( 0xFFFF << CPU_VER_offCFGID )
+#define CPU_VER_mskREV ( 0xFF << CPU_VER_offREV )
+#define CPU_VER_mskCPUID ( 0xFF << CPU_VER_offCPUID )
+
+/******************************************************************************
+ * cr1: ICM_CFG (Instruction Cache/Memory Configuration Register)
+ *****************************************************************************/
+#define ICM_CFG_offISET 0 /* I-cache sets (# of cache lines) per way */
+#define ICM_CFG_offIWAY 3 /* I-cache ways */
+#define ICM_CFG_offISZ 6 /* I-cache line size */
+#define ICM_CFG_offILCK 9 /* I-cache locking support */
+#define ICM_CFG_offILMB 10 /* On-chip ILM banks */
+#define ICM_CFG_offBSAV 13 /* ILM base register alignment version */
+/* bit 15:31 reserved */
+
+#define ICM_CFG_mskISET ( 0x7 << ICM_CFG_offISET )
+#define ICM_CFG_mskIWAY ( 0x7 << ICM_CFG_offIWAY )
+#define ICM_CFG_mskISZ ( 0x7 << ICM_CFG_offISZ )
+#define ICM_CFG_mskILCK ( 0x1 << ICM_CFG_offILCK )
+#define ICM_CFG_mskILMB ( 0x7 << ICM_CFG_offILMB )
+#define ICM_CFG_mskBSAV ( 0x3 << ICM_CFG_offBSAV )
+
+/******************************************************************************
+ * cr2: DCM_CFG (Data Cache/Memory Configuration Register)
+ *****************************************************************************/
+#define DCM_CFG_offDSET 0 /* D-cache sets (# of cache lines) per way */
+#define DCM_CFG_offDWAY 3 /* D-cache ways */
+#define DCM_CFG_offDSZ 6 /* D-cache line size */
+#define DCM_CFG_offDLCK 9 /* D-cache locking support */
+#define DCM_CFG_offDLMB 10 /* On-chip DLM banks */
+#define DCM_CFG_offBSAV 13 /* DLM base register alignment version */
+/* bit 15:31 reserved */
+
+#define DCM_CFG_mskDSET ( 0x7 << DCM_CFG_offDSET )
+#define DCM_CFG_mskDWAY ( 0x7 << DCM_CFG_offDWAY )
+#define DCM_CFG_mskDSZ ( 0x7 << DCM_CFG_offDSZ )
+#define DCM_CFG_mskDLCK ( 0x1 << DCM_CFG_offDLCK )
+#define DCM_CFG_mskDLMB ( 0x7 << DCM_CFG_offDLMB )
+#define DCM_CFG_mskBSAV ( 0x3 << DCM_CFG_offBSAV )
+
+/******************************************************************************
+ * cr3: MMU_CFG (MMU Configuration Register)
+ *****************************************************************************/
+#define MMU_CFG_offMMPS 0 /* Memory management protection scheme */
+#define MMU_CFG_offMMPV 2 /* Memory management protection version number */
+#define MMU_CFG_offFATB 7 /* Fully-associative or non-fully-associative TLB */
+
+#define MMU_CFG_offTBW 8 /* TLB ways(non-associative) TBS */
+#define MMU_CFG_offTBS 11 /* TLB sets per way(non-associative) TBS */
+/* bit 14:14 reserved */
+
+#define MMU_CFG_offEP8MIN4 15 /* 8KB page supported while minimum page is 4KB */
+#define MMU_CFG_offfEPSZ 16 /* Extra page size supported */
+#define MMU_CFG_offTLBLCK 24 /* TLB locking support */
+#define MMU_CFG_offHPTWK 25 /* Hardware Page Table Walker implemented */
+#define MMU_CFG_offDE 26 /* Default endian */
+#define MMU_CFG_offNTPT 27 /* Partitions for non-translated attributes */
+#define MMU_CFG_offIVTB 28 /* Invisible TLB */
+#define MMU_CFG_offVLPT 29 /* VLPT for fast TLB fill handling implemented */
+#define MMU_CFG_offNTME 30 /* Non-translated VA to PA mapping */
+/* bit 31 reserved */
+
+#define MMU_CFG_mskMMPS ( 0x3 << MMU_CFG_offMMPS )
+#define MMU_CFG_mskMMPV ( 0x1F << MMU_CFG_offMMPV )
+#define MMU_CFG_mskFATB ( 0x1 << MMU_CFG_offFATB )
+#define MMU_CFG_mskTBW ( 0x7 << MMU_CFG_offTBW )
+#define MMU_CFG_mskTBS ( 0x7 << MMU_CFG_offTBS )
+#define MMU_CFG_mskEP8MIN4 ( 0x1 << MMU_CFG_offEP8MIN4 )
+#define MMU_CFG_mskfEPSZ ( 0xFF << MMU_CFG_offfEPSZ )
+#define MMU_CFG_mskTLBLCK ( 0x1 << MMU_CFG_offTLBLCK )
+#define MMU_CFG_mskHPTWK ( 0x1 << MMU_CFG_offHPTWK )
+#define MMU_CFG_mskDE ( 0x1 << MMU_CFG_offDE )
+#define MMU_CFG_mskNTPT ( 0x1 << MMU_CFG_offNTPT )
+#define MMU_CFG_mskIVTB ( 0x1 << MMU_CFG_offIVTB )
+#define MMU_CFG_mskVLPT ( 0x1 << MMU_CFG_offVLPT )
+#define MMU_CFG_mskNTME ( 0x1 << MMU_CFG_offNTME )
+
+/******************************************************************************
+ * cr4: MSC_CFG (Misc Configuration Register)
+ *****************************************************************************/
+#define MSC_CFG_offEDM 0
+#define MSC_CFG_offLMDMA 1
+#define MSC_CFG_offPFM 2
+#define MSC_CFG_offHSMP 3
+#define MSC_CFG_offTRACE 4
+#define MSC_CFG_offDIV 5
+#define MSC_CFG_offMAC 6
+#define MSC_CFG_offAUDIO 7
+#define MSC_CFG_offL2C 9
+#define MSC_CFG_offRDREG 10
+#define MSC_CFG_offADR24 11
+#define MSC_CFG_offINTLC 12
+#define MSC_CFG_offBASEV 13
+#define MSC_CFG_offNOD 16
+/* bit 13:31 reserved */
+
+#define MSC_CFG_mskEDM ( 0x1 << MSC_CFG_offEDM )
+#define MSC_CFG_mskLMDMA ( 0x1 << MSC_CFG_offLMDMA )
+#define MSC_CFG_mskPFM ( 0x1 << MSC_CFG_offPFM )
+#define MSC_CFG_mskHSMP ( 0x1 << MSC_CFG_offHSMP )
+#define MSC_CFG_mskTRACE ( 0x1 << MSC_CFG_offTRACE )
+#define MSC_CFG_mskDIV ( 0x1 << MSC_CFG_offDIV )
+#define MSC_CFG_mskMAC ( 0x1 << MSC_CFG_offMAC )
+#define MSC_CFG_mskAUDIO ( 0x3 << MSC_CFG_offAUDIO )
+#define MSC_CFG_mskL2C ( 0x1 << MSC_CFG_offL2C )
+#define MSC_CFG_mskRDREG ( 0x1 << MSC_CFG_offRDREG )
+#define MSC_CFG_mskADR24 ( 0x1 << MSC_CFG_offADR24 )
+#define MSC_CFG_mskINTLC ( 0x1 << MSC_CFG_offINTLC )
+#define MSC_CFG_mskBASEV ( 0x7 << MSC_CFG_offBASEV )
+#define MSC_CFG_mskNOD ( 0x1 << MSC_CFG_offNOD )
+
+/******************************************************************************
+ * cr5: CORE_CFG (Core Identification Register)
+ *****************************************************************************/
+#define CORE_ID_offCOREID 0
+/* bit 4:31 reserved */
+
+#define CORE_ID_mskCOREID ( 0xF << CORE_ID_offCOREID )
+
+/******************************************************************************
+ * cr6: FUCOP_EXIST (FPU and Coprocessor Existence Configuration Register)
+ *****************************************************************************/
+#define FUCOP_EXIST_offCP0EX 0
+#define FUCOP_EXIST_offCP1EX 1
+#define FUCOP_EXIST_offCP2EX 2
+#define FUCOP_EXIST_offCP3EX 3
+#define FUCOP_EXIST_offCP0ISFPU 31
+
+#define FUCOP_EXIST_mskCP0EX ( 0x1 << FUCOP_EXIST_offCP0EX )
+#define FUCOP_EXIST_mskCP1EX ( 0x1 << FUCOP_EXIST_offCP1EX )
+#define FUCOP_EXIST_mskCP2EX ( 0x1 << FUCOP_EXIST_offCP2EX )
+#define FUCOP_EXIST_mskCP3EX ( 0x1 << FUCOP_EXIST_offCP3EX )
+#define FUCOP_EXIST_mskCP0ISFPU ( 0x1 << FUCOP_EXIST_offCP0ISFPU )
+
+/******************************************************************************
+ * ir0: PSW (Processor Status Word Register)
+ * ir1: IPSW (Interruption PSW Register)
+ * ir2: P_IPSW (Previous IPSW Register)
+ *****************************************************************************/
+#define PSW_offGIE 0 /* Global Interrupt Enable */
+#define PSW_offINTL 1 /* Interruption Stack Level */
+#define PSW_offPOM 3 /* Processor Operation Mode, User/Superuser */
+#define PSW_offBE 5 /* Endianness for data memory access, 1:MSB, 0:LSB */
+#define PSW_offIT 6 /* Enable instruction address translation */
+#define PSW_offDT 7 /* Enable data address translation */
+#define PSW_offIME 8 /* Instruction Machine Error flag */
+#define PSW_offDME 9 /* Data Machine Error flag */
+#define PSW_offDEX 10 /* Debug Exception */
+#define PSW_offHSS 11 /* Hardware Single Stepping */
+#define PSW_offDRBE 12 /* Device Register Endian Mode */
+#define PSW_offAEN 13 /* Audio ISA special feature */
+#define PSW_offWBNA 14 /* Write Back Non-Allocate */
+#define PSW_offIFCON 15 /* IFC On */
+#define PSW_offCPL 16 /* Current Priority Level */
+/* bit 19:31 reserved */
+
+#define PSW_mskGIE ( 0x1 << PSW_offGIE )
+#define PSW_mskINTL ( 0x3 << PSW_offINTL )
+#define PSW_mskPOM ( 0x3 << PSW_offPOM )
+#define PSW_mskBE ( 0x1 << PSW_offBE )
+#define PSW_mskIT ( 0x1 << PSW_offIT )
+#define PSW_mskDT ( 0x1 << PSW_offDT )
+#define PSW_mskIME ( 0x1 << PSW_offIME )
+#define PSW_mskDME ( 0x1 << PSW_offDME )
+#define PSW_mskDEX ( 0x1 << PSW_offDEX )
+#define PSW_mskHSS ( 0x1 << PSW_offHSS )
+#define PSW_mskDRBE ( 0x1 << PSW_offDRBE )
+#define PSW_mskAEN ( 0x1 << PSW_offAEN )
+#define PSW_mskWBNA ( 0x1 << PSW_offWBNA )
+#define PSW_mskIFCON ( 0x1 << PSW_offIFCON )
+#define PSW_mskCPL ( 0x7 << PSW_offCPL )
+
+#define PSW_SYSTEM ( 1 << PSW_offPOM )
+#define PSW_INTL_1 ( 1 << PSW_offINTL )
+#define PSW_CPL_NO ( 0 << PSW_offCPL )
+#define PSW_CPL_ANY ( 7 << PSW_offCPL )
+
+#define PSW_clr (PSW_mskGIE|PSW_mskINTL|PSW_mskPOM|PSW_mskIT|PSW_mskDT|PSW_mskIME|PSW_mskWBNA)
+#ifdef __NDS32_EB__
+#ifdef CONFIG_WBNA
+#define PSW_init (PSW_mskWBNA|(1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT|PSW_mskBE)
+#else
+#define PSW_init ((1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT|PSW_mskBE)
+#endif
+#else
+#ifdef CONFIG_WBNA
+#define PSW_init (PSW_mskWBNA|(1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT)
+#else
+#define PSW_init ((1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT)
+#endif
+#endif
+/******************************************************************************
+ * ir3: IVB (Interruption Vector Base Register)
+ *****************************************************************************/
+/* bit 0:12 reserved */
+#define IVB_offNIVIC 1 /* Number of input for IVIC Controller */
+#define IVB_offIVIC_VER 11 /* IVIC Version */
+#define IVB_offEVIC 13 /* External Vector Interrupt Controller mode */
+#define IVB_offESZ 14 /* Size of each vector entry */
+#define IVB_offIVBASE 16 /* BasePA of interrupt vector table */
+
+#define IVB_mskNIVIC ( 0x7 << IVB_offNIVIC )
+#define IVB_mskIVIC_VER ( 0x3 << IVB_offIVIC_VER )
+#define IVB_mskEVIC ( 0x1 << IVB_offEVIC )
+#define IVB_mskESZ ( 0x3 << IVB_offESZ )
+#define IVB_mskIVBASE ( 0xFFFF << IVB_offIVBASE )
+
+#define IVB_valESZ4 0
+#define IVB_valESZ16 1
+#define IVB_valESZ64 2
+#define IVB_valESZ256 3
+/******************************************************************************
+ * ir4: EVA (Exception Virtual Address Register)
+ * ir5: P_EVA (Previous EVA Register)
+ *****************************************************************************/
+
+ /* This register contains the VA that causes the exception */
+
+/******************************************************************************
+ * ir6: ITYPE (Interruption Type Register)
+ * ir7: P_ITYPE (Previous ITYPE Register)
+ *****************************************************************************/
+#define ITYPE_offETYPE 0 /* Exception Type */
+#define ITYPE_offINST 4 /* Exception caused by insn fetch or data access */
+/* bit 5:15 reserved */
+#define ITYPE_offVECTOR 5 /* Vector */
+#define ITYPE_offSWID 16 /* SWID of debugging exception */
+/* bit 31:31 reserved */
+
+#define ITYPE_mskETYPE ( 0xF << ITYPE_offETYPE )
+#define ITYPE_mskINST ( 0x1 << ITYPE_offINST )
+#define ITYPE_mskVECTOR ( 0x7F << ITYPE_offVECTOR )
+#define ITYPE_mskSWID ( 0x7FFF << ITYPE_offSWID )
+
+/* Additional definitions for ITYPE register */
+#define ITYPE_offSTYPE 16 /* Arithmetic Sub Type */
+#define ITYPE_offCPID 20 /* Co-Processor ID which generate the exception */
+
+#define ITYPE_mskSTYPE ( 0xF << ITYPE_offSTYPE )
+#define ITYPE_mskCPID ( 0x3 << ITYPE_offCPID )
+
+#define NDS32_VECTOR_mskNONEXCEPTION 0x78
+#define NDS32_VECTOR_offEXCEPTION 8
+#define NDS32_VECTOR_offINTERRUPT 9
+
+/* Interrupt vector entry */
+#define ENTRY_RESET_NMI 0
+#define ENTRY_TLB_FILL 1
+#define ENTRY_PTE_NOT_PRESENT 2
+#define ENTRY_TLB_MISC 3
+#define ENTRY_TLB_VLPT_MISS 4
+#define ENTRY_MACHINE_ERROR 5
+#define ENTRY_DEBUG_RELATED 6
+#define ENTRY_GENERAL_EXCPETION 7
+#define ENTRY_SYSCALL 8
+
+/* PTE not present exception definition */
+#define ETYPE_NON_LEAF_PTE_NOT_PRESENT 0
+#define ETYPE_LEAF_PTE_NOT_PRESENT 1
+
+/* General exception ETYPE definition */
+#define ETYPE_ALIGNMENT_CHECK 0
+#define ETYPE_RESERVED_INSTRUCTION 1
+#define ETYPE_TRAP 2
+#define ETYPE_ARITHMETIC 3
+#define ETYPE_PRECISE_BUS_ERROR 4
+#define ETYPE_IMPRECISE_BUS_ERROR 5
+#define ETYPE_COPROCESSOR 6
+#define ETYPE_RESERVED_VALUE 7
+#define ETYPE_NONEXISTENT_MEM_ADDRESS 8
+#define ETYPE_MPZIU_CONTROL 9
+#define ETYPE_NEXT_PRECISE_STACK_OFL 10
+
+/* Kerenl reserves software ID */
+#define SWID_RAISE_INTERRUPT_LEVEL 0x1a /* SWID_RAISE_INTERRUPT_LEVEL is used to
+ * raise interrupt level for debug exception
+ */
+
+/******************************************************************************
+ * ir8: MERR (Machine Error Log Register)
+ *****************************************************************************/
+/* bit 0:30 reserved */
+#define MERR_offBUSERR 31 /* Bus error caused by a load insn */
+
+#define MERR_mskBUSERR ( 0x1 << MERR_offBUSERR )
+
+/******************************************************************************
+ * ir9: IPC (Interruption Program Counter Register)
+ * ir10: P_IPC (Previous IPC Register)
+ * ir11: OIPC (Overflow Interruption Program Counter Register)
+ *****************************************************************************/
+
+ /* This is the shadow stack register of the Program Counter */
+
+/******************************************************************************
+ * ir12: P_P0 (Previous P0 Register)
+ * ir13: P_P1 (Previous P1 Register)
+ *****************************************************************************/
+
+ /* These are shadow registers of $p0 and $p1 */
+
+/******************************************************************************
+ * ir14: INT_MASK (Interruption Masking Register)
+ *****************************************************************************/
+#define INT_MASK_offH0IM 0 /* Hardware Interrupt 0 Mask bit */
+#define INT_MASK_offH1IM 1 /* Hardware Interrupt 1 Mask bit */
+#define INT_MASK_offH2IM 2 /* Hardware Interrupt 2 Mask bit */
+#define INT_MASK_offH3IM 3 /* Hardware Interrupt 3 Mask bit */
+#define INT_MASK_offH4IM 4 /* Hardware Interrupt 4 Mask bit */
+#define INT_MASK_offH5IM 5 /* Hardware Interrupt 5 Mask bit */
+/* bit 6:15 reserved */
+#define INT_MASK_offSIM 16 /* Software Interrupt Mask bit */
+/* bit 17:29 reserved */
+#define INT_MASK_offIDIVZE 30 /* Enable detection for Divide-By-Zero */
+#define INT_MASK_offDSSIM 31 /* Default Single Stepping Interruption Mask */
+
+#define INT_MASK_mskH0IM ( 0x1 << INT_MASK_offH0IM )
+#define INT_MASK_mskH1IM ( 0x1 << INT_MASK_offH1IM )
+#define INT_MASK_mskH2IM ( 0x1 << INT_MASK_offH2IM )
+#define INT_MASK_mskH3IM ( 0x1 << INT_MASK_offH3IM )
+#define INT_MASK_mskH4IM ( 0x1 << INT_MASK_offH4IM )
+#define INT_MASK_mskH5IM ( 0x1 << INT_MASK_offH5IM )
+#define INT_MASK_mskSIM ( 0x1 << INT_MASK_offSIM )
+#define INT_MASK_mskIDIVZE ( 0x1 << INT_MASK_offIDIVZE )
+#define INT_MASK_mskDSSIM ( 0x1 << INT_MASK_offDSSIM )
+
+#define INT_MASK_INITAIAL_VAL 0x10003
+
+/******************************************************************************
+ * ir15: INT_PEND (Interrupt Pending Register)
+ *****************************************************************************/
+#define INT_PEND_offH0I 0 /* Hardware Interrupt 0 pending bit */
+#define INT_PEND_offH1I 1 /* Hardware Interrupt 1 pending bit */
+#define INT_PEND_offH2I 2 /* Hardware Interrupt 2 pending bit */
+#define INT_PEND_offH3I 3 /* Hardware Interrupt 3 pending bit */
+#define INT_PEND_offH4I 4 /* Hardware Interrupt 4 pending bit */
+#define INT_PEND_offH5I 5 /* Hardware Interrupt 5 pending bit */
+
+#define INT_PEND_offCIPL 0 /* Current Interrupt Priority Level */
+
+/* bit 6:15 reserved */
+#define INT_PEND_offSWI 16 /* Software Interrupt pending bit */
+/* bit 17:31 reserved */
+
+#define INT_PEND_mskH0I ( 0x1 << INT_PEND_offH0I )
+#define INT_PEND_mskH1I ( 0x1 << INT_PEND_offH1I )
+#define INT_PEND_mskH2I ( 0x1 << INT_PEND_offH2I )
+#define INT_PEND_mskH3I ( 0x1 << INT_PEND_offH3I )
+#define INT_PEND_mskH4I ( 0x1 << INT_PEND_offH4I )
+#define INT_PEND_mskH5I ( 0x1 << INT_PEND_offH5I )
+#define INT_PEND_mskCIPL ( 0x1 << INT_PEND_offCIPL )
+#define INT_PEND_mskSWI ( 0x1 << INT_PEND_offSWI )
+
+/******************************************************************************
+ * mr0: MMU_CTL (MMU Control Register)
+ *****************************************************************************/
+#define MMU_CTL_offD 0 /* Default minimum page size */
+#define MMU_CTL_offNTC0 1 /* Non-Translated Cachebility of partition 0 */
+#define MMU_CTL_offNTC1 3 /* Non-Translated Cachebility of partition 1 */
+#define MMU_CTL_offNTC2 5 /* Non-Translated Cachebility of partition 2 */
+#define MMU_CTL_offNTC3 7 /* Non-Translated Cachebility of partition 3 */
+#define MMU_CTL_offTBALCK 9 /* TLB all-lock resolution scheme */
+#define MMU_CTL_offMPZIU 10 /* Multiple Page Size In Use bit */
+#define MMU_CTL_offNTM0 11 /* Non-Translated VA to PA of partition 0 */
+#define MMU_CTL_offNTM1 13 /* Non-Translated VA to PA of partition 1 */
+#define MMU_CTL_offNTM2 15 /* Non-Translated VA to PA of partition 2 */
+#define MMU_CTL_offNTM3 17 /* Non-Translated VA to PA of partition 3 */
+#define MMU_CTL_offUNA 23 /* Unaligned access */
+/* bit 24:31 reserved */
+
+#define MMU_CTL_mskD ( 0x1 << MMU_CTL_offD )
+#define MMU_CTL_mskNTC0 ( 0x3 << MMU_CTL_offNTC0 )
+#define MMU_CTL_mskNTC1 ( 0x3 << MMU_CTL_offNTC1 )
+#define MMU_CTL_mskNTC2 ( 0x3 << MMU_CTL_offNTC2 )
+#define MMU_CTL_mskNTC3 ( 0x3 << MMU_CTL_offNTC3 )
+#define MMU_CTL_mskTBALCK ( 0x1 << MMU_CTL_offTBALCK )
+#define MMU_CTL_mskMPZIU ( 0x1 << MMU_CTL_offMPZIU )
+#define MMU_CTL_mskNTM0 ( 0x3 << MMU_CTL_offNTM0 )
+#define MMU_CTL_mskNTM1 ( 0x3 << MMU_CTL_offNTM1 )
+#define MMU_CTL_mskNTM2 ( 0x3 << MMU_CTL_offNTM2 )
+#define MMU_CTL_mskNTM3 ( 0x3 << MMU_CTL_offNTM3 )
+
+#define MMU_CTL_D4KB 0
+#define MMU_CTL_D8KB 1
+#define MMU_CTL_UNA ( 0x1 << MMU_CTL_offUNA )
+
+#define MMU_CTL_CACHEABLE_WB 2
+#define MMU_CTL_CACHEABLE_WT 3
+
+/******************************************************************************
+ * mr1: L1_PPTB (L1 Physical Page Table Base Register)
+ *****************************************************************************/
+#define L1_PPTB_offNV 0 /* Enable Hardware Page Table Walker (HPTWK) */
+/* bit 1:11 reserved */
+#define L1_PPTB_offBASE 12 /* First level physical page table base address */
+
+#define L1_PPTB_mskNV ( 0x1 << L1_PPTB_offNV )
+#define L1_PPTB_mskBASE ( 0xFFFFF << L1_PPTB_offBASE )
+
+/******************************************************************************
+ * mr2: TLB_VPN (TLB Access VPN Register)
+ *****************************************************************************/
+/* bit 0:11 reserved */
+#define TLB_VPN_offVPN 12 /* Virtual Page Number */
+
+#define TLB_VPN_mskVPN ( 0xFFFFF << TLB_VPN_offVPN )
+
+/******************************************************************************
+ * mr3: TLB_DATA (TLB Access Data Register)
+ *****************************************************************************/
+#define TLB_DATA_offV 0 /* PTE is valid and present */
+#define TLB_DATA_offM 1 /* Page read/write access privilege */
+#define TLB_DATA_offD 4 /* Dirty bit */
+#define TLB_DATA_offX 5 /* Executable bit */
+#define TLB_DATA_offA 6 /* Access bit */
+#define TLB_DATA_offG 7 /* Global page (shared across contexts) */
+#define TLB_DATA_offC 8 /* Cacheability atribute */
+/* bit 11:11 reserved */
+#define TLB_DATA_offPPN 12 /* Phisical Page Number */
+
+#define TLB_DATA_mskV ( 0x1 << TLB_DATA_offV )
+#define TLB_DATA_mskM ( 0x7 << TLB_DATA_offM )
+#define TLB_DATA_mskD ( 0x1 << TLB_DATA_offD )
+#define TLB_DATA_mskX ( 0x1 << TLB_DATA_offX )
+#define TLB_DATA_mskA ( 0x1 << TLB_DATA_offA )
+#define TLB_DATA_mskG ( 0x1 << TLB_DATA_offG )
+#define TLB_DATA_mskC ( 0x7 << TLB_DATA_offC )
+#define TLB_DATA_mskPPN ( 0xFFFFF << TLB_DATA_offPPN )
+
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+#define TLB_DATA_kernel_text_attr (TLB_DATA_mskV|TLB_DATA_mskM|TLB_DATA_mskD|TLB_DATA_mskX|TLB_DATA_mskG|TLB_DATA_mskC)
+#else
+#define TLB_DATA_kernel_text_attr (TLB_DATA_mskV|TLB_DATA_mskM|TLB_DATA_mskD|TLB_DATA_mskX|TLB_DATA_mskG|(0x6 << TLB_DATA_offC))
+#endif
+
+/******************************************************************************
+ * mr4: TLB_MISC (TLB Access Misc Register)
+ *****************************************************************************/
+#define TLB_MISC_offACC_PSZ 0 /* Page size of a PTE entry */
+#define TLB_MISC_offCID 4 /* Context id */
+/* bit 13:31 reserved */
+
+#define TLB_MISC_mskACC_PSZ ( 0xF << TLB_MISC_offACC_PSZ )
+#define TLB_MISC_mskCID ( 0x1FF << TLB_MISC_offCID )
+
+/******************************************************************************
+ * mr5: VLPT_IDX (Virtual Linear Page Table Index Register)
+ *****************************************************************************/
+#define VLPT_IDX_offZERO 0 /* Always 0 */
+#define VLPT_IDX_offEVPN 2 /* Exception Virtual Page Number */
+#define VLPT_IDX_offVLPTB 22 /* Base VA of VLPT */
+
+#define VLPT_IDX_mskZERO ( 0x3 << VLPT_IDX_offZERO )
+#define VLPT_IDX_mskEVPN ( 0xFFFFF << VLPT_IDX_offEVPN )
+#define VLPT_IDX_mskVLPTB ( 0x3FF << VLPT_IDX_offVLPTB )
+
+/******************************************************************************
+ * mr6: ILMB (Instruction Local Memory Base Register)
+ *****************************************************************************/
+#define ILMB_offIEN 0 /* Enable ILM */
+#define ILMB_offILMSZ 1 /* Size of ILM */
+/* bit 5:19 reserved */
+#define ILMB_offIBPA 20 /* Base PA of ILM */
+
+#define ILMB_mskIEN ( 0x1 << ILMB_offIEN )
+#define ILMB_mskILMSZ ( 0xF << ILMB_offILMSZ )
+#define ILMB_mskIBPA ( 0xFFF << ILMB_offIBPA )
+
+/******************************************************************************
+ * mr7: DLMB (Data Local Memory Base Register)
+ *****************************************************************************/
+#define DLMB_offDEN 0 /* Enable DLM */
+#define DLMB_offDLMSZ 1 /* Size of DLM */
+#define DLMB_offDBM 5 /* Enable Double-Buffer Mode for DLM */
+#define DLMB_offDBB 6 /* Double-buffer bank which can be accessed by the processor */
+/* bit 7:19 reserved */
+#define DLMB_offDBPA 20 /* Base PA of DLM */
+
+#define DLMB_mskDEN ( 0x1 << DLMB_offDEN )
+#define DLMB_mskDLMSZ ( 0xF << DLMB_offDLMSZ )
+#define DLMB_mskDBM ( 0x1 << DLMB_offDBM )
+#define DLMB_mskDBB ( 0x1 << DLMB_offDBB )
+#define DLMB_mskDBPA ( 0xFFF << DLMB_offDBPA )
+
+/******************************************************************************
+ * mr8: CACHE_CTL (Cache Control Register)
+ *****************************************************************************/
+#define CACHE_CTL_offIC_EN 0 /* Enable I-cache */
+#define CACHE_CTL_offDC_EN 1 /* Enable D-cache */
+#define CACHE_CTL_offICALCK 2 /* I-cache all-lock resolution scheme */
+#define CACHE_CTL_offDCALCK 3 /* D-cache all-lock resolution scheme */
+#define CACHE_CTL_offDCCWF 4 /* Enable D-cache Critical Word Forwarding */
+#define CACHE_CTL_offDCPMW 5 /* Enable D-cache concurrent miss and write-back processing */
+/* bit 6:31 reserved */
+
+#define CACHE_CTL_mskIC_EN ( 0x1 << CACHE_CTL_offIC_EN )
+#define CACHE_CTL_mskDC_EN ( 0x1 << CACHE_CTL_offDC_EN )
+#define CACHE_CTL_mskICALCK ( 0x1 << CACHE_CTL_offICALCK )
+#define CACHE_CTL_mskDCALCK ( 0x1 << CACHE_CTL_offDCALCK )
+#define CACHE_CTL_mskDCCWF ( 0x1 << CACHE_CTL_offDCCWF )
+#define CACHE_CTL_mskDCPMW ( 0x1 << CACHE_CTL_offDCPMW )
+
+/******************************************************************************
+ * mr9: HSMP_SADDR (High Speed Memory Port Starting Address)
+ *****************************************************************************/
+#define HSMP_SADDR_offEN 0 /* Enable control bit for the High Speed Memory port */
+/* bit 1:19 reserved */
+
+#define HSMP_SADDR_offRANGE 1 /* Denote the address range (only defined in HSMP v2 ) */
+#define HSMP_SADDR_offSADDR 20 /* Starting base PA of the High Speed Memory Port region */
+
+#define HSMP_SADDR_mskEN ( 0x1 << HSMP_SADDR_offEN )
+#define HSMP_SADDR_mskRANGE ( 0xFFF << HSMP_SADDR_offRANGE )
+#define HSMP_SADDR_mskSADDR ( 0xFFF << HSMP_SADDR_offSADDR )
+
+/******************************************************************************
+ * mr10: HSMP_EADDR (High Speed Memory Port Ending Address)
+ *****************************************************************************/
+/* bit 0:19 reserved */
+#define HSMP_EADDR_offEADDR 20
+
+#define HSMP_EADDR_mskEADDR ( 0xFFF << HSMP_EADDR_offEADDR )
+
+/******************************************************************************
+ * dr0+(n*5): BPCn (n=0-7) (Breakpoint Control Register)
+ *****************************************************************************/
+#define BPC_offWP 0 /* Configuration of BPAn */
+#define BPC_offEL 1 /* Enable BPAn */
+#define BPC_offS 2 /* Data address comparison for a store instruction */
+#define BPC_offP 3 /* Compared data address is PA */
+#define BPC_offC 4 /* CID value is compared with the BPCIDn register */
+#define BPC_offBE0 5 /* Enable byte mask for the comparison with register */
+#define BPC_offBE1 6 /* Enable byte mask for the comparison with register */
+#define BPC_offBE2 7 /* Enable byte mask for the comparison with register */
+#define BPC_offBE3 8 /* Enable byte mask for the comparison with register */
+#define BPC_offT 9 /* Enable breakpoint Embedded Tracer triggering operation */
+
+#define BPC_mskWP ( 0x1 << BPC_offWP )
+#define BPC_mskEL ( 0x1 << BPC_offEL )
+#define BPC_mskS ( 0x1 << BPC_offS )
+#define BPC_mskP ( 0x1 << BPC_offP )
+#define BPC_mskC ( 0x1 << BPC_offC )
+#define BPC_mskBE0 ( 0x1 << BPC_offBE0 )
+#define BPC_mskBE1 ( 0x1 << BPC_offBE1 )
+#define BPC_mskBE2 ( 0x1 << BPC_offBE2 )
+#define BPC_mskBE3 ( 0x1 << BPC_offBE3 )
+#define BPC_mskT ( 0x1 << BPC_offT )
+
+/******************************************************************************
+ * dr1+(n*5): BPAn (n=0-7) (Breakpoint Address Register)
+ *****************************************************************************/
+
+ /* These registers contain break point address */
+
+/******************************************************************************
+ * dr2+(n*5): BPAMn (n=0-7) (Breakpoint Address Mask Register)
+ *****************************************************************************/
+
+ /* These registerd contain the address comparison mask for the BPAn register */
+
+/******************************************************************************
+ * dr3+(n*5): BPVn (n=0-7) Breakpoint Data Value Register
+ *****************************************************************************/
+
+ /* The BPVn register contains the data value that will be compared with the
+ * incoming load/store data value */
+
+/******************************************************************************
+ * dr4+(n*5): BPCIDn (n=0-7) (Breakpoint Context ID Register)
+ *****************************************************************************/
+#define BPCID_offCID 0 /* CID that will be compared with a process's CID */
+/* bit 9:31 reserved */
+
+#define BPCID_mskCID ( 0x1FF << BPCID_offCID )
+
+/******************************************************************************
+ * dr40: EDM_CFG (EDM Configuration Register)
+ *****************************************************************************/
+#define EDM_CFG_offBC 0 /* Number of hardware breakpoint sets implemented */
+#define EDM_CFG_offDIMU 3 /* Debug Instruction Memory Unit exists */
+/* bit 4:15 reserved */
+#define EDM_CFG_offVER 16 /* EDM version */
+
+#define EDM_CFG_mskBC ( 0x7 << EDM_CFG_offBC )
+#define EDM_CFG_mskDIMU ( 0x1 << EDM_CFG_offDIMU )
+#define EDM_CFG_mskVER ( 0xFFFF << EDM_CFG_offVER )
+
+/******************************************************************************
+ * dr41: EDMSW (EDM Status Word)
+ *****************************************************************************/
+#define EDMSW_offWV 0 /* Write Valid */
+#define EDMSW_offRV 1 /* Read Valid */
+#define EDMSW_offDE 2 /* Debug exception has occurred for this core */
+/* bit 3:31 reserved */
+
+#define EDMSW_mskWV ( 0x1 << EDMSW_offWV )
+#define EDMSW_mskRV ( 0x1 << EDMSW_offRV )
+#define EDMSW_mskDE ( 0x1 << EDMSW_offDE )
+
+/******************************************************************************
+ * dr42: EDM_CTL (EDM Control Register)
+ *****************************************************************************/
+/* bit 0:30 reserved */
+#define EDM_CTL_offV3_EDM_MODE 6 /* EDM compatibility control bit */
+#define EDM_CTL_offDEH_SEL 31 /* Controls where debug exception is directed to */
+
+#define EDM_CTL_mskV3_EDM_MODE ( 0x1 << EDM_CTL_offV3_EDM_MODE )
+#define EDM_CTL_mskDEH_SEL ( 0x1 << EDM_CTL_offDEH_SEL )
+
+/******************************************************************************
+ * dr43: EDM_DTR (EDM Data Transfer Register)
+ *****************************************************************************/
+
+ /* This is used to exchange data between the embedded EDM logic
+ * and the processor core */
+
+/******************************************************************************
+ * dr44: BPMTC (Breakpoint Match Trigger Counter Register)
+ *****************************************************************************/
+#define BPMTC_offBPMTC 0 /* Breakpoint match trigger counter value */
+/* bit 16:31 reserved */
+
+#define BPMTC_mskBPMTC ( 0xFFFF << BPMTC_offBPMTC )
+
+/******************************************************************************
+ * dr45: DIMBR (Debug Instruction Memory Base Register)
+ *****************************************************************************/
+/* bit 0:11 reserved */
+#define DIMBR_offDIMB 12 /* Base address of the Debug Instruction Memory (DIM) */
+#define DIMBR_mskDIMB ( 0xFFFFF << DIMBR_offDIMB )
+
+/******************************************************************************
+ * dr46: TECR0(Trigger Event Control register 0)
+ * dr47: TECR1 (Trigger Event Control register 1)
+ *****************************************************************************/
+#define TECR_offBP 0 /* Controld which BP is used as a trigger source */
+#define TECR_offNMI 8 /* Use NMI as a trigger source */
+#define TECR_offHWINT 9 /* Corresponding interrupt is used as a trigger source */
+#define TECR_offEVIC 15 /* Enable HWINT as a trigger source in EVIC mode */
+#define TECR_offSYS 16 /* Enable SYSCALL instruction as a trigger source */
+#define TECR_offDBG 17 /* Enable debug exception as a trigger source */
+#define TECR_offMRE 18 /* Enable MMU related exception as a trigger source */
+#define TECR_offE 19 /* An exception is used as a trigger source */
+/* bit 20:30 reserved */
+#define TECR_offL 31 /* Link/Cascade TECR0 trigger event to TECR1 trigger event */
+
+#define TECR_mskBP ( 0xFF << TECR_offBP )
+#define TECR_mskNMI ( 0x1 << TECR_offBNMI )
+#define TECR_mskHWINT ( 0x3F << TECR_offBHWINT )
+#define TECR_mskEVIC ( 0x1 << TECR_offBEVIC )
+#define TECR_mskSYS ( 0x1 << TECR_offBSYS )
+#define TECR_mskDBG ( 0x1 << TECR_offBDBG )
+#define TECR_mskMRE ( 0x1 << TECR_offBMRE )
+#define TECR_mskE ( 0x1 << TECR_offE )
+#define TECR_mskL ( 0x1 << TECR_offL )
+
+/******************************************************************************
+ * pfr0-2: PFMC0-2 (Performance Counter Register 0-2)
+ *****************************************************************************/
+
+ /* These registers contains performance event count */
+
+/******************************************************************************
+ * pfr3: PFM_CTL (Performance Counter Control Register)
+ *****************************************************************************/
+#define PFM_CTL_offEN0 0 /* Enable PFMC0 */
+#define PFM_CTL_offEN1 1 /* Enable PFMC1 */
+#define PFM_CTL_offEN2 2 /* Enable PFMC2 */
+#define PFM_CTL_offIE0 3 /* Enable interrupt for PFMC0 */
+#define PFM_CTL_offIE1 4 /* Enable interrupt for PFMC1 */
+#define PFM_CTL_offIE2 5 /* Enable interrupt for PFMC2 */
+#define PFM_CTL_offOVF0 6 /* Overflow bit of PFMC0 */
+#define PFM_CTL_offOVF1 7 /* Overflow bit of PFMC1 */
+#define PFM_CTL_offOVF2 8 /* Overflow bit of PFMC2 */
+#define PFM_CTL_offKS0 9 /* Enable superuser mode event counting for PFMC0 */
+#define PFM_CTL_offKS1 10 /* Enable superuser mode event counting for PFMC1 */
+#define PFM_CTL_offKS2 11 /* Enable superuser mode event counting for PFMC2 */
+#define PFM_CTL_offKU0 12 /* Enable user mode event counting for PFMC0 */
+#define PFM_CTL_offKU1 13 /* Enable user mode event counting for PFMC1 */
+#define PFM_CTL_offKU2 14 /* Enable user mode event counting for PFMC2 */
+#define PFM_CTL_offSEL0 15 /* The event selection for PFMC0 */
+#define PFM_CTL_offSEL1 21 /* The event selection for PFMC1 */
+#define PFM_CTL_offSEL2 27 /* The event selection for PFMC2 */
+/* bit 28:31 reserved */
+
+#define PFM_CTL_mskEN0 ( 0x01 << PFM_CTL_offEN0 )
+#define PFM_CTL_mskEN1 ( 0x01 << PFM_CTL_offEN1 )
+#define PFM_CTL_mskEN2 ( 0x01 << PFM_CTL_offEN2 )
+#define PFM_CTL_mskIE0 ( 0x01 << PFM_CTL_offIE0 )
+#define PFM_CTL_mskIE1 ( 0x01 << PFM_CTL_offIE1 )
+#define PFM_CTL_mskIE2 ( 0x01 << PFM_CTL_offIE2 )
+#define PFM_CTL_mskOVF0 ( 0x01 << PFM_CTL_offOVF0 )
+#define PFM_CTL_mskOVF1 ( 0x01 << PFM_CTL_offOVF1 )
+#define PFM_CTL_mskOVF2 ( 0x01 << PFM_CTL_offOVF2 )
+#define PFM_CTL_mskKS0 ( 0x01 << PFM_CTL_offKS0 )
+#define PFM_CTL_mskKS1 ( 0x01 << PFM_CTL_offKS1 )
+#define PFM_CTL_mskKS2 ( 0x01 << PFM_CTL_offKS2 )
+#define PFM_CTL_mskKU0 ( 0x01 << PFM_CTL_offKU0 )
+#define PFM_CTL_mskKU1 ( 0x01 << PFM_CTL_offKU1 )
+#define PFM_CTL_mskKU2 ( 0x01 << PFM_CTL_offKU2 )
+#define PFM_CTL_mskSEL0 ( 0x01 << PFM_CTL_offSEL0 )
+#define PFM_CTL_mskSEL1 ( 0x3F << PFM_CTL_offSEL1 )
+#define PFM_CTL_mskSEL2 ( 0x3F << PFM_CTL_offSEL2 )
+
+/******************************************************************************
+ * SDZ_CTL (Structure Downsizing Control Register)
+ *****************************************************************************/
+#define SDZ_CTL_offICDZ 0 /* I-cache downsizing control */
+#define SDZ_CTL_offDCDZ 3 /* D-cache downsizing control */
+#define SDZ_CTL_offMTBDZ 6 /* MTLB downsizing control */
+#define SDZ_CTL_offBTBDZ 9 /* Branch Target Table downsizing control */
+/* bit 12:31 reserved */
+#define SDZ_CTL_mskICDZ ( 0x07 << SDZ_CTL_offICDZ )
+#define SDZ_CTL_mskDCDZ ( 0x07 << SDZ_CTL_offDCDZ )
+#define SDZ_CTL_mskMTBDZ ( 0x07 << SDZ_CTL_offMTBDZ )
+#define SDZ_CTL_mskBTBDZ ( 0x07 << SDZ_CTL_offBTBDZ )
+
+/******************************************************************************
+ * N13MISC_CTL (N13 Miscellaneous Control Register)
+ *****************************************************************************/
+#define N13MISC_CTL_offBTB 0 /* Disable Branch Target Buffer */
+#define N13MISC_CTL_offRTP 1 /* Disable Return Target Predictor */
+#define N13MISC_CTL_offPTEPF 2 /* Disable HPTWK L2 PTE pefetch */
+#define N13MISC_CTL_offSP_SHADOW_EN 4 /* Enable shadow stack pointers */
+/* bit 6, 9:31 reserved */
+
+#define N13MISC_CTL_makBTB ( 0x1 << N13MISC_CTL_offBTB )
+#define N13MISC_CTL_makRTP ( 0x1 << N13MISC_CTL_offRTP )
+#define N13MISC_CTL_makPTEPF ( 0x1 << N13MISC_CTL_offPTEPF )
+#define N13MISC_CTL_makSP_SHADOW_EN ( 0x1 << N13MISC_CTL_offSP_SHADOW_EN )
+
+#define MISC_init (N13MISC_CTL_makBTB|N13MISC_CTL_makRTP|N13MISC_CTL_makSP_SHADOW_EN)
+
+/******************************************************************************
+ * PRUSR_ACC_CTL (Privileged Resource User Access Control Registers)
+ *****************************************************************************/
+#define PRUSR_ACC_CTL_offDMA_EN 0 /* Allow user mode access of DMA registers */
+#define PRUSR_ACC_CTL_offPFM_EN 1 /* Allow user mode access of PFM registers */
+
+#define PRUSR_ACC_CTL_mskDMA_EN ( 0x1 << PRUSR_ACC_CTL_offDMA_EN )
+#define PRUSR_ACC_CTL_mskPFM_EN ( 0x1 << PRUSR_ACC_CTL_offPFM_EN )
+
+/******************************************************************************
+ * dmar0: DMA_CFG (DMA Configuration Register)
+ *****************************************************************************/
+#define DMA_CFG_offNCHN 0 /* The number of DMA channels implemented */
+#define DMA_CFG_offUNEA 2 /* Un-aligned External Address transfer feature */
+#define DMA_CFG_off2DET 3 /* 2-D Element Transfer feature */
+/* bit 4:15 reserved */
+#define DMA_CFG_offVER 16 /* DMA architecture and implementation version */
+
+#define DMA_CFG_mskNCHN ( 0x3 << DMA_CFG_offNCHN )
+#define DMA_CFG_mskUNEA ( 0x1 << DMA_CFG_offUNEA )
+#define DMA_CFG_msk2DET ( 0x1 << DMA_CFG_off2DET )
+#define DMA_CFG_mskVER ( 0xFFFF << DMA_CFG_offVER )
+
+/******************************************************************************
+ * dmar1: DMA_GCSW (DMA Global Control and Status Word Register)
+ *****************************************************************************/
+#define DMA_GCSW_offC0STAT 0 /* DMA channel 0 state */
+#define DMA_GCSW_offC1STAT 3 /* DMA channel 1 state */
+/* bit 6:11 reserved */
+#define DMA_GCSW_offC0INT 12 /* DMA channel 0 generate interrupt */
+#define DMA_GCSW_offC1INT 13 /* DMA channel 1 generate interrupt */
+/* bit 14:30 reserved */
+#define DMA_GCSW_offEN 31 /* Enable DMA engine */
+
+#define DMA_GCSW_mskC0STAT ( 0x7 << DMA_GCSW_offC0STAT )
+#define DMA_GCSW_mskC1STAT ( 0x7 << DMA_GCSW_offC1STAT )
+#define DMA_GCSW_mskC0INT ( 0x1 << DMA_GCSW_offC0INT )
+#define DMA_GCSW_mskC1INT ( 0x1 << DMA_GCSW_offC1INT )
+#define DMA_GCSW_mskEN ( 0x1 << DMA_GCSW_offEN )
+
+/******************************************************************************
+ * dmar2: DMA_CHNSEL (DMA Channel Selection Register)
+ *****************************************************************************/
+#define DMA_CHNSEL_offCHAN 0 /* Selected channel number */
+/* bit 2:31 reserved */
+
+#define DMA_CHNSEL_mskCHAN ( 0x3 << DMA_CHNSEL_offCHAN )
+
+/******************************************************************************
+ * dmar3: DMA_ACT (DMA Action Register)
+ *****************************************************************************/
+#define DMA_ACT_offACMD 0 /* DMA Action Command */
+/* bit 2:31 reserved */
+#define DMA_ACT_mskACMD ( 0x3 << DMA_ACT_offACMD )
+
+/******************************************************************************
+ * dmar4: DMA_SETUP (DMA Setup Register)
+ *****************************************************************************/
+#define DMA_SETUP_offLM 0 /* Local Memory Selection */
+#define DMA_SETUP_offTDIR 1 /* Transfer Direction */
+#define DMA_SETUP_offTES 2 /* Transfer Element Size */
+#define DMA_SETUP_offESTR 4 /* External memory transfer Stride */
+#define DMA_SETUP_offCIE 16 /* Interrupt Enable on Completion */
+#define DMA_SETUP_offSIE 17 /* Interrupt Enable on explicit Stop */
+#define DMA_SETUP_offEIE 18 /* Interrupt Enable on Error */
+#define DMA_SETUP_offUE 19 /* Enable the Un-aligned External Address */
+#define DMA_SETUP_off2DE 20 /* Enable the 2-D External Transfer */
+#define DMA_SETUP_offCOA 21 /* Transfer Coalescable */
+/* bit 22:31 reserved */
+
+#define DMA_SETUP_mskLM ( 0x1 << DMA_SETUP_offLM )
+#define DMA_SETUP_mskTDIR ( 0x1 << DMA_SETUP_offTDIR )
+#define DMA_SETUP_mskTES ( 0x3 << DMA_SETUP_offTES )
+#define DMA_SETUP_mskESTR ( 0xFFF << DMA_SETUP_offESTR )
+#define DMA_SETUP_mskCIE ( 0x1 << DMA_SETUP_offCIE )
+#define DMA_SETUP_mskSIE ( 0x1 << DMA_SETUP_offSIE )
+#define DMA_SETUP_mskEIE ( 0x1 << DMA_SETUP_offEIE )
+#define DMA_SETUP_mskUE ( 0x1 << DMA_SETUP_offUE )
+#define DMA_SETUP_msk2DE ( 0x1 << DMA_SETUP_off2DE )
+#define DMA_SETUP_mskCOA ( 0x1 << DMA_SETUP_offCOA )
+
+/******************************************************************************
+ * dmar5: DMA_ISADDR (DMA Internal Start Address Register)
+ *****************************************************************************/
+#define DMA_ISADDR_offISADDR 0 /* Internal Start Address */
+/* bit 20:31 reserved */
+#define DMA_ISADDR_mskISADDR ( 0xFFFFF << DMA_ISADDR_offISADDR )
+
+/******************************************************************************
+ * dmar6: DMA_ESADDR (DMA External Start Address Register)
+ *****************************************************************************/
+/* This register holds External Start Address */
+
+/******************************************************************************
+ * dmar7: DMA_TCNT (DMA Transfer Element Count Register)
+ *****************************************************************************/
+#define DMA_TCNT_offTCNT 0 /* DMA transfer element count */
+/* bit 18:31 reserved */
+#define DMA_TCNT_mskTCNT ( 0x3FFFF << DMA_TCNT_offTCNT )
+
+/******************************************************************************
+ * dmar8: DMA_STATUS (DMA Status Register)
+ *****************************************************************************/
+#define DMA_STATUS_offSTAT 0 /* DMA channel state */
+#define DMA_STATUS_offSTUNA 3 /* Un-aligned error on External Stride value */
+#define DMA_STATUS_offDERR 4 /* DMA Transfer Disruption Error */
+#define DMA_STATUS_offEUNA 5 /* Un-aligned error on the External address */
+#define DMA_STATUS_offIUNA 6 /* Un-aligned error on the Internal address */
+#define DMA_STATUS_offIOOR 7 /* Out-Of-Range error on the Internal address */
+#define DMA_STATUS_offEBUS 8 /* Bus Error on an External DMA transfer */
+#define DMA_STATUS_offESUP 9 /* DMA setup error */
+/* bit 10:31 reserved */
+
+#define DMA_STATUS_mskSTAT ( 0x7 << DMA_STATUS_offSTAT )
+#define DMA_STATUS_mskSTUNA ( 0x1 << DMDMA_STATUS_offSTUNA )
+#define DMA_STATUS_mskDERR ( 0x1 << DMDMA_STATUS_offDERR )
+#define DMA_STATUS_mskEUNA ( 0x1 << DMDMA_STATUS_offEUNA )
+#define DMA_STATUS_mskIUNA ( 0x1 << DMDMA_STATUS_offIUNA )
+#define DMA_STATUS_mskIOOR ( 0x1 << DMDMA_STATUS_offIOOR )
+#define DMA_STATUS_mskEBUS ( 0x1 << DMDMA_STATUS_offEBUS )
+#define DMA_STATUS_mskESUP ( 0x1 << DMDMA_STATUS_offESUP )
+
+/******************************************************************************
+ * dmar9: DMA_2DSET (DMA 2D Setup Register)
+ *****************************************************************************/
+#define DMA_2DSET_offWECNT 0 /* The Width Element Count for a 2-D region */
+#define DMA_2DSET_offHTSTR 16 /* The Height Stride for a 2-D region */
+
+#define DMA_2DSET_mskHTSTR ( 0xFFFF << DMA_2DSET_offHTSTR )
+#define DMA_2DSET_mskWECNT ( 0xFFFF << DMA_2DSET_offWECNT )
+
+/******************************************************************************
+ * dmar10: DMA_2DSCTL (DMA 2D Startup Control Register)
+ *****************************************************************************/
+#define DMA_2DSCTL_offSTWECNT 0 /* Startup Width Element Count for a 2-D region */
+/* bit 16:31 reserved */
+
+#define DMA_2DSCTL_mskSTWECNT ( 0xFFFF << DMA_2DSCTL_offSTWECNT )
+
+/******************************************************************************
+ * fpcsr: FPCSR (Floating-Point Control Status Register)
+ *****************************************************************************/
+#define FPCSR_offRM 0
+#define FPCSR_offIVO 2
+#define FPCSR_offDBZ 3
+#define FPCSR_offOVF 4
+#define FPCSR_offUDF 5
+#define FPCSR_offIEX 6
+#define FPCSR_offIVOE 7
+#define FPCSR_offDBZE 8
+#define FPCSR_offOVFE 9
+#define FPCSR_offUDFE 10
+#define FPCSR_offIEXE 11
+#define FPCSR_offDNZ 12
+#define FPCSR_offIVOT 13
+#define FPCSR_offDBZT 14
+#define FPCSR_offOVFT 15
+#define FPCSR_offUDFT 16
+#define FPCSR_offIEXT 17
+#define FPCSR_offDNIT 18
+#define FPCSR_offRIT 19
+
+#define FPCSR_mskRM ( 0x3 << FPCSR_offRM )
+#define FPCSR_mskIVO ( 0x1 << FPCSR_offIVO )
+#define FPCSR_mskDBZ ( 0x1 << FPCSR_offDBZ )
+#define FPCSR_mskOVF ( 0x1 << FPCSR_offOVF )
+#define FPCSR_mskUDF ( 0x1 << FPCSR_offUDF )
+#define FPCSR_mskIEX ( 0x1 << FPCSR_offIEX )
+#define FPCSR_mskIVOE ( 0x1 << FPCSR_offIVOE )
+#define FPCSR_mskDBZE ( 0x1 << FPCSR_offDBZE )
+#define FPCSR_mskOVFE ( 0x1 << FPCSR_offOVFE )
+#define FPCSR_mskUDFE ( 0x1 << FPCSR_offUDFE )
+#define FPCSR_mskIEXE ( 0x1 << FPCSR_offIEXE )
+#define FPCSR_mskDNZ ( 0x1 << FPCSR_offDNZ )
+#define FPCSR_mskIVOT ( 0x1 << FPCSR_offIVOT )
+#define FPCSR_mskDBZT ( 0x1 << FPCSR_offDBZT )
+#define FPCSR_mskOVFT ( 0x1 << FPCSR_offOVFT )
+#define FPCSR_mskUDFT ( 0x1 << FPCSR_offUDFT )
+#define FPCSR_mskIEXT ( 0x1 << FPCSR_offIEXT )
+#define FPCSR_mskDNIT ( 0x1 << FPCSR_offDNIT )
+#define FPCSR_mskRIT ( 0x1 << FPCSR_offRIT )
+#define FPCSR_mskALL (FPCSR_mskIVO | FPCSR_mskDBZ | FPCSR_mskOVF | FPCSR_mskUDF | FPCSR_mskIEX)
+#define FPCSR_mskALLE (FPCSR_mskIVOE | FPCSR_mskDBZE | FPCSR_mskOVFE | FPCSR_mskUDFE | FPCSR_mskIEXE)
+#define FPCSR_mskALLT (FPCSR_mskIVOT | FPCSR_mskDBZT | FPCSR_mskOVFT | FPCSR_mskUDFT | FPCSR_mskIEXT |FPCSR_mskDNIT | FPCSR_mskRIT)
+
+/******************************************************************************
+ * fpcfg: FPCFG (Floating-Point Configuration Register)
+ *****************************************************************************/
+#define FPCFG_offSP 0
+#define FPCFG_offDP 1
+#define FPCFG_offFREG 2
+#define FPCFG_offFMA 4
+#define FPCFG_offIMVER 22
+#define FPCFG_offAVER 27
+
+#define FPCFG_mskSP ( 0x1 << FPCFG_offSP )
+#define FPCFG_mskDP ( 0x1 << FPCFG_offDP )
+#define FPCFG_mskFREG ( 0x3 << FPCFG_offFREG )
+#define FPCFG_mskFMA ( 0x1 << FPCFG_offFMA )
+#define FPCFG_mskIMVER ( 0x1F << FPCFG_offIMVER )
+#define FPCFG_mskAVER ( 0x1F << FPCFG_offAVER )
+
+/******************************************************************************
+ * fucpr: FUCOP_CTL (FPU and Coprocessor Enable Control Register)
+ *****************************************************************************/
+#define FUCOP_CTL_offCP0EN 0
+#define FUCOP_CTL_offCP1EN 1
+#define FUCOP_CTL_offCP2EN 2
+#define FUCOP_CTL_offCP3EN 3
+#define FUCOP_CTL_offAUEN 31
+
+#define FUCOP_CTL_mskCP0EN ( 0x1 << FUCOP_CTL_offCP0EN )
+#define FUCOP_CTL_mskCP1EN ( 0x1 << FUCOP_CTL_offCP1EN )
+#define FUCOP_CTL_mskCP2EN ( 0x1 << FUCOP_CTL_offCP2EN )
+#define FUCOP_CTL_mskCP3EN ( 0x1 << FUCOP_CTL_offCP3EN )
+#define FUCOP_CTL_mskAUEN ( 0x1 << FUCOP_CTL_offAUEN )
+
+#endif /* __NDS32_BITFIELD_H__ */
diff --git a/arch/nds32/include/asm/nds32.h b/arch/nds32/include/asm/nds32.h
new file mode 100644
index 0000000..9d99c3f
--- /dev/null
+++ b/arch/nds32/include/asm/nds32.h
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_NDS32_NDS32_H_
+#define _ASM_NDS32_NDS32_H_
+
+#include <asm/bitfield.h>
+#include <asm/cachectl.h>
+
+#ifndef __ASSEMBLY__
+#include <asm/barrier.h>
+#include <nds32_intrinsic.h>
+
+#ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
+#define FP_OFFSET (-3)
+#else
+#define FP_OFFSET (-2)
+#endif
+
+static inline void GIE_ENABLE(void)
+{
+ mb();
+ __nds32__gie_en();
+}
+
+static inline void GIE_DISABLE(void)
+{
+ mb();
+ __nds32__gie_dis();
+}
+
+static inline unsigned long CACHE_SET(unsigned char cache)
+{
+
+ if (cache == ICACHE)
+ return 64 << ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISET) >>
+ ICM_CFG_offISET);
+ else
+ return 64 << ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSET) >>
+ DCM_CFG_offDSET);
+}
+
+static inline unsigned long CACHE_WAY(unsigned char cache)
+{
+
+ if (cache == ICACHE)
+ return 1 +
+ ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskIWAY) >> ICM_CFG_offIWAY);
+ else
+ return 1 +
+ ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDWAY) >> DCM_CFG_offDWAY);
+}
+
+static inline unsigned long CACHE_LINE_SIZE(unsigned char cache)
+{
+
+ if (cache == ICACHE)
+ return 8 <<
+ (((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISZ) >> ICM_CFG_offISZ) - 1);
+ else
+ return 8 <<
+ (((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSZ) >> DCM_CFG_offDSZ) - 1);
+}
+
+#endif /* __ASSEMBLY__ */
+
+/* tbl and why is used in ex-scall.S and ex-exit.S */
+#define tbl $r8
+#define why $r8
+
+#define IVB_BASE PHYS_OFFSET /* in user space for intr/exc/trap/break table base, 64KB aligned
+ * We defined at the start of the physical memory */
+
+/* dispatched sub-entry exception handler numbering */
+#define RD_PROT 0 /* read protrection */
+#define WRT_PROT 1 /* write protection */
+#define NOEXEC 2 /* non executable */
+#define PAGE_MODIFY 3 /* page modified */
+#define ACC_BIT 4 /* access bit */
+#define RESVED_PTE 5 /* reserved PTE attribute */
+/* reserved 6 ~ 16 */
+
+#endif /* _ASM_NDS32_NDS32_H_ */
diff --git a/arch/nds32/kernel/asm-offsets.c b/arch/nds32/kernel/asm-offsets.c
new file mode 100644
index 0000000..3541d59
--- /dev/null
+++ b/arch/nds32/kernel/asm-offsets.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/sched.h>
+#include <linux/sched/task_stack.h>
+#include <linux/kbuild.h>
+#include <asm/thread_info.h>
+#include <asm/ptrace.h>
+
+int main(void)
+{
+ DEFINE(TSK_TI_FLAGS, offsetof(struct task_struct, thread_info.flags));
+ DEFINE(TSK_TI_PREEMPT,
+ offsetof(struct task_struct, thread_info.preempt_count));
+ DEFINE(THREAD_CPU_CONTEXT,
+ offsetof(struct task_struct, thread.cpu_context));
+ DEFINE(OSP_OFFSET, offsetof(struct pt_regs, osp));
+ DEFINE(SP_OFFSET, offsetof(struct pt_regs, sp));
+ DEFINE(FUCOP_CTL_OFFSET, offsetof(struct pt_regs, fucop_ctl));
+ DEFINE(IPSW_OFFSET, offsetof(struct pt_regs, ipsw));
+ DEFINE(SYSCALLNO_OFFSET, offsetof(struct pt_regs, syscallno));
+ DEFINE(IPC_OFFSET, offsetof(struct pt_regs, ipc));
+ DEFINE(R0_OFFSET, offsetof(struct pt_regs, uregs[0]));
+ DEFINE(R15_OFFSET, offsetof(struct pt_regs, uregs[15]));
+ DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
+ DEFINE(CLOCK_COARSE_RES, LOW_RES_NSEC);
+ return 0;
+}
--
1.7.9.5
^ permalink raw reply related
* [PATCH v5 04/39] earlycon: add reg-offset to physical address before mapping
From: Greentime Hu @ 2018-01-02 8:24 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial,
geert.uytterhoeven, linus.walleij, mark.rutland, greg, ren_guo,
rdunlap, davem, jonas, stefan.kristiansson, shorne
Cc: green.hu
In-Reply-To: <cover.1514874857.git.green.hu@gmail.com>
From: Greentime Hu <greentime@andestech.com>
It will get the wrong virtual address because port->mapbase is not added
the correct reg-offset yet. We have to update it before earlycon_map()
is called
Signed-off-by: Greentime Hu <greentime@andestech.com>
---
drivers/tty/serial/earlycon.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c
index 98928f0..17dba0a 100644
--- a/drivers/tty/serial/earlycon.c
+++ b/drivers/tty/serial/earlycon.c
@@ -253,11 +253,12 @@ int __init of_setup_earlycon(const struct earlycon_id *match,
}
port->mapbase = addr;
port->uartclk = BASE_BAUD * 16;
- port->membase = earlycon_map(port->mapbase, SZ_4K);
val = of_get_flat_dt_prop(node, "reg-offset", NULL);
if (val)
port->mapbase += be32_to_cpu(*val);
+ port->membase = earlycon_map(port->mapbase, SZ_4K);
+
val = of_get_flat_dt_prop(node, "reg-shift", NULL);
if (val)
port->regshift = be32_to_cpu(*val);
--
1.7.9.5
^ permalink raw reply related
* [PATCH v5 03/39] sparc: io: To use the define of ioremap_[nocache|wc|wb] in asm-generic/io.h
From: Greentime Hu @ 2018-01-02 8:24 UTC (permalink / raw)
To: greentime-MUIXKm3Oiri1Z/+hSey0Gg,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
linux-arch-u79uwXL29TY76Z2rM5mHXA, tglx-hfZtesqFncYOwBW4kG4KsQ,
jason-NLaQJdtUoK4Be96aLqz0jA, marc.zyngier-5wv7dgnIgG8,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, netdev-u79uwXL29TY76Z2rM5mHXA,
deanbo422-Re5JQEeQqe8AvxtiuMwx3w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
viro-RmSDqhL/yNMiFSDQTTA3OLVCufUGDwFn,
dhowells-H+wXaHxf7aLQT0dZR+AlfA, will.deacon-5wv7dgnIgG8,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A,
linux-serial-u79uwXL29TY76Z2rM5mHXA,
geert.uytterhoeven-Re5JQEeQqe8AvxtiuMwx3w,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
greg-U8xfFu+wG4EAvxtiuMwx3w, ren_guo-Y+KPrCd2zL4AvxtiuMwx3w,
rdunlap-wEGCiKHe2LqWVfeAwA7xHQ, davem-fT/PcQaiUtIeIZ0/mPfg9Q,
jonas-A9uVI2HLR7kOP4wsBPIw7w,
stefan.kristiansson-MbMCFXIvDHJFcC0YU169RA,
shorne-Re5JQEeQqe8AvxtiuMwx3w
Cc: green.hu-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <cover.1514874857.git.green.hu-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Greentime Hu <greentime-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org>
It will be built failed if commit id: d25ea659 is selected. This patch
can fix this build error.
Signed-off-by: Greentime Hu <greentime-MUIXKm3Oiri1Z/+hSey0Gg@public.gmane.org>
---
arch/sparc/include/asm/io_32.h | 5 -----
arch/sparc/kernel/ioport.c | 4 ++--
2 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h
index cd51a89..df2dc17 100644
--- a/arch/sparc/include/asm/io_32.h
+++ b/arch/sparc/include/asm/io_32.h
@@ -127,12 +127,7 @@ static inline void sbus_memcpy_toio(volatile void __iomem *dst,
* Bus number may be embedded in the higher bits of the physical address.
* This is why we have no bus number argument to ioremap().
*/
-void __iomem *ioremap(unsigned long offset, unsigned long size);
-#define ioremap_nocache(X,Y) ioremap((X),(Y))
-#define ioremap_wc(X,Y) ioremap((X),(Y))
-#define ioremap_wt(X,Y) ioremap((X),(Y))
void iounmap(volatile void __iomem *addr);
-
/* Create a virtual mapping cookie for an IO port range */
void __iomem *ioport_map(unsigned long port, unsigned int nr);
void ioport_unmap(void __iomem *);
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c
index 7eeef80..3bcef9c 100644
--- a/arch/sparc/kernel/ioport.c
+++ b/arch/sparc/kernel/ioport.c
@@ -122,12 +122,12 @@ static void xres_free(struct xresource *xrp) {
*
* Bus type is always zero on IIep.
*/
-void __iomem *ioremap(unsigned long offset, unsigned long size)
+void __iomem *ioremap(phys_addr_t offset, size_t size)
{
char name[14];
sprintf(name, "phys_%08x", (u32)offset);
- return _sparc_alloc_io(0, offset, size, name);
+ return _sparc_alloc_io(0, (unsigned long)offset, size, name);
}
EXPORT_SYMBOL(ioremap);
--
1.7.9.5
--
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^ permalink raw reply related
* [PATCH v5 02/39] openrisc: add ioremap_nocache declaration before include asm-generic/io.h and sync ioremap prototype with it.
From: Greentime Hu @ 2018-01-02 8:24 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial,
geert.uytterhoeven, linus.walleij, mark.rutland, greg, ren_guo,
rdunlap, davem, jonas, stefan.kristiansson, shorne
Cc: green.hu
In-Reply-To: <cover.1514874857.git.green.hu@gmail.com>
From: Greentime Hu <greentime@andestech.com>
It will be built failed if commit id: d25ea659 is selected. This patch can fix this
build error.
Signed-off-by: Greentime Hu <greentime@andestech.com>
---
arch/openrisc/include/asm/io.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/openrisc/include/asm/io.h b/arch/openrisc/include/asm/io.h
index 7c69139..6709b28 100644
--- a/arch/openrisc/include/asm/io.h
+++ b/arch/openrisc/include/asm/io.h
@@ -29,13 +29,14 @@
#define PIO_OFFSET 0
#define PIO_MASK 0
+#define ioremap_nocache ioremap_nocache
#include <asm-generic/io.h>
#include <asm/pgtable.h>
extern void __iomem *__ioremap(phys_addr_t offset, unsigned long size,
pgprot_t prot);
-static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
+static inline void __iomem *ioremap(phys_addr_t offset, size_t size)
{
return __ioremap(offset, size, PAGE_KERNEL);
}
--
1.7.9.5
^ permalink raw reply related
* [PATCH v5 01/39] asm-generic/io.h: move ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef CONFIG_MMU
From: Greentime Hu @ 2018-01-02 8:24 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial,
geert.uytterhoeven, linus.walleij, mark.rutland, greg, ren_guo,
rdunlap, davem, jonas, stefan.kristiansson, shorne
Cc: green.hu, Vincent Chen
In-Reply-To: <cover.1514874857.git.green.hu@gmail.com>
From: Greentime Hu <greentime@andestech.com>
It allows some architectures to use this generic macro instead of
defining theirs.
Signed-off-by: Vincent Chen <vincentc@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
include/asm-generic/io.h | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index b4531e3..7c6a39e 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -852,7 +852,16 @@ static inline void __iomem *__ioremap(phys_addr_t offset, size_t size,
}
#endif
+#ifndef iounmap
+#define iounmap iounmap
+
+static inline void iounmap(void __iomem *addr)
+{
+}
+#endif
+#endif /* CONFIG_MMU */
#ifndef ioremap_nocache
+void __iomem *ioremap(phys_addr_t phys_addr, size_t size);
#define ioremap_nocache ioremap_nocache
static inline void __iomem *ioremap_nocache(phys_addr_t offset, size_t size)
{
@@ -884,15 +893,6 @@ static inline void __iomem *ioremap_wt(phys_addr_t offset, size_t size)
}
#endif
-#ifndef iounmap
-#define iounmap iounmap
-
-static inline void iounmap(void __iomem *addr)
-{
-}
-#endif
-#endif /* CONFIG_MMU */
-
#ifdef CONFIG_HAS_IOPORT_MAP
#ifndef CONFIG_GENERIC_IOMAP
#ifndef ioport_map
--
1.7.9.5
^ permalink raw reply related
* [PATCH v5 00/39] Andes(nds32) Linux Kernel Port
From: Greentime Hu @ 2018-01-02 8:24 UTC (permalink / raw)
To: greentime, linux-kernel, arnd, linux-arch, tglx, jason,
marc.zyngier, robh+dt, netdev, deanbo422, devicetree, viro,
dhowells, will.deacon, daniel.lezcano, linux-serial,
geert.uytterhoeven, linus.walleij, mark.rutland, greg, ren_guo,
rdunlap, davem, jonas, stefan.kristiansson, shorne
Cc: Greentime Hu
This is the 5th version patchset to add the Linux kernel port for Andes(nds32)
processors. Almost all of the feedbacks from v4 patchseries has been addressed.
Thanks to everyone who provided feedback on the previous version.
This patchset adds core architecture support to Linux for Andestech's
N13, N15, D15, N10, D10 processor cores.
Based on the 16/32-bit AndeStar RISC-like architecture, we designed the
configurable AndesCore series of embedded processor families. AndesCores
range from highly performance-efficient small-footprint cores for
microcontrollers and deeply-embedded applications to 1GHz+ cores running
Linux, covering general-purpose N-series cores for a wide range of computing
need, DSP-capable D-series cores for digital signal control,
instruction-extensible E-series cores for application-specific acceleration,
and secure S-series cores for best protection of the most valuable.
The patches are based on v4.14-rc8, and can also be found in the
following git tree:
https://github.com/andestech/linux.git nds32-4.14-rc8-v5
The build script and toolchain repositories are able to be found here:
https://github.com/andestech/build_script.git
Freely available instruction set and architecture overview documents can
be found on the following page:
http://www.andestech.com/product.php?cls=9
Vincent Ren-Wei Chen and I will maintain this port. Thanks to everyone who
helped us and contributed to it. :) Any feedback is welcome.
Changes in v5:
- Remove __NR__llseek and sys_mmap()
- Add a comment to explain that we don't have clocksource cycle counter in the CPU
- Add volatile in iounmap()
- Fix typo Featuretures to Features
- Replace CPU_CACHE_NONALIASING with !CPU_CACHE_ALIASING
- Fix a endian bug when we try to get val = of_get_property(cpu, "clock-frequency", NULL)
- Add screen_info to fix the building error when CONFIG_ VGA_CONSOLE is enabled
- Remove unnecessary msync()
- Add depends on !64BIT || BROKEN for faraday Kconfig because the descriptor only supports 32bit
- Add atl2c binding document
- Remove unnecessary include headers
- Fix a vector table bug. It placed wrong vector handlers for 2 exceptions.
- Fix a vdso bug. It may encounter TLB multi-hit exception because we accidently set it as a global page.
- Add proper isb and barrier after some cache operations
- Fix a bug in system call restart flow. $r0 ~ $r5 does not be recovered before restarting system call
- Fix the build errors for OpenRISC and SPARC because io.h changed.
- Update ae3xx.dts to support atl2c.
Changes in v4:
- Add atcpit100 timer driver due to it include vdso implementations and sent
them together with nds32 may help reviewer to review.
- Update ae3xx.dts for atcpit100 clock setting and remove vdso settings.
- To get cycle counter register by timer driver instead of dts.
- Use "depends on NDS32 || COMPILE_TEST" in atcpit100 driver because it is needed for nds32 vdso
- Update defconfig becasue kconfig rename from CONFIG_CLKSRC_ATCPIT100 to CONFIG_TIMER_ATCPIT100
- Remove ag101p.dts because we are not yet ready for ag101p platform.
- Update copyright style to SPDX-License-Identifier
- Include <linux/uaccess.h> instead of <asm/uaccess.h>
- Add local_irq_save()/local_irq_restore() to protect SR_TLB_VPN in update_mmu_cache().
- Update cpu_dcache_inval_all implementation to make sure all level cache are writeback.
Changes in v3:
- Use arch's io.h instead of generic one
- Add andestech-boards binding document
- Update nds32/cpus.txt binding document
- Remove atcpit100 timer drivers
- Select NO_BOOTMEM and delete HAVE_MEMBLOCK_NODE_MAP
- make CPU_BIG_ENDIAN and CPU_LITTLE_ENDIAN are dependent
- Add cpu type to select HWZOL/CPU_CACHE_ALIASING
- Change CPU_CACHE_NONALIASING to CPU_CACHE_ALIASING
- Remove bootarg from device tree script
- Update ag101p.dts and ae3xx.dts for correct board name.
- Clear and simplify defconfig
- Implement L2C_R_REG/ L2C_W_REG with readl/writel instead of __raw_readl/__raw_writel for endian save
- Remove early_init_dt_add_memory_arch/early_init_dt_alloc_memory_arch to use the generic ones
- Refine devicetree.c
- Fix bug https://lkml.kernel.org/r/1499782590-31366-1-git-send-ema...
- Refine irqchip/irq-ativic32.c implementations
- Add COMPILE_TEST in drivers/net/ethernet/faraday/Kconfig
- Refine cache operations
- Add CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS
- Fix ZERO_PAGE define
- Remove SA_RESTORER
- Remove uapi/asm/signal.h
- Redefine user_pt_regs
- Remove spinlock.h
- Remove __ARCH_WANT_RENAMEAT and __ARCH_WANT_SYSCALL_OFF_T from unistd.h
- Remove set_fs(USER_DS) because flush_old_exec() will do this setting
- Replace in_atomic() with faulthandler_disabled()
- Add barrier.h
- Select COMMON_CLK
- Add clk_pll in dts
- Add of_clk_init() in arch/nds32/kernel/time.c
Changes in v2:
- Set GENERIC_CALIBRATE_DELAY default n
- Add earlycon support
- Remove earlyprintk
- Add CPU_BIG_ENDIAN, CPU_LITTLE_ENDIAN support
- Refine unalignment access exception handler
- Add VMSPLIT support
- Use only one defconfig
- Change interrupt-cells from 2 to 1
- Refine andestech cpu names in bindings/nds32/cpus.txt
- Get clock frequency in dts because fpga bitmap doesn't include this feature
- Update MAINTAINERS for bindings
- Remove unused configs in Kconfig
- Refine device tree scripts
- Refine coding style
- Use generic ioremap_nocache
- Remove L2CC_PA_BASE define and its codes in head.S. It will be moved to bootloader.
- Set PHYS_OFFSET to 0x0 instead of CONFIG_MEMORY_START
- Remove unused macros
- Simplify cpu_cache_* API
- Change __asm__ __volatile__ to asm volatile
- Refine uaccess.h
- Remove unused/deprecated syscall
- Use generic posix_types.h
- Remove arch_trace_hardirqs_on/arch_trace_hardirqs_off
- Fix bug of restart syscall
- Refine syscall implementations
- Use IS_ENABLED to replace ifdef as possible
- Remove device_initcall(nds32_device_probe)
- Refine vdso implementations
- Refine copy_from_user()/copy_to_user()/clear_user()/get_user()/memmove()/memcpy()
- Refine ioremap.c
- Refine irq-ativic32.c
- Fix a bug of earlycon.c
- Export ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt
- Add atcpit100 driver
Greentime Hu (36):
asm-generic/io.h: move
ioremap_nocache/ioremap_uc/ioremap_wc/ioremap_wt out of ifndef
CONFIG_MMU
openrisc: add ioremap_nocache declaration before include
asm-generic/io.h and sync ioremap prototype with it.
sparc: io: To use the define of ioremap_[nocache|wc|wb] in
asm-generic/io.h
earlycon: add reg-offset to physical address before mapping
nds32: Assembly macros and definitions
nds32: Kernel booting and initialization
nds32: Exception handling
nds32: MMU definitions
nds32: MMU initialization
nds32: MMU fault handling and page table management
nds32: Cache and TLB routines
nds32: Process management
nds32: IRQ handling
nds32: Atomic operations
nds32: Device specific operations
nds32: DMA mapping API
nds32: ELF definitions
nds32: System calls handling
nds32: VDSO support
nds32: Signal handling support
nds32: Library functions
nds32: Debugging support
nds32: L2 cache support
nds32: Loadable modules
nds32: Generic timers support
nds32: Device tree support
nds32: Miscellaneous header files
nds32: defconfig
nds32: Build infrastructure
MAINTAINERS: Add nds32
dt-bindings: nds32 CPU Bindings
dt-bindings: nds32 L2 cache controller Bindings
dt-bindings: nds32 SoC Bindings
dt-bindings: interrupt-controller: Andestech Internal Vector
Interrupt Controller
irqchip: Andestech Internal Vector Interrupt Controller driver
net: faraday add nds32 support.
Rick Chen (3):
clocksource/drivers/atcpit100: Add andestech atcpit100 timer
clocksource/drivers/atcpit100: VDSO support
dt-bindings: timer: Add andestech atcpit100 timer binding doc
.../interrupt-controller/andestech,ativic32.txt | 19 +
.../devicetree/bindings/nds32/andestech-boards | 40 +
Documentation/devicetree/bindings/nds32/atl2c.txt | 29 +
Documentation/devicetree/bindings/nds32/cpus.txt | 37 +
.../bindings/timer/andestech,atcpit100-timer.txt | 33 +
MAINTAINERS | 11 +
arch/nds32/Kconfig | 108 +++
arch/nds32/Kconfig.cpu | 161 ++++
arch/nds32/Makefile | 66 ++
arch/nds32/boot/Makefile | 15 +
arch/nds32/boot/dts/Makefile | 8 +
arch/nds32/boot/dts/ae3xx.dts | 73 ++
arch/nds32/configs/defconfig | 108 +++
arch/nds32/include/asm/Kbuild | 54 ++
arch/nds32/include/asm/assembler.h | 39 +
arch/nds32/include/asm/barrier.h | 15 +
arch/nds32/include/asm/bitfield.h | 963 ++++++++++++++++++++
arch/nds32/include/asm/cache.h | 12 +
arch/nds32/include/asm/cache_info.h | 13 +
arch/nds32/include/asm/cacheflush.h | 44 +
arch/nds32/include/asm/current.h | 12 +
arch/nds32/include/asm/delay.h | 39 +
arch/nds32/include/asm/dma-mapping.h | 14 +
arch/nds32/include/asm/elf.h | 179 ++++
arch/nds32/include/asm/fixmap.h | 29 +
arch/nds32/include/asm/futex.h | 103 +++
arch/nds32/include/asm/highmem.h | 65 ++
arch/nds32/include/asm/io.h | 83 ++
arch/nds32/include/asm/irqflags.h | 36 +
arch/nds32/include/asm/l2_cache.h | 137 +++
arch/nds32/include/asm/linkage.h | 11 +
arch/nds32/include/asm/memory.h | 105 +++
arch/nds32/include/asm/mmu.h | 12 +
arch/nds32/include/asm/mmu_context.h | 68 ++
arch/nds32/include/asm/module.h | 11 +
arch/nds32/include/asm/nds32.h | 83 ++
arch/nds32/include/asm/page.h | 67 ++
arch/nds32/include/asm/pgalloc.h | 96 ++
arch/nds32/include/asm/pgtable.h | 409 +++++++++
arch/nds32/include/asm/proc-fns.h | 44 +
arch/nds32/include/asm/processor.h | 102 +++
arch/nds32/include/asm/ptrace.h | 66 ++
arch/nds32/include/asm/shmparam.h | 19 +
arch/nds32/include/asm/string.h | 17 +
arch/nds32/include/asm/swab.h | 35 +
arch/nds32/include/asm/syscall.h | 188 ++++
arch/nds32/include/asm/syscalls.h | 13 +
arch/nds32/include/asm/thread_info.h | 78 ++
arch/nds32/include/asm/tlb.h | 28 +
arch/nds32/include/asm/tlbflush.h | 47 +
arch/nds32/include/asm/uaccess.h | 283 ++++++
arch/nds32/include/asm/unistd.h | 6 +
arch/nds32/include/asm/vdso.h | 24 +
arch/nds32/include/asm/vdso_datapage.h | 36 +
arch/nds32/include/asm/vdso_timer_info.h | 14 +
arch/nds32/include/uapi/asm/Kbuild | 28 +
arch/nds32/include/uapi/asm/auxvec.h | 12 +
arch/nds32/include/uapi/asm/byteorder.h | 13 +
arch/nds32/include/uapi/asm/cachectl.h | 14 +
arch/nds32/include/uapi/asm/param.h | 11 +
arch/nds32/include/uapi/asm/ptrace.h | 25 +
arch/nds32/include/uapi/asm/sigcontext.h | 60 ++
arch/nds32/include/uapi/asm/unistd.h | 11 +
arch/nds32/kernel/Makefile | 23 +
arch/nds32/kernel/asm-offsets.c | 28 +
arch/nds32/kernel/atl2c.c | 64 ++
arch/nds32/kernel/cacheinfo.c | 49 +
arch/nds32/kernel/devtree.c | 19 +
arch/nds32/kernel/dma.c | 459 ++++++++++
arch/nds32/kernel/ex-entry.S | 157 ++++
arch/nds32/kernel/ex-exit.S | 193 ++++
arch/nds32/kernel/ex-scall.S | 106 +++
arch/nds32/kernel/head.S | 188 ++++
arch/nds32/kernel/irq.c | 9 +
arch/nds32/kernel/module.c | 286 ++++++
arch/nds32/kernel/nds32_ksyms.c | 31 +
arch/nds32/kernel/process.c | 204 +++++
arch/nds32/kernel/ptrace.c | 311 +++++++
arch/nds32/kernel/setup.c | 387 ++++++++
arch/nds32/kernel/signal.c | 337 +++++++
arch/nds32/kernel/stacktrace.c | 47 +
arch/nds32/kernel/sys_nds32.c | 50 +
arch/nds32/kernel/syscall_table.c | 17 +
arch/nds32/kernel/time.c | 11 +
arch/nds32/kernel/traps.c | 428 +++++++++
arch/nds32/kernel/vdso.c | 230 +++++
arch/nds32/kernel/vdso/Makefile | 82 ++
arch/nds32/kernel/vdso/datapage.S | 21 +
arch/nds32/kernel/vdso/gen_vdso_offsets.sh | 15 +
arch/nds32/kernel/vdso/gettimeofday.c | 271 ++++++
arch/nds32/kernel/vdso/note.S | 11 +
arch/nds32/kernel/vdso/sigreturn.S | 19 +
arch/nds32/kernel/vdso/vdso.S | 18 +
arch/nds32/kernel/vdso/vdso.lds.S | 76 ++
arch/nds32/kernel/vmlinux.lds.S | 57 ++
arch/nds32/lib/Makefile | 3 +
arch/nds32/lib/clear_user.S | 42 +
arch/nds32/lib/copy_from_user.S | 45 +
arch/nds32/lib/copy_page.S | 37 +
arch/nds32/lib/copy_template.S | 70 ++
arch/nds32/lib/copy_to_user.S | 45 +
arch/nds32/lib/memcpy.S | 30 +
arch/nds32/lib/memmove.S | 70 ++
arch/nds32/lib/memset.S | 33 +
arch/nds32/lib/memzero.S | 18 +
arch/nds32/mm/Makefile | 7 +
arch/nds32/mm/alignment.c | 609 +++++++++++++
arch/nds32/mm/cacheflush.c | 322 +++++++
arch/nds32/mm/extable.c | 16 +
arch/nds32/mm/fault.c | 410 +++++++++
arch/nds32/mm/highmem.c | 79 ++
arch/nds32/mm/init.c | 277 ++++++
arch/nds32/mm/ioremap.c | 62 ++
arch/nds32/mm/mm-nds32.c | 90 ++
arch/nds32/mm/mmap.c | 73 ++
arch/nds32/mm/proc.c | 533 +++++++++++
arch/nds32/mm/tlb.c | 50 +
arch/openrisc/include/asm/io.h | 3 +-
arch/sparc/include/asm/io_32.h | 5 -
arch/sparc/kernel/ioport.c | 4 +-
drivers/clocksource/Kconfig | 7 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-atcpit100.c | 273 ++++++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-ativic32.c | 107 +++
drivers/net/ethernet/faraday/Kconfig | 8 +-
drivers/tty/serial/earlycon.c | 3 +-
include/asm-generic/io.h | 18 +-
128 files changed, 12115 insertions(+), 21 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
create mode 100644 Documentation/devicetree/bindings/nds32/andestech-boards
create mode 100644 Documentation/devicetree/bindings/nds32/atl2c.txt
create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txt
create mode 100644 Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
create mode 100644 arch/nds32/Kconfig
create mode 100644 arch/nds32/Kconfig.cpu
create mode 100644 arch/nds32/Makefile
create mode 100644 arch/nds32/boot/Makefile
create mode 100644 arch/nds32/boot/dts/Makefile
create mode 100644 arch/nds32/boot/dts/ae3xx.dts
create mode 100644 arch/nds32/configs/defconfig
create mode 100644 arch/nds32/include/asm/Kbuild
create mode 100644 arch/nds32/include/asm/assembler.h
create mode 100644 arch/nds32/include/asm/barrier.h
create mode 100644 arch/nds32/include/asm/bitfield.h
create mode 100644 arch/nds32/include/asm/cache.h
create mode 100644 arch/nds32/include/asm/cache_info.h
create mode 100644 arch/nds32/include/asm/cacheflush.h
create mode 100644 arch/nds32/include/asm/current.h
create mode 100644 arch/nds32/include/asm/delay.h
create mode 100644 arch/nds32/include/asm/dma-mapping.h
create mode 100644 arch/nds32/include/asm/elf.h
create mode 100644 arch/nds32/include/asm/fixmap.h
create mode 100644 arch/nds32/include/asm/futex.h
create mode 100644 arch/nds32/include/asm/highmem.h
create mode 100644 arch/nds32/include/asm/io.h
create mode 100644 arch/nds32/include/asm/irqflags.h
create mode 100644 arch/nds32/include/asm/l2_cache.h
create mode 100644 arch/nds32/include/asm/linkage.h
create mode 100644 arch/nds32/include/asm/memory.h
create mode 100644 arch/nds32/include/asm/mmu.h
create mode 100644 arch/nds32/include/asm/mmu_context.h
create mode 100644 arch/nds32/include/asm/module.h
create mode 100644 arch/nds32/include/asm/nds32.h
create mode 100644 arch/nds32/include/asm/page.h
create mode 100644 arch/nds32/include/asm/pgalloc.h
create mode 100644 arch/nds32/include/asm/pgtable.h
create mode 100644 arch/nds32/include/asm/proc-fns.h
create mode 100644 arch/nds32/include/asm/processor.h
create mode 100644 arch/nds32/include/asm/ptrace.h
create mode 100644 arch/nds32/include/asm/shmparam.h
create mode 100644 arch/nds32/include/asm/string.h
create mode 100644 arch/nds32/include/asm/swab.h
create mode 100644 arch/nds32/include/asm/syscall.h
create mode 100644 arch/nds32/include/asm/syscalls.h
create mode 100644 arch/nds32/include/asm/thread_info.h
create mode 100644 arch/nds32/include/asm/tlb.h
create mode 100644 arch/nds32/include/asm/tlbflush.h
create mode 100644 arch/nds32/include/asm/uaccess.h
create mode 100644 arch/nds32/include/asm/unistd.h
create mode 100644 arch/nds32/include/asm/vdso.h
create mode 100644 arch/nds32/include/asm/vdso_datapage.h
create mode 100644 arch/nds32/include/asm/vdso_timer_info.h
create mode 100644 arch/nds32/include/uapi/asm/Kbuild
create mode 100644 arch/nds32/include/uapi/asm/auxvec.h
create mode 100644 arch/nds32/include/uapi/asm/byteorder.h
create mode 100644 arch/nds32/include/uapi/asm/cachectl.h
create mode 100644 arch/nds32/include/uapi/asm/param.h
create mode 100644 arch/nds32/include/uapi/asm/ptrace.h
create mode 100644 arch/nds32/include/uapi/asm/sigcontext.h
create mode 100644 arch/nds32/include/uapi/asm/unistd.h
create mode 100644 arch/nds32/kernel/Makefile
create mode 100644 arch/nds32/kernel/asm-offsets.c
create mode 100644 arch/nds32/kernel/atl2c.c
create mode 100644 arch/nds32/kernel/cacheinfo.c
create mode 100644 arch/nds32/kernel/devtree.c
create mode 100644 arch/nds32/kernel/dma.c
create mode 100644 arch/nds32/kernel/ex-entry.S
create mode 100644 arch/nds32/kernel/ex-exit.S
create mode 100644 arch/nds32/kernel/ex-scall.S
create mode 100644 arch/nds32/kernel/head.S
create mode 100644 arch/nds32/kernel/irq.c
create mode 100644 arch/nds32/kernel/module.c
create mode 100644 arch/nds32/kernel/nds32_ksyms.c
create mode 100644 arch/nds32/kernel/process.c
create mode 100644 arch/nds32/kernel/ptrace.c
create mode 100644 arch/nds32/kernel/setup.c
create mode 100644 arch/nds32/kernel/signal.c
create mode 100644 arch/nds32/kernel/stacktrace.c
create mode 100644 arch/nds32/kernel/sys_nds32.c
create mode 100644 arch/nds32/kernel/syscall_table.c
create mode 100644 arch/nds32/kernel/time.c
create mode 100644 arch/nds32/kernel/traps.c
create mode 100644 arch/nds32/kernel/vdso.c
create mode 100644 arch/nds32/kernel/vdso/Makefile
create mode 100644 arch/nds32/kernel/vdso/datapage.S
create mode 100755 arch/nds32/kernel/vdso/gen_vdso_offsets.sh
create mode 100644 arch/nds32/kernel/vdso/gettimeofday.c
create mode 100644 arch/nds32/kernel/vdso/note.S
create mode 100644 arch/nds32/kernel/vdso/sigreturn.S
create mode 100644 arch/nds32/kernel/vdso/vdso.S
create mode 100644 arch/nds32/kernel/vdso/vdso.lds.S
create mode 100644 arch/nds32/kernel/vmlinux.lds.S
create mode 100644 arch/nds32/lib/Makefile
create mode 100644 arch/nds32/lib/clear_user.S
create mode 100644 arch/nds32/lib/copy_from_user.S
create mode 100644 arch/nds32/lib/copy_page.S
create mode 100644 arch/nds32/lib/copy_template.S
create mode 100644 arch/nds32/lib/copy_to_user.S
create mode 100644 arch/nds32/lib/memcpy.S
create mode 100644 arch/nds32/lib/memmove.S
create mode 100644 arch/nds32/lib/memset.S
create mode 100644 arch/nds32/lib/memzero.S
create mode 100644 arch/nds32/mm/Makefile
create mode 100644 arch/nds32/mm/alignment.c
create mode 100644 arch/nds32/mm/cacheflush.c
create mode 100644 arch/nds32/mm/extable.c
create mode 100644 arch/nds32/mm/fault.c
create mode 100644 arch/nds32/mm/highmem.c
create mode 100644 arch/nds32/mm/init.c
create mode 100644 arch/nds32/mm/ioremap.c
create mode 100644 arch/nds32/mm/mm-nds32.c
create mode 100644 arch/nds32/mm/mmap.c
create mode 100644 arch/nds32/mm/proc.c
create mode 100644 arch/nds32/mm/tlb.c
create mode 100644 drivers/clocksource/timer-atcpit100.c
create mode 100644 drivers/irqchip/irq-ativic32.c
--
1.7.9.5
^ permalink raw reply
* [RFC v2 9/9] Bluetooth: hci_h5: add support for Realtek UART Bluetooth modules
From: Martin Blumenstingl @ 2018-01-01 20:42 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-bluetooth-u79uwXL29TY76Z2rM5mHXA,
linux-serial-u79uwXL29TY76Z2rM5mHXA
Cc: mark.rutland-5wv7dgnIgG8, marcel-kz+m5ild9QBg9hUCZPvPmw,
gustavo-THi1TnShQwVAfugRpC6u6w,
johan.hedberg-Re5JQEeQqe8AvxtiuMwx3w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, jslaby-IBi9RG/b67k,
johan-DgEjT+Ai2ygdnm+yROfE0A,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Larry.Finger-tQ5ms3gMjBLk1uMJSBkQmQ, carlo-6IF/jdPJHihWk0Htik3J/w,
drake-6IF/jdPJHihWk0Htik3J/w, Martin Blumenstingl
In-Reply-To: <20180101204217.26165-1-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Realtek RTL8723BS and RTL8723DS are SDIO wifi chips with an embedded
Bluetooth controller which connects to the host via UART.
The H5 protocol is used for communication between host and device.
The Realtek "rtl8723bs_bt" and "rtl8723ds_bt" userspace Bluetooth UART
initialization tools (rtk_hciattach) use the following sequence:
1) send H5 sync pattern (already supported by hci_h5)
2) get LMP version (already supported by btrtl)
3) get ROM version (already supported by btrtl)
4) load the firmware and config for the current chipset (already
supported by btrtl)
5) read UART settings from the config blob (already supported by btrtl)
6) send UART settings via a vendor command to the device (which changes
the baudrate of the device and enables or disables flow control
depending on the config)
7) change the baudrate and flow control settings on the host
8) send the firmware and config blob to the device (already supported by
btrtl)
This uses the serdev library as well as the existing btrtl driver to
initialize the Bluetooth functionality, which consists of:
- identifying the device and loading the corresponding firmware and
config blobs (steps #2, #3 and #4)
- configuring the baudrate and flow control (steps #6 and #7)
- uploading the firmware to the device (step #8)
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
drivers/bluetooth/Kconfig | 1 +
drivers/bluetooth/hci_h5.c | 205 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 206 insertions(+)
diff --git a/drivers/bluetooth/Kconfig b/drivers/bluetooth/Kconfig
index 60e1c7d6986d..3001f1200c72 100644
--- a/drivers/bluetooth/Kconfig
+++ b/drivers/bluetooth/Kconfig
@@ -146,6 +146,7 @@ config BT_HCIUART_LL
config BT_HCIUART_3WIRE
bool "Three-wire UART (H5) protocol support"
depends on BT_HCIUART
+ select BT_RTL if SERIAL_DEV_BUS
help
The HCI Three-wire UART Transport Layer makes it possible to
user the Bluetooth HCI over a serial port interface. The HCI
diff --git a/drivers/bluetooth/hci_h5.c b/drivers/bluetooth/hci_h5.c
index 6cfc2f276250..a03acc3b1b52 100644
--- a/drivers/bluetooth/hci_h5.c
+++ b/drivers/bluetooth/hci_h5.c
@@ -28,7 +28,14 @@
#include <net/bluetooth/bluetooth.h>
#include <net/bluetooth/hci_core.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/serdev.h>
+
#include "hci_uart.h"
+#include "btrtl.h"
#define HCI_3WIRE_ACK_PKT 0
#define HCI_3WIRE_LINK_PKT 15
@@ -97,6 +104,13 @@ struct h5 {
} sleep;
};
+struct h5_device {
+ struct hci_uart hu;
+ struct gpio_desc *enable_gpio;
+ struct gpio_desc *reset_gpio;
+ int (*vendor_setup)(struct h5_device *h5_dev);
+};
+
static void h5_reset_rx(struct h5 *h5);
static void h5_link_control(struct hci_uart *hu, const void *data, size_t len)
@@ -190,6 +204,7 @@ static int h5_open(struct hci_uart *hu)
{
struct h5 *h5;
const unsigned char sync[] = { 0x01, 0x7e };
+ int err;
BT_DBG("hu %p", hu);
@@ -210,6 +225,14 @@ static int h5_open(struct hci_uart *hu)
h5->tx_win = H5_TX_WIN_MAX;
+ if (hu->serdev) {
+ err = serdev_device_open(hu->serdev);
+ if (err) {
+ bt_dev_err(hu->hdev, "failed to open serdev: %d", err);
+ return err;
+ }
+ }
+
/* Send initial sync request */
h5_link_control(hu, sync, sizeof(sync));
mod_timer(&h5->timer, jiffies + H5_SYNC_TIMEOUT);
@@ -217,6 +240,25 @@ static int h5_open(struct hci_uart *hu)
return 0;
}
+static int h5_setup(struct hci_uart *hu)
+{
+ int err;
+ struct h5_device *h5_dev;
+
+ if (!hu->serdev)
+ return 0;
+
+ h5_dev = serdev_device_get_drvdata(hu->serdev);
+
+ if (h5_dev->vendor_setup) {
+ err = h5_dev->vendor_setup(h5_dev);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
static int h5_close(struct hci_uart *hu)
{
struct h5 *h5 = hu->priv;
@@ -227,6 +269,15 @@ static int h5_close(struct hci_uart *hu)
skb_queue_purge(&h5->rel);
skb_queue_purge(&h5->unrel);
+ if (hu->serdev) {
+ struct h5_device *h5_dev;
+
+ h5_dev = serdev_device_get_drvdata(hu->serdev);
+ gpiod_set_value_cansleep(h5_dev->enable_gpio, 0);
+
+ serdev_device_close(hu->serdev);
+ }
+
kfree(h5);
return 0;
@@ -736,10 +787,160 @@ static int h5_flush(struct hci_uart *hu)
return 0;
}
+#if IS_ENABLED(CONFIG_SERIAL_DEV_BUS)
+static int h5_setup_realtek(struct h5_device *h5_dev)
+{
+ struct hci_uart *hu = &h5_dev->hu;
+ int err = 0, retry = 3;
+ struct sk_buff *skb;
+ struct btrtl_device_info *btrtl_dev;
+ __le32 baudrate_data;
+ u32 device_baudrate;
+ unsigned int controller_baudrate;
+ bool flow_control;
+
+ /* devices always start with flow control disabled and even parity */
+ serdev_device_set_flow_control(hu->serdev, false);
+ serdev_device_set_parity(hu->serdev, true, false);
+
+ do {
+ /* disable the device and put it into reset. some devices only
+ * have one of these lines, so we toggle both here to support
+ * all combinations.
+ */
+ gpiod_set_value_cansleep(h5_dev->reset_gpio, 1);
+ gpiod_set_value_cansleep(h5_dev->enable_gpio, 0);
+
+ /* wait until the device is disabled and/or reset. 500ms are
+ * chosen by manually testing on a RTL8723BS. shorter wait
+ * times lead to a non-responding device.
+ */
+ msleep(500);
+
+ /* take the device out of reset and enable it. */
+ gpiod_set_value_cansleep(h5_dev->reset_gpio, 0);
+ gpiod_set_value_cansleep(h5_dev->enable_gpio, 1);
+
+ /* after that we need to wait 500ms, otherwise the device might
+ * not respond in all cases. this was determined by testing
+ * with a RTL8723BS.
+ */
+ msleep(500);
+
+ btrtl_dev = btrtl_initialize(hu->hdev);
+ if (!IS_ERR(btrtl_dev))
+ break;
+
+ /* Toggle the enable and reset pins above and try again */
+ } while (retry--);
+
+ if (IS_ERR(btrtl_dev))
+ return PTR_ERR(btrtl_dev);
+
+ err = btrtl_get_uart_settings(hu->hdev, btrtl_dev,
+ &controller_baudrate, &device_baudrate,
+ &flow_control);
+ if (err)
+ goto out_free;
+
+ baudrate_data = cpu_to_le32(device_baudrate);
+ skb = __hci_cmd_sync(hu->hdev, 0xfc17, sizeof(baudrate_data),
+ &baudrate_data, HCI_INIT_TIMEOUT);
+ if (IS_ERR(skb)) {
+ bt_dev_err(hu->hdev, "set baud rate command failed");
+ err = -PTR_ERR(skb);
+ goto out_free;
+ } else {
+ kfree_skb(skb);
+ }
+
+ serdev_device_set_baudrate(hu->serdev, controller_baudrate);
+ serdev_device_set_flow_control(hu->serdev, flow_control);
+
+ err = btrtl_download_firmware(hu->hdev, btrtl_dev);
+
+out_free:
+ btrtl_free(btrtl_dev);
+
+ return err;
+}
+
+static const struct hci_uart_proto h5p;
+
+static int hci_h5_probe(struct serdev_device *serdev)
+{
+ struct hci_uart *hu;
+ struct h5_device *h5_dev;
+
+ h5_dev = devm_kzalloc(&serdev->dev, sizeof(*h5_dev), GFP_KERNEL);
+ if (!h5_dev)
+ return -ENOMEM;
+
+ hu = &h5_dev->hu;
+ hu->serdev = serdev;
+
+ serdev_device_set_drvdata(serdev, h5_dev);
+
+ h5_dev->vendor_setup = of_device_get_match_data(&serdev->dev);
+
+ h5_dev->enable_gpio = devm_gpiod_get_optional(&serdev->dev, "enable",
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(h5_dev->enable_gpio))
+ return PTR_ERR(h5_dev->enable_gpio);
+
+ h5_dev->reset_gpio = devm_gpiod_get_optional(&serdev->dev, "reset",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(h5_dev->reset_gpio))
+ return PTR_ERR(h5_dev->reset_gpio);
+
+ hci_uart_set_speeds(hu, 115200, 0);
+
+ return hci_uart_register_device(hu, &h5p);
+}
+
+static void hci_h5_remove(struct serdev_device *serdev)
+{
+ struct h5_device *h5_dev = serdev_device_get_drvdata(serdev);
+ struct hci_uart *hu = &h5_dev->hu;
+ struct hci_dev *hdev = hu->hdev;
+
+ cancel_work_sync(&hu->write_work);
+
+ hci_unregister_dev(hdev);
+ hci_free_dev(hdev);
+ hu->proto->close(hu);
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id hci_h5_of_match[] = {
+ {
+ .compatible = "realtek,rtl8723bs-bluetooth",
+ .data = h5_setup_realtek
+ },
+ {
+ .compatible = "realtek,rtl8723ds-bluetooth",
+ .data = h5_setup_realtek
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, hci_h5_of_match);
+#endif
+
+static struct serdev_device_driver hci_h5_drv = {
+ .driver = {
+ .name = "hci-h5",
+ .of_match_table = of_match_ptr(hci_h5_of_match),
+ },
+ .probe = hci_h5_probe,
+ .remove = hci_h5_remove,
+};
+#endif
+
static const struct hci_uart_proto h5p = {
.id = HCI_UART_3WIRE,
.name = "Three-wire (H5)",
.open = h5_open,
+ .setup = h5_setup,
.close = h5_close,
.recv = h5_recv,
.enqueue = h5_enqueue,
@@ -749,10 +950,14 @@ static const struct hci_uart_proto h5p = {
int __init h5_init(void)
{
+ serdev_device_driver_register(&hci_h5_drv);
+
return hci_uart_register_proto(&h5p);
}
int __exit h5_deinit(void)
{
+ serdev_device_driver_unregister(&hci_h5_drv);
+
return hci_uart_unregister_proto(&h5p);
}
--
2.15.1
^ permalink raw reply related
* [RFC v2 8/9] Bluetooth: drop HCI_UART_INIT_PENDING support
From: Martin Blumenstingl @ 2018-01-01 20:42 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-bluetooth-u79uwXL29TY76Z2rM5mHXA,
linux-serial-u79uwXL29TY76Z2rM5mHXA
Cc: mark.rutland-5wv7dgnIgG8, marcel-kz+m5ild9QBg9hUCZPvPmw,
gustavo-THi1TnShQwVAfugRpC6u6w,
johan.hedberg-Re5JQEeQqe8AvxtiuMwx3w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, jslaby-IBi9RG/b67k,
johan-DgEjT+Ai2ygdnm+yROfE0A,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Larry.Finger-tQ5ms3gMjBLk1uMJSBkQmQ, carlo-6IF/jdPJHihWk0Htik3J/w,
drake-6IF/jdPJHihWk0Htik3J/w, Martin Blumenstingl
In-Reply-To: <20180101204217.26165-1-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
The three-wire (H5) protocol is the only protocol which uses
HCI_UART_INIT_PENDING.
Unfortunately the benefits of using this flag are currently unknown. It
was added in commit 9f2aee848fe6 ("Bluetooth: Add delayed init sequence
support for UART controllers"). In my experiments (with the
"rtk_hciattach" tool - a customized version of hciattach for Realtek
chipsets) I started the tool before and after this patch while the
Bluetooth chipset was disabled (by pulling it's enable GPIO LOW). In
both cases hci0 was not created - thus HCI_UART_INIT_PENDING is not
required in that case.
Removing this code also has another benefit: hci_serdev.c does not
support the delayed initialization / registration. Thus the protocol
implementation (hci_h5) never receives any data with this check still
in place. For the H5 protocol this means that the initialization never
completes (because the sync response never arrives). Even if the
initialization would succeed later on the drivers would call
hci_uart_init_ready() which schedules the registration which is
currently not implemented by hci_serdev.c.
Removing the HCI_UART_INIT_PENDING check makes the code easier to read
and also fixes the initalization of devices (implemented with the serdev
library) which use the H5 protocol.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
drivers/bluetooth/hci_h5.c | 3 ---
drivers/bluetooth/hci_ldisc.c | 38 --------------------------------------
drivers/bluetooth/hci_serdev.c | 3 ---
drivers/bluetooth/hci_uart.h | 4 +---
4 files changed, 1 insertion(+), 47 deletions(-)
diff --git a/drivers/bluetooth/hci_h5.c b/drivers/bluetooth/hci_h5.c
index 6a8d0d06aba7..6cfc2f276250 100644
--- a/drivers/bluetooth/hci_h5.c
+++ b/drivers/bluetooth/hci_h5.c
@@ -210,8 +210,6 @@ static int h5_open(struct hci_uart *hu)
h5->tx_win = H5_TX_WIN_MAX;
- set_bit(HCI_UART_INIT_PENDING, &hu->hdev_flags);
-
/* Send initial sync request */
h5_link_control(hu, sync, sizeof(sync));
mod_timer(&h5->timer, jiffies + H5_SYNC_TIMEOUT);
@@ -316,7 +314,6 @@ static void h5_handle_internal_rx(struct hci_uart *hu)
h5->tx_win = (data[2] & 0x07);
BT_DBG("Three-wire init complete. tx_win %u", h5->tx_win);
h5->state = H5_ACTIVE;
- hci_uart_init_ready(hu);
return;
} else if (memcmp(data, sleep_req, 2) == 0) {
BT_DBG("Peer went to sleep");
diff --git a/drivers/bluetooth/hci_ldisc.c b/drivers/bluetooth/hci_ldisc.c
index c823914b3a80..5dd3e1bebfe4 100644
--- a/drivers/bluetooth/hci_ldisc.c
+++ b/drivers/bluetooth/hci_ldisc.c
@@ -195,39 +195,6 @@ static void hci_uart_write_work(struct work_struct *work)
clear_bit(HCI_UART_SENDING, &hu->tx_state);
}
-static void hci_uart_init_work(struct work_struct *work)
-{
- struct hci_uart *hu = container_of(work, struct hci_uart, init_ready);
- int err;
- struct hci_dev *hdev;
-
- if (!test_and_clear_bit(HCI_UART_INIT_PENDING, &hu->hdev_flags))
- return;
-
- err = hci_register_dev(hu->hdev);
- if (err < 0) {
- BT_ERR("Can't register HCI device");
- hdev = hu->hdev;
- hu->hdev = NULL;
- hci_free_dev(hdev);
- clear_bit(HCI_UART_PROTO_READY, &hu->flags);
- hu->proto->close(hu);
- return;
- }
-
- set_bit(HCI_UART_REGISTERED, &hu->flags);
-}
-
-int hci_uart_init_ready(struct hci_uart *hu)
-{
- if (!test_bit(HCI_UART_INIT_PENDING, &hu->hdev_flags))
- return -EALREADY;
-
- schedule_work(&hu->init_ready);
-
- return 0;
-}
-
/* ------- Interface to HCI layer ------ */
/* Initialize device */
static int hci_uart_open(struct hci_dev *hdev)
@@ -490,7 +457,6 @@ static int hci_uart_tty_open(struct tty_struct *tty)
hu->alignment = 1;
hu->padding = 0;
- INIT_WORK(&hu->init_ready, hci_uart_init_work);
INIT_WORK(&hu->write_work, hci_uart_write_work);
percpu_init_rwsem(&hu->proto_lock);
@@ -653,9 +619,6 @@ static int hci_uart_register_dev(struct hci_uart *hu)
else
hdev->dev_type = HCI_PRIMARY;
- if (test_bit(HCI_UART_INIT_PENDING, &hu->hdev_flags))
- return 0;
-
if (hci_register_dev(hdev) < 0) {
BT_ERR("Can't register HCI device");
hu->hdev = NULL;
@@ -699,7 +662,6 @@ static int hci_uart_set_flags(struct hci_uart *hu, unsigned long flags)
unsigned long valid_flags = BIT(HCI_UART_RAW_DEVICE) |
BIT(HCI_UART_RESET_ON_INIT) |
BIT(HCI_UART_CREATE_AMP) |
- BIT(HCI_UART_INIT_PENDING) |
BIT(HCI_UART_EXT_CONFIG) |
BIT(HCI_UART_VND_DETECT);
diff --git a/drivers/bluetooth/hci_serdev.c b/drivers/bluetooth/hci_serdev.c
index e0e6461b9200..fe67eb6d4278 100644
--- a/drivers/bluetooth/hci_serdev.c
+++ b/drivers/bluetooth/hci_serdev.c
@@ -333,9 +333,6 @@ int hci_uart_register_device(struct hci_uart *hu,
else
hdev->dev_type = HCI_PRIMARY;
- if (test_bit(HCI_UART_INIT_PENDING, &hu->hdev_flags))
- return 0;
-
if (hci_register_dev(hdev) < 0) {
BT_ERR("Can't register HCI device");
err = -ENODEV;
diff --git a/drivers/bluetooth/hci_uart.h b/drivers/bluetooth/hci_uart.h
index 66e8c68e4607..47e755ff4092 100644
--- a/drivers/bluetooth/hci_uart.h
+++ b/drivers/bluetooth/hci_uart.h
@@ -53,7 +53,7 @@
#define HCI_UART_RAW_DEVICE 0
#define HCI_UART_RESET_ON_INIT 1
#define HCI_UART_CREATE_AMP 2
-#define HCI_UART_INIT_PENDING 3
+/* 3 is unused - was HCI_UART_INIT_PENDING */
#define HCI_UART_EXT_CONFIG 4
#define HCI_UART_VND_DETECT 5
@@ -83,7 +83,6 @@ struct hci_uart {
unsigned long flags;
unsigned long hdev_flags;
- struct work_struct init_ready;
struct work_struct write_work;
const struct hci_uart_proto *proto;
@@ -115,7 +114,6 @@ int hci_uart_register_device(struct hci_uart *hu, const struct hci_uart_proto *p
void hci_uart_unregister_device(struct hci_uart *hu);
int hci_uart_tx_wakeup(struct hci_uart *hu);
-int hci_uart_init_ready(struct hci_uart *hu);
void hci_uart_set_baudrate(struct hci_uart *hu, unsigned int speed);
void hci_uart_set_flow_control(struct hci_uart *hu, bool enable);
void hci_uart_set_speeds(struct hci_uart *hu, unsigned int init_speed,
--
2.15.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [RFC v2 7/9] bluetooth: btrtl: load the config blob from devicetree when available
From: Martin Blumenstingl @ 2018-01-01 20:42 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-bluetooth-u79uwXL29TY76Z2rM5mHXA,
linux-serial-u79uwXL29TY76Z2rM5mHXA
Cc: mark.rutland-5wv7dgnIgG8, marcel-kz+m5ild9QBg9hUCZPvPmw,
gustavo-THi1TnShQwVAfugRpC6u6w,
johan.hedberg-Re5JQEeQqe8AvxtiuMwx3w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, jslaby-IBi9RG/b67k,
johan-DgEjT+Ai2ygdnm+yROfE0A,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Larry.Finger-tQ5ms3gMjBLk1uMJSBkQmQ, carlo-6IF/jdPJHihWk0Htik3J/w,
drake-6IF/jdPJHihWk0Htik3J/w, Martin Blumenstingl
In-Reply-To: <20180101204217.26165-1-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Some Realtek bluetooth devices need a "config" blob. The btrtl driver
currently only allows loading this config blob via the request_firmware
mechanism.
The UART Bluetooth chips use this config blob to specify the baudrate,
whether flow control is used and some other unknown bits. This means
that the config blob is board-specific - thus loading it via
request_firmware means that the rootfs is tied to a specific board.
The UART Bluetooth chips are implemented through serdev. This means
there is also a devicetree node which describes the Bluetooth chip.
Thus we can also load the blob from the devicetree node to keep the
filesystem independent of any board configuration data. In the future
this could be extended to support ACPI as well (in case that's needed).
Parse the devicetree node if it exists and obtain the config blob from
there. Otherwise fall back to using the "old" request_firmware
mechanism.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
drivers/bluetooth/btrtl.c | 43 +++++++++++++++++++++++++++++++++++++++++--
1 file changed, 41 insertions(+), 2 deletions(-)
diff --git a/drivers/bluetooth/btrtl.c b/drivers/bluetooth/btrtl.c
index 25e9743643f5..1494269cf4d7 100644
--- a/drivers/bluetooth/btrtl.c
+++ b/drivers/bluetooth/btrtl.c
@@ -18,6 +18,7 @@
#include <linux/module.h>
#include <linux/firmware.h>
#include <asm/unaligned.h>
+#include <linux/of.h>
#include <linux/usb.h>
#include <net/bluetooth/bluetooth.h>
@@ -379,6 +380,41 @@ void btrtl_free(struct btrtl_device_info *btrtl_dev)
}
EXPORT_SYMBOL_GPL(btrtl_free);
+static int rtl_load_config_from_dt(struct hci_dev *hdev,
+ struct btrtl_device_info *btrtl_dev)
+{
+ struct device_node *np = hdev->dev.parent->of_node;
+ int ret, config_len;
+
+ if (!of_device_is_available(np))
+ return -ENOENT;
+
+ if (!of_find_property(np, "realtek,config-data", NULL))
+ return -ENOENT;
+
+ config_len = of_property_count_u8_elems(np, "realtek,config-data");
+ if (config_len <= 0)
+ return -ENOENT;
+
+ btrtl_dev->cfg_data = kzalloc(config_len, GFP_KERNEL);
+ if (!btrtl_dev->cfg_data)
+ return -ENOMEM;
+
+ ret = of_property_read_u8_array(np, "realtek,config-data",
+ btrtl_dev->cfg_data, config_len);
+ if (ret) {
+ kfree(btrtl_dev->cfg_data);
+ return ret;
+ }
+
+ btrtl_dev->cfg_len = config_len;
+
+ bt_dev_dbg(hdev, "rtl: using config data with len %d from DT",
+ config_len);
+
+ return 0;
+}
+
struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev)
{
struct btrtl_device_info *btrtl_dev;
@@ -480,12 +516,15 @@ struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev)
goto err_free;
}
- if (cfg_name) {
+ /* try loading the config blob from device-tree first: */
+ ret = rtl_load_config_from_dt(hdev, btrtl_dev);
+ /* fall back to loading the config via request_firmware: */
+ if (ret && cfg_name) {
btrtl_dev->cfg_len = rtl_load_file(hdev, cfg_name,
&btrtl_dev->cfg_data);
if (cfg_needed && btrtl_dev->cfg_len <= 0) {
bt_dev_err(hdev,
- "mandatory config file %s not found\n",
+ "mandatory config blob not found in %s or DT\n",
cfg_name);
ret = btrtl_dev->fw_len;
goto err_free;
--
2.15.1
--
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^ permalink raw reply related
* [RFC v2 6/9] Bluetooth: btrtl: add support for the RTL8723BS and RTL8723DS chips
From: Martin Blumenstingl @ 2018-01-01 20:42 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-bluetooth-u79uwXL29TY76Z2rM5mHXA,
linux-serial-u79uwXL29TY76Z2rM5mHXA
Cc: mark.rutland-5wv7dgnIgG8, marcel-kz+m5ild9QBg9hUCZPvPmw,
gustavo-THi1TnShQwVAfugRpC6u6w,
johan.hedberg-Re5JQEeQqe8AvxtiuMwx3w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, jslaby-IBi9RG/b67k,
johan-DgEjT+Ai2ygdnm+yROfE0A,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Larry.Finger-tQ5ms3gMjBLk1uMJSBkQmQ, carlo-6IF/jdPJHihWk0Htik3J/w,
drake-6IF/jdPJHihWk0Htik3J/w, Martin Blumenstingl
In-Reply-To: <20180101204217.26165-1-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
The Realtek RTL8723BS and RTL8723DS chipsets are SDIO wifi chips. They
also contain a Bluetooth module which is connected via UART to the host.
Realtek's userspace initialization tool (rtk_hciattach) differentiates
these two via the HCI version and revision returned by the
HCI_OP_READ_LOCAL_VERSION command.
Additionally we apply these checks only the for UART devices. Everything
else is assumed to be a "RTL8723B" which was originally supported by the
driver (communicating via USB).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
drivers/bluetooth/btrtl.c | 32 ++++++++++++++++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/bluetooth/btrtl.c b/drivers/bluetooth/btrtl.c
index b6e8da4b73f8..25e9743643f5 100644
--- a/drivers/bluetooth/btrtl.c
+++ b/drivers/bluetooth/btrtl.c
@@ -418,9 +418,33 @@ struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev)
has_rom_version = false;
break;
case RTL_ROM_LMP_8723B:
- fw_name = "rtl_bt/rtl8723b_fw.bin";
- cfg_name = "rtl_bt/rtl8723b_config.bin";
+ /* all variants support reading the ROM version */
has_rom_version = true;
+
+ /*
+ * RTL8723 devices exist in different variants:
+ * - RTL8723BS (SDIO chip with UART Bluetooth)
+ * - RTL8723DS (SDIO chip with UART Bluetooth)
+ * - for backwards-compatibility everything else is assumed to
+ * be an RTL8723B communicating over USB
+ *
+ * Only UART devices really need the config because that
+ * contains the UART speed / flow control settings.
+ */
+ if (hdev->bus == HCI_UART && resp->hci_ver == 6 &&
+ le16_to_cpu(resp->hci_rev) == 0xb) {
+ fw_name = "rtl_bt/rtl8723bs_fw.bin";
+ cfg_name = "rtl_bt/rtl8723bs_config.bin";
+ cfg_needed = true;
+ } else if (hdev->bus == HCI_UART && resp->hci_ver == 8 &&
+ le16_to_cpu(resp->hci_rev) == 0xd) {
+ fw_name = "rtl_bt/rtl8723ds_fw.bin";
+ cfg_name = "rtl_bt/rtl872ds_config.bin";
+ cfg_needed = true;
+ } else {
+ fw_name = "rtl_bt/rtl8723b_fw.bin";
+ cfg_name = "rtl_bt/rtl8723b_config.bin";
+ }
break;
case RTL_ROM_LMP_8821A:
fw_name = "rtl_bt/rtl8821a_fw.bin";
@@ -637,6 +661,10 @@ MODULE_LICENSE("GPL");
MODULE_FIRMWARE("rtl_bt/rtl8723a_fw.bin");
MODULE_FIRMWARE("rtl_bt/rtl8723b_fw.bin");
MODULE_FIRMWARE("rtl_bt/rtl8723b_config.bin");
+MODULE_FIRMWARE("rtl_bt/rtl8723bs_fw.bin");
+MODULE_FIRMWARE("rtl_bt/rtl8723bs_config.bin");
+MODULE_FIRMWARE("rtl_bt/rtl8723ds_fw.bin");
+MODULE_FIRMWARE("rtl_bt/rtl8723ds_config.bin");
MODULE_FIRMWARE("rtl_bt/rtl8761a_fw.bin");
MODULE_FIRMWARE("rtl_bt/rtl8761a_config.bin");
MODULE_FIRMWARE("rtl_bt/rtl8821a_fw.bin");
--
2.15.1
^ permalink raw reply related
* [RFC v2 5/9] Bluetooth: btrtl: add support for retrieving the UART settings
From: Martin Blumenstingl @ 2018-01-01 20:42 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-bluetooth-u79uwXL29TY76Z2rM5mHXA,
linux-serial-u79uwXL29TY76Z2rM5mHXA
Cc: mark.rutland-5wv7dgnIgG8, marcel-kz+m5ild9QBg9hUCZPvPmw,
gustavo-THi1TnShQwVAfugRpC6u6w,
johan.hedberg-Re5JQEeQqe8AvxtiuMwx3w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, jslaby-IBi9RG/b67k,
johan-DgEjT+Ai2ygdnm+yROfE0A,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Larry.Finger-tQ5ms3gMjBLk1uMJSBkQmQ, carlo-6IF/jdPJHihWk0Htik3J/w,
drake-6IF/jdPJHihWk0Htik3J/w, Martin Blumenstingl
In-Reply-To: <20180101204217.26165-1-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
The UART settings are embedded in the config blob. This has to be parsed
to successfully initialize the Bluetooth part of the RTL8723BS (which is
an SDIO chip, but the Bluetooth part is connected via UART).
The Realtek "rtl8723bs_bt" and "rtl8723ds_bt" userspace Bluetooth UART
initialization tools (rtk_hciattach) use the following sequence:
- send H5 sync pattern (already supported by hci_h5)
- get LMP version (already supported by btrtl)
- get ROM version (already supported by btrtl)
- load the firmware and config for the current chipset (already
supported by btrtl)
- read UART settings from the config blob (part of this patch)
- send UART settings via a vendor command to the device (which changes
the baudrate of the device and enables or disables flow control
depending on the config)
- change the baudrate and flow control settings on the host
- send the firmware and config blob to the device (already supported by
btrtl)
Sending the last firmware and config blob download command
(rtl_download_cmd) fails if the UART settings are not updated
beforehand. This is presumably because the device applies the config
right after the firmware and config blob download - which means that at
this point the host is using different UART settings than the device
(which will obviously result in non-working communication).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
drivers/bluetooth/btrtl.c | 112 ++++++++++++++++++++++++++++++++++++++++++++++
drivers/bluetooth/btrtl.h | 25 +++++++++++
2 files changed, 137 insertions(+)
diff --git a/drivers/bluetooth/btrtl.c b/drivers/bluetooth/btrtl.c
index 300ee15875e6..b6e8da4b73f8 100644
--- a/drivers/bluetooth/btrtl.c
+++ b/drivers/bluetooth/btrtl.c
@@ -34,6 +34,7 @@
#define RTL_ROM_LMP_8821A 0x8821
#define RTL_ROM_LMP_8761A 0x8761
#define RTL_ROM_LMP_8822B 0x8822
+#define RTL_CONFIG_MAGIC 0x8723ab55
struct btrtl_device_info {
u16 lmp_subver;
@@ -518,6 +519,117 @@ int btrtl_setup_realtek(struct hci_dev *hdev)
}
EXPORT_SYMBOL_GPL(btrtl_setup_realtek);
+unsigned int btrtl_convert_baudrate(u32 device_baudrate)
+{
+ switch (device_baudrate) {
+ case 0x0252a00a:
+ return 230400;
+
+ case 0x05f75004:
+ return 921600;
+
+ case 0x00005004:
+ return 1000000;
+
+ case 0x04928002:
+ case 0x01128002:
+ return 1500000;
+
+ case 0x00005002:
+ return 2000000;
+
+ case 0x0000b001:
+ return 2500000;
+
+ case 0x04928001:
+ return 3000000;
+
+ case 0x052a6001:
+ return 3500000;
+
+ case 0x00005001:
+ return 4000000;
+
+ case 0x0252c014:
+ default:
+ return 115200;
+ }
+}
+
+int btrtl_get_uart_settings(struct hci_dev *hdev,
+ struct btrtl_device_info *btrtl_dev,
+ unsigned int *controller_baudrate,
+ u32 *device_baudrate, bool *flow_control)
+{
+ struct rtl_vendor_config *config;
+ struct rtl_vendor_config_entry *entry;
+ int i, total_data_len;
+ bool found = false;
+
+ total_data_len = btrtl_dev->cfg_len - sizeof(*config);
+ if (total_data_len <= 0) {
+ bt_dev_warn(hdev, "rtl: no config loaded");
+ return -EINVAL;
+ }
+
+ config = (struct rtl_vendor_config *)btrtl_dev->cfg_data;
+ if (le32_to_cpu(config->signature) != RTL_CONFIG_MAGIC) {
+ bt_dev_err(hdev, "rtl: invalid config magic");
+ return -EINVAL;
+ }
+
+ if (total_data_len < le16_to_cpu(config->total_len)) {
+ bt_dev_err(hdev, "rtl: config is too short");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < total_data_len; ) {
+ entry = ((void *)config->entry) + i;
+
+ switch (le16_to_cpu(entry->offset)) {
+ case 0xc:
+ if (entry->len < sizeof(*device_baudrate)) {
+ bt_dev_err(hdev,
+ "rtl: invalid UART config entry");
+ return -EINVAL;
+ }
+
+ *device_baudrate = get_unaligned_le32(entry->data);
+ *controller_baudrate = btrtl_convert_baudrate(
+ *device_baudrate);
+
+ if (entry->len >= 13)
+ *flow_control = !!(entry->data[12] & BIT(2));
+ else
+ *flow_control = false;
+
+ found = true;
+ break;
+
+ default:
+ bt_dev_dbg(hdev,
+ "rtl: skipping config entry 0x%x (len %u)",
+ le16_to_cpu(entry->offset), entry->len);
+ break;
+ };
+
+ i += sizeof(*entry) + entry->len;
+ }
+
+ if (!found) {
+ bt_dev_err(hdev, "rtl: no UART config entry found");
+ return -ENOENT;
+ }
+
+ bt_dev_dbg(hdev, "rtl: device baudrate = 0x%08x", *device_baudrate);
+ bt_dev_dbg(hdev, "rtl: controller baudrate = %u",
+ *controller_baudrate);
+ bt_dev_dbg(hdev, "rtl: flow control %d", *flow_control);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(btrtl_get_uart_settings);
+
MODULE_AUTHOR("Daniel Drake <drake-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>");
MODULE_DESCRIPTION("Bluetooth support for Realtek devices ver " VERSION);
MODULE_VERSION(VERSION);
diff --git a/drivers/bluetooth/btrtl.h b/drivers/bluetooth/btrtl.h
index 21c28dcbe5e0..2e7856fa5ac7 100644
--- a/drivers/bluetooth/btrtl.h
+++ b/drivers/bluetooth/btrtl.h
@@ -40,6 +40,18 @@ struct rtl_epatch_header {
__le16 num_patches;
} __packed;
+struct rtl_vendor_config_entry {
+ __le16 offset;
+ __u8 len;
+ __u8 data[0];
+} __packed;
+
+struct rtl_vendor_config {
+ __le32 signature;
+ __le16 total_len;
+ struct rtl_vendor_config_entry entry[0];
+} __packed;
+
#if IS_ENABLED(CONFIG_BT_RTL)
struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev);
@@ -47,6 +59,10 @@ void btrtl_free(struct btrtl_device_info *btrtl_dev);
int btrtl_download_firmware(struct hci_dev *hdev,
struct btrtl_device_info *btrtl_dev);
int btrtl_setup_realtek(struct hci_dev *hdev);
+int btrtl_get_uart_settings(struct hci_dev *hdev,
+ struct btrtl_device_info *btrtl_dev,
+ unsigned int *controller_baudrate,
+ u32 *device_baudrate, bool *flow_control);
#else
@@ -70,4 +86,13 @@ static inline int btrtl_setup_realtek(struct hci_dev *hdev)
return -EOPNOTSUPP;
}
+static inline int btrtl_get_uart_settings(struct hci_dev *hdev,
+ struct btrtl_device_info *btrtl_dev,
+ unsigned int *controller_baudrate,
+ u32 *device_baudrate,
+ bool *flow_control)
+{
+ return -ENOENT;
+}
+
#endif
--
2.15.1
^ permalink raw reply related
* [RFC v2 4/9] Bluetooth: btrtl: split the device initialization into smaller parts
From: Martin Blumenstingl @ 2018-01-01 20:42 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-bluetooth-u79uwXL29TY76Z2rM5mHXA,
linux-serial-u79uwXL29TY76Z2rM5mHXA
Cc: mark.rutland-5wv7dgnIgG8, marcel-kz+m5ild9QBg9hUCZPvPmw,
gustavo-THi1TnShQwVAfugRpC6u6w,
johan.hedberg-Re5JQEeQqe8AvxtiuMwx3w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, jslaby-IBi9RG/b67k,
johan-DgEjT+Ai2ygdnm+yROfE0A,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Larry.Finger-tQ5ms3gMjBLk1uMJSBkQmQ, carlo-6IF/jdPJHihWk0Htik3J/w,
drake-6IF/jdPJHihWk0Htik3J/w, Martin Blumenstingl
In-Reply-To: <20180101204217.26165-1-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
This prepares the btrtl code so it can be used to initialize Bluetooth
modules connected via UART (these are found for example on the RTL8723BS
and RTL8723DS SDIO chips, which come with an embedded UART Bluetooth
module).
The Realtek "rtl8723bs_bt" and "rtl8723ds_bt" userspace Bluetooth UART
initialization tools (rtk_hciattach) use the following sequence:
1) send H5 sync pattern (already supported by hci_h5)
2) get LMP version (already supported by btrtl)
3) get ROM version (already supported by btrtl)
4) load the firmware and config for the current chipset (already
supported by btrtl)
5) read UART settings from the config blob (currently not supported)
6) send UART settings via a vendor command to the device (which changes
the baudrate of the device and enables or disables flow control
depending on the config)
7) change the baudrate and flow control settings on the host
8) send the firmware and config blob to the device (already supported by
btrtl)
The main reason why the initialization has to be split is step #7. This
requires changes to the underlying "bus", which should be kept outside
of the "generic" btrtl driver.
The idea for this split is borrowed from the btbcm driver but adjusted
where needed (the btrtl driver for example needs two blobs: firmware and
config, while the btbcm only needs one).
This also prepares the code for step #5 (parsing the config blob) by
centralizing the code which loads the firmware and config blobs and
storing the result in the new struct btrtl_device_info.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
drivers/bluetooth/btrtl.c | 273 +++++++++++++++++++++++++++-------------------
drivers/bluetooth/btrtl.h | 21 ++++
2 files changed, 180 insertions(+), 114 deletions(-)
diff --git a/drivers/bluetooth/btrtl.c b/drivers/bluetooth/btrtl.c
index 3e5296287808..300ee15875e6 100644
--- a/drivers/bluetooth/btrtl.c
+++ b/drivers/bluetooth/btrtl.c
@@ -35,6 +35,15 @@
#define RTL_ROM_LMP_8761A 0x8761
#define RTL_ROM_LMP_8822B 0x8822
+struct btrtl_device_info {
+ u16 lmp_subver;
+ u8 rom_version;
+ u8 *fw_data;
+ int fw_len;
+ u8 *cfg_data;
+ int cfg_len;
+};
+
static int rtl_read_rom_version(struct hci_dev *hdev, u8 *version)
{
struct rtl_rom_version_evt *rom_version;
@@ -64,16 +73,16 @@ static int rtl_read_rom_version(struct hci_dev *hdev, u8 *version)
return 0;
}
-static int rtl8723b_parse_firmware(struct hci_dev *hdev, u16 lmp_subver,
- const struct firmware *fw,
+static int rtl8723b_parse_firmware(struct hci_dev *hdev,
+ struct btrtl_device_info *btrtl_dev,
unsigned char **_buf)
{
const u8 extension_sig[] = { 0x51, 0x04, 0xfd, 0x77 };
struct rtl_epatch_header *epatch_info;
unsigned char *buf;
- int i, ret, len;
+ int i, len;
size_t min_size;
- u8 opcode, length, data, rom_version = 0;
+ u8 opcode, length, data;
int project_id = -1;
const unsigned char *fwptr, *chip_id_base;
const unsigned char *patch_length_base, *patch_offset_base;
@@ -90,15 +99,11 @@ static int rtl8723b_parse_firmware(struct hci_dev *hdev, u16 lmp_subver,
{ RTL_ROM_LMP_8822B, 8 },
};
- ret = rtl_read_rom_version(hdev, &rom_version);
- if (ret)
- return ret;
-
min_size = sizeof(struct rtl_epatch_header) + sizeof(extension_sig) + 3;
- if (fw->size < min_size)
+ if (btrtl_dev->fw_len < min_size)
return -EINVAL;
- fwptr = fw->data + fw->size - sizeof(extension_sig);
+ fwptr = btrtl_dev->fw_data + btrtl_dev->fw_len - sizeof(extension_sig);
if (memcmp(fwptr, extension_sig, sizeof(extension_sig)) != 0) {
BT_ERR("%s: extension section signature mismatch", hdev->name);
return -EINVAL;
@@ -110,7 +115,7 @@ static int rtl8723b_parse_firmware(struct hci_dev *hdev, u16 lmp_subver,
* Once we have that, we double-check that that project_id is suitable
* for the hardware we are working with.
*/
- while (fwptr >= fw->data + (sizeof(struct rtl_epatch_header) + 3)) {
+ while (fwptr >= btrtl_dev->fw_data + (sizeof(*epatch_info) + 3)) {
opcode = *--fwptr;
length = *--fwptr;
data = *--fwptr;
@@ -150,13 +155,14 @@ static int rtl8723b_parse_firmware(struct hci_dev *hdev, u16 lmp_subver,
return -EINVAL;
}
- if (lmp_subver != project_id_to_lmp_subver[i].lmp_subver) {
+ if (btrtl_dev->lmp_subver != project_id_to_lmp_subver[i].lmp_subver) {
BT_ERR("%s: firmware is for %x but this is a %x", hdev->name,
- project_id_to_lmp_subver[i].lmp_subver, lmp_subver);
+ project_id_to_lmp_subver[i].lmp_subver,
+ btrtl_dev->lmp_subver);
return -EINVAL;
}
- epatch_info = (struct rtl_epatch_header *)fw->data;
+ epatch_info = (struct rtl_epatch_header *)btrtl_dev->fw_data;
if (memcmp(epatch_info->signature, RTL_EPATCH_SIGNATURE, 8) != 0) {
BT_ERR("%s: bad EPATCH signature", hdev->name);
return -EINVAL;
@@ -173,16 +179,16 @@ static int rtl8723b_parse_firmware(struct hci_dev *hdev, u16 lmp_subver,
* Find the right patch for this chip.
*/
min_size += 8 * num_patches;
- if (fw->size < min_size)
+ if (btrtl_dev->fw_len < min_size)
return -EINVAL;
- chip_id_base = fw->data + sizeof(struct rtl_epatch_header);
+ chip_id_base = btrtl_dev->fw_data + sizeof(struct rtl_epatch_header);
patch_length_base = chip_id_base + (sizeof(u16) * num_patches);
patch_offset_base = patch_length_base + (sizeof(u16) * num_patches);
for (i = 0; i < num_patches; i++) {
u16 chip_id = get_unaligned_le16(chip_id_base +
(i * sizeof(u16)));
- if (chip_id == rom_version + 1) {
+ if (chip_id == btrtl_dev->rom_version + 1) {
patch_length = get_unaligned_le16(patch_length_base +
(i * sizeof(u16)));
patch_offset = get_unaligned_le32(patch_offset_base +
@@ -193,20 +199,21 @@ static int rtl8723b_parse_firmware(struct hci_dev *hdev, u16 lmp_subver,
if (!patch_offset) {
BT_ERR("%s: didn't find patch for chip id %d",
- hdev->name, rom_version);
+ hdev->name, btrtl_dev->rom_version);
return -EINVAL;
}
BT_DBG("length=%x offset=%x index %d", patch_length, patch_offset, i);
min_size = patch_offset + patch_length;
- if (fw->size < min_size)
+ if (btrtl_dev->fw_len < min_size)
return -EINVAL;
/* Copy the firmware into a new buffer and write the version at
* the end.
*/
len = patch_length;
- buf = kmemdup(fw->data + patch_offset, patch_length, GFP_KERNEL);
+ buf = kmemdup(btrtl_dev->fw_data + patch_offset, patch_length,
+ GFP_KERNEL);
if (!buf)
return -ENOMEM;
@@ -268,7 +275,7 @@ static int rtl_download_firmware(struct hci_dev *hdev,
return ret;
}
-static int rtl_load_config(struct hci_dev *hdev, const char *name, u8 **buff)
+static int rtl_load_file(struct hci_dev *hdev, const char *name, u8 **buff)
{
const struct firmware *fw;
int ret;
@@ -287,95 +294,37 @@ static int rtl_load_config(struct hci_dev *hdev, const char *name, u8 **buff)
return ret;
}
-static int btrtl_setup_rtl8723a(struct hci_dev *hdev)
+static int btrtl_setup_rtl8723a(struct hci_dev *hdev,
+ struct btrtl_device_info *btrtl_dev)
{
- const struct firmware *fw;
- int ret;
-
- bt_dev_info(hdev, "rtl: loading rtl_bt/rtl8723a_fw.bin");
- ret = request_firmware(&fw, "rtl_bt/rtl8723a_fw.bin", &hdev->dev);
- if (ret < 0) {
- BT_ERR("%s: Failed to load rtl_bt/rtl8723a_fw.bin", hdev->name);
- return ret;
- }
-
- if (fw->size < 8) {
- ret = -EINVAL;
- goto out;
- }
+ if (btrtl_dev->fw_len < 8)
+ return -EINVAL;
/* Check that the firmware doesn't have the epatch signature
* (which is only for RTL8723B and newer).
*/
- if (!memcmp(fw->data, RTL_EPATCH_SIGNATURE, 8)) {
+ if (!memcmp(btrtl_dev->fw_data, RTL_EPATCH_SIGNATURE, 8)) {
BT_ERR("%s: unexpected EPATCH signature!", hdev->name);
- ret = -EINVAL;
- goto out;
+ return -EINVAL;
}
- ret = rtl_download_firmware(hdev, fw->data, fw->size);
-
-out:
- release_firmware(fw);
- return ret;
+ return rtl_download_firmware(hdev, btrtl_dev->fw_data,
+ btrtl_dev->fw_len);
}
-static int btrtl_setup_rtl8723b(struct hci_dev *hdev, u16 lmp_subver,
- const char *fw_name)
+static int btrtl_setup_rtl8723b(struct hci_dev *hdev,
+ struct btrtl_device_info *btrtl_dev)
{
unsigned char *fw_data = NULL;
- const struct firmware *fw;
int ret;
- int cfg_sz;
- u8 *cfg_buff = NULL;
u8 *tbuff;
- char *cfg_name = NULL;
- bool config_needed = false;
- switch (lmp_subver) {
- case RTL_ROM_LMP_8723B:
- cfg_name = "rtl_bt/rtl8723b_config.bin";
- break;
- case RTL_ROM_LMP_8821A:
- cfg_name = "rtl_bt/rtl8821a_config.bin";
- break;
- case RTL_ROM_LMP_8761A:
- cfg_name = "rtl_bt/rtl8761a_config.bin";
- break;
- case RTL_ROM_LMP_8822B:
- cfg_name = "rtl_bt/rtl8822b_config.bin";
- config_needed = true;
- break;
- default:
- BT_ERR("%s: rtl: no config according to lmp_subver %04x",
- hdev->name, lmp_subver);
- break;
- }
-
- if (cfg_name) {
- cfg_sz = rtl_load_config(hdev, cfg_name, &cfg_buff);
- if (cfg_sz < 0) {
- cfg_sz = 0;
- if (config_needed)
- BT_ERR("Necessary config file %s not found\n",
- cfg_name);
- }
- } else
- cfg_sz = 0;
-
- bt_dev_info(hdev, "rtl: loading %s", fw_name);
- ret = request_firmware(&fw, fw_name, &hdev->dev);
- if (ret < 0) {
- BT_ERR("%s: Failed to load %s", hdev->name, fw_name);
- goto err_req_fw;
- }
-
- ret = rtl8723b_parse_firmware(hdev, lmp_subver, fw, &fw_data);
+ ret = rtl8723b_parse_firmware(hdev, btrtl_dev, &fw_data);
if (ret < 0)
goto out;
- if (cfg_sz) {
- tbuff = kzalloc(ret + cfg_sz, GFP_KERNEL);
+ if (btrtl_dev->cfg_len > 0) {
+ tbuff = kzalloc(ret + btrtl_dev->cfg_len, GFP_KERNEL);
if (!tbuff) {
ret = -ENOMEM;
goto out;
@@ -384,22 +333,18 @@ static int btrtl_setup_rtl8723b(struct hci_dev *hdev, u16 lmp_subver,
memcpy(tbuff, fw_data, ret);
kfree(fw_data);
- memcpy(tbuff + ret, cfg_buff, cfg_sz);
- ret += cfg_sz;
+ memcpy(tbuff + ret, btrtl_dev->cfg_data, btrtl_dev->cfg_len);
+ ret += btrtl_dev->cfg_len;
fw_data = tbuff;
}
- bt_dev_info(hdev, "cfg_sz %d, total size %d", cfg_sz, ret);
+ bt_dev_info(hdev, "cfg_sz %d, total size %d", btrtl_dev->cfg_len, ret);
ret = rtl_download_firmware(hdev, fw_data, ret);
out:
- release_firmware(fw);
kfree(fw_data);
-err_req_fw:
- if (cfg_sz)
- kfree(cfg_buff);
return ret;
}
@@ -425,15 +370,34 @@ static struct sk_buff *btrtl_read_local_version(struct hci_dev *hdev)
return skb;
}
-int btrtl_setup_realtek(struct hci_dev *hdev)
+void btrtl_free(struct btrtl_device_info *btrtl_dev)
{
+ kfree(btrtl_dev->fw_data);
+ kfree(btrtl_dev->cfg_data);
+ kfree(btrtl_dev);
+}
+EXPORT_SYMBOL_GPL(btrtl_free);
+
+struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev)
+{
+ struct btrtl_device_info *btrtl_dev;
struct sk_buff *skb;
struct hci_rp_read_local_version *resp;
- u16 lmp_subver;
+ bool cfg_needed = false, has_rom_version;
+ const char *cfg_name, *fw_name;
+ int ret;
+
+ btrtl_dev = kzalloc(sizeof(*btrtl_dev), GFP_KERNEL);
+ if (!btrtl_dev) {
+ ret = -ENOMEM;
+ goto err_alloc;
+ }
skb = btrtl_read_local_version(hdev);
- if (IS_ERR(skb))
- return -PTR_ERR(skb);
+ if (IS_ERR(skb)) {
+ ret = -PTR_ERR(skb);
+ goto err_free;
+ }
resp = (struct hci_rp_read_local_version *)skb->data;
bt_dev_info(hdev, "rtl: examining hci_ver=%02x hci_rev=%04x "
@@ -441,36 +405,117 @@ int btrtl_setup_realtek(struct hci_dev *hdev)
resp->hci_ver, resp->hci_rev,
resp->lmp_ver, resp->lmp_subver);
- lmp_subver = le16_to_cpu(resp->lmp_subver);
+ btrtl_dev->lmp_subver = le16_to_cpu(resp->lmp_subver);
+
kfree_skb(skb);
+ switch (btrtl_dev->lmp_subver) {
+ case RTL_ROM_LMP_8723A:
+ case RTL_ROM_LMP_3499:
+ fw_name = "rtl_bt/rtl8723a_fw.bin";
+ cfg_name = NULL;
+ has_rom_version = false;
+ break;
+ case RTL_ROM_LMP_8723B:
+ fw_name = "rtl_bt/rtl8723b_fw.bin";
+ cfg_name = "rtl_bt/rtl8723b_config.bin";
+ has_rom_version = true;
+ break;
+ case RTL_ROM_LMP_8821A:
+ fw_name = "rtl_bt/rtl8821a_fw.bin";
+ cfg_name = "rtl_bt/rtl8821a_config.bin";
+ has_rom_version = true;
+ break;
+ case RTL_ROM_LMP_8761A:
+ fw_name = "rtl_bt/rtl8761a_fw.bin";
+ cfg_name = "rtl_bt/rtl8761a_config.bin";
+ has_rom_version = true;
+ break;
+ case RTL_ROM_LMP_8822B:
+ fw_name = "rtl_bt/rtl8822b_fw.bin";
+ cfg_name = "rtl_bt/rtl8822b_config.bin";
+ has_rom_version = true;
+ cfg_needed = true;
+ break;
+ default:
+ bt_dev_info(hdev, "rtl: assuming no firmware upload needed");
+ return btrtl_dev;
+ }
+
+ if (has_rom_version) {
+ ret = rtl_read_rom_version(hdev, &btrtl_dev->rom_version);
+ if (ret)
+ goto err_free;
+ }
+
+ btrtl_dev->fw_len = rtl_load_file(hdev, fw_name, &btrtl_dev->fw_data);
+ if (btrtl_dev->fw_len < 0) {
+ bt_dev_err(hdev, "firmware file %s not found\n", fw_name);
+ ret = btrtl_dev->fw_len;
+ goto err_free;
+ }
+
+ if (cfg_name) {
+ btrtl_dev->cfg_len = rtl_load_file(hdev, cfg_name,
+ &btrtl_dev->cfg_data);
+ if (cfg_needed && btrtl_dev->cfg_len <= 0) {
+ bt_dev_err(hdev,
+ "mandatory config file %s not found\n",
+ cfg_name);
+ ret = btrtl_dev->fw_len;
+ goto err_free;
+ }
+ }
+
+ return btrtl_dev;
+
+err_free:
+ btrtl_free(btrtl_dev);
+err_alloc:
+ return ERR_PTR(ret);
+}
+EXPORT_SYMBOL_GPL(btrtl_initialize);
+
+int btrtl_download_firmware(struct hci_dev *hdev,
+ struct btrtl_device_info *btrtl_dev)
+{
/* Match a set of subver values that correspond to stock firmware,
* which is not compatible with standard btusb.
* If matched, upload an alternative firmware that does conform to
* standard btusb. Once that firmware is uploaded, the subver changes
* to a different value.
*/
- switch (lmp_subver) {
+ switch (btrtl_dev->lmp_subver) {
case RTL_ROM_LMP_8723A:
case RTL_ROM_LMP_3499:
- return btrtl_setup_rtl8723a(hdev);
+ return btrtl_setup_rtl8723a(hdev, btrtl_dev);
case RTL_ROM_LMP_8723B:
- return btrtl_setup_rtl8723b(hdev, lmp_subver,
- "rtl_bt/rtl8723b_fw.bin");
case RTL_ROM_LMP_8821A:
- return btrtl_setup_rtl8723b(hdev, lmp_subver,
- "rtl_bt/rtl8821a_fw.bin");
case RTL_ROM_LMP_8761A:
- return btrtl_setup_rtl8723b(hdev, lmp_subver,
- "rtl_bt/rtl8761a_fw.bin");
case RTL_ROM_LMP_8822B:
- return btrtl_setup_rtl8723b(hdev, lmp_subver,
- "rtl_bt/rtl8822b_fw.bin");
+ return btrtl_setup_rtl8723b(hdev, btrtl_dev);
default:
bt_dev_info(hdev, "rtl: assuming no firmware upload needed");
return 0;
}
}
+EXPORT_SYMBOL_GPL(btrtl_download_firmware);
+
+int btrtl_setup_realtek(struct hci_dev *hdev)
+{
+ struct btrtl_device_info *btrtl_dev;
+ int ret;
+
+ btrtl_dev = btrtl_initialize(hdev);
+ if (IS_ERR(btrtl_dev))
+ return PTR_ERR(btrtl_dev);
+
+ ret = btrtl_download_firmware(hdev, btrtl_dev);
+
+ btrtl_free(btrtl_dev);
+
+ return ret;
+}
EXPORT_SYMBOL_GPL(btrtl_setup_realtek);
MODULE_AUTHOR("Daniel Drake <drake-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>");
diff --git a/drivers/bluetooth/btrtl.h b/drivers/bluetooth/btrtl.h
index 38ffe4890cd1..21c28dcbe5e0 100644
--- a/drivers/bluetooth/btrtl.h
+++ b/drivers/bluetooth/btrtl.h
@@ -17,6 +17,8 @@
#define RTL_FRAG_LEN 252
+struct btrtl_device_info;
+
struct rtl_download_cmd {
__u8 index;
__u8 data[RTL_FRAG_LEN];
@@ -40,10 +42,29 @@ struct rtl_epatch_header {
#if IS_ENABLED(CONFIG_BT_RTL)
+struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev);
+void btrtl_free(struct btrtl_device_info *btrtl_dev);
+int btrtl_download_firmware(struct hci_dev *hdev,
+ struct btrtl_device_info *btrtl_dev);
int btrtl_setup_realtek(struct hci_dev *hdev);
#else
+static inline struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev)
+{
+ return ERR_PTR(-EOPNOTSUPP);
+}
+
+static inline void btrtl_free(struct btrtl_device_info *btrtl_dev)
+{
+}
+
+static inline int btrtl_download_firmware(struct hci_dev *hdev,
+ struct btrtl_device_info *btrtl_dev)
+{
+ return -EOPNOTSUPP;
+}
+
static inline int btrtl_setup_realtek(struct hci_dev *hdev)
{
return -EOPNOTSUPP;
--
2.15.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply related
* [RFC v2 3/9] Bluetooth: btrtl: add MODULE_FIRMWARE declarations
From: Martin Blumenstingl @ 2018-01-01 20:42 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-bluetooth-u79uwXL29TY76Z2rM5mHXA,
linux-serial-u79uwXL29TY76Z2rM5mHXA
Cc: mark.rutland-5wv7dgnIgG8, marcel-kz+m5ild9QBg9hUCZPvPmw,
gustavo-THi1TnShQwVAfugRpC6u6w,
johan.hedberg-Re5JQEeQqe8AvxtiuMwx3w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, jslaby-IBi9RG/b67k,
johan-DgEjT+Ai2ygdnm+yROfE0A,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Larry.Finger-tQ5ms3gMjBLk1uMJSBkQmQ, carlo-6IF/jdPJHihWk0Htik3J/w,
drake-6IF/jdPJHihWk0Htik3J/w, Martin Blumenstingl
In-Reply-To: <20180101204217.26165-1-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
This makes the firmware names show up in modinfo.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
drivers/bluetooth/btrtl.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/bluetooth/btrtl.c b/drivers/bluetooth/btrtl.c
index 6e2ad748abba..3e5296287808 100644
--- a/drivers/bluetooth/btrtl.c
+++ b/drivers/bluetooth/btrtl.c
@@ -477,3 +477,12 @@ MODULE_AUTHOR("Daniel Drake <drake-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>");
MODULE_DESCRIPTION("Bluetooth support for Realtek devices ver " VERSION);
MODULE_VERSION(VERSION);
MODULE_LICENSE("GPL");
+MODULE_FIRMWARE("rtl_bt/rtl8723a_fw.bin");
+MODULE_FIRMWARE("rtl_bt/rtl8723b_fw.bin");
+MODULE_FIRMWARE("rtl_bt/rtl8723b_config.bin");
+MODULE_FIRMWARE("rtl_bt/rtl8761a_fw.bin");
+MODULE_FIRMWARE("rtl_bt/rtl8761a_config.bin");
+MODULE_FIRMWARE("rtl_bt/rtl8821a_fw.bin");
+MODULE_FIRMWARE("rtl_bt/rtl8821a_config.bin");
+MODULE_FIRMWARE("rtl_bt/rtl8822b_fw.bin");
+MODULE_FIRMWARE("rtl_bt/rtl8822b_config.bin");
--
2.15.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [RFC v2 2/9] dt-bindings: net: bluetooth: add support for Realtek Bluetooth chips
From: Martin Blumenstingl @ 2018-01-01 20:42 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-bluetooth-u79uwXL29TY76Z2rM5mHXA,
linux-serial-u79uwXL29TY76Z2rM5mHXA
Cc: mark.rutland-5wv7dgnIgG8, marcel-kz+m5ild9QBg9hUCZPvPmw,
gustavo-THi1TnShQwVAfugRpC6u6w,
johan.hedberg-Re5JQEeQqe8AvxtiuMwx3w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, jslaby-IBi9RG/b67k,
johan-DgEjT+Ai2ygdnm+yROfE0A,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Larry.Finger-tQ5ms3gMjBLk1uMJSBkQmQ, carlo-6IF/jdPJHihWk0Htik3J/w,
drake-6IF/jdPJHihWk0Htik3J/w, Martin Blumenstingl
In-Reply-To: <20180101204217.26165-1-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
This adds the documentation for Bluetooth functionality of the Realtek
RTL8723BS and RTL8723DS.
Both are SDIO wifi chips with an additional Bluetooth module which is
connected via UART to the host.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
.../devicetree/bindings/net/realtek-bluetooth.txt | 41 ++++++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/realtek-bluetooth.txt
diff --git a/Documentation/devicetree/bindings/net/realtek-bluetooth.txt b/Documentation/devicetree/bindings/net/realtek-bluetooth.txt
new file mode 100644
index 000000000000..1491329c4cd1
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/realtek-bluetooth.txt
@@ -0,0 +1,41 @@
+Realtek Bluetooth Chips
+-----------------------
+
+This documents the binding structure and common properties for serial
+attached Realtek devices.
+
+Serial attached Realtek devices shall be a child node of the host UART
+device the slave device is attached to. See ../serial/slave-device.txt
+for more information
+
+Required properties:
+- compatible: should contain one of the following:
+ * "realtek,rtl8723bs-bluetooth"
+ * "realtek,rtl8723ds-bluetooth"
+
+Optional properties:
+- realtek,config-data: Bluetooth chipset configuration data which is
+ needed for communication (it typically contains
+ board specific settings like the baudrate and
+ whether flow-control is used).
+ This is an array of u8 values.
+- enable-gpios: GPIO specifier, used to enable/disable the BT module
+- reset-gpios: GPIO specifier, used to reset the BT module
+
+
+Example:
+
+&uart {
+ ...
+
+ bluetooth {
+ compatible = "realtek,rtl8723bs-bluetooth";
+ enable-gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
+ realtek,config-data = /bits/ 8 <
+ 0x55 0xab 0x23 0x87 0x29 0x00 0xf4 0x00 0x01 0x01 0xf6 0x00
+ 0x02 0x81 0x00 0xfa 0x00 0x02 0x12 0x80 0x0c 0x00 0x10 0x02
+ 0x80 0x92 0x04 0x50 0xc5 0xea 0x19 0xe1 0x1b 0xfd 0xaf 0x5f
+ 0x01 0xa4 0x0b 0xd9 0x00 0x01 0x0f 0xe4 0x00 0x01 0x08>;
+ };
+};
--
2.15.1
^ permalink raw reply related
* [RFC v2 1/9] serdev: implement parity configuration
From: Martin Blumenstingl @ 2018-01-01 20:42 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-bluetooth-u79uwXL29TY76Z2rM5mHXA,
linux-serial-u79uwXL29TY76Z2rM5mHXA
Cc: mark.rutland-5wv7dgnIgG8, marcel-kz+m5ild9QBg9hUCZPvPmw,
gustavo-THi1TnShQwVAfugRpC6u6w,
johan.hedberg-Re5JQEeQqe8AvxtiuMwx3w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, jslaby-IBi9RG/b67k,
johan-DgEjT+Ai2ygdnm+yROfE0A,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Larry.Finger-tQ5ms3gMjBLk1uMJSBkQmQ, carlo-6IF/jdPJHihWk0Htik3J/w,
drake-6IF/jdPJHihWk0Htik3J/w, Martin Blumenstingl
In-Reply-To: <20180101204217.26165-1-martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
Some Bluetooth modules (for example the ones found in Realtek RTL8723BS
and RTL8723DS) want to communicate with the host with even parity
enabled.
Add a new function and the corresponding internal callbacks so parity
can be configured. This supports enabling and disabling parity as well
as setting the type to odd or even.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
---
drivers/tty/serdev/core.c | 12 ++++++++++++
drivers/tty/serdev/serdev-ttyport.c | 21 +++++++++++++++++++++
include/linux/serdev.h | 5 +++++
3 files changed, 38 insertions(+)
diff --git a/drivers/tty/serdev/core.c b/drivers/tty/serdev/core.c
index 1bef39828ca7..d327b02980f5 100644
--- a/drivers/tty/serdev/core.c
+++ b/drivers/tty/serdev/core.c
@@ -225,6 +225,18 @@ void serdev_device_set_flow_control(struct serdev_device *serdev, bool enable)
}
EXPORT_SYMBOL_GPL(serdev_device_set_flow_control);
+void serdev_device_set_parity(struct serdev_device *serdev, bool enable,
+ bool odd)
+{
+ struct serdev_controller *ctrl = serdev->ctrl;
+
+ if (!ctrl || !ctrl->ops->set_parity)
+ return;
+
+ ctrl->ops->set_parity(ctrl, enable, odd);
+}
+EXPORT_SYMBOL_GPL(serdev_device_set_parity);
+
void serdev_device_wait_until_sent(struct serdev_device *serdev, long timeout)
{
struct serdev_controller *ctrl = serdev->ctrl;
diff --git a/drivers/tty/serdev/serdev-ttyport.c b/drivers/tty/serdev/serdev-ttyport.c
index 247788a16f0b..36bed86e5c96 100644
--- a/drivers/tty/serdev/serdev-ttyport.c
+++ b/drivers/tty/serdev/serdev-ttyport.c
@@ -190,6 +190,26 @@ static void ttyport_set_flow_control(struct serdev_controller *ctrl, bool enable
tty_set_termios(tty, &ktermios);
}
+static void ttyport_set_parity(struct serdev_controller *ctrl, bool enable,
+ bool odd)
+{
+ struct serport *serport = serdev_controller_get_drvdata(ctrl);
+ struct tty_struct *tty = serport->tty;
+ struct ktermios ktermios = tty->termios;
+
+ if (enable)
+ ktermios.c_cflag |= PARENB;
+ else
+ ktermios.c_cflag &= ~PARENB;
+
+ if (odd)
+ ktermios.c_cflag |= PARODD;
+ else
+ ktermios.c_cflag &= ~PARODD;
+
+ tty_set_termios(tty, &ktermios);
+}
+
static void ttyport_wait_until_sent(struct serdev_controller *ctrl, long timeout)
{
struct serport *serport = serdev_controller_get_drvdata(ctrl);
@@ -227,6 +247,7 @@ static const struct serdev_controller_ops ctrl_ops = {
.open = ttyport_open,
.close = ttyport_close,
.set_flow_control = ttyport_set_flow_control,
+ .set_parity = ttyport_set_parity,
.set_baudrate = ttyport_set_baudrate,
.wait_until_sent = ttyport_wait_until_sent,
.get_tiocm = ttyport_get_tiocm,
diff --git a/include/linux/serdev.h b/include/linux/serdev.h
index d609e6dc5bad..07f2d4d4e88c 100644
--- a/include/linux/serdev.h
+++ b/include/linux/serdev.h
@@ -86,6 +86,7 @@ struct serdev_controller_ops {
int (*open)(struct serdev_controller *);
void (*close)(struct serdev_controller *);
void (*set_flow_control)(struct serdev_controller *, bool);
+ void (*set_parity)(struct serdev_controller *, bool, bool);
unsigned int (*set_baudrate)(struct serdev_controller *, unsigned int);
void (*wait_until_sent)(struct serdev_controller *, long);
int (*get_tiocm)(struct serdev_controller *);
@@ -195,6 +196,7 @@ int serdev_device_open(struct serdev_device *);
void serdev_device_close(struct serdev_device *);
unsigned int serdev_device_set_baudrate(struct serdev_device *, unsigned int);
void serdev_device_set_flow_control(struct serdev_device *, bool);
+void serdev_device_set_parity(struct serdev_device *, bool, bool);
int serdev_device_write_buf(struct serdev_device *, const unsigned char *, size_t);
void serdev_device_wait_until_sent(struct serdev_device *, long);
int serdev_device_get_tiocm(struct serdev_device *);
@@ -237,6 +239,9 @@ static inline unsigned int serdev_device_set_baudrate(struct serdev_device *sdev
return 0;
}
static inline void serdev_device_set_flow_control(struct serdev_device *sdev, bool enable) {}
+static inline void serdev_device_set_parity(struct serdev_device *sdev,
+ bool enable,
+ bool odd) {}
static inline int serdev_device_write_buf(struct serdev_device *serdev,
const unsigned char *buf,
size_t count)
--
2.15.1
^ permalink raw reply related
* [RFC v2 0/9] Realtek Bluetooth serdev support (H5 protocol)
From: Martin Blumenstingl @ 2018-01-01 20:42 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-bluetooth-u79uwXL29TY76Z2rM5mHXA,
linux-serial-u79uwXL29TY76Z2rM5mHXA
Cc: mark.rutland-5wv7dgnIgG8, marcel-kz+m5ild9QBg9hUCZPvPmw,
gustavo-THi1TnShQwVAfugRpC6u6w,
johan.hedberg-Re5JQEeQqe8AvxtiuMwx3w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r, jslaby-IBi9RG/b67k,
johan-DgEjT+Ai2ygdnm+yROfE0A,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Larry.Finger-tQ5ms3gMjBLk1uMJSBkQmQ, carlo-6IF/jdPJHihWk0Htik3J/w,
drake-6IF/jdPJHihWk0Htik3J/w, Martin Blumenstingl
Hello,
I am sending this series because I want to get feedback.
please don't expect it to be perfect (yet). especially since it's
touching parts of the kernel I've not worked with before.
my goal was NOT to use the user-space initialization tool for the
Bluetooth part of one of my devices (which uses a Realtek RTL8723BS).
my hope was that I only had to hook up serdev support to hci_h5 and
re-use the setup function provided by btrtl. unfortunately it wasn't
that easy.
there are no datasheets for the RTL8723BS or RTL8723DS out there.
however, there are some userspace tools which go through the whole
initialization process - this is what I used as reference:
- RTL8723BS Bluetooth sources from [0]
- RTL8723DS Bluetooth sources from [1]
These modules require a firmware and a config file (both don't seem
to be compatible with what we have in linux-firmware at the moment).
since it's an RFC I also have some questions:
- who can help testing that I didn't break any USB based Realtek
Bluetooth chips? I only have UART (embedded into the SDIO RTL8723BS
and RTL8723DS) ones
- what about the Bluetooth firmware and config blobs? how to get them
into the linux-firmware tree? maybe Larry Finger can help here :)
- what are <your name here> comments about this series?
Changes since RFC v1 at [2]:
- fixed compile error in PATCH #1 if CONFIG_SERIAL_DEV_BUS is disabled
(spotted by Intel's kbuild test robot - many thanks!)
- renamed "disable-gpios" to "enable-gpios" in the dt-bindings and
hci_h5 patches
- added a "realtek,config-data" property to devicetree which can be used
to provide the "config"-blob. I did not find a way to auto-generate
that blob. a similar property is described by "marvell-bt-8xxx.txt".
This affects the dt-bindings (Documentation) patch and introduces a
new patch for btrtl.c.
- guard against the vendor_setup callback being NULL (thanks Marcel
Holtmann for suggesting this in the review of RFC 1) in the hci_h5
patch
- added comments where the msleep() times are coming from in the hci_h5
patch
- dropped an unnecessary msleep() after sending the "change baudrate"
command (thanks Marcel Holtmann for spotting this)
- entirely drop HCI_UART_INIT_PENDING instead of just ignoring it in
hci_serdev
[0] https://github.com/lwfinger/rtl8723bs_bt
[1] https://github.com/NextThingCo/rtl8723ds_bt
[2] https://www.spinics.net/lists/linux-bluetooth/msg72862.html
Martin Blumenstingl (9):
serdev: implement parity configuration
dt-bindings: net: bluetooth: add support for Realtek Bluetooth chips
Bluetooth: btrtl: add MODULE_FIRMWARE declarations
Bluetooth: btrtl: split the device initialization into smaller parts
Bluetooth: btrtl: add support for retrieving the UART settings
Bluetooth: btrtl: add support for the RTL8723BS and RTL8723DS chips
bluetooth: btrtl: load the config blob from devicetree when available
Bluetooth: drop HCI_UART_INIT_PENDING support
Bluetooth: hci_h5: add support for Realtek UART Bluetooth modules
.../devicetree/bindings/net/realtek-bluetooth.txt | 41 ++
drivers/bluetooth/Kconfig | 1 +
drivers/bluetooth/btrtl.c | 461 ++++++++++++++++-----
drivers/bluetooth/btrtl.h | 46 ++
drivers/bluetooth/hci_h5.c | 206 ++++++++-
drivers/bluetooth/hci_ldisc.c | 38 --
drivers/bluetooth/hci_serdev.c | 3 -
drivers/bluetooth/hci_uart.h | 4 +-
drivers/tty/serdev/core.c | 12 +
drivers/tty/serdev/serdev-ttyport.c | 21 +
include/linux/serdev.h | 5 +
11 files changed, 678 insertions(+), 160 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/realtek-bluetooth.txt
--
2.15.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 2/2] serial: imx: fix endless loop during suspend
From: Fabio Estevam @ 2017-12-31 11:53 UTC (permalink / raw)
To: Martin Kaiser
Cc: Greg Kroah-Hartman, Jiri Slaby, Sascha Hauer, Philipp Zabel,
Shawn Guo, linux-serial, linux-kernel, stable
In-Reply-To: <1514395632-15390-2-git-send-email-martin@kaiser.cx>
Hi Martin,
On Wed, Dec 27, 2017 at 3:27 PM, Martin Kaiser <martin@kaiser.cx> wrote:
> Before we go into suspend mode, we enable the imx uart's interrupt for
> the awake bit in the UART Status Register 1. If, for some reason, the
> awake bit is already set before we enter suspend mode, we get an
> interrupt immediately when we enable interrupts for awake. The uart's
> clk_ipg is already disabled at this point. We end up in the interrupt
> handler, which usually tries to clear the awake bit. This doesn't work
> with the clock disabled. Therefore, we keep getting interrupts forever,
> resulting in an endless loop.
>
> Move the calls to serial_imx_enable_wakeup() into the _noirq functions,
> where interrupts are disabled and clk_ipg is active. This way, we can
> safely clear the awake bit and enable the imx interrupt for awake.
>
> Now that we do the wakeup configuration in .suspend_noirq, we need
> separate functions for .suspend_noirq and .freeze_noirq. However,
> .resume_noirq and .restore_noirq can still be shared. We just disable
> the wakeup source there, this does not conflict with hibernation.
>
> Signed-off-by: Martin Kaiser <martin@kaiser.cx>
> Cc: stable@vger.kernel.org
Which i.MX SoC did you use to test this patch?
On a imx6q-cuboxi I am no longer able to enter in suspend with this
path applied:
# echo enabled > /sys/class/tty/ttymxc0/power/wakeup
# echo mem > /sys/power/state
[ 9.766903] PM: suspend entry (deep)
[ 9.770658] PM: Syncing filesystems ... done.
[ 9.815312] Freezing user space processes ... (elapsed 0.001 seconds) done.
[ 9.824744] OOM killer disabled.
[ 9.827998] Freezing remaining freezable tasks ... (elapsed 0.001
seconds) done.
[ 9.837351] Suspending console(s) (use no_console_suspend to debug)
[ 9.915495] PM: suspend devices took 0.080 seconds
[ 9.928746] PM: noirq suspend of devices failed
[ 10.196232] mmc0: queuing unknown CIS tuple 0x80 (2 bytes)
[ 10.198148] mmc0: queuing unknown CIS tuple 0x80 (3 bytes)
[ 10.200042] mmc0: queuing unknown CIS tuple 0x80 (3 bytes)
[ 10.203420] mmc0: queuing unknown CIS tuple 0x80 (7 bytes)
[ 10.206812] mmc0: queuing unknown CIS tuple 0x80 (7 bytes)
[ 10.263097] PM: resume devices took 0.330 seconds
[ 10.266639] ata1: SATA link down (SStatus 0 SControl 300)
[ 10.310305] OOM killer enabled.
[ 10.313458] Restarting tasks ... done.
[ 10.319568] PM: suspend exit
sh: write error: Device or resource busy
Even if I do not press anything in the console the system gets out of
suspend automatically.
Thanks
^ permalink raw reply
* [GIT PULL] TTY fixes for 4.15-rc6
From: Greg KH @ 2017-12-31 11:47 UTC (permalink / raw)
To: Linus Torvalds, Jiri Slaby
Cc: Stephen Rothwell, Andrew Morton, linux-kernel, linux-serial
The following changes since commit 50c4c4e268a2d7a3e58ebb698ac74da0de40ae36:
Linux 4.15-rc3 (2017-12-10 17:56:26 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git/ tags/tty-4.15-rc6
for you to fetch changes up to 966031f340185eddd05affcf72b740549f056348:
n_tty: fix EXTPROC vs ICANON interaction with TIOCINQ (aka FIONREAD) (2017-12-21 11:19:22 +0100)
----------------------------------------------------------------
TTY fix for 4.15-rc6
Here is a single tty fix for a reported issue that you wrote the patch
for :)
It's been in linux-next for a week or so with no reported issues.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----------------------------------------------------------------
Linus Torvalds (1):
n_tty: fix EXTPROC vs ICANON interaction with TIOCINQ (aka FIONREAD)
drivers/tty/n_tty.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
^ permalink raw reply
* Re: [PATCH] gpio: serial: max310x: Support open-drain configuration for GPIOs
From: Linus Walleij @ 2017-12-28 23:38 UTC (permalink / raw)
To: Jan Kundrát
Cc: linux-gpio, Greg Kroah-Hartman, linux-serial, Alexander Shiyan
In-Reply-To: <18c9e927d2b75b3325ee3eae7e78319129faa779.1513983040.git.jan.kundrat@cesnet.cz>
On Fri, Dec 22, 2017 at 9:29 PM, Jan Kundrát <jan.kundrat@cesnet.cz> wrote:
> The push-pull vs. open-drain are the only supported output modes. The
> inputs are always unconditionally equipped with weak pull-downs. That's
> the only mode, so there's probably no point in exporting that. I wonder
> if it's worthwhile to provide a custom dbg_show method to indicate the
> current status of the outputs, though.
>
> This patch and [1] for i2c-gpio together make it possible to bit-bang an
> I2C bus over GPIOs of an UART which is connected via SPI :). Yes, this
> is crazy, but it's fast enough (while on a 26Mhz SPI HW bus with a
> dual-core 1.6GHz CPU) to drive an I2C bus at 200kHz, according to my
> scope.
>
> [1] https://patchwork.ozlabs.org/patch/852591/
>
> Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz>
> ---
> My suggestion is for this patch to go in via the tty/serial tree; I plan
> to send more patches to this driver (and some of them are alreay in
> tty-next). --jkt
OK Greg can pick this.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
(Looks very useful for hardware hacking, by the way.)
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 3.16 177/204] MIPS: AR7: Ensure that serial ports are properly set up
From: Ben Hutchings @ 2017-12-28 17:05 UTC (permalink / raw)
To: linux-kernel, stable
Cc: akpm, Yoshihiro YUNOMAE, linux-mips, Nicolas Schichan,
linux-serial, Greg Kroah-Hartman, James Hogan, Jonas Gorski,
Florian Fainelli, Ralf Baechle, Oswald Buddenhagen
In-Reply-To: <lsq.1514480743.579539031@decadent.org.uk>
3.16.52-rc1 review patch. If anyone has any objections, please let me know.
------------------
From: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
commit b084116f8587b222a2c5ef6dcd846f40f24b9420 upstream.
Without UPF_FIXED_TYPE, the data from the PORT_AR7 uart_config entry is
never copied, resulting in a dead port.
Fixes: 154615d55459 ("MIPS: AR7: Use correct UART port type")
Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
[jonas.gorski: add Fixes tag]
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Yoshihiro YUNOMAE <yoshihiro.yunomae.ez@hitachi.com>
Cc: Nicolas Schichan <nschichan@freebox.fr>
Cc: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
Cc: linux-mips@linux-mips.org
Cc: linux-serial@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/17543/
Signed-off-by: James Hogan <jhogan@kernel.org>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
---
arch/mips/ar7/platform.c | 1 +
1 file changed, 1 insertion(+)
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -581,6 +581,7 @@ static int __init ar7_register_uarts(voi
uart_port.type = PORT_AR7;
uart_port.uartclk = clk_get_rate(bus_clk) / 2;
uart_port.iotype = UPIO_MEM32;
+ uart_port.flags = UPF_FIXED_TYPE;
uart_port.regshift = 2;
uart_port.line = 0;
^ permalink raw reply
* [PATCH 3.2 82/94] MIPS: AR7: Ensure that serial ports are properly set up
From: Ben Hutchings @ 2017-12-28 16:59 UTC (permalink / raw)
To: linux-kernel, stable
Cc: akpm, Yoshihiro YUNOMAE, Ralf Baechle, Greg Kroah-Hartman,
linux-serial, Oswald Buddenhagen, linux-mips, James Hogan,
Jonas Gorski, Florian Fainelli, Nicolas Schichan
In-Reply-To: <lsq.1514480348.981935392@decadent.org.uk>
3.2.97-rc1 review patch. If anyone has any objections, please let me know.
------------------
From: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
commit b084116f8587b222a2c5ef6dcd846f40f24b9420 upstream.
Without UPF_FIXED_TYPE, the data from the PORT_AR7 uart_config entry is
never copied, resulting in a dead port.
Fixes: 154615d55459 ("MIPS: AR7: Use correct UART port type")
Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
[jonas.gorski: add Fixes tag]
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Yoshihiro YUNOMAE <yoshihiro.yunomae.ez@hitachi.com>
Cc: Nicolas Schichan <nschichan@freebox.fr>
Cc: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
Cc: linux-mips@linux-mips.org
Cc: linux-serial@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/17543/
Signed-off-by: James Hogan <jhogan@kernel.org>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
---
arch/mips/ar7/platform.c | 1 +
1 file changed, 1 insertion(+)
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -541,6 +541,7 @@ static int __init ar7_register_uarts(voi
uart_port.type = PORT_AR7;
uart_port.uartclk = clk_get_rate(bus_clk) / 2;
uart_port.iotype = UPIO_MEM32;
+ uart_port.flags = UPF_FIXED_TYPE;
uart_port.regshift = 2;
uart_port.line = 0;
^ permalink raw reply
* Re: [PATCH RFC 3/3] MIPS: AR7: ensure the port type's FCR value is used
From: Jonas Gorski @ 2017-12-28 15:38 UTC (permalink / raw)
To: James Hogan
Cc: MIPS Mailing List, linux-serial, Ralf Baechle, Greg Kroah-Hartman,
Yoshihiro YUNOMAE, Florian Fainelli, Nicolas Schichan
In-Reply-To: <20171114110211.GA5823@jhogan-linux.mipstec.com>
On 14 November 2017 at 12:02, James Hogan <james.hogan@mips.com> wrote:
> On Sun, Oct 29, 2017 at 04:27:21PM +0100, Jonas Gorski wrote:
>> Since commit aef9a7bd9b67 ("serial/uart/8250: Add tunable RX interrupt
>> trigger I/F of FIFO buffers"), the port's default FCR value isn't used
>> in serial8250_do_set_termios anymore, but copied over once in
>> serial8250_config_port and then modified as needed.
>>
>> Unfortunately, serial8250_config_port will never be called if the port
>> is shared between kernel and userspace, and the port's flag doesn't have
>> UPF_BOOT_AUTOCONF, which would trigger a serial8250_config_port as well.
>>
>> This causes garbled output from userspace:
>>
>> [ 5.220000] random: procd urandom read with 49 bits of entropy available
>> ers
>> [kee
>>
>> Fix this by forcing it to be configured on boot, resulting in the
>> expected output:
>>
>> [ 5.250000] random: procd urandom read with 50 bits of entropy available
>> Press the [f] key and hit [enter] to enter failsafe mode
>> Press the [1], [2], [3] or [4] key and hit [enter] to select the debug level
>>
>> Fixes: aef9a7bd9b67 ("serial/uart/8250: Add tunable RX interrupt trigger I/F of FIFO buffers")
>> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
>> ---
>> I'm not sure if this is just AR7's issue, or if this points to a general
>> issue for UARTs used as kernel console and login console with the "fixed"
>> commit.
>
> Thanks. Given nobody seems to have objected, I've applied to my
> mips-fixes branch, with stable tag for 3.17+.
Hmm, I don't see it in
https://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips.git/log/?h=mips-fixes
- did you maybe forget to push?
Regards
Jonas
^ permalink raw reply
* [PATCH 3/3] serial: 8250_ingenic: Parse earlycon options
From: Paul Cercueil @ 2017-12-28 13:07 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Rob Herring, linux-serial, devicetree, linux-kernel,
Paul Cercueil
In-Reply-To: <20171228130709.12457-1-paul@crapouillou.net>
In the devicetree, it is possible to specify the baudrate, parity,
bits, flow of the early console, by passing a configuration string like
this:
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:57600n8";
};
This, for instance, will configure the early console for a baudrate of
57600 bps, no parity, and 8 bits per baud.
This patches implements parsing of this configuration string in the
8250_ingenic driver, which previously just ignored it.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
drivers/tty/serial/8250/8250_ingenic.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
v1: Initial version
diff --git a/drivers/tty/serial/8250/8250_ingenic.c b/drivers/tty/serial/8250/8250_ingenic.c
index 165b4bb3de93..15a8c8dfa92b 100644
--- a/drivers/tty/serial/8250/8250_ingenic.c
+++ b/drivers/tty/serial/8250/8250_ingenic.c
@@ -91,14 +91,22 @@ static int __init ingenic_early_console_setup(struct earlycon_device *dev,
const char *opt)
{
struct uart_port *port = &dev->port;
- unsigned int baud, divisor;
+ unsigned int divisor;
+ int baud = 115200;
if (!dev->port.membase)
return -ENODEV;
+ if (opt) {
+ unsigned int parity, bits, flow; /* unused for now */
+
+ uart_parse_options(opt, &baud, &parity, &bits, &flow);
+ }
+
ingenic_early_console_setup_clock(dev);
- baud = dev->baud ?: 115200;
+ if (dev->baud)
+ baud = dev->baud;
divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * baud);
early_out(port, UART_IER, 0);
--
2.15.1
^ permalink raw reply related
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