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* Re: [PATCH v6 1/6] irqchip/mtk-sysirq: support 4 interrupt parameters for sysirq
From: Marc Zyngier @ 2019-02-11  8:50 UTC (permalink / raw)
  To: Seiya Wang
  Cc: Matthias Brugger, Erin Lo, Rob Herring, Mark Rutland,
	Thomas Gleixner, Jason Cooper, Greg Kroah-Hartman, Stephen Boyd,
	devicetree, srv_heupstream, linux-kernel, linux-serial,
	linux-mediatek, linux-arm-kernel, yingjoe.chen, mars.cheng,
	eddie.huang, linux-clk
In-Reply-To: <1549866929.22817.20.camel@mtksdccf07>

On Mon, 11 Feb 2019 06:35:29 +0000,
Seiya Wang <seiya.wang@mediatek.com> wrote:
> 
> On Thu, 2019-02-07 at 15:52 +0000, Marc Zyngier wrote:
> > On 07/02/2019 15:47, Marc Zyngier wrote:
> > > On 07/02/2019 15:20, Matthias Brugger wrote:
> > >>
> > >>
> > >> On 24/01/2019 09:07, Erin Lo wrote:
> > >>> From: Seiya Wang <seiya.wang@mediatek.com>
> > >>>
> > >>> To support partitioned PPIs, 4 interrupt parameters should be valid
> > >>> for sysirq.
> > >>>
> > >>> Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
> > >>> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> > >>> ---
> > >>>  drivers/irqchip/irq-mtk-sysirq.c | 4 ++--
> > >>>  1 file changed, 2 insertions(+), 2 deletions(-)
> > >>>
> > >>> diff --git a/drivers/irqchip/irq-mtk-sysirq.c b/drivers/irqchip/irq-mtk-sysirq.c
> > >>> index 90aaf19..282736a 100644
> > >>> --- a/drivers/irqchip/irq-mtk-sysirq.c
> > >>> +++ b/drivers/irqchip/irq-mtk-sysirq.c
> > >>> @@ -81,7 +81,7 @@ static int mtk_sysirq_domain_translate(struct irq_domain *d,
> > >>>  				       unsigned int *type)
> > >>>  {
> > >>>  	if (is_of_node(fwspec->fwnode)) {
> > >>> -		if (fwspec->param_count != 3)
> > >>> +		if (fwspec->param_count != 3 && fwspec->param_count != 4)
> > >>
> > >> Where is this 4th parameter used?
> > > 
> > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt#n14
> > Sorry, I fired Send way too early.
> > 
> > What I wanted to add is that it is not clear to me why this change would
> > be required here, as this driver only supports SPIs. It could be fixed
> > by just relaxing the binding itself.
> > 
> > Thanks,
> > 
> > 	M.
> 
> Do you mean that we should change #interrupt-cells back to 3 for sysirq
> and remove the 4th parameters of every spi interrupts in mt8183.dtsi
> (i.e. 3 parameters for spi, 4 for ppi) such that we can discard this
> patch?

It is more subtle than that:

- PPIs must have the affinity parameter in their int-spec (since you
  need that for the PMU)

- SPIs that are directly routed to the GIC must also have the affinity
  parameter (although set to zero).

- SPIs that are routed via the sysirq block (or any other) can use the
  3 parameter variant, as they are not resolved in the context of the
  GIC, but in that of the sysirq.

But in short, yes. You should be able to drop this patch altogether.

> If yes, we may need some time to verify the change before resending the
> patch.

That's absolutely fine.

Thanks,

	M.

-- 
Jazz is not dead, it just smell funny.

^ permalink raw reply

* Re: [PATCH v6 1/6] irqchip/mtk-sysirq: support 4 interrupt parameters for sysirq
From: Seiya Wang @ 2019-02-11  6:35 UTC (permalink / raw)
  To: Marc Zyngier
  Cc: Mark Rutland, devicetree, Jason Cooper, srv_heupstream,
	Greg Kroah-Hartman, Erin Lo, Stephen Boyd, linux-kernel,
	Rob Herring, linux-mediatek, linux-serial, mars.cheng,
	Matthias Brugger, yingjoe.chen, Thomas Gleixner, eddie.huang,
	linux-clk, linux-arm-kernel
In-Reply-To: <c0187acf-bd8c-2d41-d84d-d35fc63b2beb@arm.com>

On Thu, 2019-02-07 at 15:52 +0000, Marc Zyngier wrote:
> On 07/02/2019 15:47, Marc Zyngier wrote:
> > On 07/02/2019 15:20, Matthias Brugger wrote:
> >>
> >>
> >> On 24/01/2019 09:07, Erin Lo wrote:
> >>> From: Seiya Wang <seiya.wang@mediatek.com>
> >>>
> >>> To support partitioned PPIs, 4 interrupt parameters should be valid
> >>> for sysirq.
> >>>
> >>> Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
> >>> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> >>> ---
> >>>  drivers/irqchip/irq-mtk-sysirq.c | 4 ++--
> >>>  1 file changed, 2 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/drivers/irqchip/irq-mtk-sysirq.c b/drivers/irqchip/irq-mtk-sysirq.c
> >>> index 90aaf19..282736a 100644
> >>> --- a/drivers/irqchip/irq-mtk-sysirq.c
> >>> +++ b/drivers/irqchip/irq-mtk-sysirq.c
> >>> @@ -81,7 +81,7 @@ static int mtk_sysirq_domain_translate(struct irq_domain *d,
> >>>  				       unsigned int *type)
> >>>  {
> >>>  	if (is_of_node(fwspec->fwnode)) {
> >>> -		if (fwspec->param_count != 3)
> >>> +		if (fwspec->param_count != 3 && fwspec->param_count != 4)
> >>
> >> Where is this 4th parameter used?
> > 
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt#n14
> Sorry, I fired Send way too early.
> 
> What I wanted to add is that it is not clear to me why this change would
> be required here, as this driver only supports SPIs. It could be fixed
> by just relaxing the binding itself.
> 
> Thanks,
> 
> 	M.

Do you mean that we should change #interrupt-cells back to 3 for sysirq
and remove the 4th parameters of every spi interrupts in mt8183.dtsi
(i.e. 3 parameters for spi, 4 for ppi) such that we can discard this
patch?

If yes, we may need some time to verify the change before resending the
patch.

Thanks.

^ permalink raw reply

* Re: [PATCH v6 6/6] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile
From: Erin Lo @ 2019-02-09  7:37 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: Mark Rutland, Ben Ho, Mars Cheng, Mengqi Zhang, linux-clk,
	Hsin-Hsiung Wang, Rob Herring, Weiyi Lu, Marc Zyngier,
	open list:SERIAL DRIVERS, Yingjoe Chen, devicetree, Jason Cooper,
	Seiya Wang, moderated list:ARM/Mediatek SoC support,
	Thomas Gleixner, Eddie Huang,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	srv_heupstream, Greg Kroah-Hartman
In-Reply-To: <c872f03c-714a-d99f-d555-e897f80d67be@gmail.com>

On Thu, 2019-02-07 at 16:08 +0100, Matthias Brugger wrote:
> 
> On 01/02/2019 06:11, Erin Lo wrote:
> > Add back more people since mail server issue
> > 
> > On Fri, 2019-02-01 at 11:33 +0800, Erin Lo wrote:
> >> On Thu, 2019-01-31 at 15:10 -0600, Rob Herring wrote:
> >>> On Wed, Jan 30, 2019 at 8:34 PM Erin Lo <erin.lo@mediatek.com> wrote:
> >>>>
> >>>> On Wed, 2019-01-30 at 10:22 -0600, Rob Herring wrote:
> >>>>> On Thu, Jan 24, 2019 at 04:07:20PM +0800, Erin Lo wrote:
> >>>>>> From: Ben Ho <Ben.Ho@mediatek.com>
> >>>>>>
> >>>>>> Add basic chip support for Mediatek 8183, include
> >>>>>> pinctrl file, uart node with correct uart clocks, pwrap device
> >>>>>>
> >>>>>> Add clock controller nodes, include topckgen, infracfg,
> >>>>>> apmixedsys and subsystem.
> >>>>>>
> >>>>>> Signed-off-by: Ben Ho <Ben.Ho@mediatek.com>
> >>>>>> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> >>>>>> Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
> >>>>>> Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
> >>>>>> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> >>>>>> Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
> >>>>>> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> >>>>>> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
> >>>>>> ---
> >>>>>
> >>>>>
> >>>>>> +   sysirq: intpol-controller@c530a80 {
> >>>>>
> >>>>> interrupt-controller@...
> >>>>
> >>>> I will modify it in next version.
> >>>>>
> >>>>>
> >>>>> Place all the MMIO peripherals under one or more simple-bus nodes.
> >>>>>
> >>>>> Rob
> >>>>>
> >>>>
> >>>> Do you mean need to add simple-bus like this?
> >>>
> >>> Yes.
> >>
> >> We remove soc because Matthias suggested it in former MTK SoC maybe in
> >> 2015 year.
> >>
> >> We will add it back by your comment.
> >>
> >> Thank you. 
> >>
> >> Best Regards,
> >> Erin
> > 
> > Hi, Matthias,
> > Do you have any comment here?
> 
> Although I wasn't able to find it in the documentation my understanding is, that
> all devices on-chip should be under soc "bus".
> 
> I'm sorry if I created confusion with comments in the past.
> 
> Regards,
> Matthias
> 

OK! we will add soc "bus" back in next version.
Thank you for your comment.

Best Regards,
Erin

> > Thanks
> > 
> > Best Regards,
> > Erin
> >>>
> >>>>
> >>>> +   soc: soc {
> >>>> +                #address-cells = <0x1>;
> >>>> +                #size-cells = <0x1>;
> >>>> +                ranges = <0 0 0 0xffffffff>;
> >>>> +                compatible = "simple-bus";
> >>>>
> >>>>                 soc_data: soc_data@08000000 {
> >>>>                         compatible = "mediatek,mt8183-efuse",
> >>>>                                      "mediatek,efuse";
> >>>>                         reg = <0 0x08000000 0 0x0010>;
> >>>>                         #address-cells = <1>;
> >>>>                         #size-cells = <1>;
> >>>>                         status = "disabled";
> >>>>                 };
> >>>>
> >>>>                 gic: interrupt-controller@0c000000 {
> >>>>                         compatible = "arm,gic-v3";
> >>>>                         #interrupt-cells = <4>;
> >>>>
> >>>> Best Regards,
> >>>> Erin
> >>>>
> >>>>> _______________________________________________
> >>>>> Linux-mediatek mailing list
> >>>>> Linux-mediatek@lists.infradead.org
> >>>>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
> >>>>
> >>>>
> >>>>
> >>>> _______________________________________________
> >>>> linux-arm-kernel mailing list
> >>>> linux-arm-kernel@lists.infradead.org
> >>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> >>
> > 
> > 
> 
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply

* Re: [GIT PULL] TTY/Serial fixes for 5.0-rc6
From: pr-tracker-bot @ 2019-02-08 19:45 UTC (permalink / raw)
  To: Greg KH
  Cc: Linus Torvalds, Jiri Slaby, Stephen Rothwell, Andrew Morton,
	linux-kernel, linux-serial
In-Reply-To: <20190208083808.GA26882@kroah.com>

The pull request you sent on Fri, 8 Feb 2019 09:38:08 +0100:

> git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tags/tty-5.0-rc6

has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/e22a15d1c4b36877934ab360aace41ddf8a6577c

Thank you!

-- 
Deet-doot-dot, I am a bot.
https://korg.wiki.kernel.org/userdoc/prtracker

^ permalink raw reply

* [PATCH v2 10/15] serial: Add Milbeaut serial control
From: Sugaya Taichi @ 2019-02-08 12:27 UTC (permalink / raw)
  To: linux-kernel, linux-serial, linux-arm-kernel
  Cc: Greg Kroah-Hartman, Jiri Slaby, Takao Orito, Kazuhiro Kasai,
	Shinji Kanematsu, Jassi Brar, Masami Hiramatsu, Sugaya Taichi

Add Milbeaut serial control including earlycon and console.

Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com>
---
 drivers/tty/serial/Kconfig         |  25 ++
 drivers/tty/serial/Makefile        |   1 +
 drivers/tty/serial/milbeaut_usio.c | 621 +++++++++++++++++++++++++++++++++++++
 include/uapi/linux/serial_core.h   |   3 +
 4 files changed, 650 insertions(+)
 create mode 100644 drivers/tty/serial/milbeaut_usio.c

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 089a6f2..1420195 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1560,6 +1560,31 @@ config SERIAL_RDA_CONSOLE
 	  Say 'Y' here if you wish to use the RDA8810PL UART as the system
 	  console. Only earlycon is implemented currently.
 
+config SERIAL_MILBEAUT_USIO
+	tristate "Milbeaut USIO/UART serial port support"
+	depends on ARCH_MILBEAUT
+	default y
+	select SERIAL_CORE
+	help
+	  This selects the USIO/UART IP found in Socionext Milbeaut SoCs.
+
+config SERIAL_MILBEAUT_USIO_PORTS
+	int "Maximum number of CSIO/UART ports (1-8)"
+	range 1 8
+	depends on SERIAL_MILBEAUT_USIO
+	default "4"
+
+config SERIAL_MILBEAUT_USIO_CONSOLE
+	bool "Support for console on MILBEAUT USIO/UART serial port"
+	depends on SERIAL_MILBEAUT_USIO=y
+	select SERIAL_CORE_CONSOLE
+	select SERIAL_EARLYCON
+	help
+	  Say 'Y' here if you wish to use a USIO/UART of Socionext Milbeaut
+	  SoCs as the system console (the system console is the device which
+	  receives all kernel messages and warnings and which allows logins in
+	  single user mode).
+
 endmenu
 
 config SERIAL_MCTRL_GPIO
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 1511e8a..fd6fdbe 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -91,6 +91,7 @@ obj-$(CONFIG_SERIAL_PIC32)	+= pic32_uart.o
 obj-$(CONFIG_SERIAL_MPS2_UART)	+= mps2-uart.o
 obj-$(CONFIG_SERIAL_OWL)	+= owl-uart.o
 obj-$(CONFIG_SERIAL_RDA)	+= rda-uart.o
+obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o
 
 # GPIOLIB helpers for modem control lines
 obj-$(CONFIG_SERIAL_MCTRL_GPIO)	+= serial_mctrl_gpio.o
diff --git a/drivers/tty/serial/milbeaut_usio.c b/drivers/tty/serial/milbeaut_usio.c
new file mode 100644
index 0000000..43729ee
--- /dev/null
+++ b/drivers/tty/serial/milbeaut_usio.c
@@ -0,0 +1,621 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Socionext Inc.
+ */
+
+#if defined(CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/clk.h>
+#include <linux/console.h>
+#include <linux/module.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+
+#define USIO_NAME		"mlb-usio-uart"
+#define USIO_UART_DEV_NAME	"ttyUSI"
+
+static struct uart_port mlb_usio_ports[CONFIG_SERIAL_MILBEAUT_USIO_PORTS];
+
+#define RX	0
+#define TX	1
+static int mlb_usio_irq[CONFIG_SERIAL_MILBEAUT_USIO_PORTS][2];
+
+#define MLB_USIO_REG_SMR		0
+#define MLB_USIO_REG_SCR		1
+#define MLB_USIO_REG_ESCR		2
+#define MLB_USIO_REG_SSR		3
+#define MLB_USIO_REG_DR			4
+#define MLB_USIO_REG_BGR		6
+#define MLB_USIO_REG_FCR		12
+#define MLB_USIO_REG_FBYTE		14
+
+#define MLB_USIO_SMR_SOE		BIT(0)
+#define MLB_USIO_SMR_SBL		BIT(3)
+#define MLB_USIO_SCR_TXE		BIT(0)
+#define MLB_USIO_SCR_RXE		BIT(1)
+#define MLB_USIO_SCR_TBIE		BIT(2)
+#define MLB_USIO_SCR_TIE		BIT(3)
+#define MLB_USIO_SCR_RIE		BIT(4)
+#define MLB_USIO_SCR_UPCL		BIT(7)
+#define MLB_USIO_ESCR_L_8BIT		0
+#define MLB_USIO_ESCR_L_5BIT		1
+#define MLB_USIO_ESCR_L_6BIT		2
+#define MLB_USIO_ESCR_L_7BIT		3
+#define MLB_USIO_ESCR_P			BIT(3)
+#define MLB_USIO_ESCR_PEN		BIT(4)
+#define MLB_USIO_ESCR_FLWEN		BIT(7)
+#define MLB_USIO_SSR_TBI		BIT(0)
+#define MLB_USIO_SSR_TDRE		BIT(1)
+#define MLB_USIO_SSR_RDRF		BIT(2)
+#define MLB_USIO_SSR_ORE		BIT(3)
+#define MLB_USIO_SSR_FRE		BIT(4)
+#define MLB_USIO_SSR_PE			BIT(5)
+#define MLB_USIO_SSR_REC		BIT(7)
+#define MLB_USIO_SSR_BRK		BIT(8)
+#define MLB_USIO_FCR_FE1		BIT(0)
+#define MLB_USIO_FCR_FE2		BIT(1)
+#define MLB_USIO_FCR_FCL1		BIT(2)
+#define MLB_USIO_FCR_FCL2		BIT(3)
+#define MLB_USIO_FCR_FSET		BIT(4)
+#define MLB_USIO_FCR_FTIE		BIT(9)
+#define MLB_USIO_FCR_FDRQ		BIT(10)
+#define MLB_USIO_FCR_FRIIE		BIT(11)
+
+static void mlb_usio_stop_tx(struct uart_port *port)
+{
+	writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
+	       port->membase + MLB_USIO_REG_FCR);
+	writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE,
+	       port->membase + MLB_USIO_REG_SCR);
+}
+
+static void mlb_usio_tx_chars(struct uart_port *port)
+{
+	struct circ_buf *xmit = &port->state->xmit;
+	int count;
+
+	writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
+	       port->membase + MLB_USIO_REG_FCR);
+	writeb(readb(port->membase + MLB_USIO_REG_SCR) &
+	       ~(MLB_USIO_SCR_TIE | MLB_USIO_SCR_TBIE),
+	       port->membase + MLB_USIO_REG_SCR);
+
+	if (port->x_char) {
+		writew(port->x_char, port->membase + MLB_USIO_REG_DR);
+		port->icount.tx++;
+		port->x_char = 0;
+		return;
+	}
+	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
+		mlb_usio_stop_tx(port);
+		return;
+	}
+
+	count = port->fifosize -
+		(readw(port->membase + MLB_USIO_REG_FBYTE) & 0xff);
+
+	do {
+		writew(xmit->buf[xmit->tail], port->membase + MLB_USIO_REG_DR);
+
+		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+		port->icount.tx++;
+		if (uart_circ_empty(xmit))
+			break;
+
+	} while (--count > 0);
+
+	writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FDRQ,
+	       port->membase + MLB_USIO_REG_FCR);
+
+	writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
+	       port->membase + MLB_USIO_REG_SCR);
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(port);
+
+	if (uart_circ_empty(xmit))
+		mlb_usio_stop_tx(port);
+}
+
+static void mlb_usio_start_tx(struct uart_port *port)
+{
+	u16 fcr = readw(port->membase + MLB_USIO_REG_FCR);
+
+	writew(fcr | MLB_USIO_FCR_FTIE, port->membase + MLB_USIO_REG_FCR);
+	if (!(fcr & MLB_USIO_FCR_FDRQ))
+		return;
+
+	writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
+	       port->membase + MLB_USIO_REG_SCR);
+
+	if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
+		mlb_usio_tx_chars(port);
+}
+
+static void mlb_usio_stop_rx(struct uart_port *port)
+{
+	writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_RIE,
+	       port->membase + MLB_USIO_REG_SCR);
+}
+
+static void mlb_usio_enable_ms(struct uart_port *port)
+{
+	writeb(readb(port->membase + MLB_USIO_REG_SCR) |
+	       MLB_USIO_SCR_RIE | MLB_USIO_SCR_RXE,
+	       port->membase + MLB_USIO_REG_SCR);
+}
+
+static void mlb_usio_rx_chars(struct uart_port *port)
+{
+	struct tty_port *ttyport = &port->state->port;
+	unsigned long flag = 0;
+	char ch = 0;
+	u8 status;
+	int max_count = 2;
+
+	while (max_count--) {
+		status = readb(port->membase + MLB_USIO_REG_SSR);
+
+		if (!(status & MLB_USIO_SSR_RDRF))
+			break;
+
+		if (!(status & (MLB_USIO_SSR_ORE | MLB_USIO_SSR_FRE |
+				MLB_USIO_SSR_PE))) {
+			ch = readw(port->membase + MLB_USIO_REG_DR);
+			flag = TTY_NORMAL;
+			port->icount.rx++;
+			if (uart_handle_sysrq_char(port, ch))
+				continue;
+			uart_insert_char(port, status, MLB_USIO_SSR_ORE,
+					 ch, flag);
+			continue;
+		}
+		if (status & MLB_USIO_SSR_PE)
+			port->icount.parity++;
+		if (status & MLB_USIO_SSR_ORE)
+			port->icount.overrun++;
+		status &= port->read_status_mask;
+		if (status & MLB_USIO_SSR_BRK) {
+			flag = TTY_BREAK;
+			ch = 0;
+		} else
+			if (status & MLB_USIO_SSR_PE) {
+				flag = TTY_PARITY;
+				ch = 0;
+			} else
+				if (status & MLB_USIO_SSR_FRE) {
+					flag = TTY_FRAME;
+					ch = 0;
+				}
+		if (flag)
+			uart_insert_char(port, status, MLB_USIO_SSR_ORE,
+					 ch, flag);
+
+		writeb(readb(port->membase + MLB_USIO_REG_SSR) |
+				MLB_USIO_SSR_REC,
+				port->membase + MLB_USIO_REG_SSR);
+
+		max_count = readw(port->membase + MLB_USIO_REG_FBYTE) >> 8;
+		writew(readw(port->membase + MLB_USIO_REG_FCR) |
+		       MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE,
+		port->membase + MLB_USIO_REG_FCR);
+	}
+
+	tty_flip_buffer_push(ttyport);
+}
+
+static irqreturn_t mlb_usio_rx_irq(int irq, void *dev_id)
+{
+	struct uart_port *port = dev_id;
+
+	spin_lock(&port->lock);
+	mlb_usio_rx_chars(port);
+	spin_unlock(&port->lock);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t mlb_usio_tx_irq(int irq, void *dev_id)
+{
+	struct uart_port *port = dev_id;
+
+	spin_lock(&port->lock);
+	if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
+		mlb_usio_tx_chars(port);
+	spin_unlock(&port->lock);
+
+	return IRQ_HANDLED;
+}
+
+static unsigned int mlb_usio_tx_empty(struct uart_port *port)
+{
+	return (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI) ?
+		TIOCSER_TEMT : 0;
+}
+
+static void mlb_usio_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+}
+
+static unsigned int mlb_usio_get_mctrl(struct uart_port *port)
+{
+	return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
+
+}
+
+static void mlb_usio_break_ctl(struct uart_port *port, int break_state)
+{
+}
+
+static int mlb_usio_startup(struct uart_port *port)
+{
+	const char *portname = to_platform_device(port->dev)->name;
+	unsigned long flags;
+	int ret, index = port->line;
+	unsigned char  escr;
+
+	ret = request_irq(mlb_usio_irq[index][RX], mlb_usio_rx_irq,
+				0, portname, port);
+	if (ret)
+		return ret;
+	ret = request_irq(mlb_usio_irq[index][TX], mlb_usio_tx_irq,
+				0, portname, port);
+	if (ret) {
+		free_irq(mlb_usio_irq[index][RX], port);
+		return ret;
+	}
+
+	escr = readb(port->membase + MLB_USIO_REG_ESCR);
+	if (of_property_read_bool(port->dev->of_node, "uart-flow-enable"))
+		escr |= MLB_USIO_ESCR_FLWEN;
+	spin_lock_irqsave(&port->lock, flags);
+	writeb(0, port->membase + MLB_USIO_REG_SCR);
+	writeb(escr, port->membase + MLB_USIO_REG_ESCR);
+	writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
+	writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
+	writew(0, port->membase + MLB_USIO_REG_FCR);
+	writew(MLB_USIO_FCR_FCL1 | MLB_USIO_FCR_FCL2,
+	       port->membase + MLB_USIO_REG_FCR);
+	writew(MLB_USIO_FCR_FE1 | MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE,
+	       port->membase + MLB_USIO_REG_FCR);
+	writew(0, port->membase + MLB_USIO_REG_FBYTE);
+	writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
+
+	writeb(MLB_USIO_SCR_TXE  | MLB_USIO_SCR_RIE | MLB_USIO_SCR_TBIE |
+	       MLB_USIO_SCR_RXE, port->membase + MLB_USIO_REG_SCR);
+	spin_unlock_irqrestore(&port->lock, flags);
+
+	return 0;
+}
+
+static void mlb_usio_shutdown(struct uart_port *port)
+{
+	int index = port->line;
+
+	free_irq(mlb_usio_irq[index][RX], port);
+	free_irq(mlb_usio_irq[index][TX], port);
+}
+
+static void mlb_usio_set_termios(struct uart_port *port,
+			struct ktermios *termios, struct ktermios *old)
+{
+	unsigned int escr, smr = MLB_USIO_SMR_SOE;
+	unsigned long flags, baud, quot;
+
+	switch (termios->c_cflag & CSIZE) {
+	case CS5:
+		escr = MLB_USIO_ESCR_L_5BIT;
+		break;
+	case CS6:
+		escr = MLB_USIO_ESCR_L_6BIT;
+		break;
+	case CS7:
+		escr = MLB_USIO_ESCR_L_7BIT;
+		break;
+	case CS8:
+	default:
+		escr = MLB_USIO_ESCR_L_8BIT;
+		break;
+	}
+
+	if (termios->c_cflag & CSTOPB)
+		smr |= MLB_USIO_SMR_SBL;
+
+	if (termios->c_cflag & PARENB) {
+		escr |= MLB_USIO_ESCR_PEN;
+		if (termios->c_cflag & PARODD)
+			escr |= MLB_USIO_ESCR_P;
+	}
+	/* Set hard flow control */
+	if (of_property_read_bool(port->dev->of_node, "uart-flow-enable") ||
+			(termios->c_cflag & CRTSCTS))
+		escr |= MLB_USIO_ESCR_FLWEN;
+
+	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
+	if (baud > 1)
+		quot = port->uartclk / baud - 1;
+	else
+		quot = 0;
+
+	spin_lock_irqsave(&port->lock, flags);
+	uart_update_timeout(port, termios->c_cflag, baud);
+	port->read_status_mask = MLB_USIO_SSR_ORE | MLB_USIO_SSR_RDRF |
+				 MLB_USIO_SSR_TDRE;
+	if (termios->c_iflag & INPCK)
+		port->read_status_mask |= MLB_USIO_SSR_FRE | MLB_USIO_SSR_PE;
+
+	port->ignore_status_mask = 0;
+	if (termios->c_iflag & IGNPAR)
+		port->ignore_status_mask |= MLB_USIO_SSR_FRE | MLB_USIO_SSR_PE;
+	if ((termios->c_iflag & IGNBRK) && (termios->c_iflag & IGNPAR))
+		port->ignore_status_mask |= MLB_USIO_SSR_ORE;
+	if ((termios->c_cflag & CREAD) == 0)
+		port->ignore_status_mask |= MLB_USIO_SSR_RDRF;
+
+	writeb(0, port->membase + MLB_USIO_REG_SCR);
+	writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
+	writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
+	writew(0, port->membase + MLB_USIO_REG_FCR);
+	writeb(smr, port->membase + MLB_USIO_REG_SMR);
+	writeb(escr, port->membase + MLB_USIO_REG_ESCR);
+	writew(quot, port->membase + MLB_USIO_REG_BGR);
+	writew(0, port->membase + MLB_USIO_REG_FCR);
+	writew(MLB_USIO_FCR_FCL1 | MLB_USIO_FCR_FCL2 | MLB_USIO_FCR_FE1 |
+	       MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE,
+	       port->membase + MLB_USIO_REG_FCR);
+	writew(0, port->membase + MLB_USIO_REG_FBYTE);
+	writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
+	writeb(MLB_USIO_SCR_RIE | MLB_USIO_SCR_RXE | MLB_USIO_SCR_TBIE |
+	       MLB_USIO_SCR_TXE, port->membase + MLB_USIO_REG_SCR);
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static const char *mlb_usio_type(struct uart_port *port)
+{
+	return ((port->type == PORT_MLB_USIO) ? USIO_NAME : NULL);
+}
+
+static void mlb_usio_config_port(struct uart_port *port, int flags)
+{
+	if (flags & UART_CONFIG_TYPE)
+		port->type = PORT_MLB_USIO;
+}
+
+static const struct uart_ops mlb_usio_ops = {
+	.tx_empty	= mlb_usio_tx_empty,
+	.set_mctrl	= mlb_usio_set_mctrl,
+	.get_mctrl	= mlb_usio_get_mctrl,
+	.stop_tx	= mlb_usio_stop_tx,
+	.start_tx	= mlb_usio_start_tx,
+	.stop_rx	= mlb_usio_stop_rx,
+	.enable_ms	= mlb_usio_enable_ms,
+	.break_ctl	= mlb_usio_break_ctl,
+	.startup	= mlb_usio_startup,
+	.shutdown	= mlb_usio_shutdown,
+	.set_termios	= mlb_usio_set_termios,
+	.type		= mlb_usio_type,
+	.config_port	= mlb_usio_config_port,
+};
+
+#ifdef CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE
+
+static void mlb_usio_console_putchar(struct uart_port *port, int c)
+{
+	while (!(readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TDRE))
+		cpu_relax();
+
+	writew(c, port->membase + MLB_USIO_REG_DR);
+}
+
+static void mlb_usio_console_write(struct console *co, const char *s,
+			       unsigned int count)
+{
+	struct uart_port *port = &mlb_usio_ports[co->index];
+
+	uart_console_write(port, s, count, mlb_usio_console_putchar);
+}
+
+static int __init mlb_usio_console_setup(struct console *co, char *options)
+{
+	struct uart_port *port;
+	int baud = 115200;
+	int parity = 'n';
+	int flow = 'n';
+	int bits = 8;
+
+	if (co->index >= CONFIG_SERIAL_MILBEAUT_USIO_PORTS)
+		return -ENODEV;
+
+	port = &mlb_usio_ports[co->index];
+	if (!port->membase)
+		return -ENODEV;
+
+
+	if (options)
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+
+	if (of_property_read_bool(port->dev->of_node, "uart-flow-enable"))
+		flow = 'r';
+
+	return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+
+static struct uart_driver mlb_usio_uart_driver;
+static struct console mlb_usio_console = {
+	.name   = USIO_UART_DEV_NAME,
+	.write  = mlb_usio_console_write,
+	.device = uart_console_device,
+	.setup  = mlb_usio_console_setup,
+	.flags  = CON_PRINTBUFFER,
+	.index  = -1,
+	.data   = &mlb_usio_uart_driver,
+};
+
+static int __init mlb_usio_console_init(void)
+{
+	register_console(&mlb_usio_console);
+	return 0;
+}
+console_initcall(mlb_usio_console_init);
+
+
+static void mlb_usio_early_console_write(struct console *co, const char *s,
+					u_int count)
+{
+	struct earlycon_device *dev = co->data;
+
+	uart_console_write(&dev->port, s, count, mlb_usio_console_putchar);
+}
+
+static int __init mlb_usio_early_console_setup(struct earlycon_device *device,
+						const char *opt)
+{
+	if (!device->port.membase)
+		return -ENODEV;
+	device->con->write = mlb_usio_early_console_write;
+	return 0;
+}
+
+OF_EARLYCON_DECLARE(mlb_usio, "socionext,milbeaut-usio-uart",
+			mlb_usio_early_console_setup);
+
+#define USIO_CONSOLE	(&mlb_usio_console)
+#else
+#define USIO_CONSOLE	NULL
+#endif
+
+static struct  uart_driver mlb_usio_uart_driver = {
+	.owner		= THIS_MODULE,
+	.driver_name	= USIO_NAME,
+	.dev_name	= USIO_UART_DEV_NAME,
+	.cons           = USIO_CONSOLE,
+	.nr		= CONFIG_SERIAL_MILBEAUT_USIO_PORTS,
+};
+
+static int mlb_usio_probe(struct platform_device *pdev)
+{
+	struct clk *clk = devm_clk_get(&pdev->dev, 0);
+	struct uart_port *port;
+	struct resource *res;
+	int index = 0;
+	int ret;
+
+	if (IS_ERR(clk)) {
+		dev_err(&pdev->dev, "Missing clock\n");
+		return PTR_ERR(clk);
+	}
+	ret = clk_prepare_enable(clk);
+	if (ret) {
+		dev_err(&pdev->dev, "Clock enable failed: %d\n", ret);
+		return ret;
+	}
+	of_property_read_u32(pdev->dev.of_node, "index", &index);
+	port = &mlb_usio_ports[index];
+
+	port->private_data = (void *)clk;
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "Missing regs\n");
+		ret = -ENODEV;
+		goto failed;
+	}
+	port->mapbase = res->start;
+	port->membase = ioremap(res->start, (res->end - res->start + 1));
+	port->membase = devm_ioremap(&pdev->dev, res->start,
+				resource_size(res));
+
+	ret = platform_get_irq_byname(pdev, "rx");
+	mlb_usio_irq[index][RX] = ret;
+
+	ret = platform_get_irq_byname(pdev, "tx");
+	mlb_usio_irq[index][TX] = ret;
+
+	port->irq = mlb_usio_irq[index][RX];
+	port->uartclk = clk_get_rate(clk);
+	port->fifosize = 128;
+	port->iotype = UPIO_MEM32;
+	port->flags = UPF_BOOT_AUTOCONF | UPF_SPD_VHI;
+	port->line = index;
+	port->ops = &mlb_usio_ops;
+	port->dev = &pdev->dev;
+
+	ret = uart_add_one_port(&mlb_usio_uart_driver, port);
+	if (ret) {
+		dev_err(&pdev->dev, "Adding port failed: %d\n", ret);
+		goto failed1;
+	}
+	return 0;
+
+failed1:
+	iounmap(port->membase);
+
+failed:
+	clk_disable_unprepare(clk);
+	clk_put(clk);
+
+	return ret;
+}
+
+static int mlb_usio_remove(struct platform_device *pdev)
+{
+	struct uart_port *port = &mlb_usio_ports[pdev->id];
+	struct clk *clk = port->private_data;
+
+	uart_remove_one_port(&mlb_usio_uart_driver, port);
+	clk_disable_unprepare(clk);
+	clk_put(clk);
+
+	return 0;
+}
+
+static const struct of_device_id mlb_usio_dt_ids[] = {
+	{ .compatible = "socionext,milbeaut-usio-uart" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mlb_usio_dt_ids);
+
+static struct platform_driver mlb_usio_driver = {
+	.probe          = mlb_usio_probe,
+	.remove         = mlb_usio_remove,
+	.driver         = {
+		.name   = USIO_NAME,
+		.of_match_table = mlb_usio_dt_ids,
+	},
+};
+
+static int __init mlb_usio_init(void)
+{
+	int ret = uart_register_driver(&mlb_usio_uart_driver);
+
+	if (ret) {
+		pr_err("%s: uart registration failed: %d\n", __func__, ret);
+		return ret;
+	}
+	ret = platform_driver_register(&mlb_usio_driver);
+	if (ret) {
+		uart_unregister_driver(&mlb_usio_uart_driver);
+		pr_err("%s: drv registration failed: %d\n", __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void __exit mlb_usio_exit(void)
+{
+	platform_driver_unregister(&mlb_usio_driver);
+	uart_unregister_driver(&mlb_usio_uart_driver);
+}
+
+module_init(mlb_usio_init);
+module_exit(mlb_usio_exit);
+
+MODULE_AUTHOR("SOCIONEXT");
+MODULE_DESCRIPTION("MILBEAUT_USIO/UART Driver");
+MODULE_LICENSE("GPL");
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index df4a753..0f8a3bf 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -284,4 +284,7 @@
 /* RDA UART */
 #define PORT_RDA	118
 
+/* Socionext Milbeaut UART */
+#define PORT_MLB_USIO	119
+
 #endif /* _UAPILINUX_SERIAL_CORE_H */
-- 
1.9.1

^ permalink raw reply related

* [PATCH v2 09/15] dt-bindings: serial: Add Milbeaut serial driver description
From: Sugaya Taichi @ 2019-02-08 12:27 UTC (permalink / raw)
  To: linux-serial, devicetree, linux-arm-kernel, linux-kernel
  Cc: Greg Kroah-Hartman, Rob Herring, Mark Rutland, Takao Orito,
	Kazuhiro Kasai, Shinji Kanematsu, Jassi Brar, Masami Hiramatsu,
	Sugaya Taichi

Add DT bindings document for Milbeaut serial driver.

Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com>
---
 .../devicetree/bindings/serial/milbeaut-uart.txt    | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/serial/milbeaut-uart.txt

diff --git a/Documentation/devicetree/bindings/serial/milbeaut-uart.txt b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt
new file mode 100644
index 0000000..8f61c38
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt
@@ -0,0 +1,21 @@
+Socionext Milbeaut UART controller
+
+Required properties:
+- compatible: should be "socionext,milbeaut-usio-uart".
+- reg: offset and length of the register set for the device.
+- interrupts: two interrupts specifier.
+- clocks: phandle to the input clock.
+- interrupt-names: should be "rx", "tx".
+
+Optional properties:
+- uart-flow-enable: flow control enable.
+
+Example:
+	usio1: usio_uart@1e700010 {
+		compatible = "socionext,milbeaut-usio-uart";
+		reg = <0x1e700010 0x10>;
+		interrupts = <0 141 0x4>, <0 149 0x4>;
+		interrupt-names = "rx", "tx";
+		clocks = <&clk 2>;
+		uart-flow-enable;
+	};
-- 
1.9.1

^ permalink raw reply related

* [PATCH v2 00/15] Add basic support for Socionext Milbeaut M10V SoC
From: Sugaya Taichi @ 2019-02-08 12:24 UTC (permalink / raw)
  To: devicetree, linux-kernel, linux-arm-kernel, linux-clk, linux-gpio,
	linux-serial
  Cc: Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd,
	Linus Walleij, Greg Kroah-Hartman, Daniel Lezcano,
	Thomas Gleixner, Russell King, Jiri Slaby, Takao Orito,
	Kazuhiro Kasai, Shinji Kanematsu, Jassi Brar, Masami Hiramatsu,
	Sugaya Taichi

Hi,

Here is the series of patches the initial support for SC2000(M10V) of
Milbeaut SoCs. "M10V" is the internal name of SC2000, so commonly used in
source code.

SC2000 is a SoC of the Milbeaut series. equipped with a DSP optimized for
computer vision. It also features advanced functionalities such as 360-degree,
real-time spherical stitching with multi cameras, image stabilization for
without mechanical gimbals, and rolling shutter correction. More detail is
below:
https://www.socionext.com/en/products/assp/milbeaut/SC2000.html

Specifications for developers are below:
 - Quad-core 32bit Cortex-A7 on ARMv7-A architecture
 - NEON support
 - DSP
 - GPU
 - MAX 3GB DDR3
 - Cortex-M0 for power control
 - NAND Flash Interface
 - SD UHS-I
 - SD UHS-II
 - SDIO
 - USB2.0 HOST / Device
 - USB3.0 HOST / Device
 - PCI express Gen2
 - Ethernet Engine
 - I2C
 - UART
 - SPI
 - PWM

Support is quite minimal for now, since it only includes timer, clock,
pictrl and serial controller drivers, so we can only boot to userspace
through initramfs. Support for the other peripherals  will come eventually.

Changes since v1:
* Change file names.
* Change #define names.
* Refine cpu-enable-method and bindigs.
* Add documentation for Milbeaut SoCs.
* Add more infomation for timer driver.
* Add sched_clock to timer driver.
* Refine whole of clk driver.
* Add earlycon instead of earlyprintk.
* Refine Device Tree.

Sugaya Taichi (15):
  dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram
  dt-bindings: arm: Add SMP enable-method for Milbeaut
  dt-bindings: Add documentation for Milbeaut SoCs
  ARM: milbeaut: Add basic support for Milbeaut m10v SoC
  dt-bindings: timer: Add Milbeaut M10V timer description
  clocksource/drivers/timer-milbeaut: Introduce timer for Milbeaut SoCs
  ndings: clock: milbeaut: add Milbeaut clock description
  clock: milbeaut: Add Milbeaut M10V clock controller
  dt-bindings: serial: Add Milbeaut serial driver description
  serial: Add Milbeaut serial control
  dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description
  pinctrl: milbeaut: Add Milbeaut M10V pinctrl
  ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board
  ARM: configs: Add Milbeaut M10V defconfig
  MAINTAINERS: Add entry to MAINTAINERS for Milbeaut

 Documentation/devicetree/bindings/arm/cpus.yaml    |   1 +
 Documentation/devicetree/bindings/arm/milbeaut.txt |   6 +
 .../devicetree/bindings/clock/milbeaut-clock.txt   |  49 ++
 .../pinctrl/socionext,milbeaut-pinctrl.txt         |  35 +
 .../devicetree/bindings/serial/milbeaut-uart.txt   |  21 +
 .../devicetree/bindings/sram/milbeaut-smp-sram.txt |  24 +
 .../bindings/timer/socionext,milbeaut-timer.txt    |  17 +
 MAINTAINERS                                        |   9 +
 arch/arm/Kconfig                                   |   2 +
 arch/arm/Makefile                                  |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/milbeaut-m10v-evb.dts            |  32 +
 arch/arm/boot/dts/milbeaut-m10v.dtsi               | 131 ++++
 arch/arm/configs/milbeaut_m10v_defconfig           | 366 ++++++++++
 arch/arm/mach-milbeaut/Kconfig                     |  20 +
 arch/arm/mach-milbeaut/Makefile                    |   1 +
 arch/arm/mach-milbeaut/platsmp.c                   | 144 ++++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/clk-milbeaut.c                         | 626 +++++++++++++++++
 drivers/clocksource/Kconfig                        |   9 +
 drivers/clocksource/Makefile                       |   1 +
 drivers/clocksource/timer-milbeaut.c               | 161 +++++
 drivers/pinctrl/Kconfig                            |   9 +
 drivers/pinctrl/Makefile                           |   1 +
 drivers/pinctrl/pinctrl-milbeaut.c                 | 759 +++++++++++++++++++++
 drivers/tty/serial/Kconfig                         |  25 +
 drivers/tty/serial/Makefile                        |   1 +
 drivers/tty/serial/milbeaut_usio.c                 | 621 +++++++++++++++++
 include/uapi/linux/serial_core.h                   |   3 +
 29 files changed, 3077 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/milbeaut.txt
 create mode 100644 Documentation/devicetree/bindings/clock/milbeaut-clock.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/serial/milbeaut-uart.txt
 create mode 100644 Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt
 create mode 100644 Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
 create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dts
 create mode 100644 arch/arm/boot/dts/milbeaut-m10v.dtsi
 create mode 100644 arch/arm/configs/milbeaut_m10v_defconfig
 create mode 100644 arch/arm/mach-milbeaut/Kconfig
 create mode 100644 arch/arm/mach-milbeaut/Makefile
 create mode 100644 arch/arm/mach-milbeaut/platsmp.c
 create mode 100644 drivers/clk/clk-milbeaut.c
 create mode 100644 drivers/clocksource/timer-milbeaut.c
 create mode 100644 drivers/pinctrl/pinctrl-milbeaut.c
 create mode 100644 drivers/tty/serial/milbeaut_usio.c

-- 
1.9.1

^ permalink raw reply

* Re: [RFC/PATCH 0/5] DVFS in the OPP core
From: Viresh Kumar @ 2019-02-08 10:33 UTC (permalink / raw)
  To: Ulf Hansson
  Cc: Stephen Boyd, Graham Roff, Mike Turquette,
	Linux Kernel Mailing List, linux-arm-msm, Linux PM, linux-serial,
	linux-spi, Rajendra Nayak, Doug Anderson, Vincent Guittot
In-Reply-To: <CAPDyKFpmZNW7KgsgagD_6tKTQ07AJS7Kc=AGCQmMpNASuOG-Dg@mail.gmail.com>

On 08-02-19, 11:31, Ulf Hansson wrote:
> On Fri, 8 Feb 2019 at 11:05, Viresh Kumar <viresh.kumar@linaro.org> wrote:
> >
> > On 08-02-19, 10:45, Ulf Hansson wrote:
> > > On Fri, 8 Feb 2019 at 08:17, Viresh Kumar <viresh.kumar@linaro.org> wrote:
> > > >
> > > > On 07-02-19, 14:37, Ulf Hansson wrote:
> > > > > I think we also need to consider cross SoC drivers. One SoC may have
> > > > > both clocks and OPPs to manage, while another may have only clocks.
> > > >
> > > > We already have that case with CPUs as well and dev_pm_opp_set_rate()
> > > > takes care of it.
> > >
> > > I think you may have misunderstood my point. Or maybe I don't get yours. :-)
> >
> > It was me. I thought you are talking about regulators and that is what
> > is already managed, i.e. to work with or without regulators.
> >
> > > What if there is no OPP at all to use, then dev_pm_opp_set_rate() is
> > > just a noop, right? In this scenario the driver still need to call
> > > clk_set_rate().
> > >
> > > How do we cope with these cases?
> >
> > Yeah, that would be a problem and hacking the OPP core may not be the
> > right solution :(
> 
> I guess one simple way forward could just be to check if there is an
> OPP handle/table available, then use dev_pm_opp_set_rate(). When no
> OPP handle/table, use clk_set_rate() *instead*, not both.
> 
> That could work, don't you think?

Yeah, just that it adds more conditional code in drivers, while we
wanted to make them light-weight :)

-- 
viresh

^ permalink raw reply

* Re: [RFC/PATCH 0/5] DVFS in the OPP core
From: Ulf Hansson @ 2019-02-08 10:31 UTC (permalink / raw)
  To: Viresh Kumar
  Cc: Stephen Boyd, Graham Roff, Mike Turquette,
	Linux Kernel Mailing List, linux-arm-msm, Linux PM, linux-serial,
	linux-spi, Rajendra Nayak, Doug Anderson, Vincent Guittot
In-Reply-To: <20190208100529.l2y75ua3bfa6nnyx@vireshk-i7>

On Fri, 8 Feb 2019 at 11:05, Viresh Kumar <viresh.kumar@linaro.org> wrote:
>
> On 08-02-19, 10:45, Ulf Hansson wrote:
> > On Fri, 8 Feb 2019 at 08:17, Viresh Kumar <viresh.kumar@linaro.org> wrote:
> > >
> > > On 07-02-19, 14:37, Ulf Hansson wrote:
> > > > I think we also need to consider cross SoC drivers. One SoC may have
> > > > both clocks and OPPs to manage, while another may have only clocks.
> > >
> > > We already have that case with CPUs as well and dev_pm_opp_set_rate()
> > > takes care of it.
> >
> > I think you may have misunderstood my point. Or maybe I don't get yours. :-)
>
> It was me. I thought you are talking about regulators and that is what
> is already managed, i.e. to work with or without regulators.
>
> > What if there is no OPP at all to use, then dev_pm_opp_set_rate() is
> > just a noop, right? In this scenario the driver still need to call
> > clk_set_rate().
> >
> > How do we cope with these cases?
>
> Yeah, that would be a problem and hacking the OPP core may not be the
> right solution :(

I guess one simple way forward could just be to check if there is an
OPP handle/table available, then use dev_pm_opp_set_rate(). When no
OPP handle/table, use clk_set_rate() *instead*, not both.

That could work, don't you think?

Kind regards
Uffe

^ permalink raw reply

* Re: [RFC/PATCH 0/5] DVFS in the OPP core
From: Viresh Kumar @ 2019-02-08 10:05 UTC (permalink / raw)
  To: Ulf Hansson
  Cc: Stephen Boyd, Graham Roff, Mike Turquette,
	Linux Kernel Mailing List, linux-arm-msm, Linux PM, linux-serial,
	linux-spi, Rajendra Nayak, Doug Anderson, Vincent Guittot
In-Reply-To: <CAPDyKFrXWAzDChd3d2acQnF6GZw57+g6XeNtHo29q3i1qjidnQ@mail.gmail.com>

On 08-02-19, 10:45, Ulf Hansson wrote:
> On Fri, 8 Feb 2019 at 08:17, Viresh Kumar <viresh.kumar@linaro.org> wrote:
> >
> > On 07-02-19, 14:37, Ulf Hansson wrote:
> > > I think we also need to consider cross SoC drivers. One SoC may have
> > > both clocks and OPPs to manage, while another may have only clocks.
> >
> > We already have that case with CPUs as well and dev_pm_opp_set_rate()
> > takes care of it.
> 
> I think you may have misunderstood my point. Or maybe I don't get yours. :-)

It was me. I thought you are talking about regulators and that is what
is already managed, i.e. to work with or without regulators.

> What if there is no OPP at all to use, then dev_pm_opp_set_rate() is
> just a noop, right? In this scenario the driver still need to call
> clk_set_rate().
> 
> How do we cope with these cases?

Yeah, that would be a problem and hacking the OPP core may not be the
right solution :(

-- 
viresh

^ permalink raw reply

* Re: [RFC/PATCH 0/5] DVFS in the OPP core
From: Ulf Hansson @ 2019-02-08  9:45 UTC (permalink / raw)
  To: Viresh Kumar
  Cc: Stephen Boyd, Graham Roff, Mike Turquette,
	Linux Kernel Mailing List, linux-arm-msm, Linux PM, linux-serial,
	linux-spi, Rajendra Nayak, Doug Anderson, Vincent Guittot
In-Reply-To: <20190208071726.urevxs5a3vaf7gwh@vireshk-i7>

On Fri, 8 Feb 2019 at 08:17, Viresh Kumar <viresh.kumar@linaro.org> wrote:
>
> On 07-02-19, 14:37, Ulf Hansson wrote:
> > I think we also need to consider cross SoC drivers. One SoC may have
> > both clocks and OPPs to manage, while another may have only clocks.
>
> We already have that case with CPUs as well and dev_pm_opp_set_rate()
> takes care of it.

I think you may have misunderstood my point. Or maybe I don't get yours. :-)

What if there is no OPP at all to use, then dev_pm_opp_set_rate() is
just a noop, right? In this scenario the driver still need to call
clk_set_rate().

How do we cope with these cases?

>
> > Even it this may be fairly uncommon, we should consider it, before we
> > decide to fold in additional clock management, like
> > clk_prepare|unprepare() for example, behind the dev_pm_opp_set_rate()
> > API.
> >
> > The point is, the driver may need to call clk_prepare|enable()
> > anyways, unless we make that conditional depending on a DT compatible
> > string, for example. Of course, because the clock prepare/enable is
> > reference counted, there may not be a problem in practice to have both
> > the OPP and driver to deal with it.
>

Kind regards
Uffe

^ permalink raw reply

* [GIT PULL] TTY/Serial fixes for 5.0-rc6
From: Greg KH @ 2019-02-08  8:38 UTC (permalink / raw)
  To: Linus Torvalds
  Cc: Jiri Slaby, Stephen Rothwell, Andrew Morton, linux-kernel,
	linux-serial

The following changes since commit f17b5f06cb92ef2250513a1e154c47b78df07d40:

  Linux 5.0-rc4 (2019-01-27 15:18:05 -0800)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tags/tty-5.0-rc6

for you to fetch changes up to fedb5760648a291e949f2380d383b5b2d2749b5e:

  serial: fix race between flush_to_ldisc and tty_open (2019-01-31 19:43:04 +0100)

----------------------------------------------------------------
TTY/Serial fixes for 5.0-rc6

Here are some small tty and serial fixes for 5.0-rc6.

Nothing huge, just a few small fixes for reported issues.  The speakup
fix is in here as it is a tty operation issue.

All of these have been in linux-next for a while with no reported
problems.

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

----------------------------------------------------------------
Andy Shevchenko (1):
      serial: 8250_pci: Make PCI class test non fatal

Chris Brandt (1):
      serial: sh-sci: Do not free irqs that have already been freed

Greg Kroah-Hartman (1):
      serial: fix race between flush_to_ldisc and tty_open

Gustavo A. R. Silva (1):
      tty: serial: 8250_mtk: Fix potential NULL pointer dereference

Johan Hovold (1):
      staging: speakup: fix tty-operation NULL derefs

 drivers/staging/speakup/spk_ttyio.c | 6 ++++--
 drivers/tty/serial/8250/8250_mtk.c  | 3 +++
 drivers/tty/serial/8250/8250_pci.c  | 9 +++++----
 drivers/tty/serial/serial_core.c    | 6 ++++++
 drivers/tty/serial/sh-sci.c         | 9 ++++++++-
 5 files changed, 26 insertions(+), 7 deletions(-)

^ permalink raw reply

* Re: [RFC/PATCH 0/5] DVFS in the OPP core
From: Viresh Kumar @ 2019-02-08  7:17 UTC (permalink / raw)
  To: Ulf Hansson
  Cc: Stephen Boyd, Graham Roff, Mike Turquette,
	Linux Kernel Mailing List, linux-arm-msm, Linux PM, linux-serial,
	linux-spi, Rajendra Nayak, Doug Anderson, Vincent Guittot
In-Reply-To: <CAPDyKFrrncpfEfbZJ1LHvqDbkc29CaJxZnXwh4Mz7PT6Efbctg@mail.gmail.com>

On 07-02-19, 14:37, Ulf Hansson wrote:
> I think we also need to consider cross SoC drivers. One SoC may have
> both clocks and OPPs to manage, while another may have only clocks.

We already have that case with CPUs as well and dev_pm_opp_set_rate()
takes care of it.

> Even it this may be fairly uncommon, we should consider it, before we
> decide to fold in additional clock management, like
> clk_prepare|unprepare() for example, behind the dev_pm_opp_set_rate()
> API.
> 
> The point is, the driver may need to call clk_prepare|enable()
> anyways, unless we make that conditional depending on a DT compatible
> string, for example. Of course, because the clock prepare/enable is
> reference counted, there may not be a problem in practice to have both
> the OPP and driver to deal with it.

-- 
viresh

^ permalink raw reply

* Re: [RFC/PATCH 0/5] DVFS in the OPP core
From: Viresh Kumar @ 2019-02-08  7:14 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: grahamr, mturquette, linux-kernel, linux-arm-msm, linux-pm,
	linux-serial, linux-spi, Rajendra Nayak, Ulf Hansson,
	Doug Anderson, vincent.guittot
In-Reply-To: <154952629766.115909.11259861549408107064@swboyd.mtv.corp.google.com>

On 06-02-19, 23:58, Stephen Boyd wrote:
> Quoting Viresh Kumar (2019-01-31 01:23:49)
> > FWIW, I suggested exactly this solution sometime back [1]
> > 
> > - Drivers need to use two API sets to change clock rate (OPP helpers)
> >   and enable/disable them (CLK framework helpers) and this leads us to
> >   exactly that combination. Is that acceptable ? It doesn't look great
> >   to me as well..
> 
> Agreed. I don't think anyone thinks this looks great, but I'll argue
> that it's improving OPP for devices that already use it so that we can
> remove voltage requirements when their clk is off. Think about CPUs that
> are in their own clk domain where we want to remove the voltage
> requirement when those CPUs are offline, or a GPU that wants to remove
> its voltage requirement when it turns off clks. The combination is
> already out there, just OPP hasn't solved this problem.
> 
> The only other plan I had was to implement another API like
> dev_pm_set_state() or something like that and have that do something
> like what the OPP rate API does right now. The main difference being
> that the argument to the function would be some opaque u64 that's
> converted by the bus/class/genpd attached to the device into whatever
> frequency/voltage/performance state is desired (and sequenced in the
> right order too). And then I was thinking that runtime PM or explicit
> dev_pm_set_state() calls would be used to tell this new layer that the
> device was going to a lower power mode with some other number (sub-kHz
> integer?) and have that be translated again into some
> frequency/voltage/performance state.
> 
> Either way, each driver will have to change from using the clk APIs to
> changes rates to something else like one of these APIs, so I don't see a
> huge difference. Drivers will have to change.

I agree, that's why I wrote the dev_pm_opp_set_rate() API initially.

> > 
> > - Do we expect the callers will disable clk before calling
> >   opp-set-rate with 0 ? We should remove the regulator requirements as
> >   well along with perf-state.
> 
> Yes, that's the plan. Problems come along with this though, like shared
> resource constraints and actually knowing the clk on/off state,
> frequency, voltage, etc. at boot time and making sure to keep those
> constraints satisfied during normal operation.

But that isn't any different from drivers doing clk_disable directly,
right ? So that shouldn't worry us.

> > - What about enabling/disabling clock as well from OPP framework. We
> >   can enable it on the very first call to opp-set-rate and disable
> >   when freq is 0. That will simplify the drivers as well.
> 
> It works when those drivers aren't calling clk_disable() directly from
> some irq handler. I don't think that's very common, but in those cases
> we would probably want to allow drivers to quickly gate and ungate their
> clks but then defer the sleeping stuff (voltages and off chip clks) to
> the schedulable contexts. We'll still be left with a small number of
> drivers that want to only call clk_prepare() and clk_unprepare() from
> within OPP and keep calling clk_enable() and clk_disable() from their
> driver. So introduce different APIs for those drivers to indicate this
> to OPP? And only do that when it becomes a requirement?

I am not sure I understood this well. The reference counting within
clk/regulator should let both the layers (driver and opp core) work
just fine. Why would a driver don't want OPP core to call
clk_prepare_enable() all the time ?

> Otherwise I don't really see a problem with the OPP call handling the
> enable state of the clk as well.

Right, so I would like that to be part of this series when this gets
implemented.

> > > One nice feature of this approach is that we don't need to change the
> > > OPP binding to support this. We can specify only the max frequencies and
> > > the voltage requirements in DT with the existing binding and slightly
> > > tweak the OPP code to achieve these results. 
> > > 
> > > This series includes a conversion of the uart and spi drivers on
> > > qcom sdm845 where these patches are being developed. It shows how a
> > > driver is converted from the clk APIs to the OPP APIs and how
> > > enable/disable state of the clk is communicated to the OPP layer.
> > > 
> > > Some open topics and initial points for discussion are:
> > > 
> > > 1) The dev_pm_opp_set_rate() API changes may break something that's 
> > > relying on the rate rounding that OPP provides. If those exist,
> > > we may need to implement another API that is more explicit about using
> > > the clk API instead of the OPP tables.

I don't remember any such cases, I may have forgotten about those
though.

> > > 2) dev_pm_opp_set_rate(0) is an interesting solution to the problem of
> > > dropping the rate requirement. Is there anything better than this?

I am okay with it. I don't want to invent another set of APIs to
enable / disable the resources.

> > > 3) How do we handle devices that already have power-domains specified in
> > > DT? The opp binding for required-opps doesn't let us specify the power
> > > domain to target, instead it assumes that whatever power domain is
> > > attached to a device is the one that OPP needs to use to change the
> > > genpd performance state. Do we need a
> > > dev_pm_opp_set_required_opps_name() or something to be explicit about

Yeah, we may need to come up with something like this eventually. I
had written something like that earlier, but then it wasn't required.

> > > this? Can we have some way for the power domain that required-opps
> > > correspond to be expressed in the OPP tables themselves?

Not sure I understood it. Can you explain with some example please ?

> > > 4) How do we achieve the "full constraint" state? i.e. what do we do
> > > about some devices being active and others being inactive during boot
> > > and making sure that the voltage for the shared power domains doesn't
> > > drop until all devices requiring it have informed OPP about their
> > > power requirements?

We need the boot-constraint framework for that. I think this is a
problem which we have currently as well. I am waiting for the
bus-scaling framework to get in, after that we will have lot of cases
where boot-constraints would be required and it won't be limited to
just clcd then.

-- 
viresh

^ permalink raw reply

* Re: [RFC/PATCH 0/5] DVFS in the OPP core
From: Rajendra Nayak @ 2019-02-08  4:39 UTC (permalink / raw)
  To: Stephen Boyd, linux-kernel
  Cc: linux-arm-msm, linux-pm, linux-serial, linux-spi, Ulf Hansson,
	Viresh Kumar, Doug Anderson
In-Reply-To: <154956885472.115909.8681514480591552850@swboyd.mtv.corp.google.com>



On 2/8/2019 1:17 AM, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2019-02-06 22:57:12)
>>
>>> 3) How do we handle devices that already have power-domains specified in
>>> DT? The opp binding for required-opps doesn't let us specify the power
>>> domain to target, instead it assumes that whatever power domain is
>>> attached to a device is the one that OPP needs to use to change the
>>> genpd performance state. Do we need a
>>> dev_pm_opp_set_required_opps_name() or something to be explicit about
>>> this? Can we have some way for the power domain that required-opps
>>> correspond to be expressed in the OPP tables themselves?
>>
>> I was converting a few more drivers to use the proposed approach in this
>> RFC, in order to identify all outstanding issues we need to deal with,
>> and specifically for UFS, I end up with this exact scenario where UFS already
>> has an existing power domain (gdsc) and I need to add another one (rpmhpd) for
>> setting the performance state.
>>
>> If I use dev_pm_opp_of_add_table() to add the opp table from DT, the opp
>> layer assumes its the same device on which it can do a dev_pm_genpd_set_performance_state()
>> with, however the device that's actually associated with the pm_domain when we
>> have multiple power domains is infact the one (dummy) that we create when
>> the driver makes a call to dev_pm_domain_attach_by_name/id().
>>
>> Any thoughts on whats a good way to handle this?
>>
> 
> Ulf mentioned that we can use dev_pm_opp_set_genpd_virt_dev() for this.
> Does that API work here?

Ah, yes, that should work, I hadn't noticed this API existed.

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply

* Re: [RFC/PATCH 0/5] DVFS in the OPP core
From: Stephen Boyd @ 2019-02-07 19:47 UTC (permalink / raw)
  To: Rajendra Nayak, linux-kernel
  Cc: linux-arm-msm, linux-pm, linux-serial, linux-spi, Ulf Hansson,
	Viresh Kumar, Doug Anderson
In-Reply-To: <7af27aa5-3ff6-d4ee-1dc0-bac797c2bdbc@codeaurora.org>

Quoting Rajendra Nayak (2019-02-06 22:57:12)
> 
> > 3) How do we handle devices that already have power-domains specified in
> > DT? The opp binding for required-opps doesn't let us specify the power
> > domain to target, instead it assumes that whatever power domain is
> > attached to a device is the one that OPP needs to use to change the
> > genpd performance state. Do we need a
> > dev_pm_opp_set_required_opps_name() or something to be explicit about
> > this? Can we have some way for the power domain that required-opps
> > correspond to be expressed in the OPP tables themselves?
> 
> I was converting a few more drivers to use the proposed approach in this
> RFC, in order to identify all outstanding issues we need to deal with,
> and specifically for UFS, I end up with this exact scenario where UFS already
> has an existing power domain (gdsc) and I need to add another one (rpmhpd) for
> setting the performance state.
> 
> If I use dev_pm_opp_of_add_table() to add the opp table from DT, the opp
> layer assumes its the same device on which it can do a dev_pm_genpd_set_performance_state()
> with, however the device that's actually associated with the pm_domain when we
> have multiple power domains is infact the one (dummy) that we create when
> the driver makes a call to dev_pm_domain_attach_by_name/id().
> 
> Any thoughts on whats a good way to handle this?
> 

Ulf mentioned that we can use dev_pm_opp_set_genpd_virt_dev() for this.
Does that API work here?

^ permalink raw reply

* [PATCH v2] tty: serial: meson_uart: Add support for kernel debugger
From: Julien Masson @ 2019-02-07 17:11 UTC (permalink / raw)
  To: Kevin Hilman, Greg Kroah-Hartman
  Cc: linux-amlogic, linux-arm-kernel, linux-serial, Jiri Slaby,
	Julien Masson, linux-kernel

The kgdb invokes the poll_put_char and poll_get_char when communicating
with the host. This patch implement the serial polling hooks for the
meson_uart to be used for KGDB debugging over serial line.

Signed-off-by: Julien Masson <jmasson@baylibre.com>
---

Changes since v1 [0]:
* Use readl_poll_timeout_atomic instead of looping with read + cpu_relax
  -> read every 5 usecs during 1 msec
* add some comments

[0]: https://lore.kernel.org/lkml/1549015162-17418-1-git-send-email-jmasson@baylibre.com

 drivers/tty/serial/meson_uart.c | 65 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)

diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c
index 8a84259..bcff572 100644
--- a/drivers/tty/serial/meson_uart.c
+++ b/drivers/tty/serial/meson_uart.c
@@ -14,6 +14,7 @@
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/iopoll.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/of.h>
@@ -75,6 +76,8 @@
 #define AML_UART_PORT_NUM		6
 #define AML_UART_DEV_NAME		"ttyAML"
 
+#define AML_UART_POLL_USEC		5
+#define AML_UART_TIMEOUT_USEC		1000
 
 static struct uart_driver meson_uart_driver;
 
@@ -426,6 +429,64 @@ static void meson_uart_config_port(struct uart_port *port, int flags)
 	}
 }
 
+#ifdef CONFIG_CONSOLE_POLL
+/*
+ * Console polling routines for writing and reading from the uart while
+ * in an interrupt or debug context (i.e. kgdb).
+ */
+
+static int meson_uart_poll_get_char(struct uart_port *port)
+{
+	u32 c;
+	unsigned long flags;
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	if (readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)
+		c = NO_POLL_CHAR;
+	else
+		c = readl(port->membase + AML_UART_RFIFO);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+
+	return c;
+}
+
+static void meson_uart_poll_put_char(struct uart_port *port, unsigned char c)
+{
+	unsigned long flags;
+	u32 reg;
+	int ret;
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	/* Wait until FIFO is empty or timeout */
+	ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg,
+					reg & AML_UART_TX_EMPTY,
+					AML_UART_POLL_USEC,
+					AML_UART_TIMEOUT_USEC);
+	if (ret == -ETIMEDOUT) {
+		dev_err(port->dev, "Timeout waiting for UART TX EMPTY\n");
+		goto out;
+	}
+
+	/* Write the character */
+	writel(c, port->membase + AML_UART_WFIFO);
+
+	/* Wait until FIFO is empty or timeout */
+	ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg,
+					reg & AML_UART_TX_EMPTY,
+					AML_UART_POLL_USEC,
+					AML_UART_TIMEOUT_USEC);
+	if (ret == -ETIMEDOUT)
+		dev_err(port->dev, "Timeout waiting for UART TX EMPTY\n");
+
+out:
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+#endif /* CONFIG_CONSOLE_POLL */
+
 static const struct uart_ops meson_uart_ops = {
 	.set_mctrl      = meson_uart_set_mctrl,
 	.get_mctrl      = meson_uart_get_mctrl,
@@ -441,6 +502,10 @@ static const struct uart_ops meson_uart_ops = {
 	.request_port	= meson_uart_request_port,
 	.release_port	= meson_uart_release_port,
 	.verify_port	= meson_uart_verify_port,
+#ifdef CONFIG_CONSOLE_POLL
+	.poll_get_char	= meson_uart_poll_get_char,
+	.poll_put_char	= meson_uart_poll_put_char,
+#endif
 };
 
 #ifdef CONFIG_SERIAL_MESON_CONSOLE
-- 
2.7.4

^ permalink raw reply related

* Re: [PATCH] tty: serial: meson_uart: Add support for kernel debugger
From: Masson, Julien @ 2019-02-07 17:04 UTC (permalink / raw)
  To: Corentin Labbe
  Cc: Julien Masson, Greg Kroah-Hartman, linux-kernel, Kevin Hilman,
	linux-serial, Jiri Slaby, linux-amlogic, linux-arm-kernel
In-Reply-To: <20190201101056.GA10039@Red>


On Fri 01 Feb 2019 at 11:10, Corentin Labbe <clabbe.montjoie@gmail.com> wrote:

> On Fri, Feb 01, 2019 at 10:59:22AM +0100, Julien Masson wrote:
>> The kgdb invokes the poll_put_char and poll_get_char when communicating
>> with the host. This patch implement the serial polling hooks for the
>> meson_uart to be used for KGDB debugging over serial line.
>> 
>> Signed-off-by: Julien Masson <jmasson@baylibre.com>
>> ---
>> It has been tested on "Le Potato" board:
>> https://libre.computer/products/boards/aml-s905x-cc/
>> 
>> Kernel command line arguments:
>> kgdboc=ttyAML0,115200 kgdbretry=4 nokaslr kgdbcon
>> 
>> Kernel modules:
>> CONFIG_DEBUG_INFO=y
>> CONFIG_DEBUG_KERNEL=y
>> CONFIG_FRAME_POINTER=y
>> CONFIG_KGDB=y
>> CONFIG_KGDB_SERIAL_CONSOLE=y
>> 
>> Warning: for single step instruction I had to apply this patch:
>> https://lore.kernel.org/patchwork/patch/562423/
>> 
>>  drivers/tty/serial/meson_uart.c | 46 +++++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 46 insertions(+)
>> 
>> diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c
>> index 8a84259..49b20da 100644
>> --- a/drivers/tty/serial/meson_uart.c
>> +++ b/drivers/tty/serial/meson_uart.c
>> @@ -426,6 +426,48 @@ static void meson_uart_config_port(struct uart_port *port, int flags)
>>  	}
>>  }
>>  
>> +#ifdef CONFIG_CONSOLE_POLL
>> +/*
>> + * Console polling routines for writing and reading from the uart while
>> + * in an interrupt or debug context (i.e. kgdb).
>> + */
>> +
>> +static int meson_uart_poll_get_char(struct uart_port *port)
>> +{
>> +	u32 c;
>> +	unsigned long flags;
>> +
>> +	spin_lock_irqsave(&port->lock, flags);
>> +
>> +	if (readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)
>> +		c = NO_POLL_CHAR;
>> +	else
>> +		c = readl(port->membase + AML_UART_RFIFO);
>> +
>> +	spin_unlock_irqrestore(&port->lock, flags);
>> +
>> +	return c;
>> +}
>> +
>> +static void meson_uart_poll_put_char(struct uart_port *port, unsigned char c)
>> +{
>> +	unsigned long flags;
>> +
>> +	spin_lock_irqsave(&port->lock, flags);
>> +
>> +	while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_EMPTY))
>> +		cpu_relax();
>
> Hello
>
> Perhaps you could use read_poll_timeout() ?
> This will also permit to handle the timeout case.
>
> Regards

Thanks for the tips Corentin.

I tested with a poll of 5 usec and 1 msec of timeout.
I had to use readl_poll_timeout_atomic(...) since I'm in atomic context
(spinlock).

I'll send a v2 of this patch.

Regards

^ permalink raw reply

* Re: [PATCH v6 1/6] irqchip/mtk-sysirq: support 4 interrupt parameters for sysirq
From: Marc Zyngier @ 2019-02-07 15:52 UTC (permalink / raw)
  To: Matthias Brugger, Erin Lo, Rob Herring, Mark Rutland,
	Thomas Gleixner, Jason Cooper, Greg Kroah-Hartman, Stephen Boyd
  Cc: devicetree, srv_heupstream, linux-kernel, linux-serial,
	linux-mediatek, linux-arm-kernel, yingjoe.chen, mars.cheng,
	eddie.huang, linux-clk, Seiya Wang
In-Reply-To: <626b5b46-aac7-1532-386e-2fed85bf4ad9@arm.com>

On 07/02/2019 15:47, Marc Zyngier wrote:
> On 07/02/2019 15:20, Matthias Brugger wrote:
>>
>>
>> On 24/01/2019 09:07, Erin Lo wrote:
>>> From: Seiya Wang <seiya.wang@mediatek.com>
>>>
>>> To support partitioned PPIs, 4 interrupt parameters should be valid
>>> for sysirq.
>>>
>>> Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
>>> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
>>> ---
>>>  drivers/irqchip/irq-mtk-sysirq.c | 4 ++--
>>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/irqchip/irq-mtk-sysirq.c b/drivers/irqchip/irq-mtk-sysirq.c
>>> index 90aaf19..282736a 100644
>>> --- a/drivers/irqchip/irq-mtk-sysirq.c
>>> +++ b/drivers/irqchip/irq-mtk-sysirq.c
>>> @@ -81,7 +81,7 @@ static int mtk_sysirq_domain_translate(struct irq_domain *d,
>>>  				       unsigned int *type)
>>>  {
>>>  	if (is_of_node(fwspec->fwnode)) {
>>> -		if (fwspec->param_count != 3)
>>> +		if (fwspec->param_count != 3 && fwspec->param_count != 4)
>>
>> Where is this 4th parameter used?
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt#n14
Sorry, I fired Send way too early.

What I wanted to add is that it is not clear to me why this change would
be required here, as this driver only supports SPIs. It could be fixed
by just relaxing the binding itself.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

^ permalink raw reply

* Re: [PATCH v6 1/6] irqchip/mtk-sysirq: support 4 interrupt parameters for sysirq
From: Marc Zyngier @ 2019-02-07 15:47 UTC (permalink / raw)
  To: Matthias Brugger, Erin Lo, Rob Herring, Mark Rutland,
	Thomas Gleixner, Jason Cooper, Greg Kroah-Hartman, Stephen Boyd
  Cc: devicetree, srv_heupstream, linux-kernel, linux-serial,
	linux-mediatek, linux-arm-kernel, yingjoe.chen, mars.cheng,
	eddie.huang, linux-clk, Seiya Wang
In-Reply-To: <898ca3d9-002b-e28e-fc97-86bc2538e9de@gmail.com>

On 07/02/2019 15:20, Matthias Brugger wrote:
> 
> 
> On 24/01/2019 09:07, Erin Lo wrote:
>> From: Seiya Wang <seiya.wang@mediatek.com>
>>
>> To support partitioned PPIs, 4 interrupt parameters should be valid
>> for sysirq.
>>
>> Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
>> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
>> ---
>>  drivers/irqchip/irq-mtk-sysirq.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/irqchip/irq-mtk-sysirq.c b/drivers/irqchip/irq-mtk-sysirq.c
>> index 90aaf19..282736a 100644
>> --- a/drivers/irqchip/irq-mtk-sysirq.c
>> +++ b/drivers/irqchip/irq-mtk-sysirq.c
>> @@ -81,7 +81,7 @@ static int mtk_sysirq_domain_translate(struct irq_domain *d,
>>  				       unsigned int *type)
>>  {
>>  	if (is_of_node(fwspec->fwnode)) {
>> -		if (fwspec->param_count != 3)
>> +		if (fwspec->param_count != 3 && fwspec->param_count != 4)
> 
> Where is this 4th parameter used?

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt#n14

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

^ permalink raw reply

* Re: [PATCH v6 6/6] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile
From: Matthias Brugger @ 2019-02-07 15:30 UTC (permalink / raw)
  To: Erin Lo, Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Marc Zyngier, Greg Kroah-Hartman, Stephen Boyd
  Cc: devicetree, srv_heupstream, linux-kernel, linux-serial,
	linux-mediatek, linux-arm-kernel, yingjoe.chen, mars.cheng,
	eddie.huang, linux-clk, Ben Ho, Seiya Wang, Zhiyong Tao, Weiyi Lu,
	Mengqi Zhang, Hsin-Hsiung Wang
In-Reply-To: <1548317240-44682-7-git-send-email-erin.lo@mediatek.com>



On 24/01/2019 09:07, Erin Lo wrote:
> From: Ben Ho <Ben.Ho@mediatek.com>
> 
> Add basic chip support for Mediatek 8183, include
> pinctrl file, uart node with correct uart clocks, pwrap device
> 
> Add clock controller nodes, include topckgen, infracfg,
> apmixedsys and subsystem.
> 
> Signed-off-by: Ben Ho <Ben.Ho@mediatek.com>
> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
> Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/Makefile         |    1 +
>  arch/arm64/boot/dts/mediatek/mt8183-evb.dts   |  136 +++
>  arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h | 1120 +++++++++++++++++++++++++

Would you mind to make the pinfunc.h a seperate patch and adding the pinctrl
maintainers to the list.

Regards,
Matthias

>  arch/arm64/boot/dts/mediatek/mt8183.dtsi      |  408 +++++++++
>  4 files changed, 1665 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi
> 
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index e8f952f..458bbc4 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> new file mode 100644
> index 0000000..b12c6ea
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> @@ -0,0 +1,136 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Ben Ho <ben.ho@mediatek.com>
> + *	   Erin Lo <erin.lo@mediatek.com>
> + */
> +
> +/dts-v1/;
> +#include "mt8183.dtsi"
> +
> +/ {
> +	model = "MediaTek MT8183 evaluation board";
> +	compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	memory@40000000 {
> +		device_type = "memory";
> +		reg = <0 0x40000000 0 0x80000000>;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:921600n8";
> +	};
> +};
> +
> +&pio {
> +	spi_pins_0: spi0{
> +		pins_spi{
> +			pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
> +				 <PINMUX_GPIO86__FUNC_SPI0_CSB>,
> +				 <PINMUX_GPIO87__FUNC_SPI0_MO>,
> +				 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
> +			bias-disable;
> +		};
> +	};
> +
> +	spi_pins_1: spi1{
> +		pins_spi{
> +			pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
> +				 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
> +				 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
> +				 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
> +			bias-disable;
> +		};
> +	};
> +
> +	spi_pins_2: spi2{
> +		pins_spi{
> +			pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
> +				 <PINMUX_GPIO1__FUNC_SPI2_MO>,
> +				 <PINMUX_GPIO2__FUNC_SPI2_CLK>,
> +				 <PINMUX_GPIO94__FUNC_SPI2_MI>;
> +			bias-disable;
> +		};
> +	};
> +
> +	spi_pins_3: spi3{
> +		pins_spi{
> +			pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
> +				 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
> +				 <PINMUX_GPIO23__FUNC_SPI3_MO>,
> +				 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
> +			bias-disable;
> +		};
> +	};
> +
> +	spi_pins_4: spi4{
> +		pins_spi{
> +			pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
> +				 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
> +				 <PINMUX_GPIO19__FUNC_SPI4_MO>,
> +				 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
> +			bias-disable;
> +		};
> +	};
> +
> +	spi_pins_5: spi5{
> +		pins_spi{
> +			pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
> +				 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
> +				 <PINMUX_GPIO15__FUNC_SPI5_MO>,
> +				 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
> +			bias-disable;
> +		};
> +	};
> +};
> +
> +&spi0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi_pins_0>;
> +	mediatek,pad-select = <0>;
> +	status = "okay";
> +};
> +
> +&spi1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi_pins_1>;
> +	mediatek,pad-select = <0>;
> +	status = "okay";
> +};
> +
> +&spi2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi_pins_2>;
> +	mediatek,pad-select = <0>;
> +	status = "okay";
> +};
> +
> +&spi3 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi_pins_3>;
> +	mediatek,pad-select = <0>;
> +	status = "okay";
> +};
> +
> +&spi4 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi_pins_4>;
> +	mediatek,pad-select = <0>;
> +	status = "okay";
> +};
> +
> +&spi5 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi_pins_5>;
> +	mediatek,pad-select = <0>;
> +	status = "okay";
> +
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
> new file mode 100644
> index 0000000..768e41e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
> @@ -0,0 +1,1120 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 MediaTek Inc.
> + * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
> + *
> + */
> +
> +#ifndef __MT8183_PINFUNC_H
> +#define __MT8183_PINFUNC_H
> +
> +#include <dt-bindings/pinctrl/mt65xx.h>
> +
> +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
> +#define PINMUX_GPIO0__FUNC_MRG_SYNC (MTK_PIN_NO(0) | 1)
> +#define PINMUX_GPIO0__FUNC_PCM0_SYNC (MTK_PIN_NO(0) | 2)
> +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 3)
> +#define PINMUX_GPIO0__FUNC_SRCLKENAI0 (MTK_PIN_NO(0) | 4)
> +#define PINMUX_GPIO0__FUNC_SCP_SPI2_CS (MTK_PIN_NO(0) | 5)
> +#define PINMUX_GPIO0__FUNC_I2S3_MCK (MTK_PIN_NO(0) | 6)
> +#define PINMUX_GPIO0__FUNC_SPI2_CSB (MTK_PIN_NO(0) | 7)
> +
> +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
> +#define PINMUX_GPIO1__FUNC_MRG_CLK (MTK_PIN_NO(1) | 1)
> +#define PINMUX_GPIO1__FUNC_PCM0_CLK (MTK_PIN_NO(1) | 2)
> +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 3)
> +#define PINMUX_GPIO1__FUNC_CLKM3 (MTK_PIN_NO(1) | 4)
> +#define PINMUX_GPIO1__FUNC_SCP_SPI2_MO (MTK_PIN_NO(1) | 5)
> +#define PINMUX_GPIO1__FUNC_I2S3_BCK (MTK_PIN_NO(1) | 6)
> +#define PINMUX_GPIO1__FUNC_SPI2_MO (MTK_PIN_NO(1) | 7)
> +
> +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
> +#define PINMUX_GPIO2__FUNC_MRG_DO (MTK_PIN_NO(2) | 1)
> +#define PINMUX_GPIO2__FUNC_PCM0_DO (MTK_PIN_NO(2) | 2)
> +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 3)
> +#define PINMUX_GPIO2__FUNC_SCL6 (MTK_PIN_NO(2) | 4)
> +#define PINMUX_GPIO2__FUNC_SCP_SPI2_CK (MTK_PIN_NO(2) | 5)
> +#define PINMUX_GPIO2__FUNC_I2S3_LRCK (MTK_PIN_NO(2) | 6)
> +#define PINMUX_GPIO2__FUNC_SPI2_CLK (MTK_PIN_NO(2) | 7)
> +
> +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
> +#define PINMUX_GPIO3__FUNC_MRG_DI (MTK_PIN_NO(3) | 1)
> +#define PINMUX_GPIO3__FUNC_PCM0_DI (MTK_PIN_NO(3) | 2)
> +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 3)
> +#define PINMUX_GPIO3__FUNC_SDA6 (MTK_PIN_NO(3) | 4)
> +#define PINMUX_GPIO3__FUNC_TDM_MCK (MTK_PIN_NO(3) | 5)
> +#define PINMUX_GPIO3__FUNC_I2S3_DO (MTK_PIN_NO(3) | 6)
> +#define PINMUX_GPIO3__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(3) | 7)
> +
> +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
> +#define PINMUX_GPIO4__FUNC_PWM_B (MTK_PIN_NO(4) | 1)
> +#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2)
> +#define PINMUX_GPIO4__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(4) | 3)
> +#define PINMUX_GPIO4__FUNC_MD_URXD1 (MTK_PIN_NO(4) | 4)
> +#define PINMUX_GPIO4__FUNC_TDM_BCK (MTK_PIN_NO(4) | 5)
> +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6)
> +#define PINMUX_GPIO4__FUNC_DAP_MD32_SWD (MTK_PIN_NO(4) | 7)
> +
> +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
> +#define PINMUX_GPIO5__FUNC_PWM_C (MTK_PIN_NO(5) | 1)
> +#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2)
> +#define PINMUX_GPIO5__FUNC_SSPM_URXD_AO (MTK_PIN_NO(5) | 3)
> +#define PINMUX_GPIO5__FUNC_MD_UTXD1 (MTK_PIN_NO(5) | 4)
> +#define PINMUX_GPIO5__FUNC_TDM_LRCK (MTK_PIN_NO(5) | 5)
> +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6)
> +#define PINMUX_GPIO5__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(5) | 7)
> +
> +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
> +#define PINMUX_GPIO6__FUNC_PWM_A (MTK_PIN_NO(6) | 1)
> +#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2)
> +#define PINMUX_GPIO6__FUNC_IDDIG (MTK_PIN_NO(6) | 3)
> +#define PINMUX_GPIO6__FUNC_MD_URXD0 (MTK_PIN_NO(6) | 4)
> +#define PINMUX_GPIO6__FUNC_TDM_DATA0 (MTK_PIN_NO(6) | 5)
> +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6)
> +#define PINMUX_GPIO6__FUNC_CMFLASH (MTK_PIN_NO(6) | 7)
> +
> +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
> +#define PINMUX_GPIO7__FUNC_SPI1_B_MI (MTK_PIN_NO(7) | 1)
> +#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2)
> +#define PINMUX_GPIO7__FUNC_USB_DRVVBUS (MTK_PIN_NO(7) | 3)
> +#define PINMUX_GPIO7__FUNC_MD_UTXD0 (MTK_PIN_NO(7) | 4)
> +#define PINMUX_GPIO7__FUNC_TDM_DATA1 (MTK_PIN_NO(7) | 5)
> +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6)
> +#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 7)
> +
> +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
> +#define PINMUX_GPIO8__FUNC_SPI1_B_CSB (MTK_PIN_NO(8) | 1)
> +#define PINMUX_GPIO8__FUNC_ANT_SEL3 (MTK_PIN_NO(8) | 2)
> +#define PINMUX_GPIO8__FUNC_SCL7 (MTK_PIN_NO(8) | 3)
> +#define PINMUX_GPIO8__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(8) | 4)
> +#define PINMUX_GPIO8__FUNC_TDM_DATA2 (MTK_PIN_NO(8) | 5)
> +#define PINMUX_GPIO8__FUNC_MD_INT0 (MTK_PIN_NO(8) | 6)
> +#define PINMUX_GPIO8__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(8) | 7)
> +
> +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
> +#define PINMUX_GPIO9__FUNC_SPI1_B_MO (MTK_PIN_NO(9) | 1)
> +#define PINMUX_GPIO9__FUNC_ANT_SEL4 (MTK_PIN_NO(9) | 2)
> +#define PINMUX_GPIO9__FUNC_CMMCLK2 (MTK_PIN_NO(9) | 3)
> +#define PINMUX_GPIO9__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(9) | 4)
> +#define PINMUX_GPIO9__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(9) | 5)
> +#define PINMUX_GPIO9__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(9) | 6)
> +#define PINMUX_GPIO9__FUNC_DBG_MON_B10 (MTK_PIN_NO(9) | 7)
> +
> +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
> +#define PINMUX_GPIO10__FUNC_SPI1_B_CLK (MTK_PIN_NO(10) | 1)
> +#define PINMUX_GPIO10__FUNC_ANT_SEL5 (MTK_PIN_NO(10) | 2)
> +#define PINMUX_GPIO10__FUNC_CMMCLK3 (MTK_PIN_NO(10) | 3)
> +#define PINMUX_GPIO10__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(10) | 4)
> +#define PINMUX_GPIO10__FUNC_TDM_DATA3 (MTK_PIN_NO(10) | 5)
> +#define PINMUX_GPIO10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 6)
> +#define PINMUX_GPIO10__FUNC_DBG_MON_B11 (MTK_PIN_NO(10) | 7)
> +
> +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
> +#define PINMUX_GPIO11__FUNC_TP_URXD1_AO (MTK_PIN_NO(11) | 1)
> +#define PINMUX_GPIO11__FUNC_IDDIG (MTK_PIN_NO(11) | 2)
> +#define PINMUX_GPIO11__FUNC_SCL6 (MTK_PIN_NO(11) | 3)
> +#define PINMUX_GPIO11__FUNC_UCTS1 (MTK_PIN_NO(11) | 4)
> +#define PINMUX_GPIO11__FUNC_UCTS0 (MTK_PIN_NO(11) | 5)
> +#define PINMUX_GPIO11__FUNC_SRCLKENAI1 (MTK_PIN_NO(11) | 6)
> +#define PINMUX_GPIO11__FUNC_I2S5_MCK (MTK_PIN_NO(11) | 7)
> +
> +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
> +#define PINMUX_GPIO12__FUNC_TP_UTXD1_AO (MTK_PIN_NO(12) | 1)
> +#define PINMUX_GPIO12__FUNC_USB_DRVVBUS (MTK_PIN_NO(12) | 2)
> +#define PINMUX_GPIO12__FUNC_SDA6 (MTK_PIN_NO(12) | 3)
> +#define PINMUX_GPIO12__FUNC_URTS1 (MTK_PIN_NO(12) | 4)
> +#define PINMUX_GPIO12__FUNC_URTS0 (MTK_PIN_NO(12) | 5)
> +#define PINMUX_GPIO12__FUNC_I2S2_DI2 (MTK_PIN_NO(12) | 6)
> +#define PINMUX_GPIO12__FUNC_I2S5_BCK (MTK_PIN_NO(12) | 7)
> +
> +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
> +#define PINMUX_GPIO13__FUNC_DBPI_D0 (MTK_PIN_NO(13) | 1)
> +#define PINMUX_GPIO13__FUNC_SPI5_MI (MTK_PIN_NO(13) | 2)
> +#define PINMUX_GPIO13__FUNC_PCM0_SYNC (MTK_PIN_NO(13) | 3)
> +#define PINMUX_GPIO13__FUNC_MD_URXD0 (MTK_PIN_NO(13) | 4)
> +#define PINMUX_GPIO13__FUNC_ANT_SEL3 (MTK_PIN_NO(13) | 5)
> +#define PINMUX_GPIO13__FUNC_I2S0_MCK (MTK_PIN_NO(13) | 6)
> +#define PINMUX_GPIO13__FUNC_DBG_MON_B15 (MTK_PIN_NO(13) | 7)
> +
> +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
> +#define PINMUX_GPIO14__FUNC_DBPI_D1 (MTK_PIN_NO(14) | 1)
> +#define PINMUX_GPIO14__FUNC_SPI5_CSB (MTK_PIN_NO(14) | 2)
> +#define PINMUX_GPIO14__FUNC_PCM0_CLK (MTK_PIN_NO(14) | 3)
> +#define PINMUX_GPIO14__FUNC_MD_UTXD0 (MTK_PIN_NO(14) | 4)
> +#define PINMUX_GPIO14__FUNC_ANT_SEL4 (MTK_PIN_NO(14) | 5)
> +#define PINMUX_GPIO14__FUNC_I2S0_BCK (MTK_PIN_NO(14) | 6)
> +#define PINMUX_GPIO14__FUNC_DBG_MON_B16 (MTK_PIN_NO(14) | 7)
> +
> +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
> +#define PINMUX_GPIO15__FUNC_DBPI_D2 (MTK_PIN_NO(15) | 1)
> +#define PINMUX_GPIO15__FUNC_SPI5_MO (MTK_PIN_NO(15) | 2)
> +#define PINMUX_GPIO15__FUNC_PCM0_DO (MTK_PIN_NO(15) | 3)
> +#define PINMUX_GPIO15__FUNC_MD_URXD1 (MTK_PIN_NO(15) | 4)
> +#define PINMUX_GPIO15__FUNC_ANT_SEL5 (MTK_PIN_NO(15) | 5)
> +#define PINMUX_GPIO15__FUNC_I2S0_LRCK (MTK_PIN_NO(15) | 6)
> +#define PINMUX_GPIO15__FUNC_DBG_MON_B17 (MTK_PIN_NO(15) | 7)
> +
> +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
> +#define PINMUX_GPIO16__FUNC_DBPI_D3 (MTK_PIN_NO(16) | 1)
> +#define PINMUX_GPIO16__FUNC_SPI5_CLK (MTK_PIN_NO(16) | 2)
> +#define PINMUX_GPIO16__FUNC_PCM0_DI (MTK_PIN_NO(16) | 3)
> +#define PINMUX_GPIO16__FUNC_MD_UTXD1 (MTK_PIN_NO(16) | 4)
> +#define PINMUX_GPIO16__FUNC_ANT_SEL6 (MTK_PIN_NO(16) | 5)
> +#define PINMUX_GPIO16__FUNC_I2S0_DI (MTK_PIN_NO(16) | 6)
> +#define PINMUX_GPIO16__FUNC_DBG_MON_B23 (MTK_PIN_NO(16) | 7)
> +
> +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
> +#define PINMUX_GPIO17__FUNC_DBPI_D4 (MTK_PIN_NO(17) | 1)
> +#define PINMUX_GPIO17__FUNC_SPI4_MI (MTK_PIN_NO(17) | 2)
> +#define PINMUX_GPIO17__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(17) | 3)
> +#define PINMUX_GPIO17__FUNC_MD_INT0 (MTK_PIN_NO(17) | 4)
> +#define PINMUX_GPIO17__FUNC_ANT_SEL7 (MTK_PIN_NO(17) | 5)
> +#define PINMUX_GPIO17__FUNC_I2S3_MCK (MTK_PIN_NO(17) | 6)
> +#define PINMUX_GPIO17__FUNC_DBG_MON_A1 (MTK_PIN_NO(17) | 7)
> +
> +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
> +#define PINMUX_GPIO18__FUNC_DBPI_D5 (MTK_PIN_NO(18) | 1)
> +#define PINMUX_GPIO18__FUNC_SPI4_CSB (MTK_PIN_NO(18) | 2)
> +#define PINMUX_GPIO18__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(18) | 3)
> +#define PINMUX_GPIO18__FUNC_MD_INT0 (MTK_PIN_NO(18) | 4)
> +#define PINMUX_GPIO18__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(18) | 5)
> +#define PINMUX_GPIO18__FUNC_I2S3_BCK (MTK_PIN_NO(18) | 6)
> +#define PINMUX_GPIO18__FUNC_DBG_MON_A2 (MTK_PIN_NO(18) | 7)
> +
> +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
> +#define PINMUX_GPIO19__FUNC_DBPI_D6 (MTK_PIN_NO(19) | 1)
> +#define PINMUX_GPIO19__FUNC_SPI4_MO (MTK_PIN_NO(19) | 2)
> +#define PINMUX_GPIO19__FUNC_CONN_MCU_TDO (MTK_PIN_NO(19) | 3)
> +#define PINMUX_GPIO19__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(19) | 4)
> +#define PINMUX_GPIO19__FUNC_URXD1 (MTK_PIN_NO(19) | 5)
> +#define PINMUX_GPIO19__FUNC_I2S3_LRCK (MTK_PIN_NO(19) | 6)
> +#define PINMUX_GPIO19__FUNC_DBG_MON_A3 (MTK_PIN_NO(19) | 7)
> +
> +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
> +#define PINMUX_GPIO20__FUNC_DBPI_D7 (MTK_PIN_NO(20) | 1)
> +#define PINMUX_GPIO20__FUNC_SPI4_CLK (MTK_PIN_NO(20) | 2)
> +#define PINMUX_GPIO20__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(20) | 3)
> +#define PINMUX_GPIO20__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(20) | 4)
> +#define PINMUX_GPIO20__FUNC_UTXD1 (MTK_PIN_NO(20) | 5)
> +#define PINMUX_GPIO20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 6)
> +#define PINMUX_GPIO20__FUNC_DBG_MON_A19 (MTK_PIN_NO(20) | 7)
> +
> +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
> +#define PINMUX_GPIO21__FUNC_DBPI_D8 (MTK_PIN_NO(21) | 1)
> +#define PINMUX_GPIO21__FUNC_SPI3_MI (MTK_PIN_NO(21) | 2)
> +#define PINMUX_GPIO21__FUNC_CONN_MCU_TMS (MTK_PIN_NO(21) | 3)
> +#define PINMUX_GPIO21__FUNC_DAP_MD32_SWD (MTK_PIN_NO(21) | 4)
> +#define PINMUX_GPIO21__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(21) | 5)
> +#define PINMUX_GPIO21__FUNC_I2S2_MCK (MTK_PIN_NO(21) | 6)
> +#define PINMUX_GPIO21__FUNC_DBG_MON_B5 (MTK_PIN_NO(21) | 7)
> +
> +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
> +#define PINMUX_GPIO22__FUNC_DBPI_D9 (MTK_PIN_NO(22) | 1)
> +#define PINMUX_GPIO22__FUNC_SPI3_CSB (MTK_PIN_NO(22) | 2)
> +#define PINMUX_GPIO22__FUNC_CONN_MCU_TCK (MTK_PIN_NO(22) | 3)
> +#define PINMUX_GPIO22__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(22) | 4)
> +#define PINMUX_GPIO22__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(22) | 5)
> +#define PINMUX_GPIO22__FUNC_I2S2_BCK (MTK_PIN_NO(22) | 6)
> +#define PINMUX_GPIO22__FUNC_DBG_MON_B6 (MTK_PIN_NO(22) | 7)
> +
> +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
> +#define PINMUX_GPIO23__FUNC_DBPI_D10 (MTK_PIN_NO(23) | 1)
> +#define PINMUX_GPIO23__FUNC_SPI3_MO (MTK_PIN_NO(23) | 2)
> +#define PINMUX_GPIO23__FUNC_CONN_MCU_TDI (MTK_PIN_NO(23) | 3)
> +#define PINMUX_GPIO23__FUNC_UCTS1 (MTK_PIN_NO(23) | 4)
> +#define PINMUX_GPIO23__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5)
> +#define PINMUX_GPIO23__FUNC_I2S2_LRCK (MTK_PIN_NO(23) | 6)
> +#define PINMUX_GPIO23__FUNC_DBG_MON_B7 (MTK_PIN_NO(23) | 7)
> +
> +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
> +#define PINMUX_GPIO24__FUNC_DBPI_D11 (MTK_PIN_NO(24) | 1)
> +#define PINMUX_GPIO24__FUNC_SPI3_CLK (MTK_PIN_NO(24) | 2)
> +#define PINMUX_GPIO24__FUNC_SRCLKENAI0 (MTK_PIN_NO(24) | 3)
> +#define PINMUX_GPIO24__FUNC_URTS1 (MTK_PIN_NO(24) | 4)
> +#define PINMUX_GPIO24__FUNC_IO_JTAG_TCK (MTK_PIN_NO(24) | 5)
> +#define PINMUX_GPIO24__FUNC_I2S2_DI (MTK_PIN_NO(24) | 6)
> +#define PINMUX_GPIO24__FUNC_DBG_MON_B31 (MTK_PIN_NO(24) | 7)
> +
> +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
> +#define PINMUX_GPIO25__FUNC_DBPI_HSYNC (MTK_PIN_NO(25) | 1)
> +#define PINMUX_GPIO25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 2)
> +#define PINMUX_GPIO25__FUNC_SCL6 (MTK_PIN_NO(25) | 3)
> +#define PINMUX_GPIO25__FUNC_KPCOL2 (MTK_PIN_NO(25) | 4)
> +#define PINMUX_GPIO25__FUNC_IO_JTAG_TMS (MTK_PIN_NO(25) | 5)
> +#define PINMUX_GPIO25__FUNC_I2S1_MCK (MTK_PIN_NO(25) | 6)
> +#define PINMUX_GPIO25__FUNC_DBG_MON_B0 (MTK_PIN_NO(25) | 7)
> +
> +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
> +#define PINMUX_GPIO26__FUNC_DBPI_VSYNC (MTK_PIN_NO(26) | 1)
> +#define PINMUX_GPIO26__FUNC_ANT_SEL1 (MTK_PIN_NO(26) | 2)
> +#define PINMUX_GPIO26__FUNC_SDA6 (MTK_PIN_NO(26) | 3)
> +#define PINMUX_GPIO26__FUNC_KPROW2 (MTK_PIN_NO(26) | 4)
> +#define PINMUX_GPIO26__FUNC_IO_JTAG_TDI (MTK_PIN_NO(26) | 5)
> +#define PINMUX_GPIO26__FUNC_I2S1_BCK (MTK_PIN_NO(26) | 6)
> +#define PINMUX_GPIO26__FUNC_DBG_MON_B1 (MTK_PIN_NO(26) | 7)
> +
> +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
> +#define PINMUX_GPIO27__FUNC_DBPI_DE (MTK_PIN_NO(27) | 1)
> +#define PINMUX_GPIO27__FUNC_ANT_SEL2 (MTK_PIN_NO(27) | 2)
> +#define PINMUX_GPIO27__FUNC_SCL7 (MTK_PIN_NO(27) | 3)
> +#define PINMUX_GPIO27__FUNC_DMIC_CLK (MTK_PIN_NO(27) | 4)
> +#define PINMUX_GPIO27__FUNC_IO_JTAG_TDO (MTK_PIN_NO(27) | 5)
> +#define PINMUX_GPIO27__FUNC_I2S1_LRCK (MTK_PIN_NO(27) | 6)
> +#define PINMUX_GPIO27__FUNC_DBG_MON_B9 (MTK_PIN_NO(27) | 7)
> +
> +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
> +#define PINMUX_GPIO28__FUNC_DBPI_CK (MTK_PIN_NO(28) | 1)
> +#define PINMUX_GPIO28__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(28) | 2)
> +#define PINMUX_GPIO28__FUNC_SDA7 (MTK_PIN_NO(28) | 3)
> +#define PINMUX_GPIO28__FUNC_DMIC_DAT (MTK_PIN_NO(28) | 4)
> +#define PINMUX_GPIO28__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(28) | 5)
> +#define PINMUX_GPIO28__FUNC_I2S1_DO (MTK_PIN_NO(28) | 6)
> +#define PINMUX_GPIO28__FUNC_DBG_MON_B32 (MTK_PIN_NO(28) | 7)
> +
> +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
> +#define PINMUX_GPIO29__FUNC_MSDC1_CLK (MTK_PIN_NO(29) | 1)
> +#define PINMUX_GPIO29__FUNC_IO_JTAG_TCK (MTK_PIN_NO(29) | 2)
> +#define PINMUX_GPIO29__FUNC_UDI_TCK (MTK_PIN_NO(29) | 3)
> +#define PINMUX_GPIO29__FUNC_CONN_DSP_JCK (MTK_PIN_NO(29) | 4)
> +#define PINMUX_GPIO29__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(29) | 5)
> +#define PINMUX_GPIO29__FUNC_PCM1_CLK (MTK_PIN_NO(29) | 6)
> +#define PINMUX_GPIO29__FUNC_DBG_MON_A6 (MTK_PIN_NO(29) | 7)
> +
> +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
> +#define PINMUX_GPIO30__FUNC_MSDC1_DAT3 (MTK_PIN_NO(30) | 1)
> +#define PINMUX_GPIO30__FUNC_DAP_MD32_SWD (MTK_PIN_NO(30) | 2)
> +#define PINMUX_GPIO30__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 3)
> +#define PINMUX_GPIO30__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(30) | 4)
> +#define PINMUX_GPIO30__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(30) | 5)
> +#define PINMUX_GPIO30__FUNC_PCM1_DI (MTK_PIN_NO(30) | 6)
> +#define PINMUX_GPIO30__FUNC_DBG_MON_A7 (MTK_PIN_NO(30) | 7)
> +
> +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
> +#define PINMUX_GPIO31__FUNC_MSDC1_CMD (MTK_PIN_NO(31) | 1)
> +#define PINMUX_GPIO31__FUNC_IO_JTAG_TMS (MTK_PIN_NO(31) | 2)
> +#define PINMUX_GPIO31__FUNC_UDI_TMS (MTK_PIN_NO(31) | 3)
> +#define PINMUX_GPIO31__FUNC_CONN_DSP_JMS (MTK_PIN_NO(31) | 4)
> +#define PINMUX_GPIO31__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(31) | 5)
> +#define PINMUX_GPIO31__FUNC_PCM1_SYNC (MTK_PIN_NO(31) | 6)
> +#define PINMUX_GPIO31__FUNC_DBG_MON_A8 (MTK_PIN_NO(31) | 7)
> +
> +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
> +#define PINMUX_GPIO32__FUNC_MSDC1_DAT0 (MTK_PIN_NO(32) | 1)
> +#define PINMUX_GPIO32__FUNC_IO_JTAG_TDI (MTK_PIN_NO(32) | 2)
> +#define PINMUX_GPIO32__FUNC_UDI_TDI (MTK_PIN_NO(32) | 3)
> +#define PINMUX_GPIO32__FUNC_CONN_DSP_JDI (MTK_PIN_NO(32) | 4)
> +#define PINMUX_GPIO32__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(32) | 5)
> +#define PINMUX_GPIO32__FUNC_PCM1_DO0 (MTK_PIN_NO(32) | 6)
> +#define PINMUX_GPIO32__FUNC_DBG_MON_A9 (MTK_PIN_NO(32) | 7)
> +
> +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
> +#define PINMUX_GPIO33__FUNC_MSDC1_DAT2 (MTK_PIN_NO(33) | 1)
> +#define PINMUX_GPIO33__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(33) | 2)
> +#define PINMUX_GPIO33__FUNC_UDI_NTRST (MTK_PIN_NO(33) | 3)
> +#define PINMUX_GPIO33__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(33) | 4)
> +#define PINMUX_GPIO33__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(33) | 5)
> +#define PINMUX_GPIO33__FUNC_PCM1_DO2 (MTK_PIN_NO(33) | 6)
> +#define PINMUX_GPIO33__FUNC_DBG_MON_A10 (MTK_PIN_NO(33) | 7)
> +
> +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
> +#define PINMUX_GPIO34__FUNC_MSDC1_DAT1 (MTK_PIN_NO(34) | 1)
> +#define PINMUX_GPIO34__FUNC_IO_JTAG_TDO (MTK_PIN_NO(34) | 2)
> +#define PINMUX_GPIO34__FUNC_UDI_TDO (MTK_PIN_NO(34) | 3)
> +#define PINMUX_GPIO34__FUNC_CONN_DSP_JDO (MTK_PIN_NO(34) | 4)
> +#define PINMUX_GPIO34__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(34) | 5)
> +#define PINMUX_GPIO34__FUNC_PCM1_DO1 (MTK_PIN_NO(34) | 6)
> +#define PINMUX_GPIO34__FUNC_DBG_MON_A11 (MTK_PIN_NO(34) | 7)
> +
> +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
> +#define PINMUX_GPIO35__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(35) | 1)
> +#define PINMUX_GPIO35__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(35) | 2)
> +#define PINMUX_GPIO35__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(35) | 3)
> +#define PINMUX_GPIO35__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(35) | 5)
> +#define PINMUX_GPIO35__FUNC_CONN_DSP_JMS (MTK_PIN_NO(35) | 6)
> +#define PINMUX_GPIO35__FUNC_DBG_MON_A28 (MTK_PIN_NO(35) | 7)
> +
> +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
> +#define PINMUX_GPIO36__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(36) | 1)
> +#define PINMUX_GPIO36__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(36) | 2)
> +#define PINMUX_GPIO36__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(36) | 3)
> +#define PINMUX_GPIO36__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(36) | 4)
> +#define PINMUX_GPIO36__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(36) | 5)
> +#define PINMUX_GPIO36__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(36) | 6)
> +#define PINMUX_GPIO36__FUNC_DBG_MON_A29 (MTK_PIN_NO(36) | 7)
> +
> +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
> +#define PINMUX_GPIO37__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(37) | 1)
> +#define PINMUX_GPIO37__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(37) | 2)
> +#define PINMUX_GPIO37__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(37) | 3)
> +#define PINMUX_GPIO37__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(37) | 5)
> +#define PINMUX_GPIO37__FUNC_CONN_DSP_JDO (MTK_PIN_NO(37) | 6)
> +#define PINMUX_GPIO37__FUNC_DBG_MON_A30 (MTK_PIN_NO(37) | 7)
> +
> +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
> +#define PINMUX_GPIO38__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(38) | 1)
> +#define PINMUX_GPIO38__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(38) | 3)
> +#define PINMUX_GPIO38__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(38) | 4)
> +#define PINMUX_GPIO38__FUNC_DBG_MON_A20 (MTK_PIN_NO(38) | 7)
> +
> +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
> +#define PINMUX_GPIO39__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(39) | 1)
> +#define PINMUX_GPIO39__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(39) | 2)
> +#define PINMUX_GPIO39__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(39) | 3)
> +#define PINMUX_GPIO39__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(39) | 5)
> +#define PINMUX_GPIO39__FUNC_CONN_DSP_JCK (MTK_PIN_NO(39) | 6)
> +#define PINMUX_GPIO39__FUNC_DBG_MON_A31 (MTK_PIN_NO(39) | 7)
> +
> +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
> +#define PINMUX_GPIO40__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(40) | 1)
> +#define PINMUX_GPIO40__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(40) | 2)
> +#define PINMUX_GPIO40__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(40) | 3)
> +#define PINMUX_GPIO40__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(40) | 5)
> +#define PINMUX_GPIO40__FUNC_CONN_DSP_JDI (MTK_PIN_NO(40) | 6)
> +#define PINMUX_GPIO40__FUNC_DBG_MON_A32 (MTK_PIN_NO(40) | 7)
> +
> +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
> +#define PINMUX_GPIO41__FUNC_IDDIG (MTK_PIN_NO(41) | 1)
> +#define PINMUX_GPIO41__FUNC_URXD1 (MTK_PIN_NO(41) | 2)
> +#define PINMUX_GPIO41__FUNC_UCTS0 (MTK_PIN_NO(41) | 3)
> +#define PINMUX_GPIO41__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(41) | 4)
> +#define PINMUX_GPIO41__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 5)
> +#define PINMUX_GPIO41__FUNC_DMIC_CLK (MTK_PIN_NO(41) | 6)
> +
> +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
> +#define PINMUX_GPIO42__FUNC_USB_DRVVBUS (MTK_PIN_NO(42) | 1)
> +#define PINMUX_GPIO42__FUNC_UTXD1 (MTK_PIN_NO(42) | 2)
> +#define PINMUX_GPIO42__FUNC_URTS0 (MTK_PIN_NO(42) | 3)
> +#define PINMUX_GPIO42__FUNC_SSPM_URXD_AO (MTK_PIN_NO(42) | 4)
> +#define PINMUX_GPIO42__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(42) | 5)
> +#define PINMUX_GPIO42__FUNC_DMIC_DAT (MTK_PIN_NO(42) | 6)
> +
> +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
> +#define PINMUX_GPIO43__FUNC_DISP_PWM (MTK_PIN_NO(43) | 1)
> +
> +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
> +#define PINMUX_GPIO44__FUNC_DSI_TE (MTK_PIN_NO(44) | 1)
> +
> +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
> +#define PINMUX_GPIO45__FUNC_LCM_RST (MTK_PIN_NO(45) | 1)
> +
> +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
> +#define PINMUX_GPIO46__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(46) | 1)
> +#define PINMUX_GPIO46__FUNC_URXD1 (MTK_PIN_NO(46) | 2)
> +#define PINMUX_GPIO46__FUNC_UCTS1 (MTK_PIN_NO(46) | 3)
> +#define PINMUX_GPIO46__FUNC_CCU_UTXD_AO (MTK_PIN_NO(46) | 4)
> +#define PINMUX_GPIO46__FUNC_TP_UCTS1_AO (MTK_PIN_NO(46) | 5)
> +#define PINMUX_GPIO46__FUNC_IDDIG (MTK_PIN_NO(46) | 6)
> +#define PINMUX_GPIO46__FUNC_I2S5_LRCK (MTK_PIN_NO(46) | 7)
> +
> +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
> +#define PINMUX_GPIO47__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(47) | 1)
> +#define PINMUX_GPIO47__FUNC_UTXD1 (MTK_PIN_NO(47) | 2)
> +#define PINMUX_GPIO47__FUNC_URTS1 (MTK_PIN_NO(47) | 3)
> +#define PINMUX_GPIO47__FUNC_CCU_URXD_AO (MTK_PIN_NO(47) | 4)
> +#define PINMUX_GPIO47__FUNC_TP_URTS1_AO (MTK_PIN_NO(47) | 5)
> +#define PINMUX_GPIO47__FUNC_USB_DRVVBUS (MTK_PIN_NO(47) | 6)
> +#define PINMUX_GPIO47__FUNC_I2S5_DO (MTK_PIN_NO(47) | 7)
> +
> +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
> +#define PINMUX_GPIO48__FUNC_SCL5 (MTK_PIN_NO(48) | 1)
> +
> +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
> +#define PINMUX_GPIO49__FUNC_SDA5 (MTK_PIN_NO(49) | 1)
> +
> +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
> +#define PINMUX_GPIO50__FUNC_SCL3 (MTK_PIN_NO(50) | 1)
> +
> +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
> +#define PINMUX_GPIO51__FUNC_SDA3 (MTK_PIN_NO(51) | 1)
> +
> +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
> +#define PINMUX_GPIO52__FUNC_BPI_ANT2 (MTK_PIN_NO(52) | 1)
> +
> +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
> +#define PINMUX_GPIO53__FUNC_BPI_ANT0 (MTK_PIN_NO(53) | 1)
> +
> +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
> +#define PINMUX_GPIO54__FUNC_BPI_OLAT1 (MTK_PIN_NO(54) | 1)
> +
> +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
> +#define PINMUX_GPIO55__FUNC_BPI_BUS8 (MTK_PIN_NO(55) | 1)
> +
> +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
> +#define PINMUX_GPIO56__FUNC_BPI_BUS9 (MTK_PIN_NO(56) | 1)
> +#define PINMUX_GPIO56__FUNC_SCL_6306 (MTK_PIN_NO(56) | 2)
> +
> +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
> +#define PINMUX_GPIO57__FUNC_BPI_BUS10 (MTK_PIN_NO(57) | 1)
> +#define PINMUX_GPIO57__FUNC_SDA_6306 (MTK_PIN_NO(57) | 2)
> +
> +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
> +#define PINMUX_GPIO58__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(58) | 1)
> +#define PINMUX_GPIO58__FUNC_SPM_BSI_D2 (MTK_PIN_NO(58) | 2)
> +#define PINMUX_GPIO58__FUNC_PWM_B (MTK_PIN_NO(58) | 3)
> +
> +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
> +#define PINMUX_GPIO59__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(59) | 1)
> +#define PINMUX_GPIO59__FUNC_SPM_BSI_D1 (MTK_PIN_NO(59) | 2)
> +
> +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
> +#define PINMUX_GPIO60__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(60) | 1)
> +#define PINMUX_GPIO60__FUNC_SPM_BSI_D0 (MTK_PIN_NO(60) | 2)
> +
> +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
> +#define PINMUX_GPIO61__FUNC_MIPI1_SDATA (MTK_PIN_NO(61) | 1)
> +
> +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
> +#define PINMUX_GPIO62__FUNC_MIPI1_SCLK (MTK_PIN_NO(62) | 1)
> +
> +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
> +#define PINMUX_GPIO63__FUNC_MIPI0_SDATA (MTK_PIN_NO(63) | 1)
> +
> +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
> +#define PINMUX_GPIO64__FUNC_MIPI0_SCLK (MTK_PIN_NO(64) | 1)
> +
> +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
> +#define PINMUX_GPIO65__FUNC_MIPI3_SDATA (MTK_PIN_NO(65) | 1)
> +#define PINMUX_GPIO65__FUNC_BPI_OLAT2 (MTK_PIN_NO(65) | 2)
> +
> +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
> +#define PINMUX_GPIO66__FUNC_MIPI3_SCLK (MTK_PIN_NO(66) | 1)
> +#define PINMUX_GPIO66__FUNC_BPI_OLAT3 (MTK_PIN_NO(66) | 2)
> +
> +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
> +#define PINMUX_GPIO67__FUNC_MIPI2_SDATA (MTK_PIN_NO(67) | 1)
> +
> +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
> +#define PINMUX_GPIO68__FUNC_MIPI2_SCLK (MTK_PIN_NO(68) | 1)
> +
> +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
> +#define PINMUX_GPIO69__FUNC_BPI_BUS7 (MTK_PIN_NO(69) | 1)
> +
> +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
> +#define PINMUX_GPIO70__FUNC_BPI_BUS6 (MTK_PIN_NO(70) | 1)
> +
> +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
> +#define PINMUX_GPIO71__FUNC_BPI_BUS5 (MTK_PIN_NO(71) | 1)
> +
> +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
> +#define PINMUX_GPIO72__FUNC_BPI_BUS4 (MTK_PIN_NO(72) | 1)
> +
> +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
> +#define PINMUX_GPIO73__FUNC_BPI_BUS3 (MTK_PIN_NO(73) | 1)
> +
> +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
> +#define PINMUX_GPIO74__FUNC_BPI_BUS2 (MTK_PIN_NO(74) | 1)
> +
> +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
> +#define PINMUX_GPIO75__FUNC_BPI_BUS1 (MTK_PIN_NO(75) | 1)
> +
> +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
> +#define PINMUX_GPIO76__FUNC_BPI_BUS0 (MTK_PIN_NO(76) | 1)
> +
> +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
> +#define PINMUX_GPIO77__FUNC_BPI_ANT1 (MTK_PIN_NO(77) | 1)
> +
> +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
> +#define PINMUX_GPIO78__FUNC_BPI_OLAT0 (MTK_PIN_NO(78) | 1)
> +
> +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
> +#define PINMUX_GPIO79__FUNC_BPI_PA_VM1 (MTK_PIN_NO(79) | 1)
> +#define PINMUX_GPIO79__FUNC_MIPI4_SDATA (MTK_PIN_NO(79) | 2)
> +
> +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
> +#define PINMUX_GPIO80__FUNC_BPI_PA_VM0 (MTK_PIN_NO(80) | 1)
> +#define PINMUX_GPIO80__FUNC_MIPI4_SCLK (MTK_PIN_NO(80) | 2)
> +
> +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
> +#define PINMUX_GPIO81__FUNC_SDA1 (MTK_PIN_NO(81) | 1)
> +
> +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
> +#define PINMUX_GPIO82__FUNC_SDA0 (MTK_PIN_NO(82) | 1)
> +
> +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
> +#define PINMUX_GPIO83__FUNC_SCL0 (MTK_PIN_NO(83) | 1)
> +
> +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
> +#define PINMUX_GPIO84__FUNC_SCL1 (MTK_PIN_NO(84) | 1)
> +
> +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
> +#define PINMUX_GPIO85__FUNC_SPI0_MI (MTK_PIN_NO(85) | 1)
> +#define PINMUX_GPIO85__FUNC_SCP_SPI0_MI (MTK_PIN_NO(85) | 2)
> +#define PINMUX_GPIO85__FUNC_CLKM3 (MTK_PIN_NO(85) | 3)
> +#define PINMUX_GPIO85__FUNC_I2S1_BCK (MTK_PIN_NO(85) | 4)
> +#define PINMUX_GPIO85__FUNC_MFG_DFD_JTAG_TDO (MTK_PIN_NO(85) | 5)
> +#define PINMUX_GPIO85__FUNC_DFD_TDO (MTK_PIN_NO(85) | 6)
> +#define PINMUX_GPIO85__FUNC_JTDO_SEL1 (MTK_PIN_NO(85) | 7)
> +
> +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
> +#define PINMUX_GPIO86__FUNC_SPI0_CSB (MTK_PIN_NO(86) | 1)
> +#define PINMUX_GPIO86__FUNC_SCP_SPI0_CS (MTK_PIN_NO(86) | 2)
> +#define PINMUX_GPIO86__FUNC_CLKM0 (MTK_PIN_NO(86) | 3)
> +#define PINMUX_GPIO86__FUNC_I2S1_LRCK (MTK_PIN_NO(86) | 4)
> +#define PINMUX_GPIO86__FUNC_MFG_DFD_JTAG_TMS (MTK_PIN_NO(86) | 5)
> +#define PINMUX_GPIO86__FUNC_DFD_TMS (MTK_PIN_NO(86) | 6)
> +#define PINMUX_GPIO86__FUNC_JTMS_SEL1 (MTK_PIN_NO(86) | 7)
> +
> +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
> +#define PINMUX_GPIO87__FUNC_SPI0_MO (MTK_PIN_NO(87) | 1)
> +#define PINMUX_GPIO87__FUNC_SCP_SPI0_MO (MTK_PIN_NO(87) | 2)
> +#define PINMUX_GPIO87__FUNC_SDA1 (MTK_PIN_NO(87) | 3)
> +#define PINMUX_GPIO87__FUNC_I2S1_DO (MTK_PIN_NO(87) | 4)
> +#define PINMUX_GPIO87__FUNC_MFG_DFD_JTAG_TDI (MTK_PIN_NO(87) | 5)
> +#define PINMUX_GPIO87__FUNC_DFD_TDI (MTK_PIN_NO(87) | 6)
> +#define PINMUX_GPIO87__FUNC_JTDI_SEL1 (MTK_PIN_NO(87) | 7)
> +
> +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
> +#define PINMUX_GPIO88__FUNC_SPI0_CLK (MTK_PIN_NO(88) | 1)
> +#define PINMUX_GPIO88__FUNC_SCP_SPI0_CK (MTK_PIN_NO(88) | 2)
> +#define PINMUX_GPIO88__FUNC_SCL1 (MTK_PIN_NO(88) | 3)
> +#define PINMUX_GPIO88__FUNC_I2S1_MCK (MTK_PIN_NO(88) | 4)
> +#define PINMUX_GPIO88__FUNC_MFG_DFD_JTAG_TCK (MTK_PIN_NO(88) | 5)
> +#define PINMUX_GPIO88__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 6)
> +#define PINMUX_GPIO88__FUNC_JTCK_SEL1 (MTK_PIN_NO(88) | 7)
> +
> +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
> +#define PINMUX_GPIO89__FUNC_SRCLKENAI0 (MTK_PIN_NO(89) | 1)
> +#define PINMUX_GPIO89__FUNC_PWM_C (MTK_PIN_NO(89) | 2)
> +#define PINMUX_GPIO89__FUNC_I2S5_BCK (MTK_PIN_NO(89) | 3)
> +#define PINMUX_GPIO89__FUNC_ANT_SEL6 (MTK_PIN_NO(89) | 4)
> +#define PINMUX_GPIO89__FUNC_SDA8 (MTK_PIN_NO(89) | 5)
> +#define PINMUX_GPIO89__FUNC_CMVREF0 (MTK_PIN_NO(89) | 6)
> +#define PINMUX_GPIO89__FUNC_DBG_MON_A21 (MTK_PIN_NO(89) | 7)
> +
> +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
> +#define PINMUX_GPIO90__FUNC_PWM_A (MTK_PIN_NO(90) | 1)
> +#define PINMUX_GPIO90__FUNC_CMMCLK2 (MTK_PIN_NO(90) | 2)
> +#define PINMUX_GPIO90__FUNC_I2S5_LRCK (MTK_PIN_NO(90) | 3)
> +#define PINMUX_GPIO90__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(90) | 4)
> +#define PINMUX_GPIO90__FUNC_SCL8 (MTK_PIN_NO(90) | 5)
> +#define PINMUX_GPIO90__FUNC_PTA_RXD (MTK_PIN_NO(90) | 6)
> +#define PINMUX_GPIO90__FUNC_DBG_MON_A22 (MTK_PIN_NO(90) | 7)
> +
> +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
> +#define PINMUX_GPIO91__FUNC_KPROW1 (MTK_PIN_NO(91) | 1)
> +#define PINMUX_GPIO91__FUNC_PWM_B (MTK_PIN_NO(91) | 2)
> +#define PINMUX_GPIO91__FUNC_I2S5_DO (MTK_PIN_NO(91) | 3)
> +#define PINMUX_GPIO91__FUNC_ANT_SEL7 (MTK_PIN_NO(91) | 4)
> +#define PINMUX_GPIO91__FUNC_CMMCLK3 (MTK_PIN_NO(91) | 5)
> +#define PINMUX_GPIO91__FUNC_PTA_TXD (MTK_PIN_NO(91) | 6)
> +
> +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
> +#define PINMUX_GPIO92__FUNC_KPROW0 (MTK_PIN_NO(92) | 1)
> +
> +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
> +#define PINMUX_GPIO93__FUNC_KPCOL0 (MTK_PIN_NO(93) | 1)
> +#define PINMUX_GPIO93__FUNC_DBG_MON_B27 (MTK_PIN_NO(93) | 7)
> +
> +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
> +#define PINMUX_GPIO94__FUNC_KPCOL1 (MTK_PIN_NO(94) | 1)
> +#define PINMUX_GPIO94__FUNC_I2S2_DI2 (MTK_PIN_NO(94) | 2)
> +#define PINMUX_GPIO94__FUNC_I2S5_MCK (MTK_PIN_NO(94) | 3)
> +#define PINMUX_GPIO94__FUNC_CMMCLK2 (MTK_PIN_NO(94) | 4)
> +#define PINMUX_GPIO94__FUNC_SCP_SPI2_MI (MTK_PIN_NO(94) | 5)
> +#define PINMUX_GPIO94__FUNC_SRCLKENAI1 (MTK_PIN_NO(94) | 6)
> +#define PINMUX_GPIO94__FUNC_SPI2_MI (MTK_PIN_NO(94) | 7)
> +
> +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
> +#define PINMUX_GPIO95__FUNC_URXD0 (MTK_PIN_NO(95) | 1)
> +#define PINMUX_GPIO95__FUNC_UTXD0 (MTK_PIN_NO(95) | 2)
> +#define PINMUX_GPIO95__FUNC_MD_URXD0 (MTK_PIN_NO(95) | 3)
> +#define PINMUX_GPIO95__FUNC_MD_URXD1 (MTK_PIN_NO(95) | 4)
> +#define PINMUX_GPIO95__FUNC_SSPM_URXD_AO (MTK_PIN_NO(95) | 5)
> +#define PINMUX_GPIO95__FUNC_CCU_URXD_AO (MTK_PIN_NO(95) | 6)
> +
> +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
> +#define PINMUX_GPIO96__FUNC_UTXD0 (MTK_PIN_NO(96) | 1)
> +#define PINMUX_GPIO96__FUNC_URXD0 (MTK_PIN_NO(96) | 2)
> +#define PINMUX_GPIO96__FUNC_MD_UTXD0 (MTK_PIN_NO(96) | 3)
> +#define PINMUX_GPIO96__FUNC_MD_UTXD1 (MTK_PIN_NO(96) | 4)
> +#define PINMUX_GPIO96__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(96) | 5)
> +#define PINMUX_GPIO96__FUNC_CCU_UTXD_AO (MTK_PIN_NO(96) | 6)
> +#define PINMUX_GPIO96__FUNC_DBG_MON_B2 (MTK_PIN_NO(96) | 7)
> +
> +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
> +#define PINMUX_GPIO97__FUNC_UCTS0 (MTK_PIN_NO(97) | 1)
> +#define PINMUX_GPIO97__FUNC_I2S2_MCK (MTK_PIN_NO(97) | 2)
> +#define PINMUX_GPIO97__FUNC_IDDIG (MTK_PIN_NO(97) | 3)
> +#define PINMUX_GPIO97__FUNC_CONN_MCU_TDO (MTK_PIN_NO(97) | 4)
> +#define PINMUX_GPIO97__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(97) | 5)
> +#define PINMUX_GPIO97__FUNC_IO_JTAG_TDO (MTK_PIN_NO(97) | 6)
> +#define PINMUX_GPIO97__FUNC_DBG_MON_B3 (MTK_PIN_NO(97) | 7)
> +
> +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
> +#define PINMUX_GPIO98__FUNC_URTS0 (MTK_PIN_NO(98) | 1)
> +#define PINMUX_GPIO98__FUNC_I2S2_BCK (MTK_PIN_NO(98) | 2)
> +#define PINMUX_GPIO98__FUNC_USB_DRVVBUS (MTK_PIN_NO(98) | 3)
> +#define PINMUX_GPIO98__FUNC_CONN_MCU_TMS (MTK_PIN_NO(98) | 4)
> +#define PINMUX_GPIO98__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(98) | 5)
> +#define PINMUX_GPIO98__FUNC_IO_JTAG_TMS (MTK_PIN_NO(98) | 6)
> +#define PINMUX_GPIO98__FUNC_DBG_MON_B4 (MTK_PIN_NO(98) | 7)
> +
> +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
> +#define PINMUX_GPIO99__FUNC_CMMCLK0 (MTK_PIN_NO(99) | 1)
> +#define PINMUX_GPIO99__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(99) | 4)
> +#define PINMUX_GPIO99__FUNC_DBG_MON_B28 (MTK_PIN_NO(99) | 7)
> +
> +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
> +#define PINMUX_GPIO100__FUNC_CMMCLK1 (MTK_PIN_NO(100) | 1)
> +#define PINMUX_GPIO100__FUNC_PWM_C (MTK_PIN_NO(100) | 2)
> +#define PINMUX_GPIO100__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(100) | 3)
> +#define PINMUX_GPIO100__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(100) | 4)
> +#define PINMUX_GPIO100__FUNC_DBG_MON_B29 (MTK_PIN_NO(100) | 7)
> +
> +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
> +#define PINMUX_GPIO101__FUNC_CLKM2 (MTK_PIN_NO(101) | 1)
> +#define PINMUX_GPIO101__FUNC_I2S2_LRCK (MTK_PIN_NO(101) | 2)
> +#define PINMUX_GPIO101__FUNC_CMVREF1 (MTK_PIN_NO(101) | 3)
> +#define PINMUX_GPIO101__FUNC_CONN_MCU_TCK (MTK_PIN_NO(101) | 4)
> +#define PINMUX_GPIO101__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(101) | 5)
> +#define PINMUX_GPIO101__FUNC_IO_JTAG_TCK (MTK_PIN_NO(101) | 6)
> +
> +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
> +#define PINMUX_GPIO102__FUNC_CLKM1 (MTK_PIN_NO(102) | 1)
> +#define PINMUX_GPIO102__FUNC_I2S2_DI (MTK_PIN_NO(102) | 2)
> +#define PINMUX_GPIO102__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(102) | 3)
> +#define PINMUX_GPIO102__FUNC_CONN_MCU_TDI (MTK_PIN_NO(102) | 4)
> +#define PINMUX_GPIO102__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(102) | 5)
> +#define PINMUX_GPIO102__FUNC_IO_JTAG_TDI (MTK_PIN_NO(102) | 6)
> +#define PINMUX_GPIO102__FUNC_DBG_MON_B8 (MTK_PIN_NO(102) | 7)
> +
> +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
> +#define PINMUX_GPIO103__FUNC_SCL2 (MTK_PIN_NO(103) | 1)
> +
> +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
> +#define PINMUX_GPIO104__FUNC_SDA2 (MTK_PIN_NO(104) | 1)
> +
> +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
> +#define PINMUX_GPIO105__FUNC_SCL4 (MTK_PIN_NO(105) | 1)
> +
> +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
> +#define PINMUX_GPIO106__FUNC_SDA4 (MTK_PIN_NO(106) | 1)
> +
> +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
> +#define PINMUX_GPIO107__FUNC_DMIC_CLK (MTK_PIN_NO(107) | 1)
> +#define PINMUX_GPIO107__FUNC_ANT_SEL0 (MTK_PIN_NO(107) | 2)
> +#define PINMUX_GPIO107__FUNC_CLKM0 (MTK_PIN_NO(107) | 3)
> +#define PINMUX_GPIO107__FUNC_SDA7 (MTK_PIN_NO(107) | 4)
> +#define PINMUX_GPIO107__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(107) | 5)
> +#define PINMUX_GPIO107__FUNC_PWM_A (MTK_PIN_NO(107) | 6)
> +#define PINMUX_GPIO107__FUNC_DBG_MON_B12 (MTK_PIN_NO(107) | 7)
> +
> +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
> +#define PINMUX_GPIO108__FUNC_CMMCLK2 (MTK_PIN_NO(108) | 1)
> +#define PINMUX_GPIO108__FUNC_ANT_SEL1 (MTK_PIN_NO(108) | 2)
> +#define PINMUX_GPIO108__FUNC_CLKM1 (MTK_PIN_NO(108) | 3)
> +#define PINMUX_GPIO108__FUNC_SCL8 (MTK_PIN_NO(108) | 4)
> +#define PINMUX_GPIO108__FUNC_DAP_MD32_SWD (MTK_PIN_NO(108) | 5)
> +#define PINMUX_GPIO108__FUNC_PWM_B (MTK_PIN_NO(108) | 6)
> +#define PINMUX_GPIO108__FUNC_DBG_MON_B13 (MTK_PIN_NO(108) | 7)
> +
> +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
> +#define PINMUX_GPIO109__FUNC_DMIC_DAT (MTK_PIN_NO(109) | 1)
> +#define PINMUX_GPIO109__FUNC_ANT_SEL2 (MTK_PIN_NO(109) | 2)
> +#define PINMUX_GPIO109__FUNC_CLKM2 (MTK_PIN_NO(109) | 3)
> +#define PINMUX_GPIO109__FUNC_SDA8 (MTK_PIN_NO(109) | 4)
> +#define PINMUX_GPIO109__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(109) | 5)
> +#define PINMUX_GPIO109__FUNC_PWM_C (MTK_PIN_NO(109) | 6)
> +#define PINMUX_GPIO109__FUNC_DBG_MON_B14 (MTK_PIN_NO(109) | 7)
> +
> +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
> +#define PINMUX_GPIO110__FUNC_SCL7 (MTK_PIN_NO(110) | 1)
> +#define PINMUX_GPIO110__FUNC_ANT_SEL0 (MTK_PIN_NO(110) | 2)
> +#define PINMUX_GPIO110__FUNC_TP_URXD1_AO (MTK_PIN_NO(110) | 3)
> +#define PINMUX_GPIO110__FUNC_USB_DRVVBUS (MTK_PIN_NO(110) | 4)
> +#define PINMUX_GPIO110__FUNC_SRCLKENAI1 (MTK_PIN_NO(110) | 5)
> +#define PINMUX_GPIO110__FUNC_KPCOL2 (MTK_PIN_NO(110) | 6)
> +#define PINMUX_GPIO110__FUNC_URXD1 (MTK_PIN_NO(110) | 7)
> +
> +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
> +#define PINMUX_GPIO111__FUNC_CMMCLK3 (MTK_PIN_NO(111) | 1)
> +#define PINMUX_GPIO111__FUNC_ANT_SEL1 (MTK_PIN_NO(111) | 2)
> +#define PINMUX_GPIO111__FUNC_SRCLKENAI0 (MTK_PIN_NO(111) | 3)
> +#define PINMUX_GPIO111__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(111) | 4)
> +#define PINMUX_GPIO111__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(111) | 5)
> +#define PINMUX_GPIO111__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(111) | 7)
> +
> +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
> +#define PINMUX_GPIO112__FUNC_SDA7 (MTK_PIN_NO(112) | 1)
> +#define PINMUX_GPIO112__FUNC_ANT_SEL2 (MTK_PIN_NO(112) | 2)
> +#define PINMUX_GPIO112__FUNC_TP_UTXD1_AO (MTK_PIN_NO(112) | 3)
> +#define PINMUX_GPIO112__FUNC_IDDIG (MTK_PIN_NO(112) | 4)
> +#define PINMUX_GPIO112__FUNC_AGPS_SYNC (MTK_PIN_NO(112) | 5)
> +#define PINMUX_GPIO112__FUNC_KPROW2 (MTK_PIN_NO(112) | 6)
> +#define PINMUX_GPIO112__FUNC_UTXD1 (MTK_PIN_NO(112) | 7)
> +
> +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
> +#define PINMUX_GPIO113__FUNC_CONN_TOP_CLK (MTK_PIN_NO(113) | 1)
> +#define PINMUX_GPIO113__FUNC_SCL6 (MTK_PIN_NO(113) | 3)
> +#define PINMUX_GPIO113__FUNC_AUXIF_CLK0 (MTK_PIN_NO(113) | 4)
> +#define PINMUX_GPIO113__FUNC_TP_UCTS1_AO (MTK_PIN_NO(113) | 6)
> +
> +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
> +#define PINMUX_GPIO114__FUNC_CONN_TOP_DATA (MTK_PIN_NO(114) | 1)
> +#define PINMUX_GPIO114__FUNC_SDA6 (MTK_PIN_NO(114) | 3)
> +#define PINMUX_GPIO114__FUNC_AUXIF_ST0 (MTK_PIN_NO(114) | 4)
> +#define PINMUX_GPIO114__FUNC_TP_URTS1_AO (MTK_PIN_NO(114) | 6)
> +
> +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
> +#define PINMUX_GPIO115__FUNC_CONN_BT_CLK (MTK_PIN_NO(115) | 1)
> +#define PINMUX_GPIO115__FUNC_UTXD1 (MTK_PIN_NO(115) | 2)
> +#define PINMUX_GPIO115__FUNC_PTA_TXD (MTK_PIN_NO(115) | 3)
> +#define PINMUX_GPIO115__FUNC_AUXIF_CLK1 (MTK_PIN_NO(115) | 4)
> +#define PINMUX_GPIO115__FUNC_DAP_MD32_SWD (MTK_PIN_NO(115) | 5)
> +#define PINMUX_GPIO115__FUNC_TP_UTXD1_AO (MTK_PIN_NO(115) | 6)
> +
> +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
> +#define PINMUX_GPIO116__FUNC_CONN_BT_DATA (MTK_PIN_NO(116) | 1)
> +#define PINMUX_GPIO116__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(116) | 2)
> +#define PINMUX_GPIO116__FUNC_AUXIF_ST1 (MTK_PIN_NO(116) | 4)
> +#define PINMUX_GPIO116__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(116) | 5)
> +#define PINMUX_GPIO116__FUNC_TP_URXD2_AO (MTK_PIN_NO(116) | 6)
> +#define PINMUX_GPIO116__FUNC_DBG_MON_A0 (MTK_PIN_NO(116) | 7)
> +
> +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
> +#define PINMUX_GPIO117__FUNC_CONN_WF_HB0 (MTK_PIN_NO(117) | 1)
> +#define PINMUX_GPIO117__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(117) | 2)
> +#define PINMUX_GPIO117__FUNC_TP_UTXD2_AO (MTK_PIN_NO(117) | 6)
> +#define PINMUX_GPIO117__FUNC_DBG_MON_A4 (MTK_PIN_NO(117) | 7)
> +
> +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
> +#define PINMUX_GPIO118__FUNC_CONN_WF_HB1 (MTK_PIN_NO(118) | 1)
> +#define PINMUX_GPIO118__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(118) | 2)
> +#define PINMUX_GPIO118__FUNC_SSPM_URXD_AO (MTK_PIN_NO(118) | 5)
> +#define PINMUX_GPIO118__FUNC_TP_UCTS2_AO (MTK_PIN_NO(118) | 6)
> +#define PINMUX_GPIO118__FUNC_DBG_MON_A5 (MTK_PIN_NO(118) | 7)
> +
> +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
> +#define PINMUX_GPIO119__FUNC_CONN_WF_HB2 (MTK_PIN_NO(119) | 1)
> +#define PINMUX_GPIO119__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(119) | 2)
> +#define PINMUX_GPIO119__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(119) | 5)
> +#define PINMUX_GPIO119__FUNC_TP_URTS2_AO (MTK_PIN_NO(119) | 6)
> +
> +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
> +#define PINMUX_GPIO120__FUNC_CONN_WB_PTA (MTK_PIN_NO(120) | 1)
> +#define PINMUX_GPIO120__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(120) | 2)
> +#define PINMUX_GPIO120__FUNC_CCU_URXD_AO (MTK_PIN_NO(120) | 5)
> +
> +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
> +#define PINMUX_GPIO121__FUNC_CONN_HRST_B (MTK_PIN_NO(121) | 1)
> +#define PINMUX_GPIO121__FUNC_URXD1 (MTK_PIN_NO(121) | 2)
> +#define PINMUX_GPIO121__FUNC_PTA_RXD (MTK_PIN_NO(121) | 3)
> +#define PINMUX_GPIO121__FUNC_CCU_UTXD_AO (MTK_PIN_NO(121) | 5)
> +#define PINMUX_GPIO121__FUNC_TP_URXD1_AO (MTK_PIN_NO(121) | 6)
> +
> +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
> +#define PINMUX_GPIO122__FUNC_MSDC0_CMD (MTK_PIN_NO(122) | 1)
> +#define PINMUX_GPIO122__FUNC_SSPM_URXD2_AO (MTK_PIN_NO(122) | 2)
> +#define PINMUX_GPIO122__FUNC_ANT_SEL1 (MTK_PIN_NO(122) | 3)
> +#define PINMUX_GPIO122__FUNC_DBG_MON_A12 (MTK_PIN_NO(122) | 7)
> +
> +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
> +#define PINMUX_GPIO123__FUNC_MSDC0_DAT0 (MTK_PIN_NO(123) | 1)
> +#define PINMUX_GPIO123__FUNC_ANT_SEL0 (MTK_PIN_NO(123) | 3)
> +#define PINMUX_GPIO123__FUNC_DBG_MON_A13 (MTK_PIN_NO(123) | 7)
> +
> +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
> +#define PINMUX_GPIO124__FUNC_MSDC0_CLK (MTK_PIN_NO(124) | 1)
> +#define PINMUX_GPIO124__FUNC_DBG_MON_A14 (MTK_PIN_NO(124) | 7)
> +
> +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
> +#define PINMUX_GPIO125__FUNC_MSDC0_DAT2 (MTK_PIN_NO(125) | 1)
> +#define PINMUX_GPIO125__FUNC_MRG_CLK (MTK_PIN_NO(125) | 3)
> +#define PINMUX_GPIO125__FUNC_DBG_MON_A15 (MTK_PIN_NO(125) | 7)
> +
> +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
> +#define PINMUX_GPIO126__FUNC_MSDC0_DAT4 (MTK_PIN_NO(126) | 1)
> +#define PINMUX_GPIO126__FUNC_ANT_SEL5 (MTK_PIN_NO(126) | 3)
> +#define PINMUX_GPIO126__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(126) | 6)
> +#define PINMUX_GPIO126__FUNC_DBG_MON_A16 (MTK_PIN_NO(126) | 7)
> +
> +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
> +#define PINMUX_GPIO127__FUNC_MSDC0_DAT6 (MTK_PIN_NO(127) | 1)
> +#define PINMUX_GPIO127__FUNC_ANT_SEL4 (MTK_PIN_NO(127) | 3)
> +#define PINMUX_GPIO127__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(127) | 6)
> +#define PINMUX_GPIO127__FUNC_DBG_MON_A17 (MTK_PIN_NO(127) | 7)
> +
> +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
> +#define PINMUX_GPIO128__FUNC_MSDC0_DAT1 (MTK_PIN_NO(128) | 1)
> +#define PINMUX_GPIO128__FUNC_ANT_SEL2 (MTK_PIN_NO(128) | 3)
> +#define PINMUX_GPIO128__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(128) | 6)
> +#define PINMUX_GPIO128__FUNC_DBG_MON_A18 (MTK_PIN_NO(128) | 7)
> +
> +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
> +#define PINMUX_GPIO129__FUNC_MSDC0_DAT5 (MTK_PIN_NO(129) | 1)
> +#define PINMUX_GPIO129__FUNC_ANT_SEL3 (MTK_PIN_NO(129) | 3)
> +#define PINMUX_GPIO129__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(129) | 6)
> +#define PINMUX_GPIO129__FUNC_DBG_MON_A23 (MTK_PIN_NO(129) | 7)
> +
> +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
> +#define PINMUX_GPIO130__FUNC_MSDC0_DAT7 (MTK_PIN_NO(130) | 1)
> +#define PINMUX_GPIO130__FUNC_MRG_DO (MTK_PIN_NO(130) | 3)
> +#define PINMUX_GPIO130__FUNC_DBG_MON_A24 (MTK_PIN_NO(130) | 7)
> +
> +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
> +#define PINMUX_GPIO131__FUNC_MSDC0_DSL (MTK_PIN_NO(131) | 1)
> +#define PINMUX_GPIO131__FUNC_MRG_SYNC (MTK_PIN_NO(131) | 3)
> +#define PINMUX_GPIO131__FUNC_DBG_MON_A25 (MTK_PIN_NO(131) | 7)
> +
> +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
> +#define PINMUX_GPIO132__FUNC_MSDC0_DAT3 (MTK_PIN_NO(132) | 1)
> +#define PINMUX_GPIO132__FUNC_MRG_DI (MTK_PIN_NO(132) | 3)
> +#define PINMUX_GPIO132__FUNC_DBG_MON_A26 (MTK_PIN_NO(132) | 7)
> +
> +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
> +#define PINMUX_GPIO133__FUNC_MSDC0_RSTB (MTK_PIN_NO(133) | 1)
> +#define PINMUX_GPIO133__FUNC_AGPS_SYNC (MTK_PIN_NO(133) | 3)
> +#define PINMUX_GPIO133__FUNC_DBG_MON_A27 (MTK_PIN_NO(133) | 7)
> +
> +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
> +#define PINMUX_GPIO134__FUNC_RTC32K_CK (MTK_PIN_NO(134) | 1)
> +
> +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
> +#define PINMUX_GPIO135__FUNC_WATCHDOG (MTK_PIN_NO(135) | 1)
> +
> +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
> +#define PINMUX_GPIO136__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(136) | 1)
> +#define PINMUX_GPIO136__FUNC_AUD_CLK_MISO (MTK_PIN_NO(136) | 2)
> +#define PINMUX_GPIO136__FUNC_I2S1_MCK (MTK_PIN_NO(136) | 3)
> +#define PINMUX_GPIO136__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(136) | 6)
> +
> +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
> +#define PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(137) | 1)
> +#define PINMUX_GPIO137__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(137) | 2)
> +#define PINMUX_GPIO137__FUNC_I2S1_BCK (MTK_PIN_NO(137) | 3)
> +
> +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
> +#define PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(138) | 1)
> +#define PINMUX_GPIO138__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(138) | 2)
> +#define PINMUX_GPIO138__FUNC_I2S1_LRCK (MTK_PIN_NO(138) | 3)
> +#define PINMUX_GPIO138__FUNC_DBG_MON_B24 (MTK_PIN_NO(138) | 7)
> +
> +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
> +#define PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(139) | 1)
> +#define PINMUX_GPIO139__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(139) | 2)
> +#define PINMUX_GPIO139__FUNC_I2S1_DO (MTK_PIN_NO(139) | 3)
> +#define PINMUX_GPIO139__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(139) | 6)
> +
> +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
> +#define PINMUX_GPIO140__FUNC_AUD_CLK_MISO (MTK_PIN_NO(140) | 1)
> +#define PINMUX_GPIO140__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(140) | 2)
> +#define PINMUX_GPIO140__FUNC_I2S0_MCK (MTK_PIN_NO(140) | 3)
> +#define PINMUX_GPIO140__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(140) | 6)
> +
> +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
> +#define PINMUX_GPIO141__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(141) | 1)
> +#define PINMUX_GPIO141__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(141) | 2)
> +#define PINMUX_GPIO141__FUNC_I2S0_BCK (MTK_PIN_NO(141) | 3)
> +
> +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
> +#define PINMUX_GPIO142__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(142) | 1)
> +#define PINMUX_GPIO142__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(142) | 2)
> +#define PINMUX_GPIO142__FUNC_I2S0_LRCK (MTK_PIN_NO(142) | 3)
> +#define PINMUX_GPIO142__FUNC_VOW_DAT_MISO (MTK_PIN_NO(142) | 4)
> +#define PINMUX_GPIO142__FUNC_DBG_MON_B25 (MTK_PIN_NO(142) | 7)
> +
> +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
> +#define PINMUX_GPIO143__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(143) | 1)
> +#define PINMUX_GPIO143__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(143) | 2)
> +#define PINMUX_GPIO143__FUNC_I2S0_DI (MTK_PIN_NO(143) | 3)
> +#define PINMUX_GPIO143__FUNC_VOW_CLK_MISO (MTK_PIN_NO(143) | 4)
> +#define PINMUX_GPIO143__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(143) | 6)
> +#define PINMUX_GPIO143__FUNC_DBG_MON_B26 (MTK_PIN_NO(143) | 7)
> +
> +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
> +#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(144) | 1)
> +#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(144) | 2)
> +
> +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
> +#define PINMUX_GPIO145__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(145) | 1)
> +
> +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
> +#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(146) | 1)
> +#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(146) | 2)
> +
> +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
> +#define PINMUX_GPIO147__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(147) | 1)
> +
> +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
> +#define PINMUX_GPIO148__FUNC_SRCLKENA0 (MTK_PIN_NO(148) | 1)
> +
> +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
> +#define PINMUX_GPIO149__FUNC_SRCLKENA1 (MTK_PIN_NO(149) | 1)
> +
> +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
> +#define PINMUX_GPIO150__FUNC_PWM_A (MTK_PIN_NO(150) | 1)
> +#define PINMUX_GPIO150__FUNC_CMFLASH (MTK_PIN_NO(150) | 2)
> +#define PINMUX_GPIO150__FUNC_CLKM0 (MTK_PIN_NO(150) | 3)
> +#define PINMUX_GPIO150__FUNC_DBG_MON_B30 (MTK_PIN_NO(150) | 7)
> +
> +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
> +#define PINMUX_GPIO151__FUNC_PWM_B (MTK_PIN_NO(151) | 1)
> +#define PINMUX_GPIO151__FUNC_CMVREF0 (MTK_PIN_NO(151) | 2)
> +#define PINMUX_GPIO151__FUNC_CLKM1 (MTK_PIN_NO(151) | 3)
> +#define PINMUX_GPIO151__FUNC_DBG_MON_B20 (MTK_PIN_NO(151) | 7)
> +
> +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
> +#define PINMUX_GPIO152__FUNC_PWM_C (MTK_PIN_NO(152) | 1)
> +#define PINMUX_GPIO152__FUNC_CMFLASH (MTK_PIN_NO(152) | 2)
> +#define PINMUX_GPIO152__FUNC_CLKM2 (MTK_PIN_NO(152) | 3)
> +#define PINMUX_GPIO152__FUNC_DBG_MON_B21 (MTK_PIN_NO(152) | 7)
> +
> +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
> +#define PINMUX_GPIO153__FUNC_PWM_A (MTK_PIN_NO(153) | 1)
> +#define PINMUX_GPIO153__FUNC_CMVREF0 (MTK_PIN_NO(153) | 2)
> +#define PINMUX_GPIO153__FUNC_CLKM3 (MTK_PIN_NO(153) | 3)
> +#define PINMUX_GPIO153__FUNC_DBG_MON_B22 (MTK_PIN_NO(153) | 7)
> +
> +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
> +#define PINMUX_GPIO154__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(154) | 1)
> +#define PINMUX_GPIO154__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(154) | 2)
> +#define PINMUX_GPIO154__FUNC_DBG_MON_B18 (MTK_PIN_NO(154) | 7)
> +
> +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
> +#define PINMUX_GPIO155__FUNC_ANT_SEL0 (MTK_PIN_NO(155) | 1)
> +#define PINMUX_GPIO155__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(155) | 2)
> +#define PINMUX_GPIO155__FUNC_CMVREF1 (MTK_PIN_NO(155) | 3)
> +#define PINMUX_GPIO155__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(155) | 7)
> +
> +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
> +#define PINMUX_GPIO156__FUNC_ANT_SEL1 (MTK_PIN_NO(156) | 1)
> +#define PINMUX_GPIO156__FUNC_SRCLKENAI0 (MTK_PIN_NO(156) | 2)
> +#define PINMUX_GPIO156__FUNC_SCL6 (MTK_PIN_NO(156) | 3)
> +#define PINMUX_GPIO156__FUNC_KPCOL2 (MTK_PIN_NO(156) | 4)
> +#define PINMUX_GPIO156__FUNC_IDDIG (MTK_PIN_NO(156) | 5)
> +#define PINMUX_GPIO156__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(156) | 7)
> +
> +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
> +#define PINMUX_GPIO157__FUNC_ANT_SEL2 (MTK_PIN_NO(157) | 1)
> +#define PINMUX_GPIO157__FUNC_SRCLKENAI1 (MTK_PIN_NO(157) | 2)
> +#define PINMUX_GPIO157__FUNC_SDA6 (MTK_PIN_NO(157) | 3)
> +#define PINMUX_GPIO157__FUNC_KPROW2 (MTK_PIN_NO(157) | 4)
> +#define PINMUX_GPIO157__FUNC_USB_DRVVBUS (MTK_PIN_NO(157) | 5)
> +#define PINMUX_GPIO157__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(157) | 7)
> +
> +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
> +#define PINMUX_GPIO158__FUNC_ANT_SEL3 (MTK_PIN_NO(158) | 1)
> +
> +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
> +#define PINMUX_GPIO159__FUNC_ANT_SEL4 (MTK_PIN_NO(159) | 1)
> +
> +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
> +#define PINMUX_GPIO160__FUNC_ANT_SEL5 (MTK_PIN_NO(160) | 1)
> +
> +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
> +#define PINMUX_GPIO161__FUNC_SPI1_A_MI (MTK_PIN_NO(161) | 1)
> +#define PINMUX_GPIO161__FUNC_SCP_SPI1_MI (MTK_PIN_NO(161) | 2)
> +#define PINMUX_GPIO161__FUNC_IDDIG (MTK_PIN_NO(161) | 3)
> +#define PINMUX_GPIO161__FUNC_ANT_SEL6 (MTK_PIN_NO(161) | 4)
> +#define PINMUX_GPIO161__FUNC_KPCOL2 (MTK_PIN_NO(161) | 5)
> +#define PINMUX_GPIO161__FUNC_PTA_RXD (MTK_PIN_NO(161) | 6)
> +#define PINMUX_GPIO161__FUNC_DBG_MON_B19 (MTK_PIN_NO(161) | 7)
> +
> +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
> +#define PINMUX_GPIO162__FUNC_SPI1_A_CSB (MTK_PIN_NO(162) | 1)
> +#define PINMUX_GPIO162__FUNC_SCP_SPI1_CS (MTK_PIN_NO(162) | 2)
> +#define PINMUX_GPIO162__FUNC_USB_DRVVBUS (MTK_PIN_NO(162) | 3)
> +#define PINMUX_GPIO162__FUNC_ANT_SEL5 (MTK_PIN_NO(162) | 4)
> +#define PINMUX_GPIO162__FUNC_KPROW2 (MTK_PIN_NO(162) | 5)
> +#define PINMUX_GPIO162__FUNC_PTA_TXD (MTK_PIN_NO(162) | 6)
> +
> +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
> +#define PINMUX_GPIO163__FUNC_SPI1_A_MO (MTK_PIN_NO(163) | 1)
> +#define PINMUX_GPIO163__FUNC_SCP_SPI1_MO (MTK_PIN_NO(163) | 2)
> +#define PINMUX_GPIO163__FUNC_SDA1 (MTK_PIN_NO(163) | 3)
> +#define PINMUX_GPIO163__FUNC_ANT_SEL4 (MTK_PIN_NO(163) | 4)
> +#define PINMUX_GPIO163__FUNC_CMMCLK2 (MTK_PIN_NO(163) | 5)
> +#define PINMUX_GPIO163__FUNC_DMIC_CLK (MTK_PIN_NO(163) | 6)
> +
> +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
> +#define PINMUX_GPIO164__FUNC_SPI1_A_CLK (MTK_PIN_NO(164) | 1)
> +#define PINMUX_GPIO164__FUNC_SCP_SPI1_CK (MTK_PIN_NO(164) | 2)
> +#define PINMUX_GPIO164__FUNC_SCL1 (MTK_PIN_NO(164) | 3)
> +#define PINMUX_GPIO164__FUNC_ANT_SEL3 (MTK_PIN_NO(164) | 4)
> +#define PINMUX_GPIO164__FUNC_CMMCLK3 (MTK_PIN_NO(164) | 5)
> +#define PINMUX_GPIO164__FUNC_DMIC_DAT (MTK_PIN_NO(164) | 6)
> +
> +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
> +#define PINMUX_GPIO165__FUNC_PWM_B (MTK_PIN_NO(165) | 1)
> +#define PINMUX_GPIO165__FUNC_CMMCLK2 (MTK_PIN_NO(165) | 2)
> +#define PINMUX_GPIO165__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(165) | 3)
> +#define PINMUX_GPIO165__FUNC_TDM_MCK_2ND (MTK_PIN_NO(165) | 6)
> +#define PINMUX_GPIO165__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(165) | 7)
> +
> +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
> +#define PINMUX_GPIO166__FUNC_ANT_SEL6 (MTK_PIN_NO(166) | 1)
> +
> +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
> +#define PINMUX_GPIO167__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(167) | 1)
> +#define PINMUX_GPIO167__FUNC_SPM_BSI_EN (MTK_PIN_NO(167) | 2)
> +
> +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
> +#define PINMUX_GPIO168__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(168) | 1)
> +#define PINMUX_GPIO168__FUNC_SPM_BSI_CK (MTK_PIN_NO(168) | 2)
> +
> +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
> +#define PINMUX_GPIO169__FUNC_PWM_C (MTK_PIN_NO(169) | 1)
> +#define PINMUX_GPIO169__FUNC_CMMCLK3 (MTK_PIN_NO(169) | 2)
> +#define PINMUX_GPIO169__FUNC_CMVREF1 (MTK_PIN_NO(169) | 3)
> +#define PINMUX_GPIO169__FUNC_ANT_SEL7 (MTK_PIN_NO(169) | 4)
> +#define PINMUX_GPIO169__FUNC_AGPS_SYNC (MTK_PIN_NO(169) | 5)
> +#define PINMUX_GPIO169__FUNC_TDM_BCK_2ND (MTK_PIN_NO(169) | 6)
> +#define PINMUX_GPIO169__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(169) | 7)
> +
> +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
> +#define PINMUX_GPIO170__FUNC_I2S1_BCK (MTK_PIN_NO(170) | 1)
> +#define PINMUX_GPIO170__FUNC_I2S3_BCK (MTK_PIN_NO(170) | 2)
> +#define PINMUX_GPIO170__FUNC_SCL7 (MTK_PIN_NO(170) | 3)
> +#define PINMUX_GPIO170__FUNC_I2S5_BCK (MTK_PIN_NO(170) | 4)
> +#define PINMUX_GPIO170__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(170) | 5)
> +#define PINMUX_GPIO170__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(170) | 6)
> +#define PINMUX_GPIO170__FUNC_ANT_SEL3 (MTK_PIN_NO(170) | 7)
> +
> +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
> +#define PINMUX_GPIO171__FUNC_I2S1_LRCK (MTK_PIN_NO(171) | 1)
> +#define PINMUX_GPIO171__FUNC_I2S3_LRCK (MTK_PIN_NO(171) | 2)
> +#define PINMUX_GPIO171__FUNC_SDA7 (MTK_PIN_NO(171) | 3)
> +#define PINMUX_GPIO171__FUNC_I2S5_LRCK (MTK_PIN_NO(171) | 4)
> +#define PINMUX_GPIO171__FUNC_URXD1 (MTK_PIN_NO(171) | 5)
> +#define PINMUX_GPIO171__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(171) | 6)
> +#define PINMUX_GPIO171__FUNC_ANT_SEL4 (MTK_PIN_NO(171) | 7)
> +
> +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
> +#define PINMUX_GPIO172__FUNC_I2S1_DO (MTK_PIN_NO(172) | 1)
> +#define PINMUX_GPIO172__FUNC_I2S3_DO (MTK_PIN_NO(172) | 2)
> +#define PINMUX_GPIO172__FUNC_SCL8 (MTK_PIN_NO(172) | 3)
> +#define PINMUX_GPIO172__FUNC_I2S5_DO (MTK_PIN_NO(172) | 4)
> +#define PINMUX_GPIO172__FUNC_UTXD1 (MTK_PIN_NO(172) | 5)
> +#define PINMUX_GPIO172__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(172) | 6)
> +#define PINMUX_GPIO172__FUNC_ANT_SEL5 (MTK_PIN_NO(172) | 7)
> +
> +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
> +#define PINMUX_GPIO173__FUNC_I2S1_MCK (MTK_PIN_NO(173) | 1)
> +#define PINMUX_GPIO173__FUNC_I2S3_MCK (MTK_PIN_NO(173) | 2)
> +#define PINMUX_GPIO173__FUNC_SDA8 (MTK_PIN_NO(173) | 3)
> +#define PINMUX_GPIO173__FUNC_I2S5_MCK (MTK_PIN_NO(173) | 4)
> +#define PINMUX_GPIO173__FUNC_UCTS0 (MTK_PIN_NO(173) | 5)
> +#define PINMUX_GPIO173__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(173) | 6)
> +#define PINMUX_GPIO173__FUNC_ANT_SEL6 (MTK_PIN_NO(173) | 7)
> +
> +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
> +#define PINMUX_GPIO174__FUNC_I2S2_DI (MTK_PIN_NO(174) | 1)
> +#define PINMUX_GPIO174__FUNC_I2S0_DI (MTK_PIN_NO(174) | 2)
> +#define PINMUX_GPIO174__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(174) | 3)
> +#define PINMUX_GPIO174__FUNC_I2S2_DI2 (MTK_PIN_NO(174) | 4)
> +#define PINMUX_GPIO174__FUNC_URTS0 (MTK_PIN_NO(174) | 5)
> +#define PINMUX_GPIO174__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(174) | 6)
> +#define PINMUX_GPIO174__FUNC_ANT_SEL7 (MTK_PIN_NO(174) | 7)
> +
> +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
> +#define PINMUX_GPIO175__FUNC_ANT_SEL7 (MTK_PIN_NO(175) | 1)
> +
> +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
> +
> +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
> +
> +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
> +
> +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
> +
> +#endif /* __MT8183-PINFUNC_H */
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> new file mode 100644
> index 0000000..63db9cc
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -0,0 +1,408 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Ben Ho <ben.ho@mediatek.com>
> + *	   Erin Lo <erin.lo@mediatek.com>
> + */
> +
> +#include <dt-bindings/clock/mt8183-clk.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include "mt8183-pinfunc.h"
> +
> +/ {
> +	compatible = "mediatek,mt8183";
> +	interrupt-parent = <&sysirq>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +				core2 {
> +					cpu = <&cpu2>;
> +				};
> +				core3 {
> +					cpu = <&cpu3>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&cpu4>;
> +				};
> +				core1 {
> +					cpu = <&cpu5>;
> +				};
> +				core2 {
> +					cpu = <&cpu6>;
> +				};
> +				core3 {
> +					cpu = <&cpu7>;
> +				};
> +			};
> +		};
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x000>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x001>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu2: cpu@2 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x002>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu3: cpu@3 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x003>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu4: cpu@100 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x100>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu5: cpu@101 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x101>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu6: cpu@102 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x102>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu7: cpu@103 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x103>;
> +			enable-method = "psci";
> +		};
> +	};
> +
> +	pmu-a53 {
> +		compatible = "arm,cortex-a53-pmu";
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
> +	};
> +
> +	pmu-a73 {
> +		compatible = "arm,cortex-a73-pmu";
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
> +	};
> +
> +	psci {
> +		compatible      = "arm,psci-1.0";
> +		method          = "smc";
> +	};
> +
> +	clk26m: oscillator {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <26000000>;
> +		clock-output-names = "clk26m";
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
> +	};
> +
> +	gic: interrupt-controller@c000000 {
> +		compatible = "arm,gic-v3";
> +		#interrupt-cells = <4>;
> +		interrupt-parent = <&gic>;
> +		interrupt-controller;
> +		reg = <0 0x0c000000 0 0x40000>,  /* GICD */
> +		      <0 0x0c100000 0 0x200000>, /* GICR */
> +		      <0 0x0c400000 0 0x2000>,   /* GICC */
> +		      <0 0x0c410000 0 0x1000>,   /* GICH */
> +		      <0 0x0c420000 0 0x2000>;   /* GICV */
> +
> +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> +		ppi-partitions {
> +			ppi_cluster0: interrupt-partition-0 {
> +				affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
> +			};
> +			ppi_cluster1: interrupt-partition-1 {
> +				affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
> +			};
> +		};
> +	};
> +
> +	mcucfg: syscon@c530000 {
> +		compatible = "mediatek,mt8183-mcucfg", "syscon";
> +		reg = <0 0x0c530000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	sysirq: intpol-controller@c530a80 {
> +		compatible = "mediatek,mt8183-sysirq",
> +			     "mediatek,mt6577-sysirq";
> +		interrupt-controller;
> +		#interrupt-cells = <4>;
> +		interrupt-parent = <&gic>;
> +		reg = <0 0x0c530a80 0 0x50>;
> +	};
> +
> +	topckgen: syscon@10000000 {
> +		compatible = "mediatek,mt8183-topckgen", "syscon";
> +		reg = <0 0x10000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	infracfg: syscon@10001000 {
> +		compatible = "mediatek,mt8183-infracfg", "syscon";
> +		reg = <0 0x10001000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	pio: pinctrl@1000b000 {
> +		compatible = "mediatek,mt8183-pinctrl";
> +		reg = <0 0x10005000 0 0x1000>,
> +		      <0 0x11f20000 0 0x1000>,
> +		      <0 0x11e80000 0 0x1000>,
> +		      <0 0x11e70000 0 0x1000>,
> +		      <0 0x11e90000 0 0x1000>,
> +		      <0 0x11d30000 0 0x1000>,
> +		      <0 0x11d20000 0 0x1000>,
> +		      <0 0x11c50000 0 0x1000>,
> +		      <0 0x11f30000 0 0x1000>,
> +		      <0 0x1000b000 0 0x1000>;
> +		reg-names = "iocfg0", "iocfg1", "iocfg2",
> +			    "iocfg3", "iocfg4", "iocfg5",
> +			    "iocfg6", "iocfg7", "iocfg8",
> +			    "eint";
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		gpio-ranges = <&pio 0 0 192>;
> +		interrupt-controller;
> +		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-parent = <&gic>;
> +		#interrupt-cells = <4>;
> +	};
> +
> +	apmixedsys: syscon@1000c000 {
> +		compatible = "mediatek,mt8183-apmixedsys", "syscon";
> +		reg = <0 0x1000c000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	pwrap: pwrap@1000d000 {
> +		compatible = "mediatek,mt8183-pwrap";
> +		reg = <0 0x1000d000 0 0x1000>;
> +		reg-names = "pwrap";
> +		interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
> +			 <&infracfg CLK_INFRA_PMIC_AP>;
> +		clock-names = "spi", "wrap";
> +	};
> +
> +	uart0: serial@11002000 {
> +		compatible = "mediatek,mt8183-uart",
> +			     "mediatek,mt6577-uart";
> +		reg = <0 0x11002000 0 0x1000>;
> +		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW 0>;
> +		clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
> +		clock-names = "baud", "bus";
> +		status = "disabled";
> +	};
> +
> +	uart1: serial@11003000 {
> +		compatible = "mediatek,mt8183-uart",
> +			     "mediatek,mt6577-uart";
> +		reg = <0 0x11003000 0 0x1000>;
> +		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW 0>;
> +		clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
> +		clock-names = "baud", "bus";
> +		status = "disabled";
> +	};
> +
> +	uart2: serial@11004000 {
> +		compatible = "mediatek,mt8183-uart",
> +			     "mediatek,mt6577-uart";
> +		reg = <0 0x11004000 0 0x1000>;
> +		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW 0>;
> +		clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
> +		clock-names = "baud", "bus";
> +		status = "disabled";
> +	};
> +
> +	spi0: spi@1100a000 {
> +		compatible = "mediatek,mt8183-spi";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0 0x1100a000 0 0x1000>;
> +		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW 0>;
> +		clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> +			 <&topckgen CLK_TOP_MUX_SPI>,
> +			 <&infracfg CLK_INFRA_SPI0>;
> +		clock-names = "parent-clk", "sel-clk", "spi-clk";
> +		status = "disabled";
> +	};
> +
> +	spi1: spi@11010000 {
> +		compatible = "mediatek,mt8183-spi";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0 0x11010000 0 0x1000>;
> +		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW 0>;
> +		clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> +			 <&topckgen CLK_TOP_MUX_SPI>,
> +			 <&infracfg CLK_INFRA_SPI1>;
> +		clock-names = "parent-clk", "sel-clk", "spi-clk";
> +		status = "disabled";
> +	};
> +
> +	spi2: spi@11012000 {
> +		compatible = "mediatek,mt8183-spi";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0 0x11012000 0 0x1000>;
> +		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW 0>;
> +		clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> +			 <&topckgen CLK_TOP_MUX_SPI>,
> +			 <&infracfg CLK_INFRA_SPI2>;
> +		clock-names = "parent-clk", "sel-clk", "spi-clk";
> +		status = "disabled";
> +	};
> +
> +	spi3: spi@11013000 {
> +		compatible = "mediatek,mt8183-spi";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0 0x11013000 0 0x1000>;
> +		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW 0>;
> +		clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> +			 <&topckgen CLK_TOP_MUX_SPI>,
> +			 <&infracfg CLK_INFRA_SPI3>;
> +		clock-names = "parent-clk", "sel-clk", "spi-clk";
> +		status = "disabled";
> +	};
> +
> +	spi4: spi@11018000 {
> +		compatible = "mediatek,mt8183-spi";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0 0x11018000 0 0x1000>;
> +		interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW 0>;
> +		clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> +			 <&topckgen CLK_TOP_MUX_SPI>,
> +			 <&infracfg CLK_INFRA_SPI4>;
> +		clock-names = "parent-clk", "sel-clk", "spi-clk";
> +		status = "disabled";
> +	};
> +
> +	spi5: spi@11019000 {
> +		compatible = "mediatek,mt8183-spi";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0 0x11019000 0 0x1000>;
> +		interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW 0>;
> +		clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> +			 <&topckgen CLK_TOP_MUX_SPI>,
> +			 <&infracfg CLK_INFRA_SPI5>;
> +		clock-names = "parent-clk", "sel-clk", "spi-clk";
> +		status = "disabled";
> +	};
> +
> +	audiosys: syscon@11220000 {
> +		compatible = "mediatek,mt8183-audiosys", "syscon";
> +		reg = <0 0x11220000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	mfgcfg: syscon@13000000 {
> +		compatible = "mediatek,mt8183-mfgcfg", "syscon";
> +		reg = <0 0x13000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	mmsys: syscon@14000000 {
> +		compatible = "mediatek,mt8183-mmsys", "syscon";
> +		reg = <0 0x14000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	imgsys: syscon@15020000 {
> +		compatible = "mediatek,mt8183-imgsys", "syscon";
> +		reg = <0 0x15020000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	vdecsys: syscon@16000000 {
> +		compatible = "mediatek,mt8183-vdecsys", "syscon";
> +		reg = <0 0x16000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	vencsys: syscon@17000000 {
> +		compatible = "mediatek,mt8183-vencsys", "syscon";
> +		reg = <0 0x17000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	ipu_conn: syscon@19000000 {
> +		compatible = "mediatek,mt8183-ipu_conn", "syscon";
> +		reg = <0 0x19000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	ipu_adl: syscon@19010000 {
> +		compatible = "mediatek,mt8183-ipu_adl", "syscon";
> +		reg = <0 0x19010000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	ipu_core0: syscon@19180000 {
> +		compatible = "mediatek,mt8183-ipu_core0", "syscon";
> +		reg = <0 0x19180000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	ipu_core1: syscon@19280000 {
> +		compatible = "mediatek,mt8183-ipu_core1", "syscon";
> +		reg = <0 0x19280000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	camsys: syscon@1a000000 {
> +		compatible = "mediatek,mt8183-camsys", "syscon";
> +		reg = <0 0x1a000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +};
> 

^ permalink raw reply

* Re: [PATCH v6 5/6] dt-bindings: pinctrl: mt8183: add binding document
From: Matthias Brugger @ 2019-02-07 15:28 UTC (permalink / raw)
  To: Erin Lo, Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Marc Zyngier, Greg Kroah-Hartman, Stephen Boyd
  Cc: devicetree, srv_heupstream, linux-kernel, linux-serial,
	linux-mediatek, linux-arm-kernel, yingjoe.chen, mars.cheng,
	eddie.huang, linux-clk, Zhiyong Tao
In-Reply-To: <1548317240-44682-6-git-send-email-erin.lo@mediatek.com>



On 24/01/2019 09:07, Erin Lo wrote:
> From: Zhiyong Tao <zhiyong.tao@mediatek.com>
> 
> The commit adds mt8183 compatible node in binding document.
> 
> Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> ---

I'm missing Linus Walleij on the recipient list.
Pleas make sure to add all persons from the get_maintainers script.
IMHO it's a bit unfortunate that we got the driver merged, but no binding
description. Please try to send driver + binding documentation together, that
makes things easier to discuss.

Thanks,
Matthias

>  .../devicetree/bindings/pinctrl/pinctrl-mt8183.txt | 115 +++++++++++++++++++++
>  1 file changed, 115 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt
> new file mode 100644
> index 0000000..364e673
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt
> @@ -0,0 +1,115 @@
> +* Mediatek MT8183 Pin Controller
> +
> +The Mediatek's Pin controller is used to control SoC pins.
> +
> +Required properties:
> +- compatible: value should be one of the following.
> +	"mediatek,mt8183-pinctrl", compatible with mt8183 pinctrl.
> +- gpio-controller : Marks the device node as a gpio controller.
> +- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
> +  binding is used, the amount of cells must be specified as 2. See the below
> +  mentioned gpio binding representation for description of particular cells.
> +- gpio-ranges : gpio valid number range.
> +- reg: physicall address base for gpio base registers. There are nine
> +  physicall address base in mt8183. They are 0x10005000, 0x11F20000,
> +  0x11E80000, 0x11E70000, 0x11E90000, 0x11D30000, 0x11D20000, 0x11C50000,
> +  0x11F30000.
> +
> +	Eg: <&pio 6 0>
> +	<[phandle of the gpio controller node]
> +	[line number within the gpio controller]
> +	[flags]>
> +
> +	Values for gpio specifier:
> +	- Line number: is a value between 0 to 202.
> +	- Flags:  bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
> +            Only the following flags are supported:
> +            0 - GPIO_ACTIVE_HIGH
> +            1 - GPIO_ACTIVE_LOW
> +
> +Optional properties:
> +- reg-names: gpio base register names. There are nine gpio base register
> +  names in mt8183. They are "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4",
> +  "iocfg5", "iocfg6", "iocfg7", "iocfg8".
> +- interrupt-controller: Marks the device node as an interrupt controller
> +- #interrupt-cells: Should be two.
> +- interrupts : The interrupt outputs from the controller.
> +
> +Please refer to pinctrl-bindings.txt in this directory for details of the
> +common pinctrl bindings used by client devices.
> +
> +Subnode format
> +A pinctrl node should contain at least one subnodes representing the
> +pinctrl groups available on the machine. Each subnode will list the
> +pins it needs, and how they should be configured, with regard to muxer
> +configuration, pullups, drive strength, input enable/disable and input schmitt.
> +
> +    node {
> +	pinmux = <PIN_NUMBER_PINMUX>;
> +	GENERIC_PINCONFIG;
> +    };
> +
> +Required properties:
> +- pinmux: integer array, represents gpio pin number and mux setting.
> +    Supported pin number and mux varies for different SoCs, and are defined
> +    as macros in boot/dts/<soc>-pinfunc.h directly.
> +
> +Optional properties:
> +- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
> +    bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high,
> +    input-schmitt-enable, input-schmitt-disable and drive-strength are valid.
> +
> +    Some special pins have extra pull up strength, there are R0 and R1 pull-up
> +    resistors available, but for user, it's only need to set R1R0 as 00, 01, 10 or 11.
> +    So when config mediatek,pull-up-adv or mediatek,pull-down-adv,
> +    it support arguments for those special pins.
> +
> +    When config drive-strength, it can support some arguments, such as
> +    MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h.
> +
> +Examples:
> +
> +#include "mt8183-pinfunc.h"
> +
> +...
> +{
> +	pio: pinctrl@10005000 {
> +		compatible = "mediatek,mt8183-pinctrl";
> +		reg = <0 0x10005000 0 0x1000>,
> +		      <0 0x11F20000 0 0x1000>,
> +		      <0 0x11E80000 0 0x1000>,
> +		      <0 0x11E70000 0 0x1000>,
> +		      <0 0x11E90000 0 0x1000>,
> +		      <0 0x11D30000 0 0x1000>,
> +		      <0 0x11D20000 0 0x1000>,
> +		      <0 0x11C50000 0 0x1000>,
> +		      <0 0x11F30000 0 0x1000>;
> +		reg-names = "iocfg0", "iocfg1", "iocfg2",
> +			    "iocfg3", "iocfg4", "iocfg5",
> +			    "iocfg6", "iocfg7", "iocfg8";
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		gpio-ranges = <&pio 0 0 192>;
> +		interrupt-controller;
> +		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-parent = <&gic>;
> +		#interrupt-cells = <2>;
> +
> +		i2c0_pins_a: i2c0 {
> +			pins1 {
> +				pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
> +					 <PINMUX_GPIO49__FUNC_SDA5>;
> +				mediatek,pull-up-adv = <11>;
> +			};
> +		};
> +
> +		i2c1_pins_a: i2c1 {
> +			pins {
> +				pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
> +					 <PINMUX_GPIO51__FUNC_SDA3>;
> +				mediatek,pull-down-adv = <10>;
> +			};
> +		};
> +		...
> +	};
> +};
> 

^ permalink raw reply

* Re: [PATCH v6 1/6] irqchip/mtk-sysirq: support 4 interrupt parameters for sysirq
From: Matthias Brugger @ 2019-02-07 15:20 UTC (permalink / raw)
  To: Erin Lo, Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Marc Zyngier, Greg Kroah-Hartman, Stephen Boyd
  Cc: devicetree, srv_heupstream, linux-kernel, linux-serial,
	linux-mediatek, linux-arm-kernel, yingjoe.chen, mars.cheng,
	eddie.huang, linux-clk, Seiya Wang
In-Reply-To: <1548317240-44682-2-git-send-email-erin.lo@mediatek.com>



On 24/01/2019 09:07, Erin Lo wrote:
> From: Seiya Wang <seiya.wang@mediatek.com>
> 
> To support partitioned PPIs, 4 interrupt parameters should be valid
> for sysirq.
> 
> Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> ---
>  drivers/irqchip/irq-mtk-sysirq.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-mtk-sysirq.c b/drivers/irqchip/irq-mtk-sysirq.c
> index 90aaf19..282736a 100644
> --- a/drivers/irqchip/irq-mtk-sysirq.c
> +++ b/drivers/irqchip/irq-mtk-sysirq.c
> @@ -81,7 +81,7 @@ static int mtk_sysirq_domain_translate(struct irq_domain *d,
>  				       unsigned int *type)
>  {
>  	if (is_of_node(fwspec->fwnode)) {
> -		if (fwspec->param_count != 3)
> +		if (fwspec->param_count != 3 && fwspec->param_count != 4)

Where is this 4th parameter used?

Regards,
Matthias

>  			return -EINVAL;
>  
>  		/* No PPI should point to this domain */
> @@ -104,7 +104,7 @@ static int mtk_sysirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
>  	struct irq_fwspec *fwspec = arg;
>  	struct irq_fwspec gic_fwspec = *fwspec;
>  
> -	if (fwspec->param_count != 3)
> +	if (fwspec->param_count != 3 && fwspec->param_count != 4)
>  		return -EINVAL;
>  
>  	/* sysirq doesn't support PPI */
> 

^ permalink raw reply

* Re: [PATCH v6 2/6] dt-bindings: arm: Add bindings for Mediatek MT8183 SoC Platform
From: Matthias Brugger @ 2019-02-07 15:15 UTC (permalink / raw)
  To: Erin Lo, Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
	Marc Zyngier, Greg Kroah-Hartman, Stephen Boyd
  Cc: devicetree, srv_heupstream, mars.cheng, linux-kernel,
	linux-mediatek, linux-serial, yingjoe.chen, eddie.huang,
	linux-clk, linux-arm-kernel
In-Reply-To: <1548317240-44682-3-git-send-email-erin.lo@mediatek.com>



On 24/01/2019 09:07, Erin Lo wrote:
> This adds dt-binding documentation of cpu for Mediatek MT8183.
> 
> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> Reviewed-by: Rob Herring <robh@kernel.org>

pushed to v5.0-next/dts64

Thanks,
Matthias

> ---
>  Documentation/devicetree/bindings/arm/mediatek.txt | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
> index 8f260e5..f6d6ed3 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek.txt
> +++ b/Documentation/devicetree/bindings/arm/mediatek.txt
> @@ -20,6 +20,7 @@ compatible: Must contain one of
>     "mediatek,mt8127"
>     "mediatek,mt8135"
>     "mediatek,mt8173"
> +   "mediatek,mt8183"
>  
>  
>  Supported boards:
> @@ -77,3 +78,6 @@ Supported boards:
>  - MTK mt8173 tablet EVB:
>      Required root node properties:
>        - compatible = "mediatek,mt8173-evb", "mediatek,mt8173";
> +- Evaluation board for MT8183:
> +    Required root node properties:
> +      - compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
> 

^ permalink raw reply

* Re: [PATCH v6 6/6] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile
From: Matthias Brugger @ 2019-02-07 15:08 UTC (permalink / raw)
  To: Erin Lo, Rob Herring
  Cc: Mark Rutland, Ben Ho, Mars Cheng, Mengqi Zhang, linux-clk,
	Hsin-Hsiung Wang, Weiyi Lu, Marc Zyngier,
	open list:SERIAL DRIVERS, Yingjoe Chen, devicetree, Jason Cooper,
	Seiya Wang, moderated list:ARM/Mediatek SoC support,
	Thomas Gleixner, Eddie Huang,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <1548997866.26127.4.camel@mtksdaap41>



On 01/02/2019 06:11, Erin Lo wrote:
> Add back more people since mail server issue
> 
> On Fri, 2019-02-01 at 11:33 +0800, Erin Lo wrote:
>> On Thu, 2019-01-31 at 15:10 -0600, Rob Herring wrote:
>>> On Wed, Jan 30, 2019 at 8:34 PM Erin Lo <erin.lo@mediatek.com> wrote:
>>>>
>>>> On Wed, 2019-01-30 at 10:22 -0600, Rob Herring wrote:
>>>>> On Thu, Jan 24, 2019 at 04:07:20PM +0800, Erin Lo wrote:
>>>>>> From: Ben Ho <Ben.Ho@mediatek.com>
>>>>>>
>>>>>> Add basic chip support for Mediatek 8183, include
>>>>>> pinctrl file, uart node with correct uart clocks, pwrap device
>>>>>>
>>>>>> Add clock controller nodes, include topckgen, infracfg,
>>>>>> apmixedsys and subsystem.
>>>>>>
>>>>>> Signed-off-by: Ben Ho <Ben.Ho@mediatek.com>
>>>>>> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
>>>>>> Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
>>>>>> Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
>>>>>> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
>>>>>> Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
>>>>>> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
>>>>>> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
>>>>>> ---
>>>>>
>>>>>
>>>>>> +   sysirq: intpol-controller@c530a80 {
>>>>>
>>>>> interrupt-controller@...
>>>>
>>>> I will modify it in next version.
>>>>>
>>>>>
>>>>> Place all the MMIO peripherals under one or more simple-bus nodes.
>>>>>
>>>>> Rob
>>>>>
>>>>
>>>> Do you mean need to add simple-bus like this?
>>>
>>> Yes.
>>
>> We remove soc because Matthias suggested it in former MTK SoC maybe in
>> 2015 year.
>>
>> We will add it back by your comment.
>>
>> Thank you. 
>>
>> Best Regards,
>> Erin
> 
> Hi, Matthias,
> Do you have any comment here?

Although I wasn't able to find it in the documentation my understanding is, that
all devices on-chip should be under soc "bus".

I'm sorry if I created confusion with comments in the past.

Regards,
Matthias

> Thanks
> 
> Best Regards,
> Erin
>>>
>>>>
>>>> +   soc: soc {
>>>> +                #address-cells = <0x1>;
>>>> +                #size-cells = <0x1>;
>>>> +                ranges = <0 0 0 0xffffffff>;
>>>> +                compatible = "simple-bus";
>>>>
>>>>                 soc_data: soc_data@08000000 {
>>>>                         compatible = "mediatek,mt8183-efuse",
>>>>                                      "mediatek,efuse";
>>>>                         reg = <0 0x08000000 0 0x0010>;
>>>>                         #address-cells = <1>;
>>>>                         #size-cells = <1>;
>>>>                         status = "disabled";
>>>>                 };
>>>>
>>>>                 gic: interrupt-controller@0c000000 {
>>>>                         compatible = "arm,gic-v3";
>>>>                         #interrupt-cells = <4>;
>>>>
>>>> Best Regards,
>>>> Erin
>>>>
>>>>> _______________________________________________
>>>>> Linux-mediatek mailing list
>>>>> Linux-mediatek@lists.infradead.org
>>>>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
>>>>
>>>>
>>>>
>>>> _______________________________________________
>>>> linux-arm-kernel mailing list
>>>> linux-arm-kernel@lists.infradead.org
>>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
> 
> 

^ permalink raw reply


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