* [PATCH AUTOSEL 4.19 36/65] tty: serial: qcom_geni_serial: Allow mctrl when flow control is disabled
From: Sasha Levin @ 2019-02-15 2:10 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Matthias Kaehlcke, Greg Kroah-Hartman, Sasha Levin, linux-serial
In-Reply-To: <20190215021121.177674-1-sashal@kernel.org>
From: Matthias Kaehlcke <mka@chromium.org>
[ Upstream commit e8a6ca808c5ed1e2b43ab25f1f2cbd43a7574f73 ]
The geni set/get_mctrl() functions currently do nothing unless
hardware flow control is enabled. Remove this arbitrary limitation.
Suggested-by: Johan Hovold <johan@kernel.org>
Fixes: 8a8a66a1a18a ("tty: serial: qcom_geni_serial: Add support for flow control")
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/tty/serial/qcom_geni_serial.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
index 1515074e18fb..35d1f6fa0e3c 100644
--- a/drivers/tty/serial/qcom_geni_serial.c
+++ b/drivers/tty/serial/qcom_geni_serial.c
@@ -221,7 +221,7 @@ static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
u32 geni_ios;
- if (uart_console(uport) || !uart_cts_enabled(uport)) {
+ if (uart_console(uport)) {
mctrl |= TIOCM_CTS;
} else {
geni_ios = readl_relaxed(uport->membase + SE_GENI_IOS);
@@ -237,7 +237,7 @@ static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
{
u32 uart_manual_rfr = 0;
- if (uart_console(uport) || !uart_cts_enabled(uport))
+ if (uart_console(uport))
return;
if (!(mctrl & TIOCM_RTS))
--
2.19.1
^ permalink raw reply related
* [PATCH AUTOSEL 4.20 45/77] serial: fsl_lpuart: fix maximum acceptable baud rate with over-sampling
From: Sasha Levin @ 2019-02-15 2:08 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Tomonori Sakita, Atsushi Nemoto, Greg Kroah-Hartman, Sasha Levin,
linux-serial
In-Reply-To: <20190215020855.176727-1-sashal@kernel.org>
From: Tomonori Sakita <tomonori.sakita@sord.co.jp>
[ Upstream commit 815d835b7ba46685c316b000013367dacb2b461b ]
Using over-sampling ratio, lpuart can accept baud rate upto uartclk / 4.
Signed-off-by: Tomonori Sakita <tomonori.sakita@sord.co.jp>
Signed-off-by: Atsushi Nemoto <atsushi.nemoto@sord.co.jp>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/tty/serial/fsl_lpuart.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index 00c220e4f43c..989b95af1b95 100644
--- a/drivers/tty/serial/fsl_lpuart.c
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -1693,7 +1693,7 @@ lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
}
/* ask the core to calculate the divisor */
- baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
+ baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
spin_lock_irqsave(&sport->port.lock, flags);
--
2.19.1
^ permalink raw reply related
* [PATCH AUTOSEL 4.20 44/77] tty: serial: qcom_geni_serial: Allow mctrl when flow control is disabled
From: Sasha Levin @ 2019-02-15 2:08 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Matthias Kaehlcke, Greg Kroah-Hartman, Sasha Levin, linux-serial
In-Reply-To: <20190215020855.176727-1-sashal@kernel.org>
From: Matthias Kaehlcke <mka@chromium.org>
[ Upstream commit e8a6ca808c5ed1e2b43ab25f1f2cbd43a7574f73 ]
The geni set/get_mctrl() functions currently do nothing unless
hardware flow control is enabled. Remove this arbitrary limitation.
Suggested-by: Johan Hovold <johan@kernel.org>
Fixes: 8a8a66a1a18a ("tty: serial: qcom_geni_serial: Add support for flow control")
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/tty/serial/qcom_geni_serial.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
index d3b5261ee80a..76e0ad7251e1 100644
--- a/drivers/tty/serial/qcom_geni_serial.c
+++ b/drivers/tty/serial/qcom_geni_serial.c
@@ -221,7 +221,7 @@ static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
u32 geni_ios;
- if (uart_console(uport) || !uart_cts_enabled(uport)) {
+ if (uart_console(uport)) {
mctrl |= TIOCM_CTS;
} else {
geni_ios = readl_relaxed(uport->membase + SE_GENI_IOS);
@@ -237,7 +237,7 @@ static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
{
u32 uart_manual_rfr = 0;
- if (uart_console(uport) || !uart_cts_enabled(uport))
+ if (uart_console(uport))
return;
if (!(mctrl & TIOCM_RTS))
--
2.19.1
^ permalink raw reply related
* Re: [RFC PATCH v1 04/25] printk-rb: add writer interface
From: John Ogness @ 2019-02-15 1:19 UTC (permalink / raw)
To: Petr Mladek
Cc: linux-kernel, Peter Zijlstra, Sergey Senozhatsky, Steven Rostedt,
Daniel Wang, Andrew Morton, Linus Torvalds, Greg Kroah-Hartman,
Alan Cox, Jiri Slaby, Peter Feiner, linux-serial,
Sergey Senozhatsky
In-Reply-To: <87ef8aosby.fsf@linutronix.de>
On 2019-02-15, John Ogness <john.ogness@linutronix.de> wrote:
> prb_commit() does not actually care what is in the handle. It is going
> to commit everything up to the reserve.
After thinking about what I wrote here, I realized that the struct
prb_handle has no purpose in this ringbuffer implementation. We really
could simplify the writer interface to:
char *prb_reserve(struct printk_ringbuffer *rb, unsigned int size);
void prb_commit(struct printk_ringbuffer *rb);
That probably feels really strange because the writer doesn't specify
_what_ to commit. But this ringbuffer implementation doesn't need to
know that.
The only reason I can think of for having a handle is if there should be
any statistics, debugging, or sanity checking added. (For example if a
writer tried to commit something it did not reserve.)
John Ogness
^ permalink raw reply
* Re: [RFC PATCH v1 04/25] printk-rb: add writer interface
From: John Ogness @ 2019-02-14 23:36 UTC (permalink / raw)
To: Petr Mladek
Cc: linux-kernel, Peter Zijlstra, Sergey Senozhatsky, Steven Rostedt,
Daniel Wang, Andrew Morton, Linus Torvalds, Greg Kroah-Hartman,
Alan Cox, Jiri Slaby, Peter Feiner, linux-serial,
Sergey Senozhatsky
In-Reply-To: <20190214151650.5y337yy2jnnztsc6@pathway.suse.cz>
On 2019-02-14, Petr Mladek <pmladek@suse.com> wrote:
>> Add the writer functions prb_reserve() and prb_commit(). These make
>> use of processor-reentrant spin locks to limit the number of possible
>> interruption scenarios for the writers.
>>
>> Signed-off-by: John Ogness <john.ogness@linutronix.de>
>> ---
>> include/linux/printk_ringbuffer.h | 17 ++++
>> lib/printk_ringbuffer.c | 172 ++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 189 insertions(+)
>>
>> diff --git a/include/linux/printk_ringbuffer.h b/include/linux/printk_ringbuffer.h
>> index 0e6e8dd0d01e..1aec9d5666b1 100644
>> --- a/include/linux/printk_ringbuffer.h
>> +++ b/include/linux/printk_ringbuffer.h
>> @@ -24,6 +24,18 @@ struct printk_ringbuffer {
>> atomic_t ctx;
>> };
>>
>> +struct prb_entry {
>> + unsigned int size;
>> + u64 seq;
>> + char data[0];
>> +};
>> +
>> +struct prb_handle {
>> + struct printk_ringbuffer *rb;
>> + unsigned int cpu;
>> + struct prb_entry *entry;
>> +};
>
> Please, add a comment what these structures are for.
OK.
>> #define DECLARE_STATIC_PRINTKRB_CPULOCK(name) \
>> static DEFINE_PER_CPU(unsigned long, _##name##_percpu_irqflags); \
>> static struct prb_cpulock name = { \
>> @@ -45,6 +57,11 @@ static struct printk_ringbuffer name = { \
>> .ctx = ATOMIC_INIT(0), \
>> }
>>
>> +/* writer interface */
>> +char *prb_reserve(struct prb_handle *h, struct printk_ringbuffer *rb,
>> + unsigned int size);
>> +void prb_commit(struct prb_handle *h);
>> +
>> /* utility functions */
>> void prb_lock(struct prb_cpulock *cpu_lock, unsigned int *cpu_store);
>> void prb_unlock(struct prb_cpulock *cpu_lock, unsigned int cpu_store);
>> diff --git a/lib/printk_ringbuffer.c b/lib/printk_ringbuffer.c
>> index 28958b0cf774..90c7f9a9f861 100644
>> --- a/lib/printk_ringbuffer.c
>> +++ b/lib/printk_ringbuffer.c
>> @@ -2,6 +2,14 @@
>> #include <linux/smp.h>
>> #include <linux/printk_ringbuffer.h>
>>
>> +#define PRB_SIZE(rb) (1 << rb->size_bits)
>
> 1 -> 1L
OK.
>> +#define PRB_SIZE_BITMASK(rb) (PRB_SIZE(rb) - 1)
>> +#define PRB_INDEX(rb, lpos) (lpos & PRB_SIZE_BITMASK(rb))
>> +#define PRB_WRAPS(rb, lpos) (lpos >> rb->size_bits)
>> +#define PRB_WRAP_LPOS(rb, lpos, xtra) \
>> + ((PRB_WRAPS(rb, lpos) + xtra) << rb->size_bits)
>
> It took me quite some time to understand the WRAP macros.
> The extra parameter makes it even worse.
>
> I suggest to distinguish the two situation by the macro names.
> For example:
>
> PRB_THIS_WRAP_START_LPOS(rb, lpos)
> PRB_NEXT_WRAP_START_LPOS(rb, lpos)
OK.
> Also they might deserve a comment.
Agreed.
>> +#define PRB_DATA_ALIGN sizeof(long)
>> +
>> static bool __prb_trylock(struct prb_cpulock *cpu_lock,
>> unsigned int *cpu_store)
>> {
>> @@ -75,3 +83,167 @@ void prb_unlock(struct prb_cpulock *cpu_lock, unsigned int cpu_store)
>>
>> put_cpu();
>> }
>> +
>> +static struct prb_entry *to_entry(struct printk_ringbuffer *rb,
>> + unsigned long lpos)
>> +{
>> + char *buffer = rb->buffer;
>> + buffer += PRB_INDEX(rb, lpos);
>> + return (struct prb_entry *)buffer;
>> +}
>> +
>> +static int calc_next(struct printk_ringbuffer *rb, unsigned long tail,
>> + unsigned long lpos, int size, unsigned long *calced_next)
>> +{
>
> The function is so tricky that it deserves a comment.
>
> Well, I am getting really lost because of the generic name
> and all the parameters. For example, I wonder what "calced" stands
> for.
"calced" is short for "calculated". Maybe "lpos_next" would be a good
name?
The function is only doing this: Given a reserve position and size to
reserve, calculate what the next reserve position would be.
It might seem complicated because it also detects/reports the special
cases that the tail would be overwritten (returns -1) or if the
ringbuffer wraps when performing the reserve (returns 1).
> I think that it will be much easiser to follow the logic if the entire
> for-cycle around calc_next() is implemented in a single function.
calc_next() is already sitting in 2 nested loops. And calc_next()
performs manual tail-recursion using a goto. I doubt it becomes easier
to follow when calc_next is inlined in prb_reserve().
> The function push_tail() should get called from inside this function.
I disagree. calc_next's job isn't to make any changes. It only
calculates what should be done. Outer cmpxchg loops take on the
responsibility for making the change. push_tail() is not trivial because
of dealing with the situation when it fails. Below you specifically ask
about this, so I'll go deeper into push_tail() there.
>> + unsigned long next_lpos;
>> + int ret = 0;
>> +again:
>> + next_lpos = lpos + size;
>> + if (next_lpos - tail > PRB_SIZE(rb))
>> + return -1;
>
> push_tail() should get called here. prb_reserve() should bail
> out when the tail could not get pushed.
prb_reserve() does bail out if push_tail() fails. But I think it makes
more sense that it is clearly visible from prb_reserve() and not hidden
as a side-effect of calc_next(). And as I mentioned, I think things
become much more difficult to follow if calc_next is inlined in
prb_reserve().
>> +
>> + if (PRB_WRAPS(rb, lpos) != PRB_WRAPS(rb, next_lpos)) {
>> + lpos = PRB_WRAP_LPOS(rb, next_lpos, 0);
>> + ret |= 1;
>
> This is a strange trick. The function should either return a valid
> lpos that might get reserved or an error. The error means that
> prb_reserve() must fail.
Again, calc_next() does not _do_ anything. It only calculates what needs
to be done. By returning 1, it is saying, "here is the next lpos value
and by the way, it is wrapped around". The caller could see this for
itself by comparing the PRB_WRAPS of lpos and lpos_next, but since
calc_next() already had this information I figured I might as well save
some CPU cycles and inform the caller.
The calc_next() caller is the one that will need to _do_ something about
this. In the case of a wrap, the caller will need to create the
terminating entry and provide the writer with the buffer at the
beginning of the data array.
>> + goto again;
>> + }
>> +
>> + *calced_next = next_lpos;
>> + return ret;
>> +}
>> +
>
> /* Try to remove the oldest message */
That is the kind of comment that I usually get in trouble for (saying
the obvious). But I have no problems adding it.
>> +static bool push_tail(struct printk_ringbuffer *rb, unsigned long tail)
>> +{
>> + unsigned long new_tail;
>> + struct prb_entry *e;
>> + unsigned long head;
>> +
>> + if (tail != atomic_long_read(&rb->tail))
>> + return true;
>> +
>> + e = to_entry(rb, tail);
>> + if (e->size != -1)
>> + new_tail = tail + e->size;
>> + else
>> + new_tail = PRB_WRAP_LPOS(rb, tail, 1);
>> +
>> + /* make sure the new tail does not overtake the head */
>> + head = atomic_long_read(&rb->head);
>> + if (head - new_tail > PRB_SIZE(rb))
>> + return false;
>> +
>> + atomic_long_cmpxchg(&rb->tail, tail, new_tail);
>> + return true;
>> +}
>> +
>> +/*
>> + * prb_commit: Commit a reserved entry to the ring buffer.
>> + * @h: An entry handle referencing the data entry to commit.
>> + *
>> + * Commit data that has been reserved using prb_reserve(). Once the data
>> + * block has been committed, it can be invalidated at any time. If a writer
>> + * is interested in using the data after committing, the writer should make
>> + * its own copy first or use the prb_iter_ reader functions to access the
>> + * data in the ring buffer.
>> + *
>> + * It is safe to call this function from any context and state.
>> + */
>> +void prb_commit(struct prb_handle *h)
>> +{
>> + struct printk_ringbuffer *rb = h->rb;
>> + struct prb_entry *e;
>> + unsigned long head;
>> + unsigned long res;
>> +
>> + for (;;) {
>> + if (atomic_read(&rb->ctx) != 1) {
>> + /* the interrupted context will fixup head */
>> + atomic_dec(&rb->ctx);
>> + break;
>> + }
>> + /* assign sequence numbers before moving head */
>> + head = atomic_long_read(&rb->head);
>> + res = atomic_long_read(&rb->reserve);
>> + while (head != res) {
>> + e = to_entry(rb, head);
>> + if (e->size == -1) {
>> + head = PRB_WRAP_LPOS(rb, head, 1);
>> + continue;
>> + }
>> + e->seq = ++rb->seq;
>> + head += e->size;
>> + }
>> + atomic_long_set_release(&rb->head, res);
>
> This looks realy weird. It looks like you are commiting all
> reserved entries between current head and this entry.
I am.
> I would expect that every prb_entry has its own flag whether
> it was commited or not. This function should set this flag
> for its own entry. Then it should move the head to the
> first uncommited entry.
How could there be a reserved but uncommitted entry before this one? Or
after this one? The reserve/commit window is under the prb_cpulock. No
other CPU can be involved. If an NMI occurred anywhere here and it did a
reserve, it already did the matching commit.
> It will be racy because because more CPUs might commit their
> own entries in parallel and they might miss each other
> commit flags.
No other CPUs here.
> A solution might be to implement prb_push_head() that will
> do the safe thing. Then we could call it here, from klp_push_tail()
> and also from readers. I am still not sure if it will be
> race-free but it looks promissing.
Yes, this all can be implemented lockless, but it is considerably more
complex. Let's not think about that unless we decide we need it.
>> + atomic_dec(&rb->ctx);
>
> With the above approach you will not need rb->ctx. It is
> racy anyway, see below.
See my comments below.
>> +
>> + if (atomic_long_read(&rb->reserve) == res)
>> + break;
>> + atomic_inc(&rb->ctx);
>> + }
>> +
>> + prb_unlock(rb->cpulock, h->cpu);
>> +}
>> +
>> +/*
>> + * prb_reserve: Reserve an entry within a ring buffer.
>> + * @h: An entry handle to be setup and reference an entry.
>> + * @rb: A ring buffer to reserve data within.
>> + * @size: The number of bytes to reserve.
>> + *
>> + * Reserve an entry of at least @size bytes to be used by the caller. If
>> + * successful, the data region of the entry belongs to the caller and cannot
>> + * be invalidated by any other task/context. For this reason, the caller
>> + * should call prb_commit() as quickly as possible in order to avoid preventing
>> + * other tasks/contexts from reserving data in the case that the ring buffer
>> + * has wrapped.
>> + *
>> + * It is safe to call this function from any context and state.
>> + *
>> + * Returns a pointer to the reserved entry (and @h is setup to reference that
>> + * entry) or NULL if it was not possible to reserve data.
>> + */
>> +char *prb_reserve(struct prb_handle *h, struct printk_ringbuffer *rb,
>> + unsigned int size)
>> +{
>> + unsigned long tail, res1, res2;
>
> Please, better distinguish res1 and res2, e.g. old_res, new_res.
OK.
>> + int ret;
>> +
>> + if (size == 0)
>> + return NULL;
>> + size += sizeof(struct prb_entry);
>> + size += PRB_DATA_ALIGN - 1;
>> + size &= ~(PRB_DATA_ALIGN - 1);
>
> The above two lines should get hidden into PRB_ALLIGN_SIZE() or so.
OK.
>> + if (size >= PRB_SIZE(rb))
>> + return NULL;
>> +
>> + h->rb = rb;
>> + prb_lock(rb->cpulock, &h->cpu);
>> +
>> + atomic_inc(&rb->ctx);
>
> This looks racy. NMI could come between prb_lock() and this
> atomic_inc().
It wouldn't matter. I haven't done anything before the inc so NMIs can
come in and do as much reserve/committing as they want.
>> + do {
>> + for (;;) {
>> + tail = atomic_long_read(&rb->tail);
>> + res1 = atomic_long_read(&rb->reserve);
>> + ret = calc_next(rb, tail, res1, size, &res2);
>> + if (ret >= 0)
>> + break;
>> + if (!push_tail(rb, tail)) {
>> + prb_commit(h);
>
> I am a bit confused. Is it commiting a handle that haven't
> been reserved yet? Why, please?
If ctx is 1 we have the special responsibility of moving the head past
all the entries that interrupting NMIs have reserve/committed. (See the
check for "ctx != 1" in prb_commit().) The NMIs are already gone so we
are the only one that can do this.
Here we are in prb_reserve() and have already incremented ctx. We might
be the "ctx == 1" task and NMIs may have reserve/committed entries after
we incremented ctx, which means that they did not push the head. If we
now bail out because we couldn't push the tail, we still are obligated
to push the head if we are "ctx == 1".
prb_commit() does not actually care what is in the handle. It is going
to commit everything up to the reserve. The fact that I pass it a handle
is because that is what the function expects. I suppose I could create a
_prb_commit() that takes only a ringbuffer argument and prb_commit()
simply calls _prb_commit(h->rb). Then the bailout would be:
_prb_commit(rb);
Or maybe it should have a more descriptive name:
_prb_commit_all_reserved(rb);
>> + return NULL;
>> + }
>> + }
>
> Please, try to refactor the above as commented in calc_next().
I'll play with it and see how it looks.
>> + } while (!atomic_long_try_cmpxchg_acquire(&rb->reserve, &res1, res2));
>> +
>> + h->entry = to_entry(rb, res1);
>> +
>> + if (ret) {
>> + /* handle wrap */
>
> /* Write wrapping entry that is part of our reservation. */
OK.
>> + h->entry->size = -1;
>> + h->entry = to_entry(rb, PRB_WRAP_LPOS(rb, res2, 0));
>> + }
>> +
>> + h->entry->size = size;
>> +
>> + return &h->entry->data[0];
>> +}
Thank you for your comments.
John Ogness
^ permalink raw reply
* Re: [RFC PATCH v1 04/25] printk-rb: add writer interface
From: Petr Mladek @ 2019-02-14 15:16 UTC (permalink / raw)
To: John Ogness
Cc: linux-kernel, Peter Zijlstra, Sergey Senozhatsky, Steven Rostedt,
Daniel Wang, Andrew Morton, Linus Torvalds, Greg Kroah-Hartman,
Alan Cox, Jiri Slaby, Peter Feiner, linux-serial,
Sergey Senozhatsky
In-Reply-To: <20190212143003.48446-5-john.ogness@linutronix.de>
On Tue 2019-02-12 15:29:42, John Ogness wrote:
> Add the writer functions prb_reserve() and prb_commit(). These make
> use of processor-reentrant spin locks to limit the number of possible
> interruption scenarios for the writers.
>
> Signed-off-by: John Ogness <john.ogness@linutronix.de>
> ---
> include/linux/printk_ringbuffer.h | 17 ++++
> lib/printk_ringbuffer.c | 172 ++++++++++++++++++++++++++++++++++++++
> 2 files changed, 189 insertions(+)
>
> diff --git a/include/linux/printk_ringbuffer.h b/include/linux/printk_ringbuffer.h
> index 0e6e8dd0d01e..1aec9d5666b1 100644
> --- a/include/linux/printk_ringbuffer.h
> +++ b/include/linux/printk_ringbuffer.h
> @@ -24,6 +24,18 @@ struct printk_ringbuffer {
> atomic_t ctx;
> };
>
> +struct prb_entry {
> + unsigned int size;
> + u64 seq;
> + char data[0];
> +};
> +
> +struct prb_handle {
> + struct printk_ringbuffer *rb;
> + unsigned int cpu;
> + struct prb_entry *entry;
> +};
Please, add a comment what these structures are for.
> #define DECLARE_STATIC_PRINTKRB_CPULOCK(name) \
> static DEFINE_PER_CPU(unsigned long, _##name##_percpu_irqflags); \
> static struct prb_cpulock name = { \
> @@ -45,6 +57,11 @@ static struct printk_ringbuffer name = { \
> .ctx = ATOMIC_INIT(0), \
> }
>
> +/* writer interface */
> +char *prb_reserve(struct prb_handle *h, struct printk_ringbuffer *rb,
> + unsigned int size);
> +void prb_commit(struct prb_handle *h);
> +
> /* utility functions */
> void prb_lock(struct prb_cpulock *cpu_lock, unsigned int *cpu_store);
> void prb_unlock(struct prb_cpulock *cpu_lock, unsigned int cpu_store);
> diff --git a/lib/printk_ringbuffer.c b/lib/printk_ringbuffer.c
> index 28958b0cf774..90c7f9a9f861 100644
> --- a/lib/printk_ringbuffer.c
> +++ b/lib/printk_ringbuffer.c
> @@ -2,6 +2,14 @@
> #include <linux/smp.h>
> #include <linux/printk_ringbuffer.h>
>
> +#define PRB_SIZE(rb) (1 << rb->size_bits)
1 -> 1L
> +#define PRB_SIZE_BITMASK(rb) (PRB_SIZE(rb) - 1)
> +#define PRB_INDEX(rb, lpos) (lpos & PRB_SIZE_BITMASK(rb))
> +#define PRB_WRAPS(rb, lpos) (lpos >> rb->size_bits)
> +#define PRB_WRAP_LPOS(rb, lpos, xtra) \
> + ((PRB_WRAPS(rb, lpos) + xtra) << rb->size_bits)
It took me quite some time to understand the WRAP macros.
The extra parameter makes it even worse.
I suggest to distinguish the two situation by the macro names.
For example:
PRB_THIS_WRAP_START_LPOS(rb, lpos)
PRB_NEXT_WRAP_START_LPOS(rb, lpos)
Also they might deserve a comment.
> +#define PRB_DATA_ALIGN sizeof(long)
> +
> static bool __prb_trylock(struct prb_cpulock *cpu_lock,
> unsigned int *cpu_store)
> {
> @@ -75,3 +83,167 @@ void prb_unlock(struct prb_cpulock *cpu_lock, unsigned int cpu_store)
>
> put_cpu();
> }
> +
> +static struct prb_entry *to_entry(struct printk_ringbuffer *rb,
> + unsigned long lpos)
> +{
> + char *buffer = rb->buffer;
> + buffer += PRB_INDEX(rb, lpos);
> + return (struct prb_entry *)buffer;
> +}
> +
> +static int calc_next(struct printk_ringbuffer *rb, unsigned long tail,
> + unsigned long lpos, int size, unsigned long *calced_next)
> +{
The function is so tricky that it deserves a comment.
Well, I am getting really lost because of the generic name
and all the parameters. For example, I wonder what "calced" stands
for.
I think that it will be much easiser to follow the logic if the entire
for-cycle around calc_next() is implemented in a single function.
The function push_tail() should get called from inside this function.
> + unsigned long next_lpos;
> + int ret = 0;
> +again:
> + next_lpos = lpos + size;
> + if (next_lpos - tail > PRB_SIZE(rb))
> + return -1;
push_tail() should get called here. prb_reserve() should bail
out when the tail could not get pushed.
> +
> + if (PRB_WRAPS(rb, lpos) != PRB_WRAPS(rb, next_lpos)) {
> + lpos = PRB_WRAP_LPOS(rb, next_lpos, 0);
> + ret |= 1;
This is a strange trick. The function should either return a valid
lpos that might get reserved or an error. The error means that
prb_reserve() must fail.
> + goto again;
> + }
> +
> + *calced_next = next_lpos;
> + return ret;
> +}
> +
/* Try to remove the oldest message */
> +static bool push_tail(struct printk_ringbuffer *rb, unsigned long tail)
> +{
> + unsigned long new_tail;
> + struct prb_entry *e;
> + unsigned long head;
> +
> + if (tail != atomic_long_read(&rb->tail))
> + return true;
> +
> + e = to_entry(rb, tail);
> + if (e->size != -1)
> + new_tail = tail + e->size;
> + else
> + new_tail = PRB_WRAP_LPOS(rb, tail, 1);
> +
> + /* make sure the new tail does not overtake the head */
> + head = atomic_long_read(&rb->head);
> + if (head - new_tail > PRB_SIZE(rb))
> + return false;
> +
> + atomic_long_cmpxchg(&rb->tail, tail, new_tail);
> + return true;
> +}
> +
> +/*
> + * prb_commit: Commit a reserved entry to the ring buffer.
> + * @h: An entry handle referencing the data entry to commit.
> + *
> + * Commit data that has been reserved using prb_reserve(). Once the data
> + * block has been committed, it can be invalidated at any time. If a writer
> + * is interested in using the data after committing, the writer should make
> + * its own copy first or use the prb_iter_ reader functions to access the
> + * data in the ring buffer.
> + *
> + * It is safe to call this function from any context and state.
> + */
> +void prb_commit(struct prb_handle *h)
> +{
> + struct printk_ringbuffer *rb = h->rb;
> + struct prb_entry *e;
> + unsigned long head;
> + unsigned long res;
> +
> + for (;;) {
> + if (atomic_read(&rb->ctx) != 1) {
> + /* the interrupted context will fixup head */
> + atomic_dec(&rb->ctx);
> + break;
> + }
> + /* assign sequence numbers before moving head */
> + head = atomic_long_read(&rb->head);
> + res = atomic_long_read(&rb->reserve);
> + while (head != res) {
> + e = to_entry(rb, head);
> + if (e->size == -1) {
> + head = PRB_WRAP_LPOS(rb, head, 1);
> + continue;
> + }
> + e->seq = ++rb->seq;
> + head += e->size;
> + }
> + atomic_long_set_release(&rb->head, res);
This looks realy weird. It looks like you are commiting all
reserved entries between current head and this entry.
I would expect that every prb_entry has its own flag whether
it was commited or not. This function should set this flag
for its own entry. Then it should move the head to the
first uncommited entry.
It will be racy because because more CPUs might commit their
own entries in parallel and they might miss each other
commit flags.
A solution might be to implement prb_push_head() that will
do the safe thing. Then we could call it here, from klp_push_tail()
and also from readers. I am still not sure if it will be
race-free but it looks promissing.
> + atomic_dec(&rb->ctx);
With the above approach you will not need rb->ctx. It is
racy anyway, see below.
> +
> + if (atomic_long_read(&rb->reserve) == res)
> + break;
> + atomic_inc(&rb->ctx);
> + }
> +
> + prb_unlock(rb->cpulock, h->cpu);
> +}
> +
> +/*
> + * prb_reserve: Reserve an entry within a ring buffer.
> + * @h: An entry handle to be setup and reference an entry.
> + * @rb: A ring buffer to reserve data within.
> + * @size: The number of bytes to reserve.
> + *
> + * Reserve an entry of at least @size bytes to be used by the caller. If
> + * successful, the data region of the entry belongs to the caller and cannot
> + * be invalidated by any other task/context. For this reason, the caller
> + * should call prb_commit() as quickly as possible in order to avoid preventing
> + * other tasks/contexts from reserving data in the case that the ring buffer
> + * has wrapped.
> + *
> + * It is safe to call this function from any context and state.
> + *
> + * Returns a pointer to the reserved entry (and @h is setup to reference that
> + * entry) or NULL if it was not possible to reserve data.
> + */
> +char *prb_reserve(struct prb_handle *h, struct printk_ringbuffer *rb,
> + unsigned int size)
> +{
> + unsigned long tail, res1, res2;
Please, better distinguish res1 and res2, e.g. old_res, new_res.
> + int ret;
> +
> + if (size == 0)
> + return NULL;
> + size += sizeof(struct prb_entry);
> + size += PRB_DATA_ALIGN - 1;
> + size &= ~(PRB_DATA_ALIGN - 1);
The above two lines should get hidden into PRB_ALLIGN_SIZE() or so.
> + if (size >= PRB_SIZE(rb))
> + return NULL;
> +
> + h->rb = rb;
> + prb_lock(rb->cpulock, &h->cpu);
> +
> + atomic_inc(&rb->ctx);
This looks racy. NMI could come between prb_lock() and this atomic_inc().
> + do {
> + for (;;) {
> + tail = atomic_long_read(&rb->tail);
> + res1 = atomic_long_read(&rb->reserve);
> + ret = calc_next(rb, tail, res1, size, &res2);
> + if (ret >= 0)
> + break;
> + if (!push_tail(rb, tail)) {
> + prb_commit(h);
I am a bit confused. Is it commiting a handle that haven't
been reserved yet? Why, please?
> + return NULL;
> + }
> + }
Please, try to refactor the above as commented in calc_next().
> + } while (!atomic_long_try_cmpxchg_acquire(&rb->reserve, &res1, res2));
> +
> + h->entry = to_entry(rb, res1);
> +
> + if (ret) {
> + /* handle wrap */
/* Write wrapping entry that is part of our reservation. */
> + h->entry->size = -1;
> + h->entry = to_entry(rb, PRB_WRAP_LPOS(rb, res2, 0));
> + }
> +
> + h->entry->size = size;
> +
> + return &h->entry->data[0];
> +}
Best Regards,
Petr
^ permalink raw reply
* Re: [RFC PATCH v1 03/25] printk-rb: define ring buffer struct and initializer
From: Petr Mladek @ 2019-02-14 12:46 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: John Ogness, linux-kernel, Peter Zijlstra, Sergey Senozhatsky,
Steven Rostedt, Daniel Wang, Andrew Morton, Linus Torvalds,
Alan Cox, Jiri Slaby, Peter Feiner, linux-serial,
Sergey Senozhatsky
In-Reply-To: <20190212144640.GB17291@kroah.com>
On Tue 2019-02-12 15:46:40, Greg Kroah-Hartman wrote:
> On Tue, Feb 12, 2019 at 03:29:41PM +0100, John Ogness wrote:
> > See Documentation/printk-ringbuffer.txt for details about the
> > initializer arguments.
>
> You can put that documentation here in the .h file and have it pulled
> out automatically into the documentation files when they are created.
> That way you always keep everything in sync properly.
Yes, please, move the documentation into the sources.
It is so easy to get the info via editor+cscope support
than via an external text file that many people do not
know about ;-)
For example, see include/linux/livepatch.h for inspiration.
Best Regards,
Petr
^ permalink raw reply
* Re: [RFC PATCH v1 02/25] printk-rb: add prb locking functions
From: John Ogness @ 2019-02-14 12:10 UTC (permalink / raw)
To: Petr Mladek
Cc: linux-kernel, Peter Zijlstra, Sergey Senozhatsky, Steven Rostedt,
Daniel Wang, Andrew Morton, Linus Torvalds, Greg Kroah-Hartman,
Alan Cox, Jiri Slaby, Peter Feiner, linux-serial,
Sergey Senozhatsky
In-Reply-To: <20190214103324.viexpifsyons5qya@pathway.suse.cz>
On 2019-02-14, Petr Mladek <pmladek@suse.com> wrote:
>>> cpu_store looks like an implementation detail. The caller
>>> needs to remember it to handle the nesting properly.
>>>
>>> We could achieve the same with a recursion counter hidden
>>> in struct prb_lock.
>
> The atomic operations are tricky. I feel other lost in them.
> Well, I still think that it might easier to detect nesting
> on the same CPU, see below.
>
> Also there is no need to store irq flags in per-CPU variable.
> Only the first owner of the lock need to store the flags. The others
> are spinning or nested.
>
> struct prb_cpulock {
> atomic_t owner;
> unsigned int flags;
> int nesting; /* intialized to 0 */
> };
>
> void prb_lock(struct prb_cpulock *cpu_lock)
> {
> unsigned int flags;
> int cpu;
I added an explicit preempt_disable here:
cpu = get_cpu();
> /*
> * The next condition might be valid only when
> * we are nested on the same CPU. It means
> * the IRQs are already disabled and no
> * memory barrier is needed.
> */
> if (cpu_lock->owner == smp_processor_id()) {
> cpu_lock->nested++;
> return;
> }
>
> /* Not nested. Take the lock */
> local_irq_save(flags);
> cpu = smp_processor_id();
>
> for (;;) {
With fixups so it builds/runs:
unsigned int prev_cpu = -1;
> if (atomic_try_cmpxchg_acquire(&cpu_lock->owner,
&prev_cpu, cpu)) {
> cpu_lock->flags = flags;
> break;
> }
>
> cpu_relax();
> }
> }
>
> void prb_unlock(struct prb_cpulock *cpu_lock)
> {
> unsigned int flags;
>
> if (cpu_lock->nested)
> cpu_lock->nested--;
And the matching preempt_enable().
goto out;
> }
>
> /* We must be the first lock owner */
> flags = cpu_lock->flags;
> atomic_set_release(&cpu_lock->owner, -1);
> local_irq_restore(flags);
out:
put_cpu();
> }
>
> Or do I miss anything?
It looks great. I've run my stress tests on it and everything is running
well.
Thanks for simplifying this!
John Ogness
^ permalink raw reply
* Re: [RFC PATCH v1 02/25] printk-rb: add prb locking functions
From: Petr Mladek @ 2019-02-14 10:33 UTC (permalink / raw)
To: John Ogness
Cc: linux-kernel, Peter Zijlstra, Sergey Senozhatsky, Steven Rostedt,
Daniel Wang, Andrew Morton, Linus Torvalds, Greg Kroah-Hartman,
Alan Cox, Jiri Slaby, Peter Feiner, linux-serial,
Sergey Senozhatsky
In-Reply-To: <87pnrvs707.fsf@linutronix.de>
On Wed 2019-02-13 22:39:20, John Ogness wrote:
> On 2019-02-13, Petr Mladek <pmladek@suse.com> wrote:
> >> +/*
> >> + * prb_unlock: Perform a processor-reentrant spin unlock.
> >> + * @cpu_lock: A pointer to the lock object.
> >> + * @cpu_store: A "flags" object storing lock status information.
> >> + *
> >> + * Release the lock. The calling processor must be the owner of the lock.
> >> + *
> >> + * It is safe to call this function from any context and state.
> >> + */
> >> +void prb_unlock(struct prb_cpulock *cpu_lock, unsigned int cpu_store)
> >> +{
> >> + unsigned long *flags;
> >> + unsigned int cpu;
> >> +
> >> + cpu = atomic_read(&cpu_lock->owner);
> >> + atomic_set_release(&cpu_lock->owner, cpu_store);
> >> +
> >> + if (cpu_store == -1) {
> >> + flags = per_cpu_ptr(cpu_lock->irqflags, cpu);
> >> + local_irq_restore(*flags);
> >> + }
> >
> > cpu_store looks like an implementation detail. The caller
> > needs to remember it to handle the nesting properly.
>
> It's really no different than "flags" in irqsave/irqrestore.
>
> > We could achieve the same with a recursion counter hidden
> > in struct prb_lock.
>
> The only way I see how that could be implemented is if the cmpxchg
> encoded the cpu owner and counter into a single integer. (Upper half as
> counter, lower half as cpu owner.) Both fields would need to be updated
> with a single cmpxchg. The critical cmpxchg being the one where the CPU
> becomes unlocked (counter goes from 1 to 0 and cpu owner goes from N to
> -1).
The atomic operations are tricky. I feel other lost in them.
Well, I still think that it might easier to detect nesting
on the same CPU, see below.
Also there is no need to store irq flags in per-CPU variable.
Only the first owner of the lock need to store the flags. The others
are spinning or nested.
struct prb_cpulock {
atomic_t owner;
unsigned int flags;
int nesting; /* intialized to 0 */
};
void prb_lock(struct prb_cpulock *cpu_lock)
{
unsigned int flags;
int cpu;
/*
* The next condition might be valid only when
* we are nested on the same CPU. It means
* the IRQs are already disabled and no
* memory barrier is needed.
*/
if (cpu_lock->owner == smp_processor_id()) {
cpu_lock->nested++;
return;
}
/* Not nested. Take the lock */
local_irq_save(flags);
cpu = smp_processor_id();
for (;;) {
if (atomic_try_cmpxchg_acquire(&cpu_lock->owner,
-1, cpu)) {
cpu_lock->flags = flags;
break;
}
cpu_relax();
}
}
void prb_unlock(struct prb_cpulock *cpu_lock)
{
unsigned int flags;
if (cpu_lock->nested)
cpu_lock->nested--;
return;
}
/* We must be the first lock owner */
flags = cpu_lock->flags;
atomic_set_release(&cpu_lock->owner, -1);
local_irq_restore(flags);
}
Or do I miss anything?
Best Regards,
Petr
^ permalink raw reply
* Re: [PATCH v6 6/6] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile
From: Erin Lo @ 2019-02-14 10:15 UTC (permalink / raw)
To: Matthias Brugger
Cc: Mark Rutland, Ben Ho, mars.cheng, Mengqi Zhang, linux-clk,
Hsin-Hsiung Wang, Weiyi Lu, Marc Zyngier, linux-serial,
yingjoe.chen, devicetree, Jason Cooper, Seiya Wang, Rob Herring,
linux-mediatek, Thomas Gleixner, eddie.huang, linux-arm-kernel,
srv_heupstream, Greg Kroah-Hartman, Stephen Boyd
In-Reply-To: <1550139242.21510.9.camel@mtksdaap41>
On Thu, 2019-02-14 at 18:14 +0800, Erin Lo wrote:
> On Thu, 2019-02-14 at 10:01 +0100, Matthias Brugger wrote:
> >
> > On 14/02/2019 06:27, Erin Lo wrote:
> > > On Wed, 2019-02-13 at 15:54 +0100, Matthias Brugger wrote:
> > >>
> > >> On 13/02/2019 10:03, Erin Lo wrote:
> > >>> On Thu, 2019-02-07 at 16:30 +0100, Matthias Brugger wrote:
> > >>>>
> > >>>> On 24/01/2019 09:07, Erin Lo wrote:
> > >>>>> From: Ben Ho <Ben.Ho@mediatek.com>
> > >>>>>
> > >>>>> Add basic chip support for Mediatek 8183, include
> > >>>>> pinctrl file, uart node with correct uart clocks, pwrap device
> > >>>>>
> > >>>>> Add clock controller nodes, include topckgen, infracfg,
> > >>>>> apmixedsys and subsystem.
> > >>>>>
> > >>>>> Signed-off-by: Ben Ho <Ben.Ho@mediatek.com>
> > >>>>> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> > >>>>> Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
> > >>>>> Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
> > >>>>> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > >>>>> Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
> > >>>>> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> > >>>>> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
> > >>>>> ---
> > >>>>> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > >>>>> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 136 +++
> > >>>>> arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h | 1120 +++++++++++++++++++++++++
> > >>>>
> > >>>> Would you mind to make the pinfunc.h a seperate patch and adding the pinctrl
> > >>>> maintainers to the list.
> > >>>>
> > >>>> Regards,
> > >>>> Matthias
> > >>>>
> > >>>
> > >>> OK! I will take pinfunc.h out of this series.
> > >>
> > >> My take would be to somehow change this series in something like.
> > >> One patch which adds basic support for the SoC without any dependencies on other
> > >> series.
> > >> Every node that has a dependency on a different series should go in a separate
> > >> patch. In this case IMHO pinfunc.h can got with the dts node in one patch.
> > >>
> > >> Regards,
> > >> Matthias
> > >>
> > >
> > > I will separate this patch into 3 patches : basic support for the SoC,
> > > mt8183-pinfunc.h, and spi node.
> > >
> > > Is that OK?
> > > Is it ok, if pinctrl@1000b000 is included in basic node?
> > >
> >
> > Why do you want to do that? Without the pinfunc.h I can't take it independently,
> > right?
> >
> > Regards,
> > Matthias
>
> spi node need to use pio in mt8183-evb.dts, unless I don't submit spi
> relative.
> Best Regards.
> Erin
> >
> > > Best Regards.
> > > Erin
> > >
> > >>>
> > >>> Best Regards,
> > >>> Erin
> > >>>
> > >>>>> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 408 +++++++++
> > >>>>> 4 files changed, 1665 insertions(+)
> > >>>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > >>>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
> > >>>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > >>>>>
> > >>>>> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> > >>>>> index e8f952f..458bbc4 100644
> > >>>>> --- a/arch/arm64/boot/dts/mediatek/Makefile
> > >>>>> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > >>>>> @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
> > >>>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
> > >>>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
> > >>>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> > >>>>> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
> > >>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > >>>>> new file mode 100644
> > >>>>> index 0000000..b12c6ea
> > >>>>> --- /dev/null
> > >>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > >>>>> @@ -0,0 +1,136 @@
> > >>>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > >>>>> +/*
> > >>>>> + * Copyright (c) 2018 MediaTek Inc.
> > >>>>> + * Author: Ben Ho <ben.ho@mediatek.com>
> > >>>>> + * Erin Lo <erin.lo@mediatek.com>
> > >>>>> + */
> > >>>>> +
> > >>>>> +/dts-v1/;
> > >>>>> +#include "mt8183.dtsi"
> > >>>>> +
> > >>>>> +/ {
> > >>>>> + model = "MediaTek MT8183 evaluation board";
> > >>>>> + compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
> > >>>>> +
> > >>>>> + aliases {
> > >>>>> + serial0 = &uart0;
> > >>>>> + };
> > >>>>> +
> > >>>>> + memory@40000000 {
> > >>>>> + device_type = "memory";
> > >>>>> + reg = <0 0x40000000 0 0x80000000>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + chosen {
> > >>>>> + stdout-path = "serial0:921600n8";
> > >>>>> + };
> > >>>>> +};
> > >>>>> +
> > >>>>> +&pio {
> > >>>>> + spi_pins_0: spi0{
> > >>>>> + pins_spi{
> > >>>>> + pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
> > >>>>> + <PINMUX_GPIO86__FUNC_SPI0_CSB>,
> > >>>>> + <PINMUX_GPIO87__FUNC_SPI0_MO>,
> > >>>>> + <PINMUX_GPIO88__FUNC_SPI0_CLK>;
> > >>>>> + bias-disable;
> > >>>>> + };
> > >>>>> + };
> > >>>>> +
> > >>>>> + spi_pins_1: spi1{
> > >>>>> + pins_spi{
> > >>>>> + pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
> > >>>>> + <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
> > >>>>> + <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
> > >>>>> + <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
> > >>>>> + bias-disable;
> > >>>>> + };
> > >>>>> + };
> > >>>>> +
> > >>>>> + spi_pins_2: spi2{
> > >>>>> + pins_spi{
> > >>>>> + pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
> > >>>>> + <PINMUX_GPIO1__FUNC_SPI2_MO>,
> > >>>>> + <PINMUX_GPIO2__FUNC_SPI2_CLK>,
> > >>>>> + <PINMUX_GPIO94__FUNC_SPI2_MI>;
> > >>>>> + bias-disable;
> > >>>>> + };
> > >>>>> + };
> > >>>>> +
> > >>>>> + spi_pins_3: spi3{
> > >>>>> + pins_spi{
> > >>>>> + pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
> > >>>>> + <PINMUX_GPIO22__FUNC_SPI3_CSB>,
> > >>>>> + <PINMUX_GPIO23__FUNC_SPI3_MO>,
> > >>>>> + <PINMUX_GPIO24__FUNC_SPI3_CLK>;
> > >>>>> + bias-disable;
> > >>>>> + };
> > >>>>> + };
> > >>>>> +
> > >>>>> + spi_pins_4: spi4{
> > >>>>> + pins_spi{
> > >>>>> + pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
> > >>>>> + <PINMUX_GPIO18__FUNC_SPI4_CSB>,
> > >>>>> + <PINMUX_GPIO19__FUNC_SPI4_MO>,
> > >>>>> + <PINMUX_GPIO20__FUNC_SPI4_CLK>;
> > >>>>> + bias-disable;
> > >>>>> + };
> > >>>>> + };
> > >>>>> +
> > >>>>> + spi_pins_5: spi5{
> > >>>>> + pins_spi{
> > >>>>> + pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
> > >>>>> + <PINMUX_GPIO14__FUNC_SPI5_CSB>,
> > >>>>> + <PINMUX_GPIO15__FUNC_SPI5_MO>,
> > >>>>> + <PINMUX_GPIO16__FUNC_SPI5_CLK>;
> > >>>>> + bias-disable;
> > >>>>> + };
> > >>>>> + };
> > >>>>> +};
> > >>>>> +
> > >>>>> +&spi0 {
> > >>>>> + pinctrl-names = "default";
> > >>>>> + pinctrl-0 = <&spi_pins_0>;
> > >>>>> + mediatek,pad-select = <0>;
> > >>>>> + status = "okay";
> > >>>>> +};
> > >>>>> +
> > >>>>> +&spi1 {
> > >>>>> + pinctrl-names = "default";
> > >>>>> + pinctrl-0 = <&spi_pins_1>;
> > >>>>> + mediatek,pad-select = <0>;
> > >>>>> + status = "okay";
> > >>>>> +};
> > >>>>> +
> > >>>>> +&spi2 {
> > >>>>> + pinctrl-names = "default";
> > >>>>> + pinctrl-0 = <&spi_pins_2>;
> > >>>>> + mediatek,pad-select = <0>;
> > >>>>> + status = "okay";
> > >>>>> +};
> > >>>>> +
> > >>>>> +&spi3 {
> > >>>>> + pinctrl-names = "default";
> > >>>>> + pinctrl-0 = <&spi_pins_3>;
> > >>>>> + mediatek,pad-select = <0>;
> > >>>>> + status = "okay";
> > >>>>> +};
> > >>>>> +
> > >>>>> +&spi4 {
> > >>>>> + pinctrl-names = "default";
> > >>>>> + pinctrl-0 = <&spi_pins_4>;
> > >>>>> + mediatek,pad-select = <0>;
> > >>>>> + status = "okay";
> > >>>>> +};
> > >>>>> +
> > >>>>> +&spi5 {
> > >>>>> + pinctrl-names = "default";
> > >>>>> + pinctrl-0 = <&spi_pins_5>;
> > >>>>> + mediatek,pad-select = <0>;
> > >>>>> + status = "okay";
> > >>>>> +
> > >>>>> +};
> > >>>>> +
> > >>>>> +&uart0 {
> > >>>>> + status = "okay";
> > >>>>> +};
> > >>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
> > >>>>> new file mode 100644
> > >>>>> index 0000000..768e41e
> > >>>>> --- /dev/null
> > >>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
> > >>>>> @@ -0,0 +1,1120 @@
> > >>>>> +// SPDX-License-Identifier: GPL-2.0
> > >>>>> +/*
> > >>>>> + * Copyright (C) 2018 MediaTek Inc.
> > >>>>> + * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
> > >>>>> + *
> > >>>>> + */
> > >>>>> +
> > >>>>> +#ifndef __MT8183_PINFUNC_H
> > >>>>> +#define __MT8183_PINFUNC_H
> > >>>>> +
> > >>>>> +#include <dt-bindings/pinctrl/mt65xx.h>
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
> > >>>>> +#define PINMUX_GPIO0__FUNC_MRG_SYNC (MTK_PIN_NO(0) | 1)
> > >>>>> +#define PINMUX_GPIO0__FUNC_PCM0_SYNC (MTK_PIN_NO(0) | 2)
> > >>>>> +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 3)
> > >>>>> +#define PINMUX_GPIO0__FUNC_SRCLKENAI0 (MTK_PIN_NO(0) | 4)
> > >>>>> +#define PINMUX_GPIO0__FUNC_SCP_SPI2_CS (MTK_PIN_NO(0) | 5)
> > >>>>> +#define PINMUX_GPIO0__FUNC_I2S3_MCK (MTK_PIN_NO(0) | 6)
> > >>>>> +#define PINMUX_GPIO0__FUNC_SPI2_CSB (MTK_PIN_NO(0) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
> > >>>>> +#define PINMUX_GPIO1__FUNC_MRG_CLK (MTK_PIN_NO(1) | 1)
> > >>>>> +#define PINMUX_GPIO1__FUNC_PCM0_CLK (MTK_PIN_NO(1) | 2)
> > >>>>> +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 3)
> > >>>>> +#define PINMUX_GPIO1__FUNC_CLKM3 (MTK_PIN_NO(1) | 4)
> > >>>>> +#define PINMUX_GPIO1__FUNC_SCP_SPI2_MO (MTK_PIN_NO(1) | 5)
> > >>>>> +#define PINMUX_GPIO1__FUNC_I2S3_BCK (MTK_PIN_NO(1) | 6)
> > >>>>> +#define PINMUX_GPIO1__FUNC_SPI2_MO (MTK_PIN_NO(1) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
> > >>>>> +#define PINMUX_GPIO2__FUNC_MRG_DO (MTK_PIN_NO(2) | 1)
> > >>>>> +#define PINMUX_GPIO2__FUNC_PCM0_DO (MTK_PIN_NO(2) | 2)
> > >>>>> +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 3)
> > >>>>> +#define PINMUX_GPIO2__FUNC_SCL6 (MTK_PIN_NO(2) | 4)
> > >>>>> +#define PINMUX_GPIO2__FUNC_SCP_SPI2_CK (MTK_PIN_NO(2) | 5)
> > >>>>> +#define PINMUX_GPIO2__FUNC_I2S3_LRCK (MTK_PIN_NO(2) | 6)
> > >>>>> +#define PINMUX_GPIO2__FUNC_SPI2_CLK (MTK_PIN_NO(2) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
> > >>>>> +#define PINMUX_GPIO3__FUNC_MRG_DI (MTK_PIN_NO(3) | 1)
> > >>>>> +#define PINMUX_GPIO3__FUNC_PCM0_DI (MTK_PIN_NO(3) | 2)
> > >>>>> +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 3)
> > >>>>> +#define PINMUX_GPIO3__FUNC_SDA6 (MTK_PIN_NO(3) | 4)
> > >>>>> +#define PINMUX_GPIO3__FUNC_TDM_MCK (MTK_PIN_NO(3) | 5)
> > >>>>> +#define PINMUX_GPIO3__FUNC_I2S3_DO (MTK_PIN_NO(3) | 6)
> > >>>>> +#define PINMUX_GPIO3__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(3) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
> > >>>>> +#define PINMUX_GPIO4__FUNC_PWM_B (MTK_PIN_NO(4) | 1)
> > >>>>> +#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2)
> > >>>>> +#define PINMUX_GPIO4__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(4) | 3)
> > >>>>> +#define PINMUX_GPIO4__FUNC_MD_URXD1 (MTK_PIN_NO(4) | 4)
> > >>>>> +#define PINMUX_GPIO4__FUNC_TDM_BCK (MTK_PIN_NO(4) | 5)
> > >>>>> +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6)
> > >>>>> +#define PINMUX_GPIO4__FUNC_DAP_MD32_SWD (MTK_PIN_NO(4) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
> > >>>>> +#define PINMUX_GPIO5__FUNC_PWM_C (MTK_PIN_NO(5) | 1)
> > >>>>> +#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2)
> > >>>>> +#define PINMUX_GPIO5__FUNC_SSPM_URXD_AO (MTK_PIN_NO(5) | 3)
> > >>>>> +#define PINMUX_GPIO5__FUNC_MD_UTXD1 (MTK_PIN_NO(5) | 4)
> > >>>>> +#define PINMUX_GPIO5__FUNC_TDM_LRCK (MTK_PIN_NO(5) | 5)
> > >>>>> +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6)
> > >>>>> +#define PINMUX_GPIO5__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(5) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
> > >>>>> +#define PINMUX_GPIO6__FUNC_PWM_A (MTK_PIN_NO(6) | 1)
> > >>>>> +#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2)
> > >>>>> +#define PINMUX_GPIO6__FUNC_IDDIG (MTK_PIN_NO(6) | 3)
> > >>>>> +#define PINMUX_GPIO6__FUNC_MD_URXD0 (MTK_PIN_NO(6) | 4)
> > >>>>> +#define PINMUX_GPIO6__FUNC_TDM_DATA0 (MTK_PIN_NO(6) | 5)
> > >>>>> +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6)
> > >>>>> +#define PINMUX_GPIO6__FUNC_CMFLASH (MTK_PIN_NO(6) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
> > >>>>> +#define PINMUX_GPIO7__FUNC_SPI1_B_MI (MTK_PIN_NO(7) | 1)
> > >>>>> +#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2)
> > >>>>> +#define PINMUX_GPIO7__FUNC_USB_DRVVBUS (MTK_PIN_NO(7) | 3)
> > >>>>> +#define PINMUX_GPIO7__FUNC_MD_UTXD0 (MTK_PIN_NO(7) | 4)
> > >>>>> +#define PINMUX_GPIO7__FUNC_TDM_DATA1 (MTK_PIN_NO(7) | 5)
> > >>>>> +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6)
> > >>>>> +#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
> > >>>>> +#define PINMUX_GPIO8__FUNC_SPI1_B_CSB (MTK_PIN_NO(8) | 1)
> > >>>>> +#define PINMUX_GPIO8__FUNC_ANT_SEL3 (MTK_PIN_NO(8) | 2)
> > >>>>> +#define PINMUX_GPIO8__FUNC_SCL7 (MTK_PIN_NO(8) | 3)
> > >>>>> +#define PINMUX_GPIO8__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(8) | 4)
> > >>>>> +#define PINMUX_GPIO8__FUNC_TDM_DATA2 (MTK_PIN_NO(8) | 5)
> > >>>>> +#define PINMUX_GPIO8__FUNC_MD_INT0 (MTK_PIN_NO(8) | 6)
> > >>>>> +#define PINMUX_GPIO8__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(8) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
> > >>>>> +#define PINMUX_GPIO9__FUNC_SPI1_B_MO (MTK_PIN_NO(9) | 1)
> > >>>>> +#define PINMUX_GPIO9__FUNC_ANT_SEL4 (MTK_PIN_NO(9) | 2)
> > >>>>> +#define PINMUX_GPIO9__FUNC_CMMCLK2 (MTK_PIN_NO(9) | 3)
> > >>>>> +#define PINMUX_GPIO9__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(9) | 4)
> > >>>>> +#define PINMUX_GPIO9__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(9) | 5)
> > >>>>> +#define PINMUX_GPIO9__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(9) | 6)
> > >>>>> +#define PINMUX_GPIO9__FUNC_DBG_MON_B10 (MTK_PIN_NO(9) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
> > >>>>> +#define PINMUX_GPIO10__FUNC_SPI1_B_CLK (MTK_PIN_NO(10) | 1)
> > >>>>> +#define PINMUX_GPIO10__FUNC_ANT_SEL5 (MTK_PIN_NO(10) | 2)
> > >>>>> +#define PINMUX_GPIO10__FUNC_CMMCLK3 (MTK_PIN_NO(10) | 3)
> > >>>>> +#define PINMUX_GPIO10__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(10) | 4)
> > >>>>> +#define PINMUX_GPIO10__FUNC_TDM_DATA3 (MTK_PIN_NO(10) | 5)
> > >>>>> +#define PINMUX_GPIO10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 6)
> > >>>>> +#define PINMUX_GPIO10__FUNC_DBG_MON_B11 (MTK_PIN_NO(10) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
> > >>>>> +#define PINMUX_GPIO11__FUNC_TP_URXD1_AO (MTK_PIN_NO(11) | 1)
> > >>>>> +#define PINMUX_GPIO11__FUNC_IDDIG (MTK_PIN_NO(11) | 2)
> > >>>>> +#define PINMUX_GPIO11__FUNC_SCL6 (MTK_PIN_NO(11) | 3)
> > >>>>> +#define PINMUX_GPIO11__FUNC_UCTS1 (MTK_PIN_NO(11) | 4)
> > >>>>> +#define PINMUX_GPIO11__FUNC_UCTS0 (MTK_PIN_NO(11) | 5)
> > >>>>> +#define PINMUX_GPIO11__FUNC_SRCLKENAI1 (MTK_PIN_NO(11) | 6)
> > >>>>> +#define PINMUX_GPIO11__FUNC_I2S5_MCK (MTK_PIN_NO(11) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
> > >>>>> +#define PINMUX_GPIO12__FUNC_TP_UTXD1_AO (MTK_PIN_NO(12) | 1)
> > >>>>> +#define PINMUX_GPIO12__FUNC_USB_DRVVBUS (MTK_PIN_NO(12) | 2)
> > >>>>> +#define PINMUX_GPIO12__FUNC_SDA6 (MTK_PIN_NO(12) | 3)
> > >>>>> +#define PINMUX_GPIO12__FUNC_URTS1 (MTK_PIN_NO(12) | 4)
> > >>>>> +#define PINMUX_GPIO12__FUNC_URTS0 (MTK_PIN_NO(12) | 5)
> > >>>>> +#define PINMUX_GPIO12__FUNC_I2S2_DI2 (MTK_PIN_NO(12) | 6)
> > >>>>> +#define PINMUX_GPIO12__FUNC_I2S5_BCK (MTK_PIN_NO(12) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
> > >>>>> +#define PINMUX_GPIO13__FUNC_DBPI_D0 (MTK_PIN_NO(13) | 1)
> > >>>>> +#define PINMUX_GPIO13__FUNC_SPI5_MI (MTK_PIN_NO(13) | 2)
> > >>>>> +#define PINMUX_GPIO13__FUNC_PCM0_SYNC (MTK_PIN_NO(13) | 3)
> > >>>>> +#define PINMUX_GPIO13__FUNC_MD_URXD0 (MTK_PIN_NO(13) | 4)
> > >>>>> +#define PINMUX_GPIO13__FUNC_ANT_SEL3 (MTK_PIN_NO(13) | 5)
> > >>>>> +#define PINMUX_GPIO13__FUNC_I2S0_MCK (MTK_PIN_NO(13) | 6)
> > >>>>> +#define PINMUX_GPIO13__FUNC_DBG_MON_B15 (MTK_PIN_NO(13) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
> > >>>>> +#define PINMUX_GPIO14__FUNC_DBPI_D1 (MTK_PIN_NO(14) | 1)
> > >>>>> +#define PINMUX_GPIO14__FUNC_SPI5_CSB (MTK_PIN_NO(14) | 2)
> > >>>>> +#define PINMUX_GPIO14__FUNC_PCM0_CLK (MTK_PIN_NO(14) | 3)
> > >>>>> +#define PINMUX_GPIO14__FUNC_MD_UTXD0 (MTK_PIN_NO(14) | 4)
> > >>>>> +#define PINMUX_GPIO14__FUNC_ANT_SEL4 (MTK_PIN_NO(14) | 5)
> > >>>>> +#define PINMUX_GPIO14__FUNC_I2S0_BCK (MTK_PIN_NO(14) | 6)
> > >>>>> +#define PINMUX_GPIO14__FUNC_DBG_MON_B16 (MTK_PIN_NO(14) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
> > >>>>> +#define PINMUX_GPIO15__FUNC_DBPI_D2 (MTK_PIN_NO(15) | 1)
> > >>>>> +#define PINMUX_GPIO15__FUNC_SPI5_MO (MTK_PIN_NO(15) | 2)
> > >>>>> +#define PINMUX_GPIO15__FUNC_PCM0_DO (MTK_PIN_NO(15) | 3)
> > >>>>> +#define PINMUX_GPIO15__FUNC_MD_URXD1 (MTK_PIN_NO(15) | 4)
> > >>>>> +#define PINMUX_GPIO15__FUNC_ANT_SEL5 (MTK_PIN_NO(15) | 5)
> > >>>>> +#define PINMUX_GPIO15__FUNC_I2S0_LRCK (MTK_PIN_NO(15) | 6)
> > >>>>> +#define PINMUX_GPIO15__FUNC_DBG_MON_B17 (MTK_PIN_NO(15) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
> > >>>>> +#define PINMUX_GPIO16__FUNC_DBPI_D3 (MTK_PIN_NO(16) | 1)
> > >>>>> +#define PINMUX_GPIO16__FUNC_SPI5_CLK (MTK_PIN_NO(16) | 2)
> > >>>>> +#define PINMUX_GPIO16__FUNC_PCM0_DI (MTK_PIN_NO(16) | 3)
> > >>>>> +#define PINMUX_GPIO16__FUNC_MD_UTXD1 (MTK_PIN_NO(16) | 4)
> > >>>>> +#define PINMUX_GPIO16__FUNC_ANT_SEL6 (MTK_PIN_NO(16) | 5)
> > >>>>> +#define PINMUX_GPIO16__FUNC_I2S0_DI (MTK_PIN_NO(16) | 6)
> > >>>>> +#define PINMUX_GPIO16__FUNC_DBG_MON_B23 (MTK_PIN_NO(16) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
> > >>>>> +#define PINMUX_GPIO17__FUNC_DBPI_D4 (MTK_PIN_NO(17) | 1)
> > >>>>> +#define PINMUX_GPIO17__FUNC_SPI4_MI (MTK_PIN_NO(17) | 2)
> > >>>>> +#define PINMUX_GPIO17__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(17) | 3)
> > >>>>> +#define PINMUX_GPIO17__FUNC_MD_INT0 (MTK_PIN_NO(17) | 4)
> > >>>>> +#define PINMUX_GPIO17__FUNC_ANT_SEL7 (MTK_PIN_NO(17) | 5)
> > >>>>> +#define PINMUX_GPIO17__FUNC_I2S3_MCK (MTK_PIN_NO(17) | 6)
> > >>>>> +#define PINMUX_GPIO17__FUNC_DBG_MON_A1 (MTK_PIN_NO(17) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
> > >>>>> +#define PINMUX_GPIO18__FUNC_DBPI_D5 (MTK_PIN_NO(18) | 1)
> > >>>>> +#define PINMUX_GPIO18__FUNC_SPI4_CSB (MTK_PIN_NO(18) | 2)
> > >>>>> +#define PINMUX_GPIO18__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(18) | 3)
> > >>>>> +#define PINMUX_GPIO18__FUNC_MD_INT0 (MTK_PIN_NO(18) | 4)
> > >>>>> +#define PINMUX_GPIO18__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(18) | 5)
> > >>>>> +#define PINMUX_GPIO18__FUNC_I2S3_BCK (MTK_PIN_NO(18) | 6)
> > >>>>> +#define PINMUX_GPIO18__FUNC_DBG_MON_A2 (MTK_PIN_NO(18) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
> > >>>>> +#define PINMUX_GPIO19__FUNC_DBPI_D6 (MTK_PIN_NO(19) | 1)
> > >>>>> +#define PINMUX_GPIO19__FUNC_SPI4_MO (MTK_PIN_NO(19) | 2)
> > >>>>> +#define PINMUX_GPIO19__FUNC_CONN_MCU_TDO (MTK_PIN_NO(19) | 3)
> > >>>>> +#define PINMUX_GPIO19__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(19) | 4)
> > >>>>> +#define PINMUX_GPIO19__FUNC_URXD1 (MTK_PIN_NO(19) | 5)
> > >>>>> +#define PINMUX_GPIO19__FUNC_I2S3_LRCK (MTK_PIN_NO(19) | 6)
> > >>>>> +#define PINMUX_GPIO19__FUNC_DBG_MON_A3 (MTK_PIN_NO(19) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
> > >>>>> +#define PINMUX_GPIO20__FUNC_DBPI_D7 (MTK_PIN_NO(20) | 1)
> > >>>>> +#define PINMUX_GPIO20__FUNC_SPI4_CLK (MTK_PIN_NO(20) | 2)
> > >>>>> +#define PINMUX_GPIO20__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(20) | 3)
> > >>>>> +#define PINMUX_GPIO20__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(20) | 4)
> > >>>>> +#define PINMUX_GPIO20__FUNC_UTXD1 (MTK_PIN_NO(20) | 5)
> > >>>>> +#define PINMUX_GPIO20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 6)
> > >>>>> +#define PINMUX_GPIO20__FUNC_DBG_MON_A19 (MTK_PIN_NO(20) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
> > >>>>> +#define PINMUX_GPIO21__FUNC_DBPI_D8 (MTK_PIN_NO(21) | 1)
> > >>>>> +#define PINMUX_GPIO21__FUNC_SPI3_MI (MTK_PIN_NO(21) | 2)
> > >>>>> +#define PINMUX_GPIO21__FUNC_CONN_MCU_TMS (MTK_PIN_NO(21) | 3)
> > >>>>> +#define PINMUX_GPIO21__FUNC_DAP_MD32_SWD (MTK_PIN_NO(21) | 4)
> > >>>>> +#define PINMUX_GPIO21__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(21) | 5)
> > >>>>> +#define PINMUX_GPIO21__FUNC_I2S2_MCK (MTK_PIN_NO(21) | 6)
> > >>>>> +#define PINMUX_GPIO21__FUNC_DBG_MON_B5 (MTK_PIN_NO(21) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
> > >>>>> +#define PINMUX_GPIO22__FUNC_DBPI_D9 (MTK_PIN_NO(22) | 1)
> > >>>>> +#define PINMUX_GPIO22__FUNC_SPI3_CSB (MTK_PIN_NO(22) | 2)
> > >>>>> +#define PINMUX_GPIO22__FUNC_CONN_MCU_TCK (MTK_PIN_NO(22) | 3)
> > >>>>> +#define PINMUX_GPIO22__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(22) | 4)
> > >>>>> +#define PINMUX_GPIO22__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(22) | 5)
> > >>>>> +#define PINMUX_GPIO22__FUNC_I2S2_BCK (MTK_PIN_NO(22) | 6)
> > >>>>> +#define PINMUX_GPIO22__FUNC_DBG_MON_B6 (MTK_PIN_NO(22) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
> > >>>>> +#define PINMUX_GPIO23__FUNC_DBPI_D10 (MTK_PIN_NO(23) | 1)
> > >>>>> +#define PINMUX_GPIO23__FUNC_SPI3_MO (MTK_PIN_NO(23) | 2)
> > >>>>> +#define PINMUX_GPIO23__FUNC_CONN_MCU_TDI (MTK_PIN_NO(23) | 3)
> > >>>>> +#define PINMUX_GPIO23__FUNC_UCTS1 (MTK_PIN_NO(23) | 4)
> > >>>>> +#define PINMUX_GPIO23__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5)
> > >>>>> +#define PINMUX_GPIO23__FUNC_I2S2_LRCK (MTK_PIN_NO(23) | 6)
> > >>>>> +#define PINMUX_GPIO23__FUNC_DBG_MON_B7 (MTK_PIN_NO(23) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
> > >>>>> +#define PINMUX_GPIO24__FUNC_DBPI_D11 (MTK_PIN_NO(24) | 1)
> > >>>>> +#define PINMUX_GPIO24__FUNC_SPI3_CLK (MTK_PIN_NO(24) | 2)
> > >>>>> +#define PINMUX_GPIO24__FUNC_SRCLKENAI0 (MTK_PIN_NO(24) | 3)
> > >>>>> +#define PINMUX_GPIO24__FUNC_URTS1 (MTK_PIN_NO(24) | 4)
> > >>>>> +#define PINMUX_GPIO24__FUNC_IO_JTAG_TCK (MTK_PIN_NO(24) | 5)
> > >>>>> +#define PINMUX_GPIO24__FUNC_I2S2_DI (MTK_PIN_NO(24) | 6)
> > >>>>> +#define PINMUX_GPIO24__FUNC_DBG_MON_B31 (MTK_PIN_NO(24) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
> > >>>>> +#define PINMUX_GPIO25__FUNC_DBPI_HSYNC (MTK_PIN_NO(25) | 1)
> > >>>>> +#define PINMUX_GPIO25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 2)
> > >>>>> +#define PINMUX_GPIO25__FUNC_SCL6 (MTK_PIN_NO(25) | 3)
> > >>>>> +#define PINMUX_GPIO25__FUNC_KPCOL2 (MTK_PIN_NO(25) | 4)
> > >>>>> +#define PINMUX_GPIO25__FUNC_IO_JTAG_TMS (MTK_PIN_NO(25) | 5)
> > >>>>> +#define PINMUX_GPIO25__FUNC_I2S1_MCK (MTK_PIN_NO(25) | 6)
> > >>>>> +#define PINMUX_GPIO25__FUNC_DBG_MON_B0 (MTK_PIN_NO(25) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
> > >>>>> +#define PINMUX_GPIO26__FUNC_DBPI_VSYNC (MTK_PIN_NO(26) | 1)
> > >>>>> +#define PINMUX_GPIO26__FUNC_ANT_SEL1 (MTK_PIN_NO(26) | 2)
> > >>>>> +#define PINMUX_GPIO26__FUNC_SDA6 (MTK_PIN_NO(26) | 3)
> > >>>>> +#define PINMUX_GPIO26__FUNC_KPROW2 (MTK_PIN_NO(26) | 4)
> > >>>>> +#define PINMUX_GPIO26__FUNC_IO_JTAG_TDI (MTK_PIN_NO(26) | 5)
> > >>>>> +#define PINMUX_GPIO26__FUNC_I2S1_BCK (MTK_PIN_NO(26) | 6)
> > >>>>> +#define PINMUX_GPIO26__FUNC_DBG_MON_B1 (MTK_PIN_NO(26) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
> > >>>>> +#define PINMUX_GPIO27__FUNC_DBPI_DE (MTK_PIN_NO(27) | 1)
> > >>>>> +#define PINMUX_GPIO27__FUNC_ANT_SEL2 (MTK_PIN_NO(27) | 2)
> > >>>>> +#define PINMUX_GPIO27__FUNC_SCL7 (MTK_PIN_NO(27) | 3)
> > >>>>> +#define PINMUX_GPIO27__FUNC_DMIC_CLK (MTK_PIN_NO(27) | 4)
> > >>>>> +#define PINMUX_GPIO27__FUNC_IO_JTAG_TDO (MTK_PIN_NO(27) | 5)
> > >>>>> +#define PINMUX_GPIO27__FUNC_I2S1_LRCK (MTK_PIN_NO(27) | 6)
> > >>>>> +#define PINMUX_GPIO27__FUNC_DBG_MON_B9 (MTK_PIN_NO(27) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
> > >>>>> +#define PINMUX_GPIO28__FUNC_DBPI_CK (MTK_PIN_NO(28) | 1)
> > >>>>> +#define PINMUX_GPIO28__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(28) | 2)
> > >>>>> +#define PINMUX_GPIO28__FUNC_SDA7 (MTK_PIN_NO(28) | 3)
> > >>>>> +#define PINMUX_GPIO28__FUNC_DMIC_DAT (MTK_PIN_NO(28) | 4)
> > >>>>> +#define PINMUX_GPIO28__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(28) | 5)
> > >>>>> +#define PINMUX_GPIO28__FUNC_I2S1_DO (MTK_PIN_NO(28) | 6)
> > >>>>> +#define PINMUX_GPIO28__FUNC_DBG_MON_B32 (MTK_PIN_NO(28) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
> > >>>>> +#define PINMUX_GPIO29__FUNC_MSDC1_CLK (MTK_PIN_NO(29) | 1)
> > >>>>> +#define PINMUX_GPIO29__FUNC_IO_JTAG_TCK (MTK_PIN_NO(29) | 2)
> > >>>>> +#define PINMUX_GPIO29__FUNC_UDI_TCK (MTK_PIN_NO(29) | 3)
> > >>>>> +#define PINMUX_GPIO29__FUNC_CONN_DSP_JCK (MTK_PIN_NO(29) | 4)
> > >>>>> +#define PINMUX_GPIO29__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(29) | 5)
> > >>>>> +#define PINMUX_GPIO29__FUNC_PCM1_CLK (MTK_PIN_NO(29) | 6)
> > >>>>> +#define PINMUX_GPIO29__FUNC_DBG_MON_A6 (MTK_PIN_NO(29) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
> > >>>>> +#define PINMUX_GPIO30__FUNC_MSDC1_DAT3 (MTK_PIN_NO(30) | 1)
> > >>>>> +#define PINMUX_GPIO30__FUNC_DAP_MD32_SWD (MTK_PIN_NO(30) | 2)
> > >>>>> +#define PINMUX_GPIO30__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 3)
> > >>>>> +#define PINMUX_GPIO30__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(30) | 4)
> > >>>>> +#define PINMUX_GPIO30__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(30) | 5)
> > >>>>> +#define PINMUX_GPIO30__FUNC_PCM1_DI (MTK_PIN_NO(30) | 6)
> > >>>>> +#define PINMUX_GPIO30__FUNC_DBG_MON_A7 (MTK_PIN_NO(30) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
> > >>>>> +#define PINMUX_GPIO31__FUNC_MSDC1_CMD (MTK_PIN_NO(31) | 1)
> > >>>>> +#define PINMUX_GPIO31__FUNC_IO_JTAG_TMS (MTK_PIN_NO(31) | 2)
> > >>>>> +#define PINMUX_GPIO31__FUNC_UDI_TMS (MTK_PIN_NO(31) | 3)
> > >>>>> +#define PINMUX_GPIO31__FUNC_CONN_DSP_JMS (MTK_PIN_NO(31) | 4)
> > >>>>> +#define PINMUX_GPIO31__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(31) | 5)
> > >>>>> +#define PINMUX_GPIO31__FUNC_PCM1_SYNC (MTK_PIN_NO(31) | 6)
> > >>>>> +#define PINMUX_GPIO31__FUNC_DBG_MON_A8 (MTK_PIN_NO(31) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
> > >>>>> +#define PINMUX_GPIO32__FUNC_MSDC1_DAT0 (MTK_PIN_NO(32) | 1)
> > >>>>> +#define PINMUX_GPIO32__FUNC_IO_JTAG_TDI (MTK_PIN_NO(32) | 2)
> > >>>>> +#define PINMUX_GPIO32__FUNC_UDI_TDI (MTK_PIN_NO(32) | 3)
> > >>>>> +#define PINMUX_GPIO32__FUNC_CONN_DSP_JDI (MTK_PIN_NO(32) | 4)
> > >>>>> +#define PINMUX_GPIO32__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(32) | 5)
> > >>>>> +#define PINMUX_GPIO32__FUNC_PCM1_DO0 (MTK_PIN_NO(32) | 6)
> > >>>>> +#define PINMUX_GPIO32__FUNC_DBG_MON_A9 (MTK_PIN_NO(32) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
> > >>>>> +#define PINMUX_GPIO33__FUNC_MSDC1_DAT2 (MTK_PIN_NO(33) | 1)
> > >>>>> +#define PINMUX_GPIO33__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(33) | 2)
> > >>>>> +#define PINMUX_GPIO33__FUNC_UDI_NTRST (MTK_PIN_NO(33) | 3)
> > >>>>> +#define PINMUX_GPIO33__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(33) | 4)
> > >>>>> +#define PINMUX_GPIO33__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(33) | 5)
> > >>>>> +#define PINMUX_GPIO33__FUNC_PCM1_DO2 (MTK_PIN_NO(33) | 6)
> > >>>>> +#define PINMUX_GPIO33__FUNC_DBG_MON_A10 (MTK_PIN_NO(33) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
> > >>>>> +#define PINMUX_GPIO34__FUNC_MSDC1_DAT1 (MTK_PIN_NO(34) | 1)
> > >>>>> +#define PINMUX_GPIO34__FUNC_IO_JTAG_TDO (MTK_PIN_NO(34) | 2)
> > >>>>> +#define PINMUX_GPIO34__FUNC_UDI_TDO (MTK_PIN_NO(34) | 3)
> > >>>>> +#define PINMUX_GPIO34__FUNC_CONN_DSP_JDO (MTK_PIN_NO(34) | 4)
> > >>>>> +#define PINMUX_GPIO34__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(34) | 5)
> > >>>>> +#define PINMUX_GPIO34__FUNC_PCM1_DO1 (MTK_PIN_NO(34) | 6)
> > >>>>> +#define PINMUX_GPIO34__FUNC_DBG_MON_A11 (MTK_PIN_NO(34) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
> > >>>>> +#define PINMUX_GPIO35__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(35) | 1)
> > >>>>> +#define PINMUX_GPIO35__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(35) | 2)
> > >>>>> +#define PINMUX_GPIO35__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(35) | 3)
> > >>>>> +#define PINMUX_GPIO35__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(35) | 5)
> > >>>>> +#define PINMUX_GPIO35__FUNC_CONN_DSP_JMS (MTK_PIN_NO(35) | 6)
> > >>>>> +#define PINMUX_GPIO35__FUNC_DBG_MON_A28 (MTK_PIN_NO(35) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
> > >>>>> +#define PINMUX_GPIO36__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(36) | 1)
> > >>>>> +#define PINMUX_GPIO36__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(36) | 2)
> > >>>>> +#define PINMUX_GPIO36__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(36) | 3)
> > >>>>> +#define PINMUX_GPIO36__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(36) | 4)
> > >>>>> +#define PINMUX_GPIO36__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(36) | 5)
> > >>>>> +#define PINMUX_GPIO36__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(36) | 6)
> > >>>>> +#define PINMUX_GPIO36__FUNC_DBG_MON_A29 (MTK_PIN_NO(36) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
> > >>>>> +#define PINMUX_GPIO37__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(37) | 1)
> > >>>>> +#define PINMUX_GPIO37__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(37) | 2)
> > >>>>> +#define PINMUX_GPIO37__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(37) | 3)
> > >>>>> +#define PINMUX_GPIO37__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(37) | 5)
> > >>>>> +#define PINMUX_GPIO37__FUNC_CONN_DSP_JDO (MTK_PIN_NO(37) | 6)
> > >>>>> +#define PINMUX_GPIO37__FUNC_DBG_MON_A30 (MTK_PIN_NO(37) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
> > >>>>> +#define PINMUX_GPIO38__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(38) | 1)
> > >>>>> +#define PINMUX_GPIO38__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(38) | 3)
> > >>>>> +#define PINMUX_GPIO38__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(38) | 4)
> > >>>>> +#define PINMUX_GPIO38__FUNC_DBG_MON_A20 (MTK_PIN_NO(38) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
> > >>>>> +#define PINMUX_GPIO39__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(39) | 1)
> > >>>>> +#define PINMUX_GPIO39__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(39) | 2)
> > >>>>> +#define PINMUX_GPIO39__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(39) | 3)
> > >>>>> +#define PINMUX_GPIO39__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(39) | 5)
> > >>>>> +#define PINMUX_GPIO39__FUNC_CONN_DSP_JCK (MTK_PIN_NO(39) | 6)
> > >>>>> +#define PINMUX_GPIO39__FUNC_DBG_MON_A31 (MTK_PIN_NO(39) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
> > >>>>> +#define PINMUX_GPIO40__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(40) | 1)
> > >>>>> +#define PINMUX_GPIO40__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(40) | 2)
> > >>>>> +#define PINMUX_GPIO40__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(40) | 3)
> > >>>>> +#define PINMUX_GPIO40__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(40) | 5)
> > >>>>> +#define PINMUX_GPIO40__FUNC_CONN_DSP_JDI (MTK_PIN_NO(40) | 6)
> > >>>>> +#define PINMUX_GPIO40__FUNC_DBG_MON_A32 (MTK_PIN_NO(40) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
> > >>>>> +#define PINMUX_GPIO41__FUNC_IDDIG (MTK_PIN_NO(41) | 1)
> > >>>>> +#define PINMUX_GPIO41__FUNC_URXD1 (MTK_PIN_NO(41) | 2)
> > >>>>> +#define PINMUX_GPIO41__FUNC_UCTS0 (MTK_PIN_NO(41) | 3)
> > >>>>> +#define PINMUX_GPIO41__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(41) | 4)
> > >>>>> +#define PINMUX_GPIO41__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 5)
> > >>>>> +#define PINMUX_GPIO41__FUNC_DMIC_CLK (MTK_PIN_NO(41) | 6)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
> > >>>>> +#define PINMUX_GPIO42__FUNC_USB_DRVVBUS (MTK_PIN_NO(42) | 1)
> > >>>>> +#define PINMUX_GPIO42__FUNC_UTXD1 (MTK_PIN_NO(42) | 2)
> > >>>>> +#define PINMUX_GPIO42__FUNC_URTS0 (MTK_PIN_NO(42) | 3)
> > >>>>> +#define PINMUX_GPIO42__FUNC_SSPM_URXD_AO (MTK_PIN_NO(42) | 4)
> > >>>>> +#define PINMUX_GPIO42__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(42) | 5)
> > >>>>> +#define PINMUX_GPIO42__FUNC_DMIC_DAT (MTK_PIN_NO(42) | 6)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
> > >>>>> +#define PINMUX_GPIO43__FUNC_DISP_PWM (MTK_PIN_NO(43) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
> > >>>>> +#define PINMUX_GPIO44__FUNC_DSI_TE (MTK_PIN_NO(44) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
> > >>>>> +#define PINMUX_GPIO45__FUNC_LCM_RST (MTK_PIN_NO(45) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
> > >>>>> +#define PINMUX_GPIO46__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(46) | 1)
> > >>>>> +#define PINMUX_GPIO46__FUNC_URXD1 (MTK_PIN_NO(46) | 2)
> > >>>>> +#define PINMUX_GPIO46__FUNC_UCTS1 (MTK_PIN_NO(46) | 3)
> > >>>>> +#define PINMUX_GPIO46__FUNC_CCU_UTXD_AO (MTK_PIN_NO(46) | 4)
> > >>>>> +#define PINMUX_GPIO46__FUNC_TP_UCTS1_AO (MTK_PIN_NO(46) | 5)
> > >>>>> +#define PINMUX_GPIO46__FUNC_IDDIG (MTK_PIN_NO(46) | 6)
> > >>>>> +#define PINMUX_GPIO46__FUNC_I2S5_LRCK (MTK_PIN_NO(46) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
> > >>>>> +#define PINMUX_GPIO47__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(47) | 1)
> > >>>>> +#define PINMUX_GPIO47__FUNC_UTXD1 (MTK_PIN_NO(47) | 2)
> > >>>>> +#define PINMUX_GPIO47__FUNC_URTS1 (MTK_PIN_NO(47) | 3)
> > >>>>> +#define PINMUX_GPIO47__FUNC_CCU_URXD_AO (MTK_PIN_NO(47) | 4)
> > >>>>> +#define PINMUX_GPIO47__FUNC_TP_URTS1_AO (MTK_PIN_NO(47) | 5)
> > >>>>> +#define PINMUX_GPIO47__FUNC_USB_DRVVBUS (MTK_PIN_NO(47) | 6)
> > >>>>> +#define PINMUX_GPIO47__FUNC_I2S5_DO (MTK_PIN_NO(47) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
> > >>>>> +#define PINMUX_GPIO48__FUNC_SCL5 (MTK_PIN_NO(48) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
> > >>>>> +#define PINMUX_GPIO49__FUNC_SDA5 (MTK_PIN_NO(49) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
> > >>>>> +#define PINMUX_GPIO50__FUNC_SCL3 (MTK_PIN_NO(50) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
> > >>>>> +#define PINMUX_GPIO51__FUNC_SDA3 (MTK_PIN_NO(51) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
> > >>>>> +#define PINMUX_GPIO52__FUNC_BPI_ANT2 (MTK_PIN_NO(52) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
> > >>>>> +#define PINMUX_GPIO53__FUNC_BPI_ANT0 (MTK_PIN_NO(53) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
> > >>>>> +#define PINMUX_GPIO54__FUNC_BPI_OLAT1 (MTK_PIN_NO(54) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
> > >>>>> +#define PINMUX_GPIO55__FUNC_BPI_BUS8 (MTK_PIN_NO(55) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
> > >>>>> +#define PINMUX_GPIO56__FUNC_BPI_BUS9 (MTK_PIN_NO(56) | 1)
> > >>>>> +#define PINMUX_GPIO56__FUNC_SCL_6306 (MTK_PIN_NO(56) | 2)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
> > >>>>> +#define PINMUX_GPIO57__FUNC_BPI_BUS10 (MTK_PIN_NO(57) | 1)
> > >>>>> +#define PINMUX_GPIO57__FUNC_SDA_6306 (MTK_PIN_NO(57) | 2)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
> > >>>>> +#define PINMUX_GPIO58__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(58) | 1)
> > >>>>> +#define PINMUX_GPIO58__FUNC_SPM_BSI_D2 (MTK_PIN_NO(58) | 2)
> > >>>>> +#define PINMUX_GPIO58__FUNC_PWM_B (MTK_PIN_NO(58) | 3)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
> > >>>>> +#define PINMUX_GPIO59__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(59) | 1)
> > >>>>> +#define PINMUX_GPIO59__FUNC_SPM_BSI_D1 (MTK_PIN_NO(59) | 2)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
> > >>>>> +#define PINMUX_GPIO60__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(60) | 1)
> > >>>>> +#define PINMUX_GPIO60__FUNC_SPM_BSI_D0 (MTK_PIN_NO(60) | 2)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
> > >>>>> +#define PINMUX_GPIO61__FUNC_MIPI1_SDATA (MTK_PIN_NO(61) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
> > >>>>> +#define PINMUX_GPIO62__FUNC_MIPI1_SCLK (MTK_PIN_NO(62) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
> > >>>>> +#define PINMUX_GPIO63__FUNC_MIPI0_SDATA (MTK_PIN_NO(63) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
> > >>>>> +#define PINMUX_GPIO64__FUNC_MIPI0_SCLK (MTK_PIN_NO(64) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
> > >>>>> +#define PINMUX_GPIO65__FUNC_MIPI3_SDATA (MTK_PIN_NO(65) | 1)
> > >>>>> +#define PINMUX_GPIO65__FUNC_BPI_OLAT2 (MTK_PIN_NO(65) | 2)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
> > >>>>> +#define PINMUX_GPIO66__FUNC_MIPI3_SCLK (MTK_PIN_NO(66) | 1)
> > >>>>> +#define PINMUX_GPIO66__FUNC_BPI_OLAT3 (MTK_PIN_NO(66) | 2)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
> > >>>>> +#define PINMUX_GPIO67__FUNC_MIPI2_SDATA (MTK_PIN_NO(67) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
> > >>>>> +#define PINMUX_GPIO68__FUNC_MIPI2_SCLK (MTK_PIN_NO(68) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
> > >>>>> +#define PINMUX_GPIO69__FUNC_BPI_BUS7 (MTK_PIN_NO(69) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
> > >>>>> +#define PINMUX_GPIO70__FUNC_BPI_BUS6 (MTK_PIN_NO(70) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
> > >>>>> +#define PINMUX_GPIO71__FUNC_BPI_BUS5 (MTK_PIN_NO(71) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
> > >>>>> +#define PINMUX_GPIO72__FUNC_BPI_BUS4 (MTK_PIN_NO(72) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
> > >>>>> +#define PINMUX_GPIO73__FUNC_BPI_BUS3 (MTK_PIN_NO(73) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
> > >>>>> +#define PINMUX_GPIO74__FUNC_BPI_BUS2 (MTK_PIN_NO(74) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
> > >>>>> +#define PINMUX_GPIO75__FUNC_BPI_BUS1 (MTK_PIN_NO(75) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
> > >>>>> +#define PINMUX_GPIO76__FUNC_BPI_BUS0 (MTK_PIN_NO(76) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
> > >>>>> +#define PINMUX_GPIO77__FUNC_BPI_ANT1 (MTK_PIN_NO(77) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
> > >>>>> +#define PINMUX_GPIO78__FUNC_BPI_OLAT0 (MTK_PIN_NO(78) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
> > >>>>> +#define PINMUX_GPIO79__FUNC_BPI_PA_VM1 (MTK_PIN_NO(79) | 1)
> > >>>>> +#define PINMUX_GPIO79__FUNC_MIPI4_SDATA (MTK_PIN_NO(79) | 2)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
> > >>>>> +#define PINMUX_GPIO80__FUNC_BPI_PA_VM0 (MTK_PIN_NO(80) | 1)
> > >>>>> +#define PINMUX_GPIO80__FUNC_MIPI4_SCLK (MTK_PIN_NO(80) | 2)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
> > >>>>> +#define PINMUX_GPIO81__FUNC_SDA1 (MTK_PIN_NO(81) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
> > >>>>> +#define PINMUX_GPIO82__FUNC_SDA0 (MTK_PIN_NO(82) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
> > >>>>> +#define PINMUX_GPIO83__FUNC_SCL0 (MTK_PIN_NO(83) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
> > >>>>> +#define PINMUX_GPIO84__FUNC_SCL1 (MTK_PIN_NO(84) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
> > >>>>> +#define PINMUX_GPIO85__FUNC_SPI0_MI (MTK_PIN_NO(85) | 1)
> > >>>>> +#define PINMUX_GPIO85__FUNC_SCP_SPI0_MI (MTK_PIN_NO(85) | 2)
> > >>>>> +#define PINMUX_GPIO85__FUNC_CLKM3 (MTK_PIN_NO(85) | 3)
> > >>>>> +#define PINMUX_GPIO85__FUNC_I2S1_BCK (MTK_PIN_NO(85) | 4)
> > >>>>> +#define PINMUX_GPIO85__FUNC_MFG_DFD_JTAG_TDO (MTK_PIN_NO(85) | 5)
> > >>>>> +#define PINMUX_GPIO85__FUNC_DFD_TDO (MTK_PIN_NO(85) | 6)
> > >>>>> +#define PINMUX_GPIO85__FUNC_JTDO_SEL1 (MTK_PIN_NO(85) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
> > >>>>> +#define PINMUX_GPIO86__FUNC_SPI0_CSB (MTK_PIN_NO(86) | 1)
> > >>>>> +#define PINMUX_GPIO86__FUNC_SCP_SPI0_CS (MTK_PIN_NO(86) | 2)
> > >>>>> +#define PINMUX_GPIO86__FUNC_CLKM0 (MTK_PIN_NO(86) | 3)
> > >>>>> +#define PINMUX_GPIO86__FUNC_I2S1_LRCK (MTK_PIN_NO(86) | 4)
> > >>>>> +#define PINMUX_GPIO86__FUNC_MFG_DFD_JTAG_TMS (MTK_PIN_NO(86) | 5)
> > >>>>> +#define PINMUX_GPIO86__FUNC_DFD_TMS (MTK_PIN_NO(86) | 6)
> > >>>>> +#define PINMUX_GPIO86__FUNC_JTMS_SEL1 (MTK_PIN_NO(86) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
> > >>>>> +#define PINMUX_GPIO87__FUNC_SPI0_MO (MTK_PIN_NO(87) | 1)
> > >>>>> +#define PINMUX_GPIO87__FUNC_SCP_SPI0_MO (MTK_PIN_NO(87) | 2)
> > >>>>> +#define PINMUX_GPIO87__FUNC_SDA1 (MTK_PIN_NO(87) | 3)
> > >>>>> +#define PINMUX_GPIO87__FUNC_I2S1_DO (MTK_PIN_NO(87) | 4)
> > >>>>> +#define PINMUX_GPIO87__FUNC_MFG_DFD_JTAG_TDI (MTK_PIN_NO(87) | 5)
> > >>>>> +#define PINMUX_GPIO87__FUNC_DFD_TDI (MTK_PIN_NO(87) | 6)
> > >>>>> +#define PINMUX_GPIO87__FUNC_JTDI_SEL1 (MTK_PIN_NO(87) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
> > >>>>> +#define PINMUX_GPIO88__FUNC_SPI0_CLK (MTK_PIN_NO(88) | 1)
> > >>>>> +#define PINMUX_GPIO88__FUNC_SCP_SPI0_CK (MTK_PIN_NO(88) | 2)
> > >>>>> +#define PINMUX_GPIO88__FUNC_SCL1 (MTK_PIN_NO(88) | 3)
> > >>>>> +#define PINMUX_GPIO88__FUNC_I2S1_MCK (MTK_PIN_NO(88) | 4)
> > >>>>> +#define PINMUX_GPIO88__FUNC_MFG_DFD_JTAG_TCK (MTK_PIN_NO(88) | 5)
> > >>>>> +#define PINMUX_GPIO88__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 6)
> > >>>>> +#define PINMUX_GPIO88__FUNC_JTCK_SEL1 (MTK_PIN_NO(88) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
> > >>>>> +#define PINMUX_GPIO89__FUNC_SRCLKENAI0 (MTK_PIN_NO(89) | 1)
> > >>>>> +#define PINMUX_GPIO89__FUNC_PWM_C (MTK_PIN_NO(89) | 2)
> > >>>>> +#define PINMUX_GPIO89__FUNC_I2S5_BCK (MTK_PIN_NO(89) | 3)
> > >>>>> +#define PINMUX_GPIO89__FUNC_ANT_SEL6 (MTK_PIN_NO(89) | 4)
> > >>>>> +#define PINMUX_GPIO89__FUNC_SDA8 (MTK_PIN_NO(89) | 5)
> > >>>>> +#define PINMUX_GPIO89__FUNC_CMVREF0 (MTK_PIN_NO(89) | 6)
> > >>>>> +#define PINMUX_GPIO89__FUNC_DBG_MON_A21 (MTK_PIN_NO(89) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
> > >>>>> +#define PINMUX_GPIO90__FUNC_PWM_A (MTK_PIN_NO(90) | 1)
> > >>>>> +#define PINMUX_GPIO90__FUNC_CMMCLK2 (MTK_PIN_NO(90) | 2)
> > >>>>> +#define PINMUX_GPIO90__FUNC_I2S5_LRCK (MTK_PIN_NO(90) | 3)
> > >>>>> +#define PINMUX_GPIO90__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(90) | 4)
> > >>>>> +#define PINMUX_GPIO90__FUNC_SCL8 (MTK_PIN_NO(90) | 5)
> > >>>>> +#define PINMUX_GPIO90__FUNC_PTA_RXD (MTK_PIN_NO(90) | 6)
> > >>>>> +#define PINMUX_GPIO90__FUNC_DBG_MON_A22 (MTK_PIN_NO(90) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
> > >>>>> +#define PINMUX_GPIO91__FUNC_KPROW1 (MTK_PIN_NO(91) | 1)
> > >>>>> +#define PINMUX_GPIO91__FUNC_PWM_B (MTK_PIN_NO(91) | 2)
> > >>>>> +#define PINMUX_GPIO91__FUNC_I2S5_DO (MTK_PIN_NO(91) | 3)
> > >>>>> +#define PINMUX_GPIO91__FUNC_ANT_SEL7 (MTK_PIN_NO(91) | 4)
> > >>>>> +#define PINMUX_GPIO91__FUNC_CMMCLK3 (MTK_PIN_NO(91) | 5)
> > >>>>> +#define PINMUX_GPIO91__FUNC_PTA_TXD (MTK_PIN_NO(91) | 6)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
> > >>>>> +#define PINMUX_GPIO92__FUNC_KPROW0 (MTK_PIN_NO(92) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
> > >>>>> +#define PINMUX_GPIO93__FUNC_KPCOL0 (MTK_PIN_NO(93) | 1)
> > >>>>> +#define PINMUX_GPIO93__FUNC_DBG_MON_B27 (MTK_PIN_NO(93) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
> > >>>>> +#define PINMUX_GPIO94__FUNC_KPCOL1 (MTK_PIN_NO(94) | 1)
> > >>>>> +#define PINMUX_GPIO94__FUNC_I2S2_DI2 (MTK_PIN_NO(94) | 2)
> > >>>>> +#define PINMUX_GPIO94__FUNC_I2S5_MCK (MTK_PIN_NO(94) | 3)
> > >>>>> +#define PINMUX_GPIO94__FUNC_CMMCLK2 (MTK_PIN_NO(94) | 4)
> > >>>>> +#define PINMUX_GPIO94__FUNC_SCP_SPI2_MI (MTK_PIN_NO(94) | 5)
> > >>>>> +#define PINMUX_GPIO94__FUNC_SRCLKENAI1 (MTK_PIN_NO(94) | 6)
> > >>>>> +#define PINMUX_GPIO94__FUNC_SPI2_MI (MTK_PIN_NO(94) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
> > >>>>> +#define PINMUX_GPIO95__FUNC_URXD0 (MTK_PIN_NO(95) | 1)
> > >>>>> +#define PINMUX_GPIO95__FUNC_UTXD0 (MTK_PIN_NO(95) | 2)
> > >>>>> +#define PINMUX_GPIO95__FUNC_MD_URXD0 (MTK_PIN_NO(95) | 3)
> > >>>>> +#define PINMUX_GPIO95__FUNC_MD_URXD1 (MTK_PIN_NO(95) | 4)
> > >>>>> +#define PINMUX_GPIO95__FUNC_SSPM_URXD_AO (MTK_PIN_NO(95) | 5)
> > >>>>> +#define PINMUX_GPIO95__FUNC_CCU_URXD_AO (MTK_PIN_NO(95) | 6)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
> > >>>>> +#define PINMUX_GPIO96__FUNC_UTXD0 (MTK_PIN_NO(96) | 1)
> > >>>>> +#define PINMUX_GPIO96__FUNC_URXD0 (MTK_PIN_NO(96) | 2)
> > >>>>> +#define PINMUX_GPIO96__FUNC_MD_UTXD0 (MTK_PIN_NO(96) | 3)
> > >>>>> +#define PINMUX_GPIO96__FUNC_MD_UTXD1 (MTK_PIN_NO(96) | 4)
> > >>>>> +#define PINMUX_GPIO96__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(96) | 5)
> > >>>>> +#define PINMUX_GPIO96__FUNC_CCU_UTXD_AO (MTK_PIN_NO(96) | 6)
> > >>>>> +#define PINMUX_GPIO96__FUNC_DBG_MON_B2 (MTK_PIN_NO(96) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
> > >>>>> +#define PINMUX_GPIO97__FUNC_UCTS0 (MTK_PIN_NO(97) | 1)
> > >>>>> +#define PINMUX_GPIO97__FUNC_I2S2_MCK (MTK_PIN_NO(97) | 2)
> > >>>>> +#define PINMUX_GPIO97__FUNC_IDDIG (MTK_PIN_NO(97) | 3)
> > >>>>> +#define PINMUX_GPIO97__FUNC_CONN_MCU_TDO (MTK_PIN_NO(97) | 4)
> > >>>>> +#define PINMUX_GPIO97__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(97) | 5)
> > >>>>> +#define PINMUX_GPIO97__FUNC_IO_JTAG_TDO (MTK_PIN_NO(97) | 6)
> > >>>>> +#define PINMUX_GPIO97__FUNC_DBG_MON_B3 (MTK_PIN_NO(97) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
> > >>>>> +#define PINMUX_GPIO98__FUNC_URTS0 (MTK_PIN_NO(98) | 1)
> > >>>>> +#define PINMUX_GPIO98__FUNC_I2S2_BCK (MTK_PIN_NO(98) | 2)
> > >>>>> +#define PINMUX_GPIO98__FUNC_USB_DRVVBUS (MTK_PIN_NO(98) | 3)
> > >>>>> +#define PINMUX_GPIO98__FUNC_CONN_MCU_TMS (MTK_PIN_NO(98) | 4)
> > >>>>> +#define PINMUX_GPIO98__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(98) | 5)
> > >>>>> +#define PINMUX_GPIO98__FUNC_IO_JTAG_TMS (MTK_PIN_NO(98) | 6)
> > >>>>> +#define PINMUX_GPIO98__FUNC_DBG_MON_B4 (MTK_PIN_NO(98) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
> > >>>>> +#define PINMUX_GPIO99__FUNC_CMMCLK0 (MTK_PIN_NO(99) | 1)
> > >>>>> +#define PINMUX_GPIO99__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(99) | 4)
> > >>>>> +#define PINMUX_GPIO99__FUNC_DBG_MON_B28 (MTK_PIN_NO(99) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
> > >>>>> +#define PINMUX_GPIO100__FUNC_CMMCLK1 (MTK_PIN_NO(100) | 1)
> > >>>>> +#define PINMUX_GPIO100__FUNC_PWM_C (MTK_PIN_NO(100) | 2)
> > >>>>> +#define PINMUX_GPIO100__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(100) | 3)
> > >>>>> +#define PINMUX_GPIO100__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(100) | 4)
> > >>>>> +#define PINMUX_GPIO100__FUNC_DBG_MON_B29 (MTK_PIN_NO(100) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
> > >>>>> +#define PINMUX_GPIO101__FUNC_CLKM2 (MTK_PIN_NO(101) | 1)
> > >>>>> +#define PINMUX_GPIO101__FUNC_I2S2_LRCK (MTK_PIN_NO(101) | 2)
> > >>>>> +#define PINMUX_GPIO101__FUNC_CMVREF1 (MTK_PIN_NO(101) | 3)
> > >>>>> +#define PINMUX_GPIO101__FUNC_CONN_MCU_TCK (MTK_PIN_NO(101) | 4)
> > >>>>> +#define PINMUX_GPIO101__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(101) | 5)
> > >>>>> +#define PINMUX_GPIO101__FUNC_IO_JTAG_TCK (MTK_PIN_NO(101) | 6)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
> > >>>>> +#define PINMUX_GPIO102__FUNC_CLKM1 (MTK_PIN_NO(102) | 1)
> > >>>>> +#define PINMUX_GPIO102__FUNC_I2S2_DI (MTK_PIN_NO(102) | 2)
> > >>>>> +#define PINMUX_GPIO102__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(102) | 3)
> > >>>>> +#define PINMUX_GPIO102__FUNC_CONN_MCU_TDI (MTK_PIN_NO(102) | 4)
> > >>>>> +#define PINMUX_GPIO102__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(102) | 5)
> > >>>>> +#define PINMUX_GPIO102__FUNC_IO_JTAG_TDI (MTK_PIN_NO(102) | 6)
> > >>>>> +#define PINMUX_GPIO102__FUNC_DBG_MON_B8 (MTK_PIN_NO(102) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
> > >>>>> +#define PINMUX_GPIO103__FUNC_SCL2 (MTK_PIN_NO(103) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
> > >>>>> +#define PINMUX_GPIO104__FUNC_SDA2 (MTK_PIN_NO(104) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
> > >>>>> +#define PINMUX_GPIO105__FUNC_SCL4 (MTK_PIN_NO(105) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
> > >>>>> +#define PINMUX_GPIO106__FUNC_SDA4 (MTK_PIN_NO(106) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
> > >>>>> +#define PINMUX_GPIO107__FUNC_DMIC_CLK (MTK_PIN_NO(107) | 1)
> > >>>>> +#define PINMUX_GPIO107__FUNC_ANT_SEL0 (MTK_PIN_NO(107) | 2)
> > >>>>> +#define PINMUX_GPIO107__FUNC_CLKM0 (MTK_PIN_NO(107) | 3)
> > >>>>> +#define PINMUX_GPIO107__FUNC_SDA7 (MTK_PIN_NO(107) | 4)
> > >>>>> +#define PINMUX_GPIO107__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(107) | 5)
> > >>>>> +#define PINMUX_GPIO107__FUNC_PWM_A (MTK_PIN_NO(107) | 6)
> > >>>>> +#define PINMUX_GPIO107__FUNC_DBG_MON_B12 (MTK_PIN_NO(107) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
> > >>>>> +#define PINMUX_GPIO108__FUNC_CMMCLK2 (MTK_PIN_NO(108) | 1)
> > >>>>> +#define PINMUX_GPIO108__FUNC_ANT_SEL1 (MTK_PIN_NO(108) | 2)
> > >>>>> +#define PINMUX_GPIO108__FUNC_CLKM1 (MTK_PIN_NO(108) | 3)
> > >>>>> +#define PINMUX_GPIO108__FUNC_SCL8 (MTK_PIN_NO(108) | 4)
> > >>>>> +#define PINMUX_GPIO108__FUNC_DAP_MD32_SWD (MTK_PIN_NO(108) | 5)
> > >>>>> +#define PINMUX_GPIO108__FUNC_PWM_B (MTK_PIN_NO(108) | 6)
> > >>>>> +#define PINMUX_GPIO108__FUNC_DBG_MON_B13 (MTK_PIN_NO(108) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
> > >>>>> +#define PINMUX_GPIO109__FUNC_DMIC_DAT (MTK_PIN_NO(109) | 1)
> > >>>>> +#define PINMUX_GPIO109__FUNC_ANT_SEL2 (MTK_PIN_NO(109) | 2)
> > >>>>> +#define PINMUX_GPIO109__FUNC_CLKM2 (MTK_PIN_NO(109) | 3)
> > >>>>> +#define PINMUX_GPIO109__FUNC_SDA8 (MTK_PIN_NO(109) | 4)
> > >>>>> +#define PINMUX_GPIO109__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(109) | 5)
> > >>>>> +#define PINMUX_GPIO109__FUNC_PWM_C (MTK_PIN_NO(109) | 6)
> > >>>>> +#define PINMUX_GPIO109__FUNC_DBG_MON_B14 (MTK_PIN_NO(109) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
> > >>>>> +#define PINMUX_GPIO110__FUNC_SCL7 (MTK_PIN_NO(110) | 1)
> > >>>>> +#define PINMUX_GPIO110__FUNC_ANT_SEL0 (MTK_PIN_NO(110) | 2)
> > >>>>> +#define PINMUX_GPIO110__FUNC_TP_URXD1_AO (MTK_PIN_NO(110) | 3)
> > >>>>> +#define PINMUX_GPIO110__FUNC_USB_DRVVBUS (MTK_PIN_NO(110) | 4)
> > >>>>> +#define PINMUX_GPIO110__FUNC_SRCLKENAI1 (MTK_PIN_NO(110) | 5)
> > >>>>> +#define PINMUX_GPIO110__FUNC_KPCOL2 (MTK_PIN_NO(110) | 6)
> > >>>>> +#define PINMUX_GPIO110__FUNC_URXD1 (MTK_PIN_NO(110) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
> > >>>>> +#define PINMUX_GPIO111__FUNC_CMMCLK3 (MTK_PIN_NO(111) | 1)
> > >>>>> +#define PINMUX_GPIO111__FUNC_ANT_SEL1 (MTK_PIN_NO(111) | 2)
> > >>>>> +#define PINMUX_GPIO111__FUNC_SRCLKENAI0 (MTK_PIN_NO(111) | 3)
> > >>>>> +#define PINMUX_GPIO111__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(111) | 4)
> > >>>>> +#define PINMUX_GPIO111__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(111) | 5)
> > >>>>> +#define PINMUX_GPIO111__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(111) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
> > >>>>> +#define PINMUX_GPIO112__FUNC_SDA7 (MTK_PIN_NO(112) | 1)
> > >>>>> +#define PINMUX_GPIO112__FUNC_ANT_SEL2 (MTK_PIN_NO(112) | 2)
> > >>>>> +#define PINMUX_GPIO112__FUNC_TP_UTXD1_AO (MTK_PIN_NO(112) | 3)
> > >>>>> +#define PINMUX_GPIO112__FUNC_IDDIG (MTK_PIN_NO(112) | 4)
> > >>>>> +#define PINMUX_GPIO112__FUNC_AGPS_SYNC (MTK_PIN_NO(112) | 5)
> > >>>>> +#define PINMUX_GPIO112__FUNC_KPROW2 (MTK_PIN_NO(112) | 6)
> > >>>>> +#define PINMUX_GPIO112__FUNC_UTXD1 (MTK_PIN_NO(112) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
> > >>>>> +#define PINMUX_GPIO113__FUNC_CONN_TOP_CLK (MTK_PIN_NO(113) | 1)
> > >>>>> +#define PINMUX_GPIO113__FUNC_SCL6 (MTK_PIN_NO(113) | 3)
> > >>>>> +#define PINMUX_GPIO113__FUNC_AUXIF_CLK0 (MTK_PIN_NO(113) | 4)
> > >>>>> +#define PINMUX_GPIO113__FUNC_TP_UCTS1_AO (MTK_PIN_NO(113) | 6)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
> > >>>>> +#define PINMUX_GPIO114__FUNC_CONN_TOP_DATA (MTK_PIN_NO(114) | 1)
> > >>>>> +#define PINMUX_GPIO114__FUNC_SDA6 (MTK_PIN_NO(114) | 3)
> > >>>>> +#define PINMUX_GPIO114__FUNC_AUXIF_ST0 (MTK_PIN_NO(114) | 4)
> > >>>>> +#define PINMUX_GPIO114__FUNC_TP_URTS1_AO (MTK_PIN_NO(114) | 6)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
> > >>>>> +#define PINMUX_GPIO115__FUNC_CONN_BT_CLK (MTK_PIN_NO(115) | 1)
> > >>>>> +#define PINMUX_GPIO115__FUNC_UTXD1 (MTK_PIN_NO(115) | 2)
> > >>>>> +#define PINMUX_GPIO115__FUNC_PTA_TXD (MTK_PIN_NO(115) | 3)
> > >>>>> +#define PINMUX_GPIO115__FUNC_AUXIF_CLK1 (MTK_PIN_NO(115) | 4)
> > >>>>> +#define PINMUX_GPIO115__FUNC_DAP_MD32_SWD (MTK_PIN_NO(115) | 5)
> > >>>>> +#define PINMUX_GPIO115__FUNC_TP_UTXD1_AO (MTK_PIN_NO(115) | 6)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
> > >>>>> +#define PINMUX_GPIO116__FUNC_CONN_BT_DATA (MTK_PIN_NO(116) | 1)
> > >>>>> +#define PINMUX_GPIO116__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(116) | 2)
> > >>>>> +#define PINMUX_GPIO116__FUNC_AUXIF_ST1 (MTK_PIN_NO(116) | 4)
> > >>>>> +#define PINMUX_GPIO116__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(116) | 5)
> > >>>>> +#define PINMUX_GPIO116__FUNC_TP_URXD2_AO (MTK_PIN_NO(116) | 6)
> > >>>>> +#define PINMUX_GPIO116__FUNC_DBG_MON_A0 (MTK_PIN_NO(116) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
> > >>>>> +#define PINMUX_GPIO117__FUNC_CONN_WF_HB0 (MTK_PIN_NO(117) | 1)
> > >>>>> +#define PINMUX_GPIO117__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(117) | 2)
> > >>>>> +#define PINMUX_GPIO117__FUNC_TP_UTXD2_AO (MTK_PIN_NO(117) | 6)
> > >>>>> +#define PINMUX_GPIO117__FUNC_DBG_MON_A4 (MTK_PIN_NO(117) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
> > >>>>> +#define PINMUX_GPIO118__FUNC_CONN_WF_HB1 (MTK_PIN_NO(118) | 1)
> > >>>>> +#define PINMUX_GPIO118__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(118) | 2)
> > >>>>> +#define PINMUX_GPIO118__FUNC_SSPM_URXD_AO (MTK_PIN_NO(118) | 5)
> > >>>>> +#define PINMUX_GPIO118__FUNC_TP_UCTS2_AO (MTK_PIN_NO(118) | 6)
> > >>>>> +#define PINMUX_GPIO118__FUNC_DBG_MON_A5 (MTK_PIN_NO(118) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
> > >>>>> +#define PINMUX_GPIO119__FUNC_CONN_WF_HB2 (MTK_PIN_NO(119) | 1)
> > >>>>> +#define PINMUX_GPIO119__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(119) | 2)
> > >>>>> +#define PINMUX_GPIO119__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(119) | 5)
> > >>>>> +#define PINMUX_GPIO119__FUNC_TP_URTS2_AO (MTK_PIN_NO(119) | 6)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
> > >>>>> +#define PINMUX_GPIO120__FUNC_CONN_WB_PTA (MTK_PIN_NO(120) | 1)
> > >>>>> +#define PINMUX_GPIO120__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(120) | 2)
> > >>>>> +#define PINMUX_GPIO120__FUNC_CCU_URXD_AO (MTK_PIN_NO(120) | 5)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
> > >>>>> +#define PINMUX_GPIO121__FUNC_CONN_HRST_B (MTK_PIN_NO(121) | 1)
> > >>>>> +#define PINMUX_GPIO121__FUNC_URXD1 (MTK_PIN_NO(121) | 2)
> > >>>>> +#define PINMUX_GPIO121__FUNC_PTA_RXD (MTK_PIN_NO(121) | 3)
> > >>>>> +#define PINMUX_GPIO121__FUNC_CCU_UTXD_AO (MTK_PIN_NO(121) | 5)
> > >>>>> +#define PINMUX_GPIO121__FUNC_TP_URXD1_AO (MTK_PIN_NO(121) | 6)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
> > >>>>> +#define PINMUX_GPIO122__FUNC_MSDC0_CMD (MTK_PIN_NO(122) | 1)
> > >>>>> +#define PINMUX_GPIO122__FUNC_SSPM_URXD2_AO (MTK_PIN_NO(122) | 2)
> > >>>>> +#define PINMUX_GPIO122__FUNC_ANT_SEL1 (MTK_PIN_NO(122) | 3)
> > >>>>> +#define PINMUX_GPIO122__FUNC_DBG_MON_A12 (MTK_PIN_NO(122) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
> > >>>>> +#define PINMUX_GPIO123__FUNC_MSDC0_DAT0 (MTK_PIN_NO(123) | 1)
> > >>>>> +#define PINMUX_GPIO123__FUNC_ANT_SEL0 (MTK_PIN_NO(123) | 3)
> > >>>>> +#define PINMUX_GPIO123__FUNC_DBG_MON_A13 (MTK_PIN_NO(123) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
> > >>>>> +#define PINMUX_GPIO124__FUNC_MSDC0_CLK (MTK_PIN_NO(124) | 1)
> > >>>>> +#define PINMUX_GPIO124__FUNC_DBG_MON_A14 (MTK_PIN_NO(124) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
> > >>>>> +#define PINMUX_GPIO125__FUNC_MSDC0_DAT2 (MTK_PIN_NO(125) | 1)
> > >>>>> +#define PINMUX_GPIO125__FUNC_MRG_CLK (MTK_PIN_NO(125) | 3)
> > >>>>> +#define PINMUX_GPIO125__FUNC_DBG_MON_A15 (MTK_PIN_NO(125) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
> > >>>>> +#define PINMUX_GPIO126__FUNC_MSDC0_DAT4 (MTK_PIN_NO(126) | 1)
> > >>>>> +#define PINMUX_GPIO126__FUNC_ANT_SEL5 (MTK_PIN_NO(126) | 3)
> > >>>>> +#define PINMUX_GPIO126__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(126) | 6)
> > >>>>> +#define PINMUX_GPIO126__FUNC_DBG_MON_A16 (MTK_PIN_NO(126) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
> > >>>>> +#define PINMUX_GPIO127__FUNC_MSDC0_DAT6 (MTK_PIN_NO(127) | 1)
> > >>>>> +#define PINMUX_GPIO127__FUNC_ANT_SEL4 (MTK_PIN_NO(127) | 3)
> > >>>>> +#define PINMUX_GPIO127__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(127) | 6)
> > >>>>> +#define PINMUX_GPIO127__FUNC_DBG_MON_A17 (MTK_PIN_NO(127) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
> > >>>>> +#define PINMUX_GPIO128__FUNC_MSDC0_DAT1 (MTK_PIN_NO(128) | 1)
> > >>>>> +#define PINMUX_GPIO128__FUNC_ANT_SEL2 (MTK_PIN_NO(128) | 3)
> > >>>>> +#define PINMUX_GPIO128__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(128) | 6)
> > >>>>> +#define PINMUX_GPIO128__FUNC_DBG_MON_A18 (MTK_PIN_NO(128) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
> > >>>>> +#define PINMUX_GPIO129__FUNC_MSDC0_DAT5 (MTK_PIN_NO(129) | 1)
> > >>>>> +#define PINMUX_GPIO129__FUNC_ANT_SEL3 (MTK_PIN_NO(129) | 3)
> > >>>>> +#define PINMUX_GPIO129__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(129) | 6)
> > >>>>> +#define PINMUX_GPIO129__FUNC_DBG_MON_A23 (MTK_PIN_NO(129) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
> > >>>>> +#define PINMUX_GPIO130__FUNC_MSDC0_DAT7 (MTK_PIN_NO(130) | 1)
> > >>>>> +#define PINMUX_GPIO130__FUNC_MRG_DO (MTK_PIN_NO(130) | 3)
> > >>>>> +#define PINMUX_GPIO130__FUNC_DBG_MON_A24 (MTK_PIN_NO(130) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
> > >>>>> +#define PINMUX_GPIO131__FUNC_MSDC0_DSL (MTK_PIN_NO(131) | 1)
> > >>>>> +#define PINMUX_GPIO131__FUNC_MRG_SYNC (MTK_PIN_NO(131) | 3)
> > >>>>> +#define PINMUX_GPIO131__FUNC_DBG_MON_A25 (MTK_PIN_NO(131) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
> > >>>>> +#define PINMUX_GPIO132__FUNC_MSDC0_DAT3 (MTK_PIN_NO(132) | 1)
> > >>>>> +#define PINMUX_GPIO132__FUNC_MRG_DI (MTK_PIN_NO(132) | 3)
> > >>>>> +#define PINMUX_GPIO132__FUNC_DBG_MON_A26 (MTK_PIN_NO(132) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
> > >>>>> +#define PINMUX_GPIO133__FUNC_MSDC0_RSTB (MTK_PIN_NO(133) | 1)
> > >>>>> +#define PINMUX_GPIO133__FUNC_AGPS_SYNC (MTK_PIN_NO(133) | 3)
> > >>>>> +#define PINMUX_GPIO133__FUNC_DBG_MON_A27 (MTK_PIN_NO(133) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
> > >>>>> +#define PINMUX_GPIO134__FUNC_RTC32K_CK (MTK_PIN_NO(134) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
> > >>>>> +#define PINMUX_GPIO135__FUNC_WATCHDOG (MTK_PIN_NO(135) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
> > >>>>> +#define PINMUX_GPIO136__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(136) | 1)
> > >>>>> +#define PINMUX_GPIO136__FUNC_AUD_CLK_MISO (MTK_PIN_NO(136) | 2)
> > >>>>> +#define PINMUX_GPIO136__FUNC_I2S1_MCK (MTK_PIN_NO(136) | 3)
> > >>>>> +#define PINMUX_GPIO136__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(136) | 6)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
> > >>>>> +#define PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(137) | 1)
> > >>>>> +#define PINMUX_GPIO137__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(137) | 2)
> > >>>>> +#define PINMUX_GPIO137__FUNC_I2S1_BCK (MTK_PIN_NO(137) | 3)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
> > >>>>> +#define PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(138) | 1)
> > >>>>> +#define PINMUX_GPIO138__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(138) | 2)
> > >>>>> +#define PINMUX_GPIO138__FUNC_I2S1_LRCK (MTK_PIN_NO(138) | 3)
> > >>>>> +#define PINMUX_GPIO138__FUNC_DBG_MON_B24 (MTK_PIN_NO(138) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
> > >>>>> +#define PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(139) | 1)
> > >>>>> +#define PINMUX_GPIO139__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(139) | 2)
> > >>>>> +#define PINMUX_GPIO139__FUNC_I2S1_DO (MTK_PIN_NO(139) | 3)
> > >>>>> +#define PINMUX_GPIO139__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(139) | 6)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
> > >>>>> +#define PINMUX_GPIO140__FUNC_AUD_CLK_MISO (MTK_PIN_NO(140) | 1)
> > >>>>> +#define PINMUX_GPIO140__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(140) | 2)
> > >>>>> +#define PINMUX_GPIO140__FUNC_I2S0_MCK (MTK_PIN_NO(140) | 3)
> > >>>>> +#define PINMUX_GPIO140__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(140) | 6)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
> > >>>>> +#define PINMUX_GPIO141__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(141) | 1)
> > >>>>> +#define PINMUX_GPIO141__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(141) | 2)
> > >>>>> +#define PINMUX_GPIO141__FUNC_I2S0_BCK (MTK_PIN_NO(141) | 3)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
> > >>>>> +#define PINMUX_GPIO142__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(142) | 1)
> > >>>>> +#define PINMUX_GPIO142__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(142) | 2)
> > >>>>> +#define PINMUX_GPIO142__FUNC_I2S0_LRCK (MTK_PIN_NO(142) | 3)
> > >>>>> +#define PINMUX_GPIO142__FUNC_VOW_DAT_MISO (MTK_PIN_NO(142) | 4)
> > >>>>> +#define PINMUX_GPIO142__FUNC_DBG_MON_B25 (MTK_PIN_NO(142) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
> > >>>>> +#define PINMUX_GPIO143__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(143) | 1)
> > >>>>> +#define PINMUX_GPIO143__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(143) | 2)
> > >>>>> +#define PINMUX_GPIO143__FUNC_I2S0_DI (MTK_PIN_NO(143) | 3)
> > >>>>> +#define PINMUX_GPIO143__FUNC_VOW_CLK_MISO (MTK_PIN_NO(143) | 4)
> > >>>>> +#define PINMUX_GPIO143__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(143) | 6)
> > >>>>> +#define PINMUX_GPIO143__FUNC_DBG_MON_B26 (MTK_PIN_NO(143) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
> > >>>>> +#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(144) | 1)
> > >>>>> +#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(144) | 2)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
> > >>>>> +#define PINMUX_GPIO145__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(145) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
> > >>>>> +#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(146) | 1)
> > >>>>> +#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(146) | 2)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
> > >>>>> +#define PINMUX_GPIO147__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(147) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
> > >>>>> +#define PINMUX_GPIO148__FUNC_SRCLKENA0 (MTK_PIN_NO(148) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
> > >>>>> +#define PINMUX_GPIO149__FUNC_SRCLKENA1 (MTK_PIN_NO(149) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
> > >>>>> +#define PINMUX_GPIO150__FUNC_PWM_A (MTK_PIN_NO(150) | 1)
> > >>>>> +#define PINMUX_GPIO150__FUNC_CMFLASH (MTK_PIN_NO(150) | 2)
> > >>>>> +#define PINMUX_GPIO150__FUNC_CLKM0 (MTK_PIN_NO(150) | 3)
> > >>>>> +#define PINMUX_GPIO150__FUNC_DBG_MON_B30 (MTK_PIN_NO(150) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
> > >>>>> +#define PINMUX_GPIO151__FUNC_PWM_B (MTK_PIN_NO(151) | 1)
> > >>>>> +#define PINMUX_GPIO151__FUNC_CMVREF0 (MTK_PIN_NO(151) | 2)
> > >>>>> +#define PINMUX_GPIO151__FUNC_CLKM1 (MTK_PIN_NO(151) | 3)
> > >>>>> +#define PINMUX_GPIO151__FUNC_DBG_MON_B20 (MTK_PIN_NO(151) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
> > >>>>> +#define PINMUX_GPIO152__FUNC_PWM_C (MTK_PIN_NO(152) | 1)
> > >>>>> +#define PINMUX_GPIO152__FUNC_CMFLASH (MTK_PIN_NO(152) | 2)
> > >>>>> +#define PINMUX_GPIO152__FUNC_CLKM2 (MTK_PIN_NO(152) | 3)
> > >>>>> +#define PINMUX_GPIO152__FUNC_DBG_MON_B21 (MTK_PIN_NO(152) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
> > >>>>> +#define PINMUX_GPIO153__FUNC_PWM_A (MTK_PIN_NO(153) | 1)
> > >>>>> +#define PINMUX_GPIO153__FUNC_CMVREF0 (MTK_PIN_NO(153) | 2)
> > >>>>> +#define PINMUX_GPIO153__FUNC_CLKM3 (MTK_PIN_NO(153) | 3)
> > >>>>> +#define PINMUX_GPIO153__FUNC_DBG_MON_B22 (MTK_PIN_NO(153) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
> > >>>>> +#define PINMUX_GPIO154__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(154) | 1)
> > >>>>> +#define PINMUX_GPIO154__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(154) | 2)
> > >>>>> +#define PINMUX_GPIO154__FUNC_DBG_MON_B18 (MTK_PIN_NO(154) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
> > >>>>> +#define PINMUX_GPIO155__FUNC_ANT_SEL0 (MTK_PIN_NO(155) | 1)
> > >>>>> +#define PINMUX_GPIO155__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(155) | 2)
> > >>>>> +#define PINMUX_GPIO155__FUNC_CMVREF1 (MTK_PIN_NO(155) | 3)
> > >>>>> +#define PINMUX_GPIO155__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(155) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
> > >>>>> +#define PINMUX_GPIO156__FUNC_ANT_SEL1 (MTK_PIN_NO(156) | 1)
> > >>>>> +#define PINMUX_GPIO156__FUNC_SRCLKENAI0 (MTK_PIN_NO(156) | 2)
> > >>>>> +#define PINMUX_GPIO156__FUNC_SCL6 (MTK_PIN_NO(156) | 3)
> > >>>>> +#define PINMUX_GPIO156__FUNC_KPCOL2 (MTK_PIN_NO(156) | 4)
> > >>>>> +#define PINMUX_GPIO156__FUNC_IDDIG (MTK_PIN_NO(156) | 5)
> > >>>>> +#define PINMUX_GPIO156__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(156) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
> > >>>>> +#define PINMUX_GPIO157__FUNC_ANT_SEL2 (MTK_PIN_NO(157) | 1)
> > >>>>> +#define PINMUX_GPIO157__FUNC_SRCLKENAI1 (MTK_PIN_NO(157) | 2)
> > >>>>> +#define PINMUX_GPIO157__FUNC_SDA6 (MTK_PIN_NO(157) | 3)
> > >>>>> +#define PINMUX_GPIO157__FUNC_KPROW2 (MTK_PIN_NO(157) | 4)
> > >>>>> +#define PINMUX_GPIO157__FUNC_USB_DRVVBUS (MTK_PIN_NO(157) | 5)
> > >>>>> +#define PINMUX_GPIO157__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(157) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
> > >>>>> +#define PINMUX_GPIO158__FUNC_ANT_SEL3 (MTK_PIN_NO(158) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
> > >>>>> +#define PINMUX_GPIO159__FUNC_ANT_SEL4 (MTK_PIN_NO(159) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
> > >>>>> +#define PINMUX_GPIO160__FUNC_ANT_SEL5 (MTK_PIN_NO(160) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
> > >>>>> +#define PINMUX_GPIO161__FUNC_SPI1_A_MI (MTK_PIN_NO(161) | 1)
> > >>>>> +#define PINMUX_GPIO161__FUNC_SCP_SPI1_MI (MTK_PIN_NO(161) | 2)
> > >>>>> +#define PINMUX_GPIO161__FUNC_IDDIG (MTK_PIN_NO(161) | 3)
> > >>>>> +#define PINMUX_GPIO161__FUNC_ANT_SEL6 (MTK_PIN_NO(161) | 4)
> > >>>>> +#define PINMUX_GPIO161__FUNC_KPCOL2 (MTK_PIN_NO(161) | 5)
> > >>>>> +#define PINMUX_GPIO161__FUNC_PTA_RXD (MTK_PIN_NO(161) | 6)
> > >>>>> +#define PINMUX_GPIO161__FUNC_DBG_MON_B19 (MTK_PIN_NO(161) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
> > >>>>> +#define PINMUX_GPIO162__FUNC_SPI1_A_CSB (MTK_PIN_NO(162) | 1)
> > >>>>> +#define PINMUX_GPIO162__FUNC_SCP_SPI1_CS (MTK_PIN_NO(162) | 2)
> > >>>>> +#define PINMUX_GPIO162__FUNC_USB_DRVVBUS (MTK_PIN_NO(162) | 3)
> > >>>>> +#define PINMUX_GPIO162__FUNC_ANT_SEL5 (MTK_PIN_NO(162) | 4)
> > >>>>> +#define PINMUX_GPIO162__FUNC_KPROW2 (MTK_PIN_NO(162) | 5)
> > >>>>> +#define PINMUX_GPIO162__FUNC_PTA_TXD (MTK_PIN_NO(162) | 6)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
> > >>>>> +#define PINMUX_GPIO163__FUNC_SPI1_A_MO (MTK_PIN_NO(163) | 1)
> > >>>>> +#define PINMUX_GPIO163__FUNC_SCP_SPI1_MO (MTK_PIN_NO(163) | 2)
> > >>>>> +#define PINMUX_GPIO163__FUNC_SDA1 (MTK_PIN_NO(163) | 3)
> > >>>>> +#define PINMUX_GPIO163__FUNC_ANT_SEL4 (MTK_PIN_NO(163) | 4)
> > >>>>> +#define PINMUX_GPIO163__FUNC_CMMCLK2 (MTK_PIN_NO(163) | 5)
> > >>>>> +#define PINMUX_GPIO163__FUNC_DMIC_CLK (MTK_PIN_NO(163) | 6)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
> > >>>>> +#define PINMUX_GPIO164__FUNC_SPI1_A_CLK (MTK_PIN_NO(164) | 1)
> > >>>>> +#define PINMUX_GPIO164__FUNC_SCP_SPI1_CK (MTK_PIN_NO(164) | 2)
> > >>>>> +#define PINMUX_GPIO164__FUNC_SCL1 (MTK_PIN_NO(164) | 3)
> > >>>>> +#define PINMUX_GPIO164__FUNC_ANT_SEL3 (MTK_PIN_NO(164) | 4)
> > >>>>> +#define PINMUX_GPIO164__FUNC_CMMCLK3 (MTK_PIN_NO(164) | 5)
> > >>>>> +#define PINMUX_GPIO164__FUNC_DMIC_DAT (MTK_PIN_NO(164) | 6)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
> > >>>>> +#define PINMUX_GPIO165__FUNC_PWM_B (MTK_PIN_NO(165) | 1)
> > >>>>> +#define PINMUX_GPIO165__FUNC_CMMCLK2 (MTK_PIN_NO(165) | 2)
> > >>>>> +#define PINMUX_GPIO165__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(165) | 3)
> > >>>>> +#define PINMUX_GPIO165__FUNC_TDM_MCK_2ND (MTK_PIN_NO(165) | 6)
> > >>>>> +#define PINMUX_GPIO165__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(165) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
> > >>>>> +#define PINMUX_GPIO166__FUNC_ANT_SEL6 (MTK_PIN_NO(166) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
> > >>>>> +#define PINMUX_GPIO167__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(167) | 1)
> > >>>>> +#define PINMUX_GPIO167__FUNC_SPM_BSI_EN (MTK_PIN_NO(167) | 2)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
> > >>>>> +#define PINMUX_GPIO168__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(168) | 1)
> > >>>>> +#define PINMUX_GPIO168__FUNC_SPM_BSI_CK (MTK_PIN_NO(168) | 2)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
> > >>>>> +#define PINMUX_GPIO169__FUNC_PWM_C (MTK_PIN_NO(169) | 1)
> > >>>>> +#define PINMUX_GPIO169__FUNC_CMMCLK3 (MTK_PIN_NO(169) | 2)
> > >>>>> +#define PINMUX_GPIO169__FUNC_CMVREF1 (MTK_PIN_NO(169) | 3)
> > >>>>> +#define PINMUX_GPIO169__FUNC_ANT_SEL7 (MTK_PIN_NO(169) | 4)
> > >>>>> +#define PINMUX_GPIO169__FUNC_AGPS_SYNC (MTK_PIN_NO(169) | 5)
> > >>>>> +#define PINMUX_GPIO169__FUNC_TDM_BCK_2ND (MTK_PIN_NO(169) | 6)
> > >>>>> +#define PINMUX_GPIO169__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(169) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
> > >>>>> +#define PINMUX_GPIO170__FUNC_I2S1_BCK (MTK_PIN_NO(170) | 1)
> > >>>>> +#define PINMUX_GPIO170__FUNC_I2S3_BCK (MTK_PIN_NO(170) | 2)
> > >>>>> +#define PINMUX_GPIO170__FUNC_SCL7 (MTK_PIN_NO(170) | 3)
> > >>>>> +#define PINMUX_GPIO170__FUNC_I2S5_BCK (MTK_PIN_NO(170) | 4)
> > >>>>> +#define PINMUX_GPIO170__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(170) | 5)
> > >>>>> +#define PINMUX_GPIO170__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(170) | 6)
> > >>>>> +#define PINMUX_GPIO170__FUNC_ANT_SEL3 (MTK_PIN_NO(170) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
> > >>>>> +#define PINMUX_GPIO171__FUNC_I2S1_LRCK (MTK_PIN_NO(171) | 1)
> > >>>>> +#define PINMUX_GPIO171__FUNC_I2S3_LRCK (MTK_PIN_NO(171) | 2)
> > >>>>> +#define PINMUX_GPIO171__FUNC_SDA7 (MTK_PIN_NO(171) | 3)
> > >>>>> +#define PINMUX_GPIO171__FUNC_I2S5_LRCK (MTK_PIN_NO(171) | 4)
> > >>>>> +#define PINMUX_GPIO171__FUNC_URXD1 (MTK_PIN_NO(171) | 5)
> > >>>>> +#define PINMUX_GPIO171__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(171) | 6)
> > >>>>> +#define PINMUX_GPIO171__FUNC_ANT_SEL4 (MTK_PIN_NO(171) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
> > >>>>> +#define PINMUX_GPIO172__FUNC_I2S1_DO (MTK_PIN_NO(172) | 1)
> > >>>>> +#define PINMUX_GPIO172__FUNC_I2S3_DO (MTK_PIN_NO(172) | 2)
> > >>>>> +#define PINMUX_GPIO172__FUNC_SCL8 (MTK_PIN_NO(172) | 3)
> > >>>>> +#define PINMUX_GPIO172__FUNC_I2S5_DO (MTK_PIN_NO(172) | 4)
> > >>>>> +#define PINMUX_GPIO172__FUNC_UTXD1 (MTK_PIN_NO(172) | 5)
> > >>>>> +#define PINMUX_GPIO172__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(172) | 6)
> > >>>>> +#define PINMUX_GPIO172__FUNC_ANT_SEL5 (MTK_PIN_NO(172) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
> > >>>>> +#define PINMUX_GPIO173__FUNC_I2S1_MCK (MTK_PIN_NO(173) | 1)
> > >>>>> +#define PINMUX_GPIO173__FUNC_I2S3_MCK (MTK_PIN_NO(173) | 2)
> > >>>>> +#define PINMUX_GPIO173__FUNC_SDA8 (MTK_PIN_NO(173) | 3)
> > >>>>> +#define PINMUX_GPIO173__FUNC_I2S5_MCK (MTK_PIN_NO(173) | 4)
> > >>>>> +#define PINMUX_GPIO173__FUNC_UCTS0 (MTK_PIN_NO(173) | 5)
> > >>>>> +#define PINMUX_GPIO173__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(173) | 6)
> > >>>>> +#define PINMUX_GPIO173__FUNC_ANT_SEL6 (MTK_PIN_NO(173) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
> > >>>>> +#define PINMUX_GPIO174__FUNC_I2S2_DI (MTK_PIN_NO(174) | 1)
> > >>>>> +#define PINMUX_GPIO174__FUNC_I2S0_DI (MTK_PIN_NO(174) | 2)
> > >>>>> +#define PINMUX_GPIO174__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(174) | 3)
> > >>>>> +#define PINMUX_GPIO174__FUNC_I2S2_DI2 (MTK_PIN_NO(174) | 4)
> > >>>>> +#define PINMUX_GPIO174__FUNC_URTS0 (MTK_PIN_NO(174) | 5)
> > >>>>> +#define PINMUX_GPIO174__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(174) | 6)
> > >>>>> +#define PINMUX_GPIO174__FUNC_ANT_SEL7 (MTK_PIN_NO(174) | 7)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
> > >>>>> +#define PINMUX_GPIO175__FUNC_ANT_SEL7 (MTK_PIN_NO(175) | 1)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
> > >>>>> +
> > >>>>> +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
> > >>>>> +
> > >>>>> +#endif /* __MT8183-PINFUNC_H */
> > >>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > >>>>> new file mode 100644
> > >>>>> index 0000000..63db9cc
> > >>>>> --- /dev/null
> > >>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > >>>>> @@ -0,0 +1,408 @@
> > >>>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > >>>>> +/*
> > >>>>> + * Copyright (c) 2018 MediaTek Inc.
> > >>>>> + * Author: Ben Ho <ben.ho@mediatek.com>
> > >>>>> + * Erin Lo <erin.lo@mediatek.com>
> > >>>>> + */
> > >>>>> +
> > >>>>> +#include <dt-bindings/clock/mt8183-clk.h>
> > >>>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > >>>>> +#include <dt-bindings/interrupt-controller/irq.h>
> > >>>>> +#include "mt8183-pinfunc.h"
> > >>>>> +
> > >>>>> +/ {
> > >>>>> + compatible = "mediatek,mt8183";
> > >>>>> + interrupt-parent = <&sysirq>;
> > >>>>> + #address-cells = <2>;
> > >>>>> + #size-cells = <2>;
> > >>>>> +
> > >>>>> + cpus {
> > >>>>> + #address-cells = <1>;
> > >>>>> + #size-cells = <0>;
> > >>>>> +
> > >>>>> + cpu-map {
> > >>>>> + cluster0 {
> > >>>>> + core0 {
> > >>>>> + cpu = <&cpu0>;
> > >>>>> + };
> > >>>>> + core1 {
> > >>>>> + cpu = <&cpu1>;
> > >>>>> + };
> > >>>>> + core2 {
> > >>>>> + cpu = <&cpu2>;
> > >>>>> + };
> > >>>>> + core3 {
> > >>>>> + cpu = <&cpu3>;
> > >>>>> + };
> > >>>>> + };
> > >>>>> +
> > >>>>> + cluster1 {
> > >>>>> + core0 {
> > >>>>> + cpu = <&cpu4>;
> > >>>>> + };
> > >>>>> + core1 {
> > >>>>> + cpu = <&cpu5>;
> > >>>>> + };
> > >>>>> + core2 {
> > >>>>> + cpu = <&cpu6>;
> > >>>>> + };
> > >>>>> + core3 {
> > >>>>> + cpu = <&cpu7>;
> > >>>>> + };
> > >>>>> + };
> > >>>>> + };
> > >>>>> +
> > >>>>> + cpu0: cpu@0 {
> > >>>>> + device_type = "cpu";
> > >>>>> + compatible = "arm,cortex-a53";
> > >>>>> + reg = <0x000>;
> > >>>>> + enable-method = "psci";
> > >>>>> + };
> > >>>>> +
> > >>>>> + cpu1: cpu@1 {
> > >>>>> + device_type = "cpu";
> > >>>>> + compatible = "arm,cortex-a53";
> > >>>>> + reg = <0x001>;
> > >>>>> + enable-method = "psci";
> > >>>>> + };
> > >>>>> +
> > >>>>> + cpu2: cpu@2 {
> > >>>>> + device_type = "cpu";
> > >>>>> + compatible = "arm,cortex-a53";
> > >>>>> + reg = <0x002>;
> > >>>>> + enable-method = "psci";
> > >>>>> + };
> > >>>>> +
> > >>>>> + cpu3: cpu@3 {
> > >>>>> + device_type = "cpu";
> > >>>>> + compatible = "arm,cortex-a53";
> > >>>>> + reg = <0x003>;
> > >>>>> + enable-method = "psci";
> > >>>>> + };
> > >>>>> +
> > >>>>> + cpu4: cpu@100 {
> > >>>>> + device_type = "cpu";
> > >>>>> + compatible = "arm,cortex-a73";
> > >>>>> + reg = <0x100>;
> > >>>>> + enable-method = "psci";
> > >>>>> + };
> > >>>>> +
> > >>>>> + cpu5: cpu@101 {
> > >>>>> + device_type = "cpu";
> > >>>>> + compatible = "arm,cortex-a73";
> > >>>>> + reg = <0x101>;
> > >>>>> + enable-method = "psci";
> > >>>>> + };
> > >>>>> +
> > >>>>> + cpu6: cpu@102 {
> > >>>>> + device_type = "cpu";
> > >>>>> + compatible = "arm,cortex-a73";
> > >>>>> + reg = <0x102>;
> > >>>>> + enable-method = "psci";
> > >>>>> + };
> > >>>>> +
> > >>>>> + cpu7: cpu@103 {
> > >>>>> + device_type = "cpu";
> > >>>>> + compatible = "arm,cortex-a73";
> > >>>>> + reg = <0x103>;
> > >>>>> + enable-method = "psci";
> > >>>>> + };
> > >>>>> + };
> > >>>>> +
> > >>>>> + pmu-a53 {
> > >>>>> + compatible = "arm,cortex-a53-pmu";
> > >>>>> + interrupt-parent = <&gic>;
> > >>>>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + pmu-a73 {
> > >>>>> + compatible = "arm,cortex-a73-pmu";
> > >>>>> + interrupt-parent = <&gic>;
> > >>>>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + psci {
> > >>>>> + compatible = "arm,psci-1.0";
> > >>>>> + method = "smc";
> > >>>>> + };
> > >>>>> +
> > >>>>> + clk26m: oscillator {
> > >>>>> + compatible = "fixed-clock";
> > >>>>> + #clock-cells = <0>;
> > >>>>> + clock-frequency = <26000000>;
> > >>>>> + clock-output-names = "clk26m";
> > >>>>> + };
> > >>>>> +
> > >>>>> + timer {
> > >>>>> + compatible = "arm,armv8-timer";
> > >>>>> + interrupt-parent = <&gic>;
> > >>>>> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
> > >>>>> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
> > >>>>> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
> > >>>>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + gic: interrupt-controller@c000000 {
> > >>>>> + compatible = "arm,gic-v3";
> > >>>>> + #interrupt-cells = <4>;
> > >>>>> + interrupt-parent = <&gic>;
> > >>>>> + interrupt-controller;
> > >>>>> + reg = <0 0x0c000000 0 0x40000>, /* GICD */
> > >>>>> + <0 0x0c100000 0 0x200000>, /* GICR */
> > >>>>> + <0 0x0c400000 0 0x2000>, /* GICC */
> > >>>>> + <0 0x0c410000 0 0x1000>, /* GICH */
> > >>>>> + <0 0x0c420000 0 0x2000>; /* GICV */
> > >>>>> +
> > >>>>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> > >>>>> + ppi-partitions {
> > >>>>> + ppi_cluster0: interrupt-partition-0 {
> > >>>>> + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
> > >>>>> + };
> > >>>>> + ppi_cluster1: interrupt-partition-1 {
> > >>>>> + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
> > >>>>> + };
> > >>>>> + };
> > >>>>> + };
> > >>>>> +
> > >>>>> + mcucfg: syscon@c530000 {
> > >>>>> + compatible = "mediatek,mt8183-mcucfg", "syscon";
> > >>>>> + reg = <0 0x0c530000 0 0x1000>;
> > >>>>> + #clock-cells = <1>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + sysirq: intpol-controller@c530a80 {
> > >>>>> + compatible = "mediatek,mt8183-sysirq",
> > >>>>> + "mediatek,mt6577-sysirq";
> > >>>>> + interrupt-controller;
> > >>>>> + #interrupt-cells = <4>;
> > >>>>> + interrupt-parent = <&gic>;
> > >>>>> + reg = <0 0x0c530a80 0 0x50>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + topckgen: syscon@10000000 {
> > >>>>> + compatible = "mediatek,mt8183-topckgen", "syscon";
> > >>>>> + reg = <0 0x10000000 0 0x1000>;
> > >>>>> + #clock-cells = <1>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + infracfg: syscon@10001000 {
> > >>>>> + compatible = "mediatek,mt8183-infracfg", "syscon";
> > >>>>> + reg = <0 0x10001000 0 0x1000>;
> > >>>>> + #clock-cells = <1>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + pio: pinctrl@1000b000 {
> > >>>>> + compatible = "mediatek,mt8183-pinctrl";
> > >>>>> + reg = <0 0x10005000 0 0x1000>,
> > >>>>> + <0 0x11f20000 0 0x1000>,
> > >>>>> + <0 0x11e80000 0 0x1000>,
> > >>>>> + <0 0x11e70000 0 0x1000>,
> > >>>>> + <0 0x11e90000 0 0x1000>,
> > >>>>> + <0 0x11d30000 0 0x1000>,
> > >>>>> + <0 0x11d20000 0 0x1000>,
> > >>>>> + <0 0x11c50000 0 0x1000>,
> > >>>>> + <0 0x11f30000 0 0x1000>,
> > >>>>> + <0 0x1000b000 0 0x1000>;
> > >>>>> + reg-names = "iocfg0", "iocfg1", "iocfg2",
> > >>>>> + "iocfg3", "iocfg4", "iocfg5",
> > >>>>> + "iocfg6", "iocfg7", "iocfg8",
> > >>>>> + "eint";
> > >>>>> + gpio-controller;
> > >>>>> + #gpio-cells = <2>;
> > >>>>> + gpio-ranges = <&pio 0 0 192>;
> > >>>>> + interrupt-controller;
> > >>>>> + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>;
> > >>>>> + interrupt-parent = <&gic>;
> > >>>>> + #interrupt-cells = <4>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + apmixedsys: syscon@1000c000 {
> > >>>>> + compatible = "mediatek,mt8183-apmixedsys", "syscon";
> > >>>>> + reg = <0 0x1000c000 0 0x1000>;
> > >>>>> + #clock-cells = <1>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + pwrap: pwrap@1000d000 {
> > >>>>> + compatible = "mediatek,mt8183-pwrap";
> > >>>>> + reg = <0 0x1000d000 0 0x1000>;
> > >>>>> + reg-names = "pwrap";
> > >>>>> + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 0>;
> > >>>>> + clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
> > >>>>> + <&infracfg CLK_INFRA_PMIC_AP>;
> > >>>>> + clock-names = "spi", "wrap";
> > >>>>> + };
> > >>>>> +
> > >>>>> + uart0: serial@11002000 {
> > >>>>> + compatible = "mediatek,mt8183-uart",
> > >>>>> + "mediatek,mt6577-uart";
> > >>>>> + reg = <0 0x11002000 0 0x1000>;
> > >>>>> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW 0>;
> > >>>>> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
> > >>>>> + clock-names = "baud", "bus";
> > >>>>> + status = "disabled";
> > >>>>> + };
> > >>>>> +
> > >>>>> + uart1: serial@11003000 {
> > >>>>> + compatible = "mediatek,mt8183-uart",
> > >>>>> + "mediatek,mt6577-uart";
> > >>>>> + reg = <0 0x11003000 0 0x1000>;
> > >>>>> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW 0>;
> > >>>>> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
> > >>>>> + clock-names = "baud", "bus";
> > >>>>> + status = "disabled";
> > >>>>> + };
> > >>>>> +
> > >>>>> + uart2: serial@11004000 {
> > >>>>> + compatible = "mediatek,mt8183-uart",
> > >>>>> + "mediatek,mt6577-uart";
> > >>>>> + reg = <0 0x11004000 0 0x1000>;
> > >>>>> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW 0>;
> > >>>>> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
> > >>>>> + clock-names = "baud", "bus";
> > >>>>> + status = "disabled";
> > >>>>> + };
> > >>>>> +
> > >>>>> + spi0: spi@1100a000 {
> > >>>>> + compatible = "mediatek,mt8183-spi";
> > >>>>> + #address-cells = <1>;
> > >>>>> + #size-cells = <0>;
> > >>>>> + reg = <0 0x1100a000 0 0x1000>;
> > >>>>> + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW 0>;
> > >>>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> > >>>>> + <&topckgen CLK_TOP_MUX_SPI>,
> > >>>>> + <&infracfg CLK_INFRA_SPI0>;
> > >>>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> > >>>>> + status = "disabled";
> > >>>>> + };
> > >>>>> +
> > >>>>> + spi1: spi@11010000 {
> > >>>>> + compatible = "mediatek,mt8183-spi";
> > >>>>> + #address-cells = <1>;
> > >>>>> + #size-cells = <0>;
> > >>>>> + reg = <0 0x11010000 0 0x1000>;
> > >>>>> + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW 0>;
> > >>>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> > >>>>> + <&topckgen CLK_TOP_MUX_SPI>,
> > >>>>> + <&infracfg CLK_INFRA_SPI1>;
> > >>>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> > >>>>> + status = "disabled";
> > >>>>> + };
> > >>>>> +
> > >>>>> + spi2: spi@11012000 {
> > >>>>> + compatible = "mediatek,mt8183-spi";
> > >>>>> + #address-cells = <1>;
> > >>>>> + #size-cells = <0>;
> > >>>>> + reg = <0 0x11012000 0 0x1000>;
> > >>>>> + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW 0>;
> > >>>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> > >>>>> + <&topckgen CLK_TOP_MUX_SPI>,
> > >>>>> + <&infracfg CLK_INFRA_SPI2>;
> > >>>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> > >>>>> + status = "disabled";
> > >>>>> + };
> > >>>>> +
> > >>>>> + spi3: spi@11013000 {
> > >>>>> + compatible = "mediatek,mt8183-spi";
> > >>>>> + #address-cells = <1>;
> > >>>>> + #size-cells = <0>;
> > >>>>> + reg = <0 0x11013000 0 0x1000>;
> > >>>>> + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW 0>;
> > >>>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> > >>>>> + <&topckgen CLK_TOP_MUX_SPI>,
> > >>>>> + <&infracfg CLK_INFRA_SPI3>;
> > >>>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> > >>>>> + status = "disabled";
> > >>>>> + };
> > >>>>> +
> > >>>>> + spi4: spi@11018000 {
> > >>>>> + compatible = "mediatek,mt8183-spi";
> > >>>>> + #address-cells = <1>;
> > >>>>> + #size-cells = <0>;
> > >>>>> + reg = <0 0x11018000 0 0x1000>;
> > >>>>> + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW 0>;
> > >>>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> > >>>>> + <&topckgen CLK_TOP_MUX_SPI>,
> > >>>>> + <&infracfg CLK_INFRA_SPI4>;
> > >>>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> > >>>>> + status = "disabled";
> > >>>>> + };
> > >>>>> +
> > >>>>> + spi5: spi@11019000 {
> > >>>>> + compatible = "mediatek,mt8183-spi";
> > >>>>> + #address-cells = <1>;
> > >>>>> + #size-cells = <0>;
> > >>>>> + reg = <0 0x11019000 0 0x1000>;
> > >>>>> + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW 0>;
> > >>>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> > >>>>> + <&topckgen CLK_TOP_MUX_SPI>,
> > >>>>> + <&infracfg CLK_INFRA_SPI5>;
> > >>>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> > >>>>> + status = "disabled";
> > >>>>> + };
> > >>>>> +
> > >>>>> + audiosys: syscon@11220000 {
> > >>>>> + compatible = "mediatek,mt8183-audiosys", "syscon";
> > >>>>> + reg = <0 0x11220000 0 0x1000>;
> > >>>>> + #clock-cells = <1>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + mfgcfg: syscon@13000000 {
> > >>>>> + compatible = "mediatek,mt8183-mfgcfg", "syscon";
> > >>>>> + reg = <0 0x13000000 0 0x1000>;
> > >>>>> + #clock-cells = <1>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + mmsys: syscon@14000000 {
> > >>>>> + compatible = "mediatek,mt8183-mmsys", "syscon";
> > >>>>> + reg = <0 0x14000000 0 0x1000>;
> > >>>>> + #clock-cells = <1>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + imgsys: syscon@15020000 {
> > >>>>> + compatible = "mediatek,mt8183-imgsys", "syscon";
> > >>>>> + reg = <0 0x15020000 0 0x1000>;
> > >>>>> + #clock-cells = <1>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + vdecsys: syscon@16000000 {
> > >>>>> + compatible = "mediatek,mt8183-vdecsys", "syscon";
> > >>>>> + reg = <0 0x16000000 0 0x1000>;
> > >>>>> + #clock-cells = <1>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + vencsys: syscon@17000000 {
> > >>>>> + compatible = "mediatek,mt8183-vencsys", "syscon";
> > >>>>> + reg = <0 0x17000000 0 0x1000>;
> > >>>>> + #clock-cells = <1>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + ipu_conn: syscon@19000000 {
> > >>>>> + compatible = "mediatek,mt8183-ipu_conn", "syscon";
> > >>>>> + reg = <0 0x19000000 0 0x1000>;
> > >>>>> + #clock-cells = <1>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + ipu_adl: syscon@19010000 {
> > >>>>> + compatible = "mediatek,mt8183-ipu_adl", "syscon";
> > >>>>> + reg = <0 0x19010000 0 0x1000>;
> > >>>>> + #clock-cells = <1>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + ipu_core0: syscon@19180000 {
> > >>>>> + compatible = "mediatek,mt8183-ipu_core0", "syscon";
> > >>>>> + reg = <0 0x19180000 0 0x1000>;
> > >>>>> + #clock-cells = <1>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + ipu_core1: syscon@19280000 {
> > >>>>> + compatible = "mediatek,mt8183-ipu_core1", "syscon";
> > >>>>> + reg = <0 0x19280000 0 0x1000>;
> > >>>>> + #clock-cells = <1>;
> > >>>>> + };
> > >>>>> +
> > >>>>> + camsys: syscon@1a000000 {
> > >>>>> + compatible = "mediatek,mt8183-camsys", "syscon";
> > >>>>> + reg = <0 0x1a000000 0 0x1000>;
> > >>>>> + #clock-cells = <1>;
> > >>>>> + };
> > >>>>> +};
> > >>>>>
> > >>>>
> > >>>> _______________________________________________
> > >>>> Linux-mediatek mailing list
> > >>>> Linux-mediatek@lists.infradead.org
> > >>>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
> > >>>
> > >>>
> > >>
> > >> _______________________________________________
> > >> Linux-mediatek mailing list
> > >> Linux-mediatek@lists.infradead.org
> > >> http://lists.infradead.org/mailman/listinfo/linux-mediatek
> > >
> > >
>
^ permalink raw reply
* Re: [PATCH v6 6/6] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile
From: Erin Lo @ 2019-02-14 10:14 UTC (permalink / raw)
To: Matthias Brugger
Cc: Mark Rutland, Ben Ho, mars.cheng, Mengqi Zhang, linux-clk,
Hsin-Hsiung Wang, Weiyi Lu, Marc Zyngier, linux-serial,
yingjoe.chen, devicetree, Jason Cooper, Seiya Wang, Rob Herring,
linux-mediatek, Thomas Gleixner, eddie.huang, linux-arm-kernel,
srv_heupstream, Greg Kroah-Hartman, Stephen Boyd
In-Reply-To: <e750c805-d744-fec3-a6cb-5ef1a2348cf4@gmail.com>
On Thu, 2019-02-14 at 10:01 +0100, Matthias Brugger wrote:
>
> On 14/02/2019 06:27, Erin Lo wrote:
> > On Wed, 2019-02-13 at 15:54 +0100, Matthias Brugger wrote:
> >>
> >> On 13/02/2019 10:03, Erin Lo wrote:
> >>> On Thu, 2019-02-07 at 16:30 +0100, Matthias Brugger wrote:
> >>>>
> >>>> On 24/01/2019 09:07, Erin Lo wrote:
> >>>>> From: Ben Ho <Ben.Ho@mediatek.com>
> >>>>>
> >>>>> Add basic chip support for Mediatek 8183, include
> >>>>> pinctrl file, uart node with correct uart clocks, pwrap device
> >>>>>
> >>>>> Add clock controller nodes, include topckgen, infracfg,
> >>>>> apmixedsys and subsystem.
> >>>>>
> >>>>> Signed-off-by: Ben Ho <Ben.Ho@mediatek.com>
> >>>>> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> >>>>> Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
> >>>>> Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
> >>>>> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> >>>>> Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
> >>>>> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> >>>>> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
> >>>>> ---
> >>>>> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> >>>>> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 136 +++
> >>>>> arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h | 1120 +++++++++++++++++++++++++
> >>>>
> >>>> Would you mind to make the pinfunc.h a seperate patch and adding the pinctrl
> >>>> maintainers to the list.
> >>>>
> >>>> Regards,
> >>>> Matthias
> >>>>
> >>>
> >>> OK! I will take pinfunc.h out of this series.
> >>
> >> My take would be to somehow change this series in something like.
> >> One patch which adds basic support for the SoC without any dependencies on other
> >> series.
> >> Every node that has a dependency on a different series should go in a separate
> >> patch. In this case IMHO pinfunc.h can got with the dts node in one patch.
> >>
> >> Regards,
> >> Matthias
> >>
> >
> > I will separate this patch into 3 patches : basic support for the SoC,
> > mt8183-pinfunc.h, and spi node.
> >
> > Is that OK?
> > Is it ok, if pinctrl@1000b000 is included in basic node?
> >
>
> Why do you want to do that? Without the pinfunc.h I can't take it independently,
> right?
>
> Regards,
> Matthias
spi node need to use pio in mt8183-evb.dts, unless I don't submit spi
relative.
>
> > Best Regards.
> > Erin
> >
> >>>
> >>> Best Regards,
> >>> Erin
> >>>
> >>>>> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 408 +++++++++
> >>>>> 4 files changed, 1665 insertions(+)
> >>>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> >>>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
> >>>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >>>>>
> >>>>> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> >>>>> index e8f952f..458bbc4 100644
> >>>>> --- a/arch/arm64/boot/dts/mediatek/Makefile
> >>>>> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> >>>>> @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
> >>>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
> >>>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
> >>>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> >>>>> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
> >>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> >>>>> new file mode 100644
> >>>>> index 0000000..b12c6ea
> >>>>> --- /dev/null
> >>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> >>>>> @@ -0,0 +1,136 @@
> >>>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >>>>> +/*
> >>>>> + * Copyright (c) 2018 MediaTek Inc.
> >>>>> + * Author: Ben Ho <ben.ho@mediatek.com>
> >>>>> + * Erin Lo <erin.lo@mediatek.com>
> >>>>> + */
> >>>>> +
> >>>>> +/dts-v1/;
> >>>>> +#include "mt8183.dtsi"
> >>>>> +
> >>>>> +/ {
> >>>>> + model = "MediaTek MT8183 evaluation board";
> >>>>> + compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
> >>>>> +
> >>>>> + aliases {
> >>>>> + serial0 = &uart0;
> >>>>> + };
> >>>>> +
> >>>>> + memory@40000000 {
> >>>>> + device_type = "memory";
> >>>>> + reg = <0 0x40000000 0 0x80000000>;
> >>>>> + };
> >>>>> +
> >>>>> + chosen {
> >>>>> + stdout-path = "serial0:921600n8";
> >>>>> + };
> >>>>> +};
> >>>>> +
> >>>>> +&pio {
> >>>>> + spi_pins_0: spi0{
> >>>>> + pins_spi{
> >>>>> + pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
> >>>>> + <PINMUX_GPIO86__FUNC_SPI0_CSB>,
> >>>>> + <PINMUX_GPIO87__FUNC_SPI0_MO>,
> >>>>> + <PINMUX_GPIO88__FUNC_SPI0_CLK>;
> >>>>> + bias-disable;
> >>>>> + };
> >>>>> + };
> >>>>> +
> >>>>> + spi_pins_1: spi1{
> >>>>> + pins_spi{
> >>>>> + pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
> >>>>> + <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
> >>>>> + <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
> >>>>> + <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
> >>>>> + bias-disable;
> >>>>> + };
> >>>>> + };
> >>>>> +
> >>>>> + spi_pins_2: spi2{
> >>>>> + pins_spi{
> >>>>> + pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
> >>>>> + <PINMUX_GPIO1__FUNC_SPI2_MO>,
> >>>>> + <PINMUX_GPIO2__FUNC_SPI2_CLK>,
> >>>>> + <PINMUX_GPIO94__FUNC_SPI2_MI>;
> >>>>> + bias-disable;
> >>>>> + };
> >>>>> + };
> >>>>> +
> >>>>> + spi_pins_3: spi3{
> >>>>> + pins_spi{
> >>>>> + pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
> >>>>> + <PINMUX_GPIO22__FUNC_SPI3_CSB>,
> >>>>> + <PINMUX_GPIO23__FUNC_SPI3_MO>,
> >>>>> + <PINMUX_GPIO24__FUNC_SPI3_CLK>;
> >>>>> + bias-disable;
> >>>>> + };
> >>>>> + };
> >>>>> +
> >>>>> + spi_pins_4: spi4{
> >>>>> + pins_spi{
> >>>>> + pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
> >>>>> + <PINMUX_GPIO18__FUNC_SPI4_CSB>,
> >>>>> + <PINMUX_GPIO19__FUNC_SPI4_MO>,
> >>>>> + <PINMUX_GPIO20__FUNC_SPI4_CLK>;
> >>>>> + bias-disable;
> >>>>> + };
> >>>>> + };
> >>>>> +
> >>>>> + spi_pins_5: spi5{
> >>>>> + pins_spi{
> >>>>> + pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
> >>>>> + <PINMUX_GPIO14__FUNC_SPI5_CSB>,
> >>>>> + <PINMUX_GPIO15__FUNC_SPI5_MO>,
> >>>>> + <PINMUX_GPIO16__FUNC_SPI5_CLK>;
> >>>>> + bias-disable;
> >>>>> + };
> >>>>> + };
> >>>>> +};
> >>>>> +
> >>>>> +&spi0 {
> >>>>> + pinctrl-names = "default";
> >>>>> + pinctrl-0 = <&spi_pins_0>;
> >>>>> + mediatek,pad-select = <0>;
> >>>>> + status = "okay";
> >>>>> +};
> >>>>> +
> >>>>> +&spi1 {
> >>>>> + pinctrl-names = "default";
> >>>>> + pinctrl-0 = <&spi_pins_1>;
> >>>>> + mediatek,pad-select = <0>;
> >>>>> + status = "okay";
> >>>>> +};
> >>>>> +
> >>>>> +&spi2 {
> >>>>> + pinctrl-names = "default";
> >>>>> + pinctrl-0 = <&spi_pins_2>;
> >>>>> + mediatek,pad-select = <0>;
> >>>>> + status = "okay";
> >>>>> +};
> >>>>> +
> >>>>> +&spi3 {
> >>>>> + pinctrl-names = "default";
> >>>>> + pinctrl-0 = <&spi_pins_3>;
> >>>>> + mediatek,pad-select = <0>;
> >>>>> + status = "okay";
> >>>>> +};
> >>>>> +
> >>>>> +&spi4 {
> >>>>> + pinctrl-names = "default";
> >>>>> + pinctrl-0 = <&spi_pins_4>;
> >>>>> + mediatek,pad-select = <0>;
> >>>>> + status = "okay";
> >>>>> +};
> >>>>> +
> >>>>> +&spi5 {
> >>>>> + pinctrl-names = "default";
> >>>>> + pinctrl-0 = <&spi_pins_5>;
> >>>>> + mediatek,pad-select = <0>;
> >>>>> + status = "okay";
> >>>>> +
> >>>>> +};
> >>>>> +
> >>>>> +&uart0 {
> >>>>> + status = "okay";
> >>>>> +};
> >>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
> >>>>> new file mode 100644
> >>>>> index 0000000..768e41e
> >>>>> --- /dev/null
> >>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
> >>>>> @@ -0,0 +1,1120 @@
> >>>>> +// SPDX-License-Identifier: GPL-2.0
> >>>>> +/*
> >>>>> + * Copyright (C) 2018 MediaTek Inc.
> >>>>> + * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
> >>>>> + *
> >>>>> + */
> >>>>> +
> >>>>> +#ifndef __MT8183_PINFUNC_H
> >>>>> +#define __MT8183_PINFUNC_H
> >>>>> +
> >>>>> +#include <dt-bindings/pinctrl/mt65xx.h>
> >>>>> +
> >>>>> +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
> >>>>> +#define PINMUX_GPIO0__FUNC_MRG_SYNC (MTK_PIN_NO(0) | 1)
> >>>>> +#define PINMUX_GPIO0__FUNC_PCM0_SYNC (MTK_PIN_NO(0) | 2)
> >>>>> +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 3)
> >>>>> +#define PINMUX_GPIO0__FUNC_SRCLKENAI0 (MTK_PIN_NO(0) | 4)
> >>>>> +#define PINMUX_GPIO0__FUNC_SCP_SPI2_CS (MTK_PIN_NO(0) | 5)
> >>>>> +#define PINMUX_GPIO0__FUNC_I2S3_MCK (MTK_PIN_NO(0) | 6)
> >>>>> +#define PINMUX_GPIO0__FUNC_SPI2_CSB (MTK_PIN_NO(0) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
> >>>>> +#define PINMUX_GPIO1__FUNC_MRG_CLK (MTK_PIN_NO(1) | 1)
> >>>>> +#define PINMUX_GPIO1__FUNC_PCM0_CLK (MTK_PIN_NO(1) | 2)
> >>>>> +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 3)
> >>>>> +#define PINMUX_GPIO1__FUNC_CLKM3 (MTK_PIN_NO(1) | 4)
> >>>>> +#define PINMUX_GPIO1__FUNC_SCP_SPI2_MO (MTK_PIN_NO(1) | 5)
> >>>>> +#define PINMUX_GPIO1__FUNC_I2S3_BCK (MTK_PIN_NO(1) | 6)
> >>>>> +#define PINMUX_GPIO1__FUNC_SPI2_MO (MTK_PIN_NO(1) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
> >>>>> +#define PINMUX_GPIO2__FUNC_MRG_DO (MTK_PIN_NO(2) | 1)
> >>>>> +#define PINMUX_GPIO2__FUNC_PCM0_DO (MTK_PIN_NO(2) | 2)
> >>>>> +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 3)
> >>>>> +#define PINMUX_GPIO2__FUNC_SCL6 (MTK_PIN_NO(2) | 4)
> >>>>> +#define PINMUX_GPIO2__FUNC_SCP_SPI2_CK (MTK_PIN_NO(2) | 5)
> >>>>> +#define PINMUX_GPIO2__FUNC_I2S3_LRCK (MTK_PIN_NO(2) | 6)
> >>>>> +#define PINMUX_GPIO2__FUNC_SPI2_CLK (MTK_PIN_NO(2) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
> >>>>> +#define PINMUX_GPIO3__FUNC_MRG_DI (MTK_PIN_NO(3) | 1)
> >>>>> +#define PINMUX_GPIO3__FUNC_PCM0_DI (MTK_PIN_NO(3) | 2)
> >>>>> +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 3)
> >>>>> +#define PINMUX_GPIO3__FUNC_SDA6 (MTK_PIN_NO(3) | 4)
> >>>>> +#define PINMUX_GPIO3__FUNC_TDM_MCK (MTK_PIN_NO(3) | 5)
> >>>>> +#define PINMUX_GPIO3__FUNC_I2S3_DO (MTK_PIN_NO(3) | 6)
> >>>>> +#define PINMUX_GPIO3__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(3) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
> >>>>> +#define PINMUX_GPIO4__FUNC_PWM_B (MTK_PIN_NO(4) | 1)
> >>>>> +#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2)
> >>>>> +#define PINMUX_GPIO4__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(4) | 3)
> >>>>> +#define PINMUX_GPIO4__FUNC_MD_URXD1 (MTK_PIN_NO(4) | 4)
> >>>>> +#define PINMUX_GPIO4__FUNC_TDM_BCK (MTK_PIN_NO(4) | 5)
> >>>>> +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6)
> >>>>> +#define PINMUX_GPIO4__FUNC_DAP_MD32_SWD (MTK_PIN_NO(4) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
> >>>>> +#define PINMUX_GPIO5__FUNC_PWM_C (MTK_PIN_NO(5) | 1)
> >>>>> +#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2)
> >>>>> +#define PINMUX_GPIO5__FUNC_SSPM_URXD_AO (MTK_PIN_NO(5) | 3)
> >>>>> +#define PINMUX_GPIO5__FUNC_MD_UTXD1 (MTK_PIN_NO(5) | 4)
> >>>>> +#define PINMUX_GPIO5__FUNC_TDM_LRCK (MTK_PIN_NO(5) | 5)
> >>>>> +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6)
> >>>>> +#define PINMUX_GPIO5__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(5) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
> >>>>> +#define PINMUX_GPIO6__FUNC_PWM_A (MTK_PIN_NO(6) | 1)
> >>>>> +#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2)
> >>>>> +#define PINMUX_GPIO6__FUNC_IDDIG (MTK_PIN_NO(6) | 3)
> >>>>> +#define PINMUX_GPIO6__FUNC_MD_URXD0 (MTK_PIN_NO(6) | 4)
> >>>>> +#define PINMUX_GPIO6__FUNC_TDM_DATA0 (MTK_PIN_NO(6) | 5)
> >>>>> +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6)
> >>>>> +#define PINMUX_GPIO6__FUNC_CMFLASH (MTK_PIN_NO(6) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
> >>>>> +#define PINMUX_GPIO7__FUNC_SPI1_B_MI (MTK_PIN_NO(7) | 1)
> >>>>> +#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2)
> >>>>> +#define PINMUX_GPIO7__FUNC_USB_DRVVBUS (MTK_PIN_NO(7) | 3)
> >>>>> +#define PINMUX_GPIO7__FUNC_MD_UTXD0 (MTK_PIN_NO(7) | 4)
> >>>>> +#define PINMUX_GPIO7__FUNC_TDM_DATA1 (MTK_PIN_NO(7) | 5)
> >>>>> +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6)
> >>>>> +#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
> >>>>> +#define PINMUX_GPIO8__FUNC_SPI1_B_CSB (MTK_PIN_NO(8) | 1)
> >>>>> +#define PINMUX_GPIO8__FUNC_ANT_SEL3 (MTK_PIN_NO(8) | 2)
> >>>>> +#define PINMUX_GPIO8__FUNC_SCL7 (MTK_PIN_NO(8) | 3)
> >>>>> +#define PINMUX_GPIO8__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(8) | 4)
> >>>>> +#define PINMUX_GPIO8__FUNC_TDM_DATA2 (MTK_PIN_NO(8) | 5)
> >>>>> +#define PINMUX_GPIO8__FUNC_MD_INT0 (MTK_PIN_NO(8) | 6)
> >>>>> +#define PINMUX_GPIO8__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(8) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
> >>>>> +#define PINMUX_GPIO9__FUNC_SPI1_B_MO (MTK_PIN_NO(9) | 1)
> >>>>> +#define PINMUX_GPIO9__FUNC_ANT_SEL4 (MTK_PIN_NO(9) | 2)
> >>>>> +#define PINMUX_GPIO9__FUNC_CMMCLK2 (MTK_PIN_NO(9) | 3)
> >>>>> +#define PINMUX_GPIO9__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(9) | 4)
> >>>>> +#define PINMUX_GPIO9__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(9) | 5)
> >>>>> +#define PINMUX_GPIO9__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(9) | 6)
> >>>>> +#define PINMUX_GPIO9__FUNC_DBG_MON_B10 (MTK_PIN_NO(9) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
> >>>>> +#define PINMUX_GPIO10__FUNC_SPI1_B_CLK (MTK_PIN_NO(10) | 1)
> >>>>> +#define PINMUX_GPIO10__FUNC_ANT_SEL5 (MTK_PIN_NO(10) | 2)
> >>>>> +#define PINMUX_GPIO10__FUNC_CMMCLK3 (MTK_PIN_NO(10) | 3)
> >>>>> +#define PINMUX_GPIO10__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(10) | 4)
> >>>>> +#define PINMUX_GPIO10__FUNC_TDM_DATA3 (MTK_PIN_NO(10) | 5)
> >>>>> +#define PINMUX_GPIO10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 6)
> >>>>> +#define PINMUX_GPIO10__FUNC_DBG_MON_B11 (MTK_PIN_NO(10) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
> >>>>> +#define PINMUX_GPIO11__FUNC_TP_URXD1_AO (MTK_PIN_NO(11) | 1)
> >>>>> +#define PINMUX_GPIO11__FUNC_IDDIG (MTK_PIN_NO(11) | 2)
> >>>>> +#define PINMUX_GPIO11__FUNC_SCL6 (MTK_PIN_NO(11) | 3)
> >>>>> +#define PINMUX_GPIO11__FUNC_UCTS1 (MTK_PIN_NO(11) | 4)
> >>>>> +#define PINMUX_GPIO11__FUNC_UCTS0 (MTK_PIN_NO(11) | 5)
> >>>>> +#define PINMUX_GPIO11__FUNC_SRCLKENAI1 (MTK_PIN_NO(11) | 6)
> >>>>> +#define PINMUX_GPIO11__FUNC_I2S5_MCK (MTK_PIN_NO(11) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
> >>>>> +#define PINMUX_GPIO12__FUNC_TP_UTXD1_AO (MTK_PIN_NO(12) | 1)
> >>>>> +#define PINMUX_GPIO12__FUNC_USB_DRVVBUS (MTK_PIN_NO(12) | 2)
> >>>>> +#define PINMUX_GPIO12__FUNC_SDA6 (MTK_PIN_NO(12) | 3)
> >>>>> +#define PINMUX_GPIO12__FUNC_URTS1 (MTK_PIN_NO(12) | 4)
> >>>>> +#define PINMUX_GPIO12__FUNC_URTS0 (MTK_PIN_NO(12) | 5)
> >>>>> +#define PINMUX_GPIO12__FUNC_I2S2_DI2 (MTK_PIN_NO(12) | 6)
> >>>>> +#define PINMUX_GPIO12__FUNC_I2S5_BCK (MTK_PIN_NO(12) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
> >>>>> +#define PINMUX_GPIO13__FUNC_DBPI_D0 (MTK_PIN_NO(13) | 1)
> >>>>> +#define PINMUX_GPIO13__FUNC_SPI5_MI (MTK_PIN_NO(13) | 2)
> >>>>> +#define PINMUX_GPIO13__FUNC_PCM0_SYNC (MTK_PIN_NO(13) | 3)
> >>>>> +#define PINMUX_GPIO13__FUNC_MD_URXD0 (MTK_PIN_NO(13) | 4)
> >>>>> +#define PINMUX_GPIO13__FUNC_ANT_SEL3 (MTK_PIN_NO(13) | 5)
> >>>>> +#define PINMUX_GPIO13__FUNC_I2S0_MCK (MTK_PIN_NO(13) | 6)
> >>>>> +#define PINMUX_GPIO13__FUNC_DBG_MON_B15 (MTK_PIN_NO(13) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
> >>>>> +#define PINMUX_GPIO14__FUNC_DBPI_D1 (MTK_PIN_NO(14) | 1)
> >>>>> +#define PINMUX_GPIO14__FUNC_SPI5_CSB (MTK_PIN_NO(14) | 2)
> >>>>> +#define PINMUX_GPIO14__FUNC_PCM0_CLK (MTK_PIN_NO(14) | 3)
> >>>>> +#define PINMUX_GPIO14__FUNC_MD_UTXD0 (MTK_PIN_NO(14) | 4)
> >>>>> +#define PINMUX_GPIO14__FUNC_ANT_SEL4 (MTK_PIN_NO(14) | 5)
> >>>>> +#define PINMUX_GPIO14__FUNC_I2S0_BCK (MTK_PIN_NO(14) | 6)
> >>>>> +#define PINMUX_GPIO14__FUNC_DBG_MON_B16 (MTK_PIN_NO(14) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
> >>>>> +#define PINMUX_GPIO15__FUNC_DBPI_D2 (MTK_PIN_NO(15) | 1)
> >>>>> +#define PINMUX_GPIO15__FUNC_SPI5_MO (MTK_PIN_NO(15) | 2)
> >>>>> +#define PINMUX_GPIO15__FUNC_PCM0_DO (MTK_PIN_NO(15) | 3)
> >>>>> +#define PINMUX_GPIO15__FUNC_MD_URXD1 (MTK_PIN_NO(15) | 4)
> >>>>> +#define PINMUX_GPIO15__FUNC_ANT_SEL5 (MTK_PIN_NO(15) | 5)
> >>>>> +#define PINMUX_GPIO15__FUNC_I2S0_LRCK (MTK_PIN_NO(15) | 6)
> >>>>> +#define PINMUX_GPIO15__FUNC_DBG_MON_B17 (MTK_PIN_NO(15) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
> >>>>> +#define PINMUX_GPIO16__FUNC_DBPI_D3 (MTK_PIN_NO(16) | 1)
> >>>>> +#define PINMUX_GPIO16__FUNC_SPI5_CLK (MTK_PIN_NO(16) | 2)
> >>>>> +#define PINMUX_GPIO16__FUNC_PCM0_DI (MTK_PIN_NO(16) | 3)
> >>>>> +#define PINMUX_GPIO16__FUNC_MD_UTXD1 (MTK_PIN_NO(16) | 4)
> >>>>> +#define PINMUX_GPIO16__FUNC_ANT_SEL6 (MTK_PIN_NO(16) | 5)
> >>>>> +#define PINMUX_GPIO16__FUNC_I2S0_DI (MTK_PIN_NO(16) | 6)
> >>>>> +#define PINMUX_GPIO16__FUNC_DBG_MON_B23 (MTK_PIN_NO(16) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
> >>>>> +#define PINMUX_GPIO17__FUNC_DBPI_D4 (MTK_PIN_NO(17) | 1)
> >>>>> +#define PINMUX_GPIO17__FUNC_SPI4_MI (MTK_PIN_NO(17) | 2)
> >>>>> +#define PINMUX_GPIO17__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(17) | 3)
> >>>>> +#define PINMUX_GPIO17__FUNC_MD_INT0 (MTK_PIN_NO(17) | 4)
> >>>>> +#define PINMUX_GPIO17__FUNC_ANT_SEL7 (MTK_PIN_NO(17) | 5)
> >>>>> +#define PINMUX_GPIO17__FUNC_I2S3_MCK (MTK_PIN_NO(17) | 6)
> >>>>> +#define PINMUX_GPIO17__FUNC_DBG_MON_A1 (MTK_PIN_NO(17) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
> >>>>> +#define PINMUX_GPIO18__FUNC_DBPI_D5 (MTK_PIN_NO(18) | 1)
> >>>>> +#define PINMUX_GPIO18__FUNC_SPI4_CSB (MTK_PIN_NO(18) | 2)
> >>>>> +#define PINMUX_GPIO18__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(18) | 3)
> >>>>> +#define PINMUX_GPIO18__FUNC_MD_INT0 (MTK_PIN_NO(18) | 4)
> >>>>> +#define PINMUX_GPIO18__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(18) | 5)
> >>>>> +#define PINMUX_GPIO18__FUNC_I2S3_BCK (MTK_PIN_NO(18) | 6)
> >>>>> +#define PINMUX_GPIO18__FUNC_DBG_MON_A2 (MTK_PIN_NO(18) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
> >>>>> +#define PINMUX_GPIO19__FUNC_DBPI_D6 (MTK_PIN_NO(19) | 1)
> >>>>> +#define PINMUX_GPIO19__FUNC_SPI4_MO (MTK_PIN_NO(19) | 2)
> >>>>> +#define PINMUX_GPIO19__FUNC_CONN_MCU_TDO (MTK_PIN_NO(19) | 3)
> >>>>> +#define PINMUX_GPIO19__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(19) | 4)
> >>>>> +#define PINMUX_GPIO19__FUNC_URXD1 (MTK_PIN_NO(19) | 5)
> >>>>> +#define PINMUX_GPIO19__FUNC_I2S3_LRCK (MTK_PIN_NO(19) | 6)
> >>>>> +#define PINMUX_GPIO19__FUNC_DBG_MON_A3 (MTK_PIN_NO(19) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
> >>>>> +#define PINMUX_GPIO20__FUNC_DBPI_D7 (MTK_PIN_NO(20) | 1)
> >>>>> +#define PINMUX_GPIO20__FUNC_SPI4_CLK (MTK_PIN_NO(20) | 2)
> >>>>> +#define PINMUX_GPIO20__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(20) | 3)
> >>>>> +#define PINMUX_GPIO20__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(20) | 4)
> >>>>> +#define PINMUX_GPIO20__FUNC_UTXD1 (MTK_PIN_NO(20) | 5)
> >>>>> +#define PINMUX_GPIO20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 6)
> >>>>> +#define PINMUX_GPIO20__FUNC_DBG_MON_A19 (MTK_PIN_NO(20) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
> >>>>> +#define PINMUX_GPIO21__FUNC_DBPI_D8 (MTK_PIN_NO(21) | 1)
> >>>>> +#define PINMUX_GPIO21__FUNC_SPI3_MI (MTK_PIN_NO(21) | 2)
> >>>>> +#define PINMUX_GPIO21__FUNC_CONN_MCU_TMS (MTK_PIN_NO(21) | 3)
> >>>>> +#define PINMUX_GPIO21__FUNC_DAP_MD32_SWD (MTK_PIN_NO(21) | 4)
> >>>>> +#define PINMUX_GPIO21__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(21) | 5)
> >>>>> +#define PINMUX_GPIO21__FUNC_I2S2_MCK (MTK_PIN_NO(21) | 6)
> >>>>> +#define PINMUX_GPIO21__FUNC_DBG_MON_B5 (MTK_PIN_NO(21) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
> >>>>> +#define PINMUX_GPIO22__FUNC_DBPI_D9 (MTK_PIN_NO(22) | 1)
> >>>>> +#define PINMUX_GPIO22__FUNC_SPI3_CSB (MTK_PIN_NO(22) | 2)
> >>>>> +#define PINMUX_GPIO22__FUNC_CONN_MCU_TCK (MTK_PIN_NO(22) | 3)
> >>>>> +#define PINMUX_GPIO22__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(22) | 4)
> >>>>> +#define PINMUX_GPIO22__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(22) | 5)
> >>>>> +#define PINMUX_GPIO22__FUNC_I2S2_BCK (MTK_PIN_NO(22) | 6)
> >>>>> +#define PINMUX_GPIO22__FUNC_DBG_MON_B6 (MTK_PIN_NO(22) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
> >>>>> +#define PINMUX_GPIO23__FUNC_DBPI_D10 (MTK_PIN_NO(23) | 1)
> >>>>> +#define PINMUX_GPIO23__FUNC_SPI3_MO (MTK_PIN_NO(23) | 2)
> >>>>> +#define PINMUX_GPIO23__FUNC_CONN_MCU_TDI (MTK_PIN_NO(23) | 3)
> >>>>> +#define PINMUX_GPIO23__FUNC_UCTS1 (MTK_PIN_NO(23) | 4)
> >>>>> +#define PINMUX_GPIO23__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5)
> >>>>> +#define PINMUX_GPIO23__FUNC_I2S2_LRCK (MTK_PIN_NO(23) | 6)
> >>>>> +#define PINMUX_GPIO23__FUNC_DBG_MON_B7 (MTK_PIN_NO(23) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
> >>>>> +#define PINMUX_GPIO24__FUNC_DBPI_D11 (MTK_PIN_NO(24) | 1)
> >>>>> +#define PINMUX_GPIO24__FUNC_SPI3_CLK (MTK_PIN_NO(24) | 2)
> >>>>> +#define PINMUX_GPIO24__FUNC_SRCLKENAI0 (MTK_PIN_NO(24) | 3)
> >>>>> +#define PINMUX_GPIO24__FUNC_URTS1 (MTK_PIN_NO(24) | 4)
> >>>>> +#define PINMUX_GPIO24__FUNC_IO_JTAG_TCK (MTK_PIN_NO(24) | 5)
> >>>>> +#define PINMUX_GPIO24__FUNC_I2S2_DI (MTK_PIN_NO(24) | 6)
> >>>>> +#define PINMUX_GPIO24__FUNC_DBG_MON_B31 (MTK_PIN_NO(24) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
> >>>>> +#define PINMUX_GPIO25__FUNC_DBPI_HSYNC (MTK_PIN_NO(25) | 1)
> >>>>> +#define PINMUX_GPIO25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 2)
> >>>>> +#define PINMUX_GPIO25__FUNC_SCL6 (MTK_PIN_NO(25) | 3)
> >>>>> +#define PINMUX_GPIO25__FUNC_KPCOL2 (MTK_PIN_NO(25) | 4)
> >>>>> +#define PINMUX_GPIO25__FUNC_IO_JTAG_TMS (MTK_PIN_NO(25) | 5)
> >>>>> +#define PINMUX_GPIO25__FUNC_I2S1_MCK (MTK_PIN_NO(25) | 6)
> >>>>> +#define PINMUX_GPIO25__FUNC_DBG_MON_B0 (MTK_PIN_NO(25) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
> >>>>> +#define PINMUX_GPIO26__FUNC_DBPI_VSYNC (MTK_PIN_NO(26) | 1)
> >>>>> +#define PINMUX_GPIO26__FUNC_ANT_SEL1 (MTK_PIN_NO(26) | 2)
> >>>>> +#define PINMUX_GPIO26__FUNC_SDA6 (MTK_PIN_NO(26) | 3)
> >>>>> +#define PINMUX_GPIO26__FUNC_KPROW2 (MTK_PIN_NO(26) | 4)
> >>>>> +#define PINMUX_GPIO26__FUNC_IO_JTAG_TDI (MTK_PIN_NO(26) | 5)
> >>>>> +#define PINMUX_GPIO26__FUNC_I2S1_BCK (MTK_PIN_NO(26) | 6)
> >>>>> +#define PINMUX_GPIO26__FUNC_DBG_MON_B1 (MTK_PIN_NO(26) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
> >>>>> +#define PINMUX_GPIO27__FUNC_DBPI_DE (MTK_PIN_NO(27) | 1)
> >>>>> +#define PINMUX_GPIO27__FUNC_ANT_SEL2 (MTK_PIN_NO(27) | 2)
> >>>>> +#define PINMUX_GPIO27__FUNC_SCL7 (MTK_PIN_NO(27) | 3)
> >>>>> +#define PINMUX_GPIO27__FUNC_DMIC_CLK (MTK_PIN_NO(27) | 4)
> >>>>> +#define PINMUX_GPIO27__FUNC_IO_JTAG_TDO (MTK_PIN_NO(27) | 5)
> >>>>> +#define PINMUX_GPIO27__FUNC_I2S1_LRCK (MTK_PIN_NO(27) | 6)
> >>>>> +#define PINMUX_GPIO27__FUNC_DBG_MON_B9 (MTK_PIN_NO(27) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
> >>>>> +#define PINMUX_GPIO28__FUNC_DBPI_CK (MTK_PIN_NO(28) | 1)
> >>>>> +#define PINMUX_GPIO28__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(28) | 2)
> >>>>> +#define PINMUX_GPIO28__FUNC_SDA7 (MTK_PIN_NO(28) | 3)
> >>>>> +#define PINMUX_GPIO28__FUNC_DMIC_DAT (MTK_PIN_NO(28) | 4)
> >>>>> +#define PINMUX_GPIO28__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(28) | 5)
> >>>>> +#define PINMUX_GPIO28__FUNC_I2S1_DO (MTK_PIN_NO(28) | 6)
> >>>>> +#define PINMUX_GPIO28__FUNC_DBG_MON_B32 (MTK_PIN_NO(28) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
> >>>>> +#define PINMUX_GPIO29__FUNC_MSDC1_CLK (MTK_PIN_NO(29) | 1)
> >>>>> +#define PINMUX_GPIO29__FUNC_IO_JTAG_TCK (MTK_PIN_NO(29) | 2)
> >>>>> +#define PINMUX_GPIO29__FUNC_UDI_TCK (MTK_PIN_NO(29) | 3)
> >>>>> +#define PINMUX_GPIO29__FUNC_CONN_DSP_JCK (MTK_PIN_NO(29) | 4)
> >>>>> +#define PINMUX_GPIO29__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(29) | 5)
> >>>>> +#define PINMUX_GPIO29__FUNC_PCM1_CLK (MTK_PIN_NO(29) | 6)
> >>>>> +#define PINMUX_GPIO29__FUNC_DBG_MON_A6 (MTK_PIN_NO(29) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
> >>>>> +#define PINMUX_GPIO30__FUNC_MSDC1_DAT3 (MTK_PIN_NO(30) | 1)
> >>>>> +#define PINMUX_GPIO30__FUNC_DAP_MD32_SWD (MTK_PIN_NO(30) | 2)
> >>>>> +#define PINMUX_GPIO30__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 3)
> >>>>> +#define PINMUX_GPIO30__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(30) | 4)
> >>>>> +#define PINMUX_GPIO30__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(30) | 5)
> >>>>> +#define PINMUX_GPIO30__FUNC_PCM1_DI (MTK_PIN_NO(30) | 6)
> >>>>> +#define PINMUX_GPIO30__FUNC_DBG_MON_A7 (MTK_PIN_NO(30) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
> >>>>> +#define PINMUX_GPIO31__FUNC_MSDC1_CMD (MTK_PIN_NO(31) | 1)
> >>>>> +#define PINMUX_GPIO31__FUNC_IO_JTAG_TMS (MTK_PIN_NO(31) | 2)
> >>>>> +#define PINMUX_GPIO31__FUNC_UDI_TMS (MTK_PIN_NO(31) | 3)
> >>>>> +#define PINMUX_GPIO31__FUNC_CONN_DSP_JMS (MTK_PIN_NO(31) | 4)
> >>>>> +#define PINMUX_GPIO31__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(31) | 5)
> >>>>> +#define PINMUX_GPIO31__FUNC_PCM1_SYNC (MTK_PIN_NO(31) | 6)
> >>>>> +#define PINMUX_GPIO31__FUNC_DBG_MON_A8 (MTK_PIN_NO(31) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
> >>>>> +#define PINMUX_GPIO32__FUNC_MSDC1_DAT0 (MTK_PIN_NO(32) | 1)
> >>>>> +#define PINMUX_GPIO32__FUNC_IO_JTAG_TDI (MTK_PIN_NO(32) | 2)
> >>>>> +#define PINMUX_GPIO32__FUNC_UDI_TDI (MTK_PIN_NO(32) | 3)
> >>>>> +#define PINMUX_GPIO32__FUNC_CONN_DSP_JDI (MTK_PIN_NO(32) | 4)
> >>>>> +#define PINMUX_GPIO32__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(32) | 5)
> >>>>> +#define PINMUX_GPIO32__FUNC_PCM1_DO0 (MTK_PIN_NO(32) | 6)
> >>>>> +#define PINMUX_GPIO32__FUNC_DBG_MON_A9 (MTK_PIN_NO(32) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
> >>>>> +#define PINMUX_GPIO33__FUNC_MSDC1_DAT2 (MTK_PIN_NO(33) | 1)
> >>>>> +#define PINMUX_GPIO33__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(33) | 2)
> >>>>> +#define PINMUX_GPIO33__FUNC_UDI_NTRST (MTK_PIN_NO(33) | 3)
> >>>>> +#define PINMUX_GPIO33__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(33) | 4)
> >>>>> +#define PINMUX_GPIO33__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(33) | 5)
> >>>>> +#define PINMUX_GPIO33__FUNC_PCM1_DO2 (MTK_PIN_NO(33) | 6)
> >>>>> +#define PINMUX_GPIO33__FUNC_DBG_MON_A10 (MTK_PIN_NO(33) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
> >>>>> +#define PINMUX_GPIO34__FUNC_MSDC1_DAT1 (MTK_PIN_NO(34) | 1)
> >>>>> +#define PINMUX_GPIO34__FUNC_IO_JTAG_TDO (MTK_PIN_NO(34) | 2)
> >>>>> +#define PINMUX_GPIO34__FUNC_UDI_TDO (MTK_PIN_NO(34) | 3)
> >>>>> +#define PINMUX_GPIO34__FUNC_CONN_DSP_JDO (MTK_PIN_NO(34) | 4)
> >>>>> +#define PINMUX_GPIO34__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(34) | 5)
> >>>>> +#define PINMUX_GPIO34__FUNC_PCM1_DO1 (MTK_PIN_NO(34) | 6)
> >>>>> +#define PINMUX_GPIO34__FUNC_DBG_MON_A11 (MTK_PIN_NO(34) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
> >>>>> +#define PINMUX_GPIO35__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(35) | 1)
> >>>>> +#define PINMUX_GPIO35__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(35) | 2)
> >>>>> +#define PINMUX_GPIO35__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(35) | 3)
> >>>>> +#define PINMUX_GPIO35__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(35) | 5)
> >>>>> +#define PINMUX_GPIO35__FUNC_CONN_DSP_JMS (MTK_PIN_NO(35) | 6)
> >>>>> +#define PINMUX_GPIO35__FUNC_DBG_MON_A28 (MTK_PIN_NO(35) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
> >>>>> +#define PINMUX_GPIO36__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(36) | 1)
> >>>>> +#define PINMUX_GPIO36__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(36) | 2)
> >>>>> +#define PINMUX_GPIO36__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(36) | 3)
> >>>>> +#define PINMUX_GPIO36__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(36) | 4)
> >>>>> +#define PINMUX_GPIO36__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(36) | 5)
> >>>>> +#define PINMUX_GPIO36__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(36) | 6)
> >>>>> +#define PINMUX_GPIO36__FUNC_DBG_MON_A29 (MTK_PIN_NO(36) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
> >>>>> +#define PINMUX_GPIO37__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(37) | 1)
> >>>>> +#define PINMUX_GPIO37__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(37) | 2)
> >>>>> +#define PINMUX_GPIO37__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(37) | 3)
> >>>>> +#define PINMUX_GPIO37__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(37) | 5)
> >>>>> +#define PINMUX_GPIO37__FUNC_CONN_DSP_JDO (MTK_PIN_NO(37) | 6)
> >>>>> +#define PINMUX_GPIO37__FUNC_DBG_MON_A30 (MTK_PIN_NO(37) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
> >>>>> +#define PINMUX_GPIO38__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(38) | 1)
> >>>>> +#define PINMUX_GPIO38__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(38) | 3)
> >>>>> +#define PINMUX_GPIO38__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(38) | 4)
> >>>>> +#define PINMUX_GPIO38__FUNC_DBG_MON_A20 (MTK_PIN_NO(38) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
> >>>>> +#define PINMUX_GPIO39__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(39) | 1)
> >>>>> +#define PINMUX_GPIO39__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(39) | 2)
> >>>>> +#define PINMUX_GPIO39__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(39) | 3)
> >>>>> +#define PINMUX_GPIO39__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(39) | 5)
> >>>>> +#define PINMUX_GPIO39__FUNC_CONN_DSP_JCK (MTK_PIN_NO(39) | 6)
> >>>>> +#define PINMUX_GPIO39__FUNC_DBG_MON_A31 (MTK_PIN_NO(39) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
> >>>>> +#define PINMUX_GPIO40__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(40) | 1)
> >>>>> +#define PINMUX_GPIO40__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(40) | 2)
> >>>>> +#define PINMUX_GPIO40__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(40) | 3)
> >>>>> +#define PINMUX_GPIO40__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(40) | 5)
> >>>>> +#define PINMUX_GPIO40__FUNC_CONN_DSP_JDI (MTK_PIN_NO(40) | 6)
> >>>>> +#define PINMUX_GPIO40__FUNC_DBG_MON_A32 (MTK_PIN_NO(40) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
> >>>>> +#define PINMUX_GPIO41__FUNC_IDDIG (MTK_PIN_NO(41) | 1)
> >>>>> +#define PINMUX_GPIO41__FUNC_URXD1 (MTK_PIN_NO(41) | 2)
> >>>>> +#define PINMUX_GPIO41__FUNC_UCTS0 (MTK_PIN_NO(41) | 3)
> >>>>> +#define PINMUX_GPIO41__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(41) | 4)
> >>>>> +#define PINMUX_GPIO41__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 5)
> >>>>> +#define PINMUX_GPIO41__FUNC_DMIC_CLK (MTK_PIN_NO(41) | 6)
> >>>>> +
> >>>>> +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
> >>>>> +#define PINMUX_GPIO42__FUNC_USB_DRVVBUS (MTK_PIN_NO(42) | 1)
> >>>>> +#define PINMUX_GPIO42__FUNC_UTXD1 (MTK_PIN_NO(42) | 2)
> >>>>> +#define PINMUX_GPIO42__FUNC_URTS0 (MTK_PIN_NO(42) | 3)
> >>>>> +#define PINMUX_GPIO42__FUNC_SSPM_URXD_AO (MTK_PIN_NO(42) | 4)
> >>>>> +#define PINMUX_GPIO42__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(42) | 5)
> >>>>> +#define PINMUX_GPIO42__FUNC_DMIC_DAT (MTK_PIN_NO(42) | 6)
> >>>>> +
> >>>>> +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
> >>>>> +#define PINMUX_GPIO43__FUNC_DISP_PWM (MTK_PIN_NO(43) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
> >>>>> +#define PINMUX_GPIO44__FUNC_DSI_TE (MTK_PIN_NO(44) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
> >>>>> +#define PINMUX_GPIO45__FUNC_LCM_RST (MTK_PIN_NO(45) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
> >>>>> +#define PINMUX_GPIO46__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(46) | 1)
> >>>>> +#define PINMUX_GPIO46__FUNC_URXD1 (MTK_PIN_NO(46) | 2)
> >>>>> +#define PINMUX_GPIO46__FUNC_UCTS1 (MTK_PIN_NO(46) | 3)
> >>>>> +#define PINMUX_GPIO46__FUNC_CCU_UTXD_AO (MTK_PIN_NO(46) | 4)
> >>>>> +#define PINMUX_GPIO46__FUNC_TP_UCTS1_AO (MTK_PIN_NO(46) | 5)
> >>>>> +#define PINMUX_GPIO46__FUNC_IDDIG (MTK_PIN_NO(46) | 6)
> >>>>> +#define PINMUX_GPIO46__FUNC_I2S5_LRCK (MTK_PIN_NO(46) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
> >>>>> +#define PINMUX_GPIO47__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(47) | 1)
> >>>>> +#define PINMUX_GPIO47__FUNC_UTXD1 (MTK_PIN_NO(47) | 2)
> >>>>> +#define PINMUX_GPIO47__FUNC_URTS1 (MTK_PIN_NO(47) | 3)
> >>>>> +#define PINMUX_GPIO47__FUNC_CCU_URXD_AO (MTK_PIN_NO(47) | 4)
> >>>>> +#define PINMUX_GPIO47__FUNC_TP_URTS1_AO (MTK_PIN_NO(47) | 5)
> >>>>> +#define PINMUX_GPIO47__FUNC_USB_DRVVBUS (MTK_PIN_NO(47) | 6)
> >>>>> +#define PINMUX_GPIO47__FUNC_I2S5_DO (MTK_PIN_NO(47) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
> >>>>> +#define PINMUX_GPIO48__FUNC_SCL5 (MTK_PIN_NO(48) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
> >>>>> +#define PINMUX_GPIO49__FUNC_SDA5 (MTK_PIN_NO(49) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
> >>>>> +#define PINMUX_GPIO50__FUNC_SCL3 (MTK_PIN_NO(50) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
> >>>>> +#define PINMUX_GPIO51__FUNC_SDA3 (MTK_PIN_NO(51) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
> >>>>> +#define PINMUX_GPIO52__FUNC_BPI_ANT2 (MTK_PIN_NO(52) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
> >>>>> +#define PINMUX_GPIO53__FUNC_BPI_ANT0 (MTK_PIN_NO(53) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
> >>>>> +#define PINMUX_GPIO54__FUNC_BPI_OLAT1 (MTK_PIN_NO(54) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
> >>>>> +#define PINMUX_GPIO55__FUNC_BPI_BUS8 (MTK_PIN_NO(55) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
> >>>>> +#define PINMUX_GPIO56__FUNC_BPI_BUS9 (MTK_PIN_NO(56) | 1)
> >>>>> +#define PINMUX_GPIO56__FUNC_SCL_6306 (MTK_PIN_NO(56) | 2)
> >>>>> +
> >>>>> +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
> >>>>> +#define PINMUX_GPIO57__FUNC_BPI_BUS10 (MTK_PIN_NO(57) | 1)
> >>>>> +#define PINMUX_GPIO57__FUNC_SDA_6306 (MTK_PIN_NO(57) | 2)
> >>>>> +
> >>>>> +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
> >>>>> +#define PINMUX_GPIO58__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(58) | 1)
> >>>>> +#define PINMUX_GPIO58__FUNC_SPM_BSI_D2 (MTK_PIN_NO(58) | 2)
> >>>>> +#define PINMUX_GPIO58__FUNC_PWM_B (MTK_PIN_NO(58) | 3)
> >>>>> +
> >>>>> +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
> >>>>> +#define PINMUX_GPIO59__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(59) | 1)
> >>>>> +#define PINMUX_GPIO59__FUNC_SPM_BSI_D1 (MTK_PIN_NO(59) | 2)
> >>>>> +
> >>>>> +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
> >>>>> +#define PINMUX_GPIO60__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(60) | 1)
> >>>>> +#define PINMUX_GPIO60__FUNC_SPM_BSI_D0 (MTK_PIN_NO(60) | 2)
> >>>>> +
> >>>>> +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
> >>>>> +#define PINMUX_GPIO61__FUNC_MIPI1_SDATA (MTK_PIN_NO(61) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
> >>>>> +#define PINMUX_GPIO62__FUNC_MIPI1_SCLK (MTK_PIN_NO(62) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
> >>>>> +#define PINMUX_GPIO63__FUNC_MIPI0_SDATA (MTK_PIN_NO(63) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
> >>>>> +#define PINMUX_GPIO64__FUNC_MIPI0_SCLK (MTK_PIN_NO(64) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
> >>>>> +#define PINMUX_GPIO65__FUNC_MIPI3_SDATA (MTK_PIN_NO(65) | 1)
> >>>>> +#define PINMUX_GPIO65__FUNC_BPI_OLAT2 (MTK_PIN_NO(65) | 2)
> >>>>> +
> >>>>> +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
> >>>>> +#define PINMUX_GPIO66__FUNC_MIPI3_SCLK (MTK_PIN_NO(66) | 1)
> >>>>> +#define PINMUX_GPIO66__FUNC_BPI_OLAT3 (MTK_PIN_NO(66) | 2)
> >>>>> +
> >>>>> +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
> >>>>> +#define PINMUX_GPIO67__FUNC_MIPI2_SDATA (MTK_PIN_NO(67) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
> >>>>> +#define PINMUX_GPIO68__FUNC_MIPI2_SCLK (MTK_PIN_NO(68) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
> >>>>> +#define PINMUX_GPIO69__FUNC_BPI_BUS7 (MTK_PIN_NO(69) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
> >>>>> +#define PINMUX_GPIO70__FUNC_BPI_BUS6 (MTK_PIN_NO(70) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
> >>>>> +#define PINMUX_GPIO71__FUNC_BPI_BUS5 (MTK_PIN_NO(71) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
> >>>>> +#define PINMUX_GPIO72__FUNC_BPI_BUS4 (MTK_PIN_NO(72) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
> >>>>> +#define PINMUX_GPIO73__FUNC_BPI_BUS3 (MTK_PIN_NO(73) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
> >>>>> +#define PINMUX_GPIO74__FUNC_BPI_BUS2 (MTK_PIN_NO(74) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
> >>>>> +#define PINMUX_GPIO75__FUNC_BPI_BUS1 (MTK_PIN_NO(75) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
> >>>>> +#define PINMUX_GPIO76__FUNC_BPI_BUS0 (MTK_PIN_NO(76) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
> >>>>> +#define PINMUX_GPIO77__FUNC_BPI_ANT1 (MTK_PIN_NO(77) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
> >>>>> +#define PINMUX_GPIO78__FUNC_BPI_OLAT0 (MTK_PIN_NO(78) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
> >>>>> +#define PINMUX_GPIO79__FUNC_BPI_PA_VM1 (MTK_PIN_NO(79) | 1)
> >>>>> +#define PINMUX_GPIO79__FUNC_MIPI4_SDATA (MTK_PIN_NO(79) | 2)
> >>>>> +
> >>>>> +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
> >>>>> +#define PINMUX_GPIO80__FUNC_BPI_PA_VM0 (MTK_PIN_NO(80) | 1)
> >>>>> +#define PINMUX_GPIO80__FUNC_MIPI4_SCLK (MTK_PIN_NO(80) | 2)
> >>>>> +
> >>>>> +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
> >>>>> +#define PINMUX_GPIO81__FUNC_SDA1 (MTK_PIN_NO(81) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
> >>>>> +#define PINMUX_GPIO82__FUNC_SDA0 (MTK_PIN_NO(82) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
> >>>>> +#define PINMUX_GPIO83__FUNC_SCL0 (MTK_PIN_NO(83) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
> >>>>> +#define PINMUX_GPIO84__FUNC_SCL1 (MTK_PIN_NO(84) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
> >>>>> +#define PINMUX_GPIO85__FUNC_SPI0_MI (MTK_PIN_NO(85) | 1)
> >>>>> +#define PINMUX_GPIO85__FUNC_SCP_SPI0_MI (MTK_PIN_NO(85) | 2)
> >>>>> +#define PINMUX_GPIO85__FUNC_CLKM3 (MTK_PIN_NO(85) | 3)
> >>>>> +#define PINMUX_GPIO85__FUNC_I2S1_BCK (MTK_PIN_NO(85) | 4)
> >>>>> +#define PINMUX_GPIO85__FUNC_MFG_DFD_JTAG_TDO (MTK_PIN_NO(85) | 5)
> >>>>> +#define PINMUX_GPIO85__FUNC_DFD_TDO (MTK_PIN_NO(85) | 6)
> >>>>> +#define PINMUX_GPIO85__FUNC_JTDO_SEL1 (MTK_PIN_NO(85) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
> >>>>> +#define PINMUX_GPIO86__FUNC_SPI0_CSB (MTK_PIN_NO(86) | 1)
> >>>>> +#define PINMUX_GPIO86__FUNC_SCP_SPI0_CS (MTK_PIN_NO(86) | 2)
> >>>>> +#define PINMUX_GPIO86__FUNC_CLKM0 (MTK_PIN_NO(86) | 3)
> >>>>> +#define PINMUX_GPIO86__FUNC_I2S1_LRCK (MTK_PIN_NO(86) | 4)
> >>>>> +#define PINMUX_GPIO86__FUNC_MFG_DFD_JTAG_TMS (MTK_PIN_NO(86) | 5)
> >>>>> +#define PINMUX_GPIO86__FUNC_DFD_TMS (MTK_PIN_NO(86) | 6)
> >>>>> +#define PINMUX_GPIO86__FUNC_JTMS_SEL1 (MTK_PIN_NO(86) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
> >>>>> +#define PINMUX_GPIO87__FUNC_SPI0_MO (MTK_PIN_NO(87) | 1)
> >>>>> +#define PINMUX_GPIO87__FUNC_SCP_SPI0_MO (MTK_PIN_NO(87) | 2)
> >>>>> +#define PINMUX_GPIO87__FUNC_SDA1 (MTK_PIN_NO(87) | 3)
> >>>>> +#define PINMUX_GPIO87__FUNC_I2S1_DO (MTK_PIN_NO(87) | 4)
> >>>>> +#define PINMUX_GPIO87__FUNC_MFG_DFD_JTAG_TDI (MTK_PIN_NO(87) | 5)
> >>>>> +#define PINMUX_GPIO87__FUNC_DFD_TDI (MTK_PIN_NO(87) | 6)
> >>>>> +#define PINMUX_GPIO87__FUNC_JTDI_SEL1 (MTK_PIN_NO(87) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
> >>>>> +#define PINMUX_GPIO88__FUNC_SPI0_CLK (MTK_PIN_NO(88) | 1)
> >>>>> +#define PINMUX_GPIO88__FUNC_SCP_SPI0_CK (MTK_PIN_NO(88) | 2)
> >>>>> +#define PINMUX_GPIO88__FUNC_SCL1 (MTK_PIN_NO(88) | 3)
> >>>>> +#define PINMUX_GPIO88__FUNC_I2S1_MCK (MTK_PIN_NO(88) | 4)
> >>>>> +#define PINMUX_GPIO88__FUNC_MFG_DFD_JTAG_TCK (MTK_PIN_NO(88) | 5)
> >>>>> +#define PINMUX_GPIO88__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 6)
> >>>>> +#define PINMUX_GPIO88__FUNC_JTCK_SEL1 (MTK_PIN_NO(88) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
> >>>>> +#define PINMUX_GPIO89__FUNC_SRCLKENAI0 (MTK_PIN_NO(89) | 1)
> >>>>> +#define PINMUX_GPIO89__FUNC_PWM_C (MTK_PIN_NO(89) | 2)
> >>>>> +#define PINMUX_GPIO89__FUNC_I2S5_BCK (MTK_PIN_NO(89) | 3)
> >>>>> +#define PINMUX_GPIO89__FUNC_ANT_SEL6 (MTK_PIN_NO(89) | 4)
> >>>>> +#define PINMUX_GPIO89__FUNC_SDA8 (MTK_PIN_NO(89) | 5)
> >>>>> +#define PINMUX_GPIO89__FUNC_CMVREF0 (MTK_PIN_NO(89) | 6)
> >>>>> +#define PINMUX_GPIO89__FUNC_DBG_MON_A21 (MTK_PIN_NO(89) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
> >>>>> +#define PINMUX_GPIO90__FUNC_PWM_A (MTK_PIN_NO(90) | 1)
> >>>>> +#define PINMUX_GPIO90__FUNC_CMMCLK2 (MTK_PIN_NO(90) | 2)
> >>>>> +#define PINMUX_GPIO90__FUNC_I2S5_LRCK (MTK_PIN_NO(90) | 3)
> >>>>> +#define PINMUX_GPIO90__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(90) | 4)
> >>>>> +#define PINMUX_GPIO90__FUNC_SCL8 (MTK_PIN_NO(90) | 5)
> >>>>> +#define PINMUX_GPIO90__FUNC_PTA_RXD (MTK_PIN_NO(90) | 6)
> >>>>> +#define PINMUX_GPIO90__FUNC_DBG_MON_A22 (MTK_PIN_NO(90) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
> >>>>> +#define PINMUX_GPIO91__FUNC_KPROW1 (MTK_PIN_NO(91) | 1)
> >>>>> +#define PINMUX_GPIO91__FUNC_PWM_B (MTK_PIN_NO(91) | 2)
> >>>>> +#define PINMUX_GPIO91__FUNC_I2S5_DO (MTK_PIN_NO(91) | 3)
> >>>>> +#define PINMUX_GPIO91__FUNC_ANT_SEL7 (MTK_PIN_NO(91) | 4)
> >>>>> +#define PINMUX_GPIO91__FUNC_CMMCLK3 (MTK_PIN_NO(91) | 5)
> >>>>> +#define PINMUX_GPIO91__FUNC_PTA_TXD (MTK_PIN_NO(91) | 6)
> >>>>> +
> >>>>> +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
> >>>>> +#define PINMUX_GPIO92__FUNC_KPROW0 (MTK_PIN_NO(92) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
> >>>>> +#define PINMUX_GPIO93__FUNC_KPCOL0 (MTK_PIN_NO(93) | 1)
> >>>>> +#define PINMUX_GPIO93__FUNC_DBG_MON_B27 (MTK_PIN_NO(93) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
> >>>>> +#define PINMUX_GPIO94__FUNC_KPCOL1 (MTK_PIN_NO(94) | 1)
> >>>>> +#define PINMUX_GPIO94__FUNC_I2S2_DI2 (MTK_PIN_NO(94) | 2)
> >>>>> +#define PINMUX_GPIO94__FUNC_I2S5_MCK (MTK_PIN_NO(94) | 3)
> >>>>> +#define PINMUX_GPIO94__FUNC_CMMCLK2 (MTK_PIN_NO(94) | 4)
> >>>>> +#define PINMUX_GPIO94__FUNC_SCP_SPI2_MI (MTK_PIN_NO(94) | 5)
> >>>>> +#define PINMUX_GPIO94__FUNC_SRCLKENAI1 (MTK_PIN_NO(94) | 6)
> >>>>> +#define PINMUX_GPIO94__FUNC_SPI2_MI (MTK_PIN_NO(94) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
> >>>>> +#define PINMUX_GPIO95__FUNC_URXD0 (MTK_PIN_NO(95) | 1)
> >>>>> +#define PINMUX_GPIO95__FUNC_UTXD0 (MTK_PIN_NO(95) | 2)
> >>>>> +#define PINMUX_GPIO95__FUNC_MD_URXD0 (MTK_PIN_NO(95) | 3)
> >>>>> +#define PINMUX_GPIO95__FUNC_MD_URXD1 (MTK_PIN_NO(95) | 4)
> >>>>> +#define PINMUX_GPIO95__FUNC_SSPM_URXD_AO (MTK_PIN_NO(95) | 5)
> >>>>> +#define PINMUX_GPIO95__FUNC_CCU_URXD_AO (MTK_PIN_NO(95) | 6)
> >>>>> +
> >>>>> +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
> >>>>> +#define PINMUX_GPIO96__FUNC_UTXD0 (MTK_PIN_NO(96) | 1)
> >>>>> +#define PINMUX_GPIO96__FUNC_URXD0 (MTK_PIN_NO(96) | 2)
> >>>>> +#define PINMUX_GPIO96__FUNC_MD_UTXD0 (MTK_PIN_NO(96) | 3)
> >>>>> +#define PINMUX_GPIO96__FUNC_MD_UTXD1 (MTK_PIN_NO(96) | 4)
> >>>>> +#define PINMUX_GPIO96__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(96) | 5)
> >>>>> +#define PINMUX_GPIO96__FUNC_CCU_UTXD_AO (MTK_PIN_NO(96) | 6)
> >>>>> +#define PINMUX_GPIO96__FUNC_DBG_MON_B2 (MTK_PIN_NO(96) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
> >>>>> +#define PINMUX_GPIO97__FUNC_UCTS0 (MTK_PIN_NO(97) | 1)
> >>>>> +#define PINMUX_GPIO97__FUNC_I2S2_MCK (MTK_PIN_NO(97) | 2)
> >>>>> +#define PINMUX_GPIO97__FUNC_IDDIG (MTK_PIN_NO(97) | 3)
> >>>>> +#define PINMUX_GPIO97__FUNC_CONN_MCU_TDO (MTK_PIN_NO(97) | 4)
> >>>>> +#define PINMUX_GPIO97__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(97) | 5)
> >>>>> +#define PINMUX_GPIO97__FUNC_IO_JTAG_TDO (MTK_PIN_NO(97) | 6)
> >>>>> +#define PINMUX_GPIO97__FUNC_DBG_MON_B3 (MTK_PIN_NO(97) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
> >>>>> +#define PINMUX_GPIO98__FUNC_URTS0 (MTK_PIN_NO(98) | 1)
> >>>>> +#define PINMUX_GPIO98__FUNC_I2S2_BCK (MTK_PIN_NO(98) | 2)
> >>>>> +#define PINMUX_GPIO98__FUNC_USB_DRVVBUS (MTK_PIN_NO(98) | 3)
> >>>>> +#define PINMUX_GPIO98__FUNC_CONN_MCU_TMS (MTK_PIN_NO(98) | 4)
> >>>>> +#define PINMUX_GPIO98__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(98) | 5)
> >>>>> +#define PINMUX_GPIO98__FUNC_IO_JTAG_TMS (MTK_PIN_NO(98) | 6)
> >>>>> +#define PINMUX_GPIO98__FUNC_DBG_MON_B4 (MTK_PIN_NO(98) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
> >>>>> +#define PINMUX_GPIO99__FUNC_CMMCLK0 (MTK_PIN_NO(99) | 1)
> >>>>> +#define PINMUX_GPIO99__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(99) | 4)
> >>>>> +#define PINMUX_GPIO99__FUNC_DBG_MON_B28 (MTK_PIN_NO(99) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
> >>>>> +#define PINMUX_GPIO100__FUNC_CMMCLK1 (MTK_PIN_NO(100) | 1)
> >>>>> +#define PINMUX_GPIO100__FUNC_PWM_C (MTK_PIN_NO(100) | 2)
> >>>>> +#define PINMUX_GPIO100__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(100) | 3)
> >>>>> +#define PINMUX_GPIO100__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(100) | 4)
> >>>>> +#define PINMUX_GPIO100__FUNC_DBG_MON_B29 (MTK_PIN_NO(100) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
> >>>>> +#define PINMUX_GPIO101__FUNC_CLKM2 (MTK_PIN_NO(101) | 1)
> >>>>> +#define PINMUX_GPIO101__FUNC_I2S2_LRCK (MTK_PIN_NO(101) | 2)
> >>>>> +#define PINMUX_GPIO101__FUNC_CMVREF1 (MTK_PIN_NO(101) | 3)
> >>>>> +#define PINMUX_GPIO101__FUNC_CONN_MCU_TCK (MTK_PIN_NO(101) | 4)
> >>>>> +#define PINMUX_GPIO101__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(101) | 5)
> >>>>> +#define PINMUX_GPIO101__FUNC_IO_JTAG_TCK (MTK_PIN_NO(101) | 6)
> >>>>> +
> >>>>> +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
> >>>>> +#define PINMUX_GPIO102__FUNC_CLKM1 (MTK_PIN_NO(102) | 1)
> >>>>> +#define PINMUX_GPIO102__FUNC_I2S2_DI (MTK_PIN_NO(102) | 2)
> >>>>> +#define PINMUX_GPIO102__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(102) | 3)
> >>>>> +#define PINMUX_GPIO102__FUNC_CONN_MCU_TDI (MTK_PIN_NO(102) | 4)
> >>>>> +#define PINMUX_GPIO102__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(102) | 5)
> >>>>> +#define PINMUX_GPIO102__FUNC_IO_JTAG_TDI (MTK_PIN_NO(102) | 6)
> >>>>> +#define PINMUX_GPIO102__FUNC_DBG_MON_B8 (MTK_PIN_NO(102) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
> >>>>> +#define PINMUX_GPIO103__FUNC_SCL2 (MTK_PIN_NO(103) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
> >>>>> +#define PINMUX_GPIO104__FUNC_SDA2 (MTK_PIN_NO(104) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
> >>>>> +#define PINMUX_GPIO105__FUNC_SCL4 (MTK_PIN_NO(105) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
> >>>>> +#define PINMUX_GPIO106__FUNC_SDA4 (MTK_PIN_NO(106) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
> >>>>> +#define PINMUX_GPIO107__FUNC_DMIC_CLK (MTK_PIN_NO(107) | 1)
> >>>>> +#define PINMUX_GPIO107__FUNC_ANT_SEL0 (MTK_PIN_NO(107) | 2)
> >>>>> +#define PINMUX_GPIO107__FUNC_CLKM0 (MTK_PIN_NO(107) | 3)
> >>>>> +#define PINMUX_GPIO107__FUNC_SDA7 (MTK_PIN_NO(107) | 4)
> >>>>> +#define PINMUX_GPIO107__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(107) | 5)
> >>>>> +#define PINMUX_GPIO107__FUNC_PWM_A (MTK_PIN_NO(107) | 6)
> >>>>> +#define PINMUX_GPIO107__FUNC_DBG_MON_B12 (MTK_PIN_NO(107) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
> >>>>> +#define PINMUX_GPIO108__FUNC_CMMCLK2 (MTK_PIN_NO(108) | 1)
> >>>>> +#define PINMUX_GPIO108__FUNC_ANT_SEL1 (MTK_PIN_NO(108) | 2)
> >>>>> +#define PINMUX_GPIO108__FUNC_CLKM1 (MTK_PIN_NO(108) | 3)
> >>>>> +#define PINMUX_GPIO108__FUNC_SCL8 (MTK_PIN_NO(108) | 4)
> >>>>> +#define PINMUX_GPIO108__FUNC_DAP_MD32_SWD (MTK_PIN_NO(108) | 5)
> >>>>> +#define PINMUX_GPIO108__FUNC_PWM_B (MTK_PIN_NO(108) | 6)
> >>>>> +#define PINMUX_GPIO108__FUNC_DBG_MON_B13 (MTK_PIN_NO(108) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
> >>>>> +#define PINMUX_GPIO109__FUNC_DMIC_DAT (MTK_PIN_NO(109) | 1)
> >>>>> +#define PINMUX_GPIO109__FUNC_ANT_SEL2 (MTK_PIN_NO(109) | 2)
> >>>>> +#define PINMUX_GPIO109__FUNC_CLKM2 (MTK_PIN_NO(109) | 3)
> >>>>> +#define PINMUX_GPIO109__FUNC_SDA8 (MTK_PIN_NO(109) | 4)
> >>>>> +#define PINMUX_GPIO109__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(109) | 5)
> >>>>> +#define PINMUX_GPIO109__FUNC_PWM_C (MTK_PIN_NO(109) | 6)
> >>>>> +#define PINMUX_GPIO109__FUNC_DBG_MON_B14 (MTK_PIN_NO(109) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
> >>>>> +#define PINMUX_GPIO110__FUNC_SCL7 (MTK_PIN_NO(110) | 1)
> >>>>> +#define PINMUX_GPIO110__FUNC_ANT_SEL0 (MTK_PIN_NO(110) | 2)
> >>>>> +#define PINMUX_GPIO110__FUNC_TP_URXD1_AO (MTK_PIN_NO(110) | 3)
> >>>>> +#define PINMUX_GPIO110__FUNC_USB_DRVVBUS (MTK_PIN_NO(110) | 4)
> >>>>> +#define PINMUX_GPIO110__FUNC_SRCLKENAI1 (MTK_PIN_NO(110) | 5)
> >>>>> +#define PINMUX_GPIO110__FUNC_KPCOL2 (MTK_PIN_NO(110) | 6)
> >>>>> +#define PINMUX_GPIO110__FUNC_URXD1 (MTK_PIN_NO(110) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
> >>>>> +#define PINMUX_GPIO111__FUNC_CMMCLK3 (MTK_PIN_NO(111) | 1)
> >>>>> +#define PINMUX_GPIO111__FUNC_ANT_SEL1 (MTK_PIN_NO(111) | 2)
> >>>>> +#define PINMUX_GPIO111__FUNC_SRCLKENAI0 (MTK_PIN_NO(111) | 3)
> >>>>> +#define PINMUX_GPIO111__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(111) | 4)
> >>>>> +#define PINMUX_GPIO111__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(111) | 5)
> >>>>> +#define PINMUX_GPIO111__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(111) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
> >>>>> +#define PINMUX_GPIO112__FUNC_SDA7 (MTK_PIN_NO(112) | 1)
> >>>>> +#define PINMUX_GPIO112__FUNC_ANT_SEL2 (MTK_PIN_NO(112) | 2)
> >>>>> +#define PINMUX_GPIO112__FUNC_TP_UTXD1_AO (MTK_PIN_NO(112) | 3)
> >>>>> +#define PINMUX_GPIO112__FUNC_IDDIG (MTK_PIN_NO(112) | 4)
> >>>>> +#define PINMUX_GPIO112__FUNC_AGPS_SYNC (MTK_PIN_NO(112) | 5)
> >>>>> +#define PINMUX_GPIO112__FUNC_KPROW2 (MTK_PIN_NO(112) | 6)
> >>>>> +#define PINMUX_GPIO112__FUNC_UTXD1 (MTK_PIN_NO(112) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
> >>>>> +#define PINMUX_GPIO113__FUNC_CONN_TOP_CLK (MTK_PIN_NO(113) | 1)
> >>>>> +#define PINMUX_GPIO113__FUNC_SCL6 (MTK_PIN_NO(113) | 3)
> >>>>> +#define PINMUX_GPIO113__FUNC_AUXIF_CLK0 (MTK_PIN_NO(113) | 4)
> >>>>> +#define PINMUX_GPIO113__FUNC_TP_UCTS1_AO (MTK_PIN_NO(113) | 6)
> >>>>> +
> >>>>> +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
> >>>>> +#define PINMUX_GPIO114__FUNC_CONN_TOP_DATA (MTK_PIN_NO(114) | 1)
> >>>>> +#define PINMUX_GPIO114__FUNC_SDA6 (MTK_PIN_NO(114) | 3)
> >>>>> +#define PINMUX_GPIO114__FUNC_AUXIF_ST0 (MTK_PIN_NO(114) | 4)
> >>>>> +#define PINMUX_GPIO114__FUNC_TP_URTS1_AO (MTK_PIN_NO(114) | 6)
> >>>>> +
> >>>>> +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
> >>>>> +#define PINMUX_GPIO115__FUNC_CONN_BT_CLK (MTK_PIN_NO(115) | 1)
> >>>>> +#define PINMUX_GPIO115__FUNC_UTXD1 (MTK_PIN_NO(115) | 2)
> >>>>> +#define PINMUX_GPIO115__FUNC_PTA_TXD (MTK_PIN_NO(115) | 3)
> >>>>> +#define PINMUX_GPIO115__FUNC_AUXIF_CLK1 (MTK_PIN_NO(115) | 4)
> >>>>> +#define PINMUX_GPIO115__FUNC_DAP_MD32_SWD (MTK_PIN_NO(115) | 5)
> >>>>> +#define PINMUX_GPIO115__FUNC_TP_UTXD1_AO (MTK_PIN_NO(115) | 6)
> >>>>> +
> >>>>> +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
> >>>>> +#define PINMUX_GPIO116__FUNC_CONN_BT_DATA (MTK_PIN_NO(116) | 1)
> >>>>> +#define PINMUX_GPIO116__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(116) | 2)
> >>>>> +#define PINMUX_GPIO116__FUNC_AUXIF_ST1 (MTK_PIN_NO(116) | 4)
> >>>>> +#define PINMUX_GPIO116__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(116) | 5)
> >>>>> +#define PINMUX_GPIO116__FUNC_TP_URXD2_AO (MTK_PIN_NO(116) | 6)
> >>>>> +#define PINMUX_GPIO116__FUNC_DBG_MON_A0 (MTK_PIN_NO(116) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
> >>>>> +#define PINMUX_GPIO117__FUNC_CONN_WF_HB0 (MTK_PIN_NO(117) | 1)
> >>>>> +#define PINMUX_GPIO117__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(117) | 2)
> >>>>> +#define PINMUX_GPIO117__FUNC_TP_UTXD2_AO (MTK_PIN_NO(117) | 6)
> >>>>> +#define PINMUX_GPIO117__FUNC_DBG_MON_A4 (MTK_PIN_NO(117) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
> >>>>> +#define PINMUX_GPIO118__FUNC_CONN_WF_HB1 (MTK_PIN_NO(118) | 1)
> >>>>> +#define PINMUX_GPIO118__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(118) | 2)
> >>>>> +#define PINMUX_GPIO118__FUNC_SSPM_URXD_AO (MTK_PIN_NO(118) | 5)
> >>>>> +#define PINMUX_GPIO118__FUNC_TP_UCTS2_AO (MTK_PIN_NO(118) | 6)
> >>>>> +#define PINMUX_GPIO118__FUNC_DBG_MON_A5 (MTK_PIN_NO(118) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
> >>>>> +#define PINMUX_GPIO119__FUNC_CONN_WF_HB2 (MTK_PIN_NO(119) | 1)
> >>>>> +#define PINMUX_GPIO119__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(119) | 2)
> >>>>> +#define PINMUX_GPIO119__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(119) | 5)
> >>>>> +#define PINMUX_GPIO119__FUNC_TP_URTS2_AO (MTK_PIN_NO(119) | 6)
> >>>>> +
> >>>>> +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
> >>>>> +#define PINMUX_GPIO120__FUNC_CONN_WB_PTA (MTK_PIN_NO(120) | 1)
> >>>>> +#define PINMUX_GPIO120__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(120) | 2)
> >>>>> +#define PINMUX_GPIO120__FUNC_CCU_URXD_AO (MTK_PIN_NO(120) | 5)
> >>>>> +
> >>>>> +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
> >>>>> +#define PINMUX_GPIO121__FUNC_CONN_HRST_B (MTK_PIN_NO(121) | 1)
> >>>>> +#define PINMUX_GPIO121__FUNC_URXD1 (MTK_PIN_NO(121) | 2)
> >>>>> +#define PINMUX_GPIO121__FUNC_PTA_RXD (MTK_PIN_NO(121) | 3)
> >>>>> +#define PINMUX_GPIO121__FUNC_CCU_UTXD_AO (MTK_PIN_NO(121) | 5)
> >>>>> +#define PINMUX_GPIO121__FUNC_TP_URXD1_AO (MTK_PIN_NO(121) | 6)
> >>>>> +
> >>>>> +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
> >>>>> +#define PINMUX_GPIO122__FUNC_MSDC0_CMD (MTK_PIN_NO(122) | 1)
> >>>>> +#define PINMUX_GPIO122__FUNC_SSPM_URXD2_AO (MTK_PIN_NO(122) | 2)
> >>>>> +#define PINMUX_GPIO122__FUNC_ANT_SEL1 (MTK_PIN_NO(122) | 3)
> >>>>> +#define PINMUX_GPIO122__FUNC_DBG_MON_A12 (MTK_PIN_NO(122) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
> >>>>> +#define PINMUX_GPIO123__FUNC_MSDC0_DAT0 (MTK_PIN_NO(123) | 1)
> >>>>> +#define PINMUX_GPIO123__FUNC_ANT_SEL0 (MTK_PIN_NO(123) | 3)
> >>>>> +#define PINMUX_GPIO123__FUNC_DBG_MON_A13 (MTK_PIN_NO(123) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
> >>>>> +#define PINMUX_GPIO124__FUNC_MSDC0_CLK (MTK_PIN_NO(124) | 1)
> >>>>> +#define PINMUX_GPIO124__FUNC_DBG_MON_A14 (MTK_PIN_NO(124) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
> >>>>> +#define PINMUX_GPIO125__FUNC_MSDC0_DAT2 (MTK_PIN_NO(125) | 1)
> >>>>> +#define PINMUX_GPIO125__FUNC_MRG_CLK (MTK_PIN_NO(125) | 3)
> >>>>> +#define PINMUX_GPIO125__FUNC_DBG_MON_A15 (MTK_PIN_NO(125) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
> >>>>> +#define PINMUX_GPIO126__FUNC_MSDC0_DAT4 (MTK_PIN_NO(126) | 1)
> >>>>> +#define PINMUX_GPIO126__FUNC_ANT_SEL5 (MTK_PIN_NO(126) | 3)
> >>>>> +#define PINMUX_GPIO126__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(126) | 6)
> >>>>> +#define PINMUX_GPIO126__FUNC_DBG_MON_A16 (MTK_PIN_NO(126) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
> >>>>> +#define PINMUX_GPIO127__FUNC_MSDC0_DAT6 (MTK_PIN_NO(127) | 1)
> >>>>> +#define PINMUX_GPIO127__FUNC_ANT_SEL4 (MTK_PIN_NO(127) | 3)
> >>>>> +#define PINMUX_GPIO127__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(127) | 6)
> >>>>> +#define PINMUX_GPIO127__FUNC_DBG_MON_A17 (MTK_PIN_NO(127) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
> >>>>> +#define PINMUX_GPIO128__FUNC_MSDC0_DAT1 (MTK_PIN_NO(128) | 1)
> >>>>> +#define PINMUX_GPIO128__FUNC_ANT_SEL2 (MTK_PIN_NO(128) | 3)
> >>>>> +#define PINMUX_GPIO128__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(128) | 6)
> >>>>> +#define PINMUX_GPIO128__FUNC_DBG_MON_A18 (MTK_PIN_NO(128) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
> >>>>> +#define PINMUX_GPIO129__FUNC_MSDC0_DAT5 (MTK_PIN_NO(129) | 1)
> >>>>> +#define PINMUX_GPIO129__FUNC_ANT_SEL3 (MTK_PIN_NO(129) | 3)
> >>>>> +#define PINMUX_GPIO129__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(129) | 6)
> >>>>> +#define PINMUX_GPIO129__FUNC_DBG_MON_A23 (MTK_PIN_NO(129) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
> >>>>> +#define PINMUX_GPIO130__FUNC_MSDC0_DAT7 (MTK_PIN_NO(130) | 1)
> >>>>> +#define PINMUX_GPIO130__FUNC_MRG_DO (MTK_PIN_NO(130) | 3)
> >>>>> +#define PINMUX_GPIO130__FUNC_DBG_MON_A24 (MTK_PIN_NO(130) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
> >>>>> +#define PINMUX_GPIO131__FUNC_MSDC0_DSL (MTK_PIN_NO(131) | 1)
> >>>>> +#define PINMUX_GPIO131__FUNC_MRG_SYNC (MTK_PIN_NO(131) | 3)
> >>>>> +#define PINMUX_GPIO131__FUNC_DBG_MON_A25 (MTK_PIN_NO(131) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
> >>>>> +#define PINMUX_GPIO132__FUNC_MSDC0_DAT3 (MTK_PIN_NO(132) | 1)
> >>>>> +#define PINMUX_GPIO132__FUNC_MRG_DI (MTK_PIN_NO(132) | 3)
> >>>>> +#define PINMUX_GPIO132__FUNC_DBG_MON_A26 (MTK_PIN_NO(132) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
> >>>>> +#define PINMUX_GPIO133__FUNC_MSDC0_RSTB (MTK_PIN_NO(133) | 1)
> >>>>> +#define PINMUX_GPIO133__FUNC_AGPS_SYNC (MTK_PIN_NO(133) | 3)
> >>>>> +#define PINMUX_GPIO133__FUNC_DBG_MON_A27 (MTK_PIN_NO(133) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
> >>>>> +#define PINMUX_GPIO134__FUNC_RTC32K_CK (MTK_PIN_NO(134) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
> >>>>> +#define PINMUX_GPIO135__FUNC_WATCHDOG (MTK_PIN_NO(135) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
> >>>>> +#define PINMUX_GPIO136__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(136) | 1)
> >>>>> +#define PINMUX_GPIO136__FUNC_AUD_CLK_MISO (MTK_PIN_NO(136) | 2)
> >>>>> +#define PINMUX_GPIO136__FUNC_I2S1_MCK (MTK_PIN_NO(136) | 3)
> >>>>> +#define PINMUX_GPIO136__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(136) | 6)
> >>>>> +
> >>>>> +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
> >>>>> +#define PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(137) | 1)
> >>>>> +#define PINMUX_GPIO137__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(137) | 2)
> >>>>> +#define PINMUX_GPIO137__FUNC_I2S1_BCK (MTK_PIN_NO(137) | 3)
> >>>>> +
> >>>>> +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
> >>>>> +#define PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(138) | 1)
> >>>>> +#define PINMUX_GPIO138__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(138) | 2)
> >>>>> +#define PINMUX_GPIO138__FUNC_I2S1_LRCK (MTK_PIN_NO(138) | 3)
> >>>>> +#define PINMUX_GPIO138__FUNC_DBG_MON_B24 (MTK_PIN_NO(138) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
> >>>>> +#define PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(139) | 1)
> >>>>> +#define PINMUX_GPIO139__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(139) | 2)
> >>>>> +#define PINMUX_GPIO139__FUNC_I2S1_DO (MTK_PIN_NO(139) | 3)
> >>>>> +#define PINMUX_GPIO139__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(139) | 6)
> >>>>> +
> >>>>> +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
> >>>>> +#define PINMUX_GPIO140__FUNC_AUD_CLK_MISO (MTK_PIN_NO(140) | 1)
> >>>>> +#define PINMUX_GPIO140__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(140) | 2)
> >>>>> +#define PINMUX_GPIO140__FUNC_I2S0_MCK (MTK_PIN_NO(140) | 3)
> >>>>> +#define PINMUX_GPIO140__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(140) | 6)
> >>>>> +
> >>>>> +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
> >>>>> +#define PINMUX_GPIO141__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(141) | 1)
> >>>>> +#define PINMUX_GPIO141__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(141) | 2)
> >>>>> +#define PINMUX_GPIO141__FUNC_I2S0_BCK (MTK_PIN_NO(141) | 3)
> >>>>> +
> >>>>> +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
> >>>>> +#define PINMUX_GPIO142__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(142) | 1)
> >>>>> +#define PINMUX_GPIO142__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(142) | 2)
> >>>>> +#define PINMUX_GPIO142__FUNC_I2S0_LRCK (MTK_PIN_NO(142) | 3)
> >>>>> +#define PINMUX_GPIO142__FUNC_VOW_DAT_MISO (MTK_PIN_NO(142) | 4)
> >>>>> +#define PINMUX_GPIO142__FUNC_DBG_MON_B25 (MTK_PIN_NO(142) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
> >>>>> +#define PINMUX_GPIO143__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(143) | 1)
> >>>>> +#define PINMUX_GPIO143__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(143) | 2)
> >>>>> +#define PINMUX_GPIO143__FUNC_I2S0_DI (MTK_PIN_NO(143) | 3)
> >>>>> +#define PINMUX_GPIO143__FUNC_VOW_CLK_MISO (MTK_PIN_NO(143) | 4)
> >>>>> +#define PINMUX_GPIO143__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(143) | 6)
> >>>>> +#define PINMUX_GPIO143__FUNC_DBG_MON_B26 (MTK_PIN_NO(143) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
> >>>>> +#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(144) | 1)
> >>>>> +#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(144) | 2)
> >>>>> +
> >>>>> +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
> >>>>> +#define PINMUX_GPIO145__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(145) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
> >>>>> +#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(146) | 1)
> >>>>> +#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(146) | 2)
> >>>>> +
> >>>>> +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
> >>>>> +#define PINMUX_GPIO147__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(147) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
> >>>>> +#define PINMUX_GPIO148__FUNC_SRCLKENA0 (MTK_PIN_NO(148) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
> >>>>> +#define PINMUX_GPIO149__FUNC_SRCLKENA1 (MTK_PIN_NO(149) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
> >>>>> +#define PINMUX_GPIO150__FUNC_PWM_A (MTK_PIN_NO(150) | 1)
> >>>>> +#define PINMUX_GPIO150__FUNC_CMFLASH (MTK_PIN_NO(150) | 2)
> >>>>> +#define PINMUX_GPIO150__FUNC_CLKM0 (MTK_PIN_NO(150) | 3)
> >>>>> +#define PINMUX_GPIO150__FUNC_DBG_MON_B30 (MTK_PIN_NO(150) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
> >>>>> +#define PINMUX_GPIO151__FUNC_PWM_B (MTK_PIN_NO(151) | 1)
> >>>>> +#define PINMUX_GPIO151__FUNC_CMVREF0 (MTK_PIN_NO(151) | 2)
> >>>>> +#define PINMUX_GPIO151__FUNC_CLKM1 (MTK_PIN_NO(151) | 3)
> >>>>> +#define PINMUX_GPIO151__FUNC_DBG_MON_B20 (MTK_PIN_NO(151) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
> >>>>> +#define PINMUX_GPIO152__FUNC_PWM_C (MTK_PIN_NO(152) | 1)
> >>>>> +#define PINMUX_GPIO152__FUNC_CMFLASH (MTK_PIN_NO(152) | 2)
> >>>>> +#define PINMUX_GPIO152__FUNC_CLKM2 (MTK_PIN_NO(152) | 3)
> >>>>> +#define PINMUX_GPIO152__FUNC_DBG_MON_B21 (MTK_PIN_NO(152) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
> >>>>> +#define PINMUX_GPIO153__FUNC_PWM_A (MTK_PIN_NO(153) | 1)
> >>>>> +#define PINMUX_GPIO153__FUNC_CMVREF0 (MTK_PIN_NO(153) | 2)
> >>>>> +#define PINMUX_GPIO153__FUNC_CLKM3 (MTK_PIN_NO(153) | 3)
> >>>>> +#define PINMUX_GPIO153__FUNC_DBG_MON_B22 (MTK_PIN_NO(153) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
> >>>>> +#define PINMUX_GPIO154__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(154) | 1)
> >>>>> +#define PINMUX_GPIO154__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(154) | 2)
> >>>>> +#define PINMUX_GPIO154__FUNC_DBG_MON_B18 (MTK_PIN_NO(154) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
> >>>>> +#define PINMUX_GPIO155__FUNC_ANT_SEL0 (MTK_PIN_NO(155) | 1)
> >>>>> +#define PINMUX_GPIO155__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(155) | 2)
> >>>>> +#define PINMUX_GPIO155__FUNC_CMVREF1 (MTK_PIN_NO(155) | 3)
> >>>>> +#define PINMUX_GPIO155__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(155) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
> >>>>> +#define PINMUX_GPIO156__FUNC_ANT_SEL1 (MTK_PIN_NO(156) | 1)
> >>>>> +#define PINMUX_GPIO156__FUNC_SRCLKENAI0 (MTK_PIN_NO(156) | 2)
> >>>>> +#define PINMUX_GPIO156__FUNC_SCL6 (MTK_PIN_NO(156) | 3)
> >>>>> +#define PINMUX_GPIO156__FUNC_KPCOL2 (MTK_PIN_NO(156) | 4)
> >>>>> +#define PINMUX_GPIO156__FUNC_IDDIG (MTK_PIN_NO(156) | 5)
> >>>>> +#define PINMUX_GPIO156__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(156) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
> >>>>> +#define PINMUX_GPIO157__FUNC_ANT_SEL2 (MTK_PIN_NO(157) | 1)
> >>>>> +#define PINMUX_GPIO157__FUNC_SRCLKENAI1 (MTK_PIN_NO(157) | 2)
> >>>>> +#define PINMUX_GPIO157__FUNC_SDA6 (MTK_PIN_NO(157) | 3)
> >>>>> +#define PINMUX_GPIO157__FUNC_KPROW2 (MTK_PIN_NO(157) | 4)
> >>>>> +#define PINMUX_GPIO157__FUNC_USB_DRVVBUS (MTK_PIN_NO(157) | 5)
> >>>>> +#define PINMUX_GPIO157__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(157) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
> >>>>> +#define PINMUX_GPIO158__FUNC_ANT_SEL3 (MTK_PIN_NO(158) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
> >>>>> +#define PINMUX_GPIO159__FUNC_ANT_SEL4 (MTK_PIN_NO(159) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
> >>>>> +#define PINMUX_GPIO160__FUNC_ANT_SEL5 (MTK_PIN_NO(160) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
> >>>>> +#define PINMUX_GPIO161__FUNC_SPI1_A_MI (MTK_PIN_NO(161) | 1)
> >>>>> +#define PINMUX_GPIO161__FUNC_SCP_SPI1_MI (MTK_PIN_NO(161) | 2)
> >>>>> +#define PINMUX_GPIO161__FUNC_IDDIG (MTK_PIN_NO(161) | 3)
> >>>>> +#define PINMUX_GPIO161__FUNC_ANT_SEL6 (MTK_PIN_NO(161) | 4)
> >>>>> +#define PINMUX_GPIO161__FUNC_KPCOL2 (MTK_PIN_NO(161) | 5)
> >>>>> +#define PINMUX_GPIO161__FUNC_PTA_RXD (MTK_PIN_NO(161) | 6)
> >>>>> +#define PINMUX_GPIO161__FUNC_DBG_MON_B19 (MTK_PIN_NO(161) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
> >>>>> +#define PINMUX_GPIO162__FUNC_SPI1_A_CSB (MTK_PIN_NO(162) | 1)
> >>>>> +#define PINMUX_GPIO162__FUNC_SCP_SPI1_CS (MTK_PIN_NO(162) | 2)
> >>>>> +#define PINMUX_GPIO162__FUNC_USB_DRVVBUS (MTK_PIN_NO(162) | 3)
> >>>>> +#define PINMUX_GPIO162__FUNC_ANT_SEL5 (MTK_PIN_NO(162) | 4)
> >>>>> +#define PINMUX_GPIO162__FUNC_KPROW2 (MTK_PIN_NO(162) | 5)
> >>>>> +#define PINMUX_GPIO162__FUNC_PTA_TXD (MTK_PIN_NO(162) | 6)
> >>>>> +
> >>>>> +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
> >>>>> +#define PINMUX_GPIO163__FUNC_SPI1_A_MO (MTK_PIN_NO(163) | 1)
> >>>>> +#define PINMUX_GPIO163__FUNC_SCP_SPI1_MO (MTK_PIN_NO(163) | 2)
> >>>>> +#define PINMUX_GPIO163__FUNC_SDA1 (MTK_PIN_NO(163) | 3)
> >>>>> +#define PINMUX_GPIO163__FUNC_ANT_SEL4 (MTK_PIN_NO(163) | 4)
> >>>>> +#define PINMUX_GPIO163__FUNC_CMMCLK2 (MTK_PIN_NO(163) | 5)
> >>>>> +#define PINMUX_GPIO163__FUNC_DMIC_CLK (MTK_PIN_NO(163) | 6)
> >>>>> +
> >>>>> +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
> >>>>> +#define PINMUX_GPIO164__FUNC_SPI1_A_CLK (MTK_PIN_NO(164) | 1)
> >>>>> +#define PINMUX_GPIO164__FUNC_SCP_SPI1_CK (MTK_PIN_NO(164) | 2)
> >>>>> +#define PINMUX_GPIO164__FUNC_SCL1 (MTK_PIN_NO(164) | 3)
> >>>>> +#define PINMUX_GPIO164__FUNC_ANT_SEL3 (MTK_PIN_NO(164) | 4)
> >>>>> +#define PINMUX_GPIO164__FUNC_CMMCLK3 (MTK_PIN_NO(164) | 5)
> >>>>> +#define PINMUX_GPIO164__FUNC_DMIC_DAT (MTK_PIN_NO(164) | 6)
> >>>>> +
> >>>>> +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
> >>>>> +#define PINMUX_GPIO165__FUNC_PWM_B (MTK_PIN_NO(165) | 1)
> >>>>> +#define PINMUX_GPIO165__FUNC_CMMCLK2 (MTK_PIN_NO(165) | 2)
> >>>>> +#define PINMUX_GPIO165__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(165) | 3)
> >>>>> +#define PINMUX_GPIO165__FUNC_TDM_MCK_2ND (MTK_PIN_NO(165) | 6)
> >>>>> +#define PINMUX_GPIO165__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(165) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
> >>>>> +#define PINMUX_GPIO166__FUNC_ANT_SEL6 (MTK_PIN_NO(166) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
> >>>>> +#define PINMUX_GPIO167__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(167) | 1)
> >>>>> +#define PINMUX_GPIO167__FUNC_SPM_BSI_EN (MTK_PIN_NO(167) | 2)
> >>>>> +
> >>>>> +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
> >>>>> +#define PINMUX_GPIO168__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(168) | 1)
> >>>>> +#define PINMUX_GPIO168__FUNC_SPM_BSI_CK (MTK_PIN_NO(168) | 2)
> >>>>> +
> >>>>> +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
> >>>>> +#define PINMUX_GPIO169__FUNC_PWM_C (MTK_PIN_NO(169) | 1)
> >>>>> +#define PINMUX_GPIO169__FUNC_CMMCLK3 (MTK_PIN_NO(169) | 2)
> >>>>> +#define PINMUX_GPIO169__FUNC_CMVREF1 (MTK_PIN_NO(169) | 3)
> >>>>> +#define PINMUX_GPIO169__FUNC_ANT_SEL7 (MTK_PIN_NO(169) | 4)
> >>>>> +#define PINMUX_GPIO169__FUNC_AGPS_SYNC (MTK_PIN_NO(169) | 5)
> >>>>> +#define PINMUX_GPIO169__FUNC_TDM_BCK_2ND (MTK_PIN_NO(169) | 6)
> >>>>> +#define PINMUX_GPIO169__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(169) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
> >>>>> +#define PINMUX_GPIO170__FUNC_I2S1_BCK (MTK_PIN_NO(170) | 1)
> >>>>> +#define PINMUX_GPIO170__FUNC_I2S3_BCK (MTK_PIN_NO(170) | 2)
> >>>>> +#define PINMUX_GPIO170__FUNC_SCL7 (MTK_PIN_NO(170) | 3)
> >>>>> +#define PINMUX_GPIO170__FUNC_I2S5_BCK (MTK_PIN_NO(170) | 4)
> >>>>> +#define PINMUX_GPIO170__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(170) | 5)
> >>>>> +#define PINMUX_GPIO170__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(170) | 6)
> >>>>> +#define PINMUX_GPIO170__FUNC_ANT_SEL3 (MTK_PIN_NO(170) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
> >>>>> +#define PINMUX_GPIO171__FUNC_I2S1_LRCK (MTK_PIN_NO(171) | 1)
> >>>>> +#define PINMUX_GPIO171__FUNC_I2S3_LRCK (MTK_PIN_NO(171) | 2)
> >>>>> +#define PINMUX_GPIO171__FUNC_SDA7 (MTK_PIN_NO(171) | 3)
> >>>>> +#define PINMUX_GPIO171__FUNC_I2S5_LRCK (MTK_PIN_NO(171) | 4)
> >>>>> +#define PINMUX_GPIO171__FUNC_URXD1 (MTK_PIN_NO(171) | 5)
> >>>>> +#define PINMUX_GPIO171__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(171) | 6)
> >>>>> +#define PINMUX_GPIO171__FUNC_ANT_SEL4 (MTK_PIN_NO(171) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
> >>>>> +#define PINMUX_GPIO172__FUNC_I2S1_DO (MTK_PIN_NO(172) | 1)
> >>>>> +#define PINMUX_GPIO172__FUNC_I2S3_DO (MTK_PIN_NO(172) | 2)
> >>>>> +#define PINMUX_GPIO172__FUNC_SCL8 (MTK_PIN_NO(172) | 3)
> >>>>> +#define PINMUX_GPIO172__FUNC_I2S5_DO (MTK_PIN_NO(172) | 4)
> >>>>> +#define PINMUX_GPIO172__FUNC_UTXD1 (MTK_PIN_NO(172) | 5)
> >>>>> +#define PINMUX_GPIO172__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(172) | 6)
> >>>>> +#define PINMUX_GPIO172__FUNC_ANT_SEL5 (MTK_PIN_NO(172) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
> >>>>> +#define PINMUX_GPIO173__FUNC_I2S1_MCK (MTK_PIN_NO(173) | 1)
> >>>>> +#define PINMUX_GPIO173__FUNC_I2S3_MCK (MTK_PIN_NO(173) | 2)
> >>>>> +#define PINMUX_GPIO173__FUNC_SDA8 (MTK_PIN_NO(173) | 3)
> >>>>> +#define PINMUX_GPIO173__FUNC_I2S5_MCK (MTK_PIN_NO(173) | 4)
> >>>>> +#define PINMUX_GPIO173__FUNC_UCTS0 (MTK_PIN_NO(173) | 5)
> >>>>> +#define PINMUX_GPIO173__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(173) | 6)
> >>>>> +#define PINMUX_GPIO173__FUNC_ANT_SEL6 (MTK_PIN_NO(173) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
> >>>>> +#define PINMUX_GPIO174__FUNC_I2S2_DI (MTK_PIN_NO(174) | 1)
> >>>>> +#define PINMUX_GPIO174__FUNC_I2S0_DI (MTK_PIN_NO(174) | 2)
> >>>>> +#define PINMUX_GPIO174__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(174) | 3)
> >>>>> +#define PINMUX_GPIO174__FUNC_I2S2_DI2 (MTK_PIN_NO(174) | 4)
> >>>>> +#define PINMUX_GPIO174__FUNC_URTS0 (MTK_PIN_NO(174) | 5)
> >>>>> +#define PINMUX_GPIO174__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(174) | 6)
> >>>>> +#define PINMUX_GPIO174__FUNC_ANT_SEL7 (MTK_PIN_NO(174) | 7)
> >>>>> +
> >>>>> +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
> >>>>> +#define PINMUX_GPIO175__FUNC_ANT_SEL7 (MTK_PIN_NO(175) | 1)
> >>>>> +
> >>>>> +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
> >>>>> +
> >>>>> +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
> >>>>> +
> >>>>> +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
> >>>>> +
> >>>>> +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
> >>>>> +
> >>>>> +#endif /* __MT8183-PINFUNC_H */
> >>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >>>>> new file mode 100644
> >>>>> index 0000000..63db9cc
> >>>>> --- /dev/null
> >>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >>>>> @@ -0,0 +1,408 @@
> >>>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >>>>> +/*
> >>>>> + * Copyright (c) 2018 MediaTek Inc.
> >>>>> + * Author: Ben Ho <ben.ho@mediatek.com>
> >>>>> + * Erin Lo <erin.lo@mediatek.com>
> >>>>> + */
> >>>>> +
> >>>>> +#include <dt-bindings/clock/mt8183-clk.h>
> >>>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> >>>>> +#include <dt-bindings/interrupt-controller/irq.h>
> >>>>> +#include "mt8183-pinfunc.h"
> >>>>> +
> >>>>> +/ {
> >>>>> + compatible = "mediatek,mt8183";
> >>>>> + interrupt-parent = <&sysirq>;
> >>>>> + #address-cells = <2>;
> >>>>> + #size-cells = <2>;
> >>>>> +
> >>>>> + cpus {
> >>>>> + #address-cells = <1>;
> >>>>> + #size-cells = <0>;
> >>>>> +
> >>>>> + cpu-map {
> >>>>> + cluster0 {
> >>>>> + core0 {
> >>>>> + cpu = <&cpu0>;
> >>>>> + };
> >>>>> + core1 {
> >>>>> + cpu = <&cpu1>;
> >>>>> + };
> >>>>> + core2 {
> >>>>> + cpu = <&cpu2>;
> >>>>> + };
> >>>>> + core3 {
> >>>>> + cpu = <&cpu3>;
> >>>>> + };
> >>>>> + };
> >>>>> +
> >>>>> + cluster1 {
> >>>>> + core0 {
> >>>>> + cpu = <&cpu4>;
> >>>>> + };
> >>>>> + core1 {
> >>>>> + cpu = <&cpu5>;
> >>>>> + };
> >>>>> + core2 {
> >>>>> + cpu = <&cpu6>;
> >>>>> + };
> >>>>> + core3 {
> >>>>> + cpu = <&cpu7>;
> >>>>> + };
> >>>>> + };
> >>>>> + };
> >>>>> +
> >>>>> + cpu0: cpu@0 {
> >>>>> + device_type = "cpu";
> >>>>> + compatible = "arm,cortex-a53";
> >>>>> + reg = <0x000>;
> >>>>> + enable-method = "psci";
> >>>>> + };
> >>>>> +
> >>>>> + cpu1: cpu@1 {
> >>>>> + device_type = "cpu";
> >>>>> + compatible = "arm,cortex-a53";
> >>>>> + reg = <0x001>;
> >>>>> + enable-method = "psci";
> >>>>> + };
> >>>>> +
> >>>>> + cpu2: cpu@2 {
> >>>>> + device_type = "cpu";
> >>>>> + compatible = "arm,cortex-a53";
> >>>>> + reg = <0x002>;
> >>>>> + enable-method = "psci";
> >>>>> + };
> >>>>> +
> >>>>> + cpu3: cpu@3 {
> >>>>> + device_type = "cpu";
> >>>>> + compatible = "arm,cortex-a53";
> >>>>> + reg = <0x003>;
> >>>>> + enable-method = "psci";
> >>>>> + };
> >>>>> +
> >>>>> + cpu4: cpu@100 {
> >>>>> + device_type = "cpu";
> >>>>> + compatible = "arm,cortex-a73";
> >>>>> + reg = <0x100>;
> >>>>> + enable-method = "psci";
> >>>>> + };
> >>>>> +
> >>>>> + cpu5: cpu@101 {
> >>>>> + device_type = "cpu";
> >>>>> + compatible = "arm,cortex-a73";
> >>>>> + reg = <0x101>;
> >>>>> + enable-method = "psci";
> >>>>> + };
> >>>>> +
> >>>>> + cpu6: cpu@102 {
> >>>>> + device_type = "cpu";
> >>>>> + compatible = "arm,cortex-a73";
> >>>>> + reg = <0x102>;
> >>>>> + enable-method = "psci";
> >>>>> + };
> >>>>> +
> >>>>> + cpu7: cpu@103 {
> >>>>> + device_type = "cpu";
> >>>>> + compatible = "arm,cortex-a73";
> >>>>> + reg = <0x103>;
> >>>>> + enable-method = "psci";
> >>>>> + };
> >>>>> + };
> >>>>> +
> >>>>> + pmu-a53 {
> >>>>> + compatible = "arm,cortex-a53-pmu";
> >>>>> + interrupt-parent = <&gic>;
> >>>>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
> >>>>> + };
> >>>>> +
> >>>>> + pmu-a73 {
> >>>>> + compatible = "arm,cortex-a73-pmu";
> >>>>> + interrupt-parent = <&gic>;
> >>>>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
> >>>>> + };
> >>>>> +
> >>>>> + psci {
> >>>>> + compatible = "arm,psci-1.0";
> >>>>> + method = "smc";
> >>>>> + };
> >>>>> +
> >>>>> + clk26m: oscillator {
> >>>>> + compatible = "fixed-clock";
> >>>>> + #clock-cells = <0>;
> >>>>> + clock-frequency = <26000000>;
> >>>>> + clock-output-names = "clk26m";
> >>>>> + };
> >>>>> +
> >>>>> + timer {
> >>>>> + compatible = "arm,armv8-timer";
> >>>>> + interrupt-parent = <&gic>;
> >>>>> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
> >>>>> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
> >>>>> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
> >>>>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
> >>>>> + };
> >>>>> +
> >>>>> + gic: interrupt-controller@c000000 {
> >>>>> + compatible = "arm,gic-v3";
> >>>>> + #interrupt-cells = <4>;
> >>>>> + interrupt-parent = <&gic>;
> >>>>> + interrupt-controller;
> >>>>> + reg = <0 0x0c000000 0 0x40000>, /* GICD */
> >>>>> + <0 0x0c100000 0 0x200000>, /* GICR */
> >>>>> + <0 0x0c400000 0 0x2000>, /* GICC */
> >>>>> + <0 0x0c410000 0 0x1000>, /* GICH */
> >>>>> + <0 0x0c420000 0 0x2000>; /* GICV */
> >>>>> +
> >>>>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> >>>>> + ppi-partitions {
> >>>>> + ppi_cluster0: interrupt-partition-0 {
> >>>>> + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
> >>>>> + };
> >>>>> + ppi_cluster1: interrupt-partition-1 {
> >>>>> + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
> >>>>> + };
> >>>>> + };
> >>>>> + };
> >>>>> +
> >>>>> + mcucfg: syscon@c530000 {
> >>>>> + compatible = "mediatek,mt8183-mcucfg", "syscon";
> >>>>> + reg = <0 0x0c530000 0 0x1000>;
> >>>>> + #clock-cells = <1>;
> >>>>> + };
> >>>>> +
> >>>>> + sysirq: intpol-controller@c530a80 {
> >>>>> + compatible = "mediatek,mt8183-sysirq",
> >>>>> + "mediatek,mt6577-sysirq";
> >>>>> + interrupt-controller;
> >>>>> + #interrupt-cells = <4>;
> >>>>> + interrupt-parent = <&gic>;
> >>>>> + reg = <0 0x0c530a80 0 0x50>;
> >>>>> + };
> >>>>> +
> >>>>> + topckgen: syscon@10000000 {
> >>>>> + compatible = "mediatek,mt8183-topckgen", "syscon";
> >>>>> + reg = <0 0x10000000 0 0x1000>;
> >>>>> + #clock-cells = <1>;
> >>>>> + };
> >>>>> +
> >>>>> + infracfg: syscon@10001000 {
> >>>>> + compatible = "mediatek,mt8183-infracfg", "syscon";
> >>>>> + reg = <0 0x10001000 0 0x1000>;
> >>>>> + #clock-cells = <1>;
> >>>>> + };
> >>>>> +
> >>>>> + pio: pinctrl@1000b000 {
> >>>>> + compatible = "mediatek,mt8183-pinctrl";
> >>>>> + reg = <0 0x10005000 0 0x1000>,
> >>>>> + <0 0x11f20000 0 0x1000>,
> >>>>> + <0 0x11e80000 0 0x1000>,
> >>>>> + <0 0x11e70000 0 0x1000>,
> >>>>> + <0 0x11e90000 0 0x1000>,
> >>>>> + <0 0x11d30000 0 0x1000>,
> >>>>> + <0 0x11d20000 0 0x1000>,
> >>>>> + <0 0x11c50000 0 0x1000>,
> >>>>> + <0 0x11f30000 0 0x1000>,
> >>>>> + <0 0x1000b000 0 0x1000>;
> >>>>> + reg-names = "iocfg0", "iocfg1", "iocfg2",
> >>>>> + "iocfg3", "iocfg4", "iocfg5",
> >>>>> + "iocfg6", "iocfg7", "iocfg8",
> >>>>> + "eint";
> >>>>> + gpio-controller;
> >>>>> + #gpio-cells = <2>;
> >>>>> + gpio-ranges = <&pio 0 0 192>;
> >>>>> + interrupt-controller;
> >>>>> + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>;
> >>>>> + interrupt-parent = <&gic>;
> >>>>> + #interrupt-cells = <4>;
> >>>>> + };
> >>>>> +
> >>>>> + apmixedsys: syscon@1000c000 {
> >>>>> + compatible = "mediatek,mt8183-apmixedsys", "syscon";
> >>>>> + reg = <0 0x1000c000 0 0x1000>;
> >>>>> + #clock-cells = <1>;
> >>>>> + };
> >>>>> +
> >>>>> + pwrap: pwrap@1000d000 {
> >>>>> + compatible = "mediatek,mt8183-pwrap";
> >>>>> + reg = <0 0x1000d000 0 0x1000>;
> >>>>> + reg-names = "pwrap";
> >>>>> + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 0>;
> >>>>> + clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
> >>>>> + <&infracfg CLK_INFRA_PMIC_AP>;
> >>>>> + clock-names = "spi", "wrap";
> >>>>> + };
> >>>>> +
> >>>>> + uart0: serial@11002000 {
> >>>>> + compatible = "mediatek,mt8183-uart",
> >>>>> + "mediatek,mt6577-uart";
> >>>>> + reg = <0 0x11002000 0 0x1000>;
> >>>>> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW 0>;
> >>>>> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
> >>>>> + clock-names = "baud", "bus";
> >>>>> + status = "disabled";
> >>>>> + };
> >>>>> +
> >>>>> + uart1: serial@11003000 {
> >>>>> + compatible = "mediatek,mt8183-uart",
> >>>>> + "mediatek,mt6577-uart";
> >>>>> + reg = <0 0x11003000 0 0x1000>;
> >>>>> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW 0>;
> >>>>> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
> >>>>> + clock-names = "baud", "bus";
> >>>>> + status = "disabled";
> >>>>> + };
> >>>>> +
> >>>>> + uart2: serial@11004000 {
> >>>>> + compatible = "mediatek,mt8183-uart",
> >>>>> + "mediatek,mt6577-uart";
> >>>>> + reg = <0 0x11004000 0 0x1000>;
> >>>>> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW 0>;
> >>>>> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
> >>>>> + clock-names = "baud", "bus";
> >>>>> + status = "disabled";
> >>>>> + };
> >>>>> +
> >>>>> + spi0: spi@1100a000 {
> >>>>> + compatible = "mediatek,mt8183-spi";
> >>>>> + #address-cells = <1>;
> >>>>> + #size-cells = <0>;
> >>>>> + reg = <0 0x1100a000 0 0x1000>;
> >>>>> + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW 0>;
> >>>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> >>>>> + <&topckgen CLK_TOP_MUX_SPI>,
> >>>>> + <&infracfg CLK_INFRA_SPI0>;
> >>>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> >>>>> + status = "disabled";
> >>>>> + };
> >>>>> +
> >>>>> + spi1: spi@11010000 {
> >>>>> + compatible = "mediatek,mt8183-spi";
> >>>>> + #address-cells = <1>;
> >>>>> + #size-cells = <0>;
> >>>>> + reg = <0 0x11010000 0 0x1000>;
> >>>>> + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW 0>;
> >>>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> >>>>> + <&topckgen CLK_TOP_MUX_SPI>,
> >>>>> + <&infracfg CLK_INFRA_SPI1>;
> >>>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> >>>>> + status = "disabled";
> >>>>> + };
> >>>>> +
> >>>>> + spi2: spi@11012000 {
> >>>>> + compatible = "mediatek,mt8183-spi";
> >>>>> + #address-cells = <1>;
> >>>>> + #size-cells = <0>;
> >>>>> + reg = <0 0x11012000 0 0x1000>;
> >>>>> + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW 0>;
> >>>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> >>>>> + <&topckgen CLK_TOP_MUX_SPI>,
> >>>>> + <&infracfg CLK_INFRA_SPI2>;
> >>>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> >>>>> + status = "disabled";
> >>>>> + };
> >>>>> +
> >>>>> + spi3: spi@11013000 {
> >>>>> + compatible = "mediatek,mt8183-spi";
> >>>>> + #address-cells = <1>;
> >>>>> + #size-cells = <0>;
> >>>>> + reg = <0 0x11013000 0 0x1000>;
> >>>>> + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW 0>;
> >>>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> >>>>> + <&topckgen CLK_TOP_MUX_SPI>,
> >>>>> + <&infracfg CLK_INFRA_SPI3>;
> >>>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> >>>>> + status = "disabled";
> >>>>> + };
> >>>>> +
> >>>>> + spi4: spi@11018000 {
> >>>>> + compatible = "mediatek,mt8183-spi";
> >>>>> + #address-cells = <1>;
> >>>>> + #size-cells = <0>;
> >>>>> + reg = <0 0x11018000 0 0x1000>;
> >>>>> + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW 0>;
> >>>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> >>>>> + <&topckgen CLK_TOP_MUX_SPI>,
> >>>>> + <&infracfg CLK_INFRA_SPI4>;
> >>>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> >>>>> + status = "disabled";
> >>>>> + };
> >>>>> +
> >>>>> + spi5: spi@11019000 {
> >>>>> + compatible = "mediatek,mt8183-spi";
> >>>>> + #address-cells = <1>;
> >>>>> + #size-cells = <0>;
> >>>>> + reg = <0 0x11019000 0 0x1000>;
> >>>>> + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW 0>;
> >>>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> >>>>> + <&topckgen CLK_TOP_MUX_SPI>,
> >>>>> + <&infracfg CLK_INFRA_SPI5>;
> >>>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> >>>>> + status = "disabled";
> >>>>> + };
> >>>>> +
> >>>>> + audiosys: syscon@11220000 {
> >>>>> + compatible = "mediatek,mt8183-audiosys", "syscon";
> >>>>> + reg = <0 0x11220000 0 0x1000>;
> >>>>> + #clock-cells = <1>;
> >>>>> + };
> >>>>> +
> >>>>> + mfgcfg: syscon@13000000 {
> >>>>> + compatible = "mediatek,mt8183-mfgcfg", "syscon";
> >>>>> + reg = <0 0x13000000 0 0x1000>;
> >>>>> + #clock-cells = <1>;
> >>>>> + };
> >>>>> +
> >>>>> + mmsys: syscon@14000000 {
> >>>>> + compatible = "mediatek,mt8183-mmsys", "syscon";
> >>>>> + reg = <0 0x14000000 0 0x1000>;
> >>>>> + #clock-cells = <1>;
> >>>>> + };
> >>>>> +
> >>>>> + imgsys: syscon@15020000 {
> >>>>> + compatible = "mediatek,mt8183-imgsys", "syscon";
> >>>>> + reg = <0 0x15020000 0 0x1000>;
> >>>>> + #clock-cells = <1>;
> >>>>> + };
> >>>>> +
> >>>>> + vdecsys: syscon@16000000 {
> >>>>> + compatible = "mediatek,mt8183-vdecsys", "syscon";
> >>>>> + reg = <0 0x16000000 0 0x1000>;
> >>>>> + #clock-cells = <1>;
> >>>>> + };
> >>>>> +
> >>>>> + vencsys: syscon@17000000 {
> >>>>> + compatible = "mediatek,mt8183-vencsys", "syscon";
> >>>>> + reg = <0 0x17000000 0 0x1000>;
> >>>>> + #clock-cells = <1>;
> >>>>> + };
> >>>>> +
> >>>>> + ipu_conn: syscon@19000000 {
> >>>>> + compatible = "mediatek,mt8183-ipu_conn", "syscon";
> >>>>> + reg = <0 0x19000000 0 0x1000>;
> >>>>> + #clock-cells = <1>;
> >>>>> + };
> >>>>> +
> >>>>> + ipu_adl: syscon@19010000 {
> >>>>> + compatible = "mediatek,mt8183-ipu_adl", "syscon";
> >>>>> + reg = <0 0x19010000 0 0x1000>;
> >>>>> + #clock-cells = <1>;
> >>>>> + };
> >>>>> +
> >>>>> + ipu_core0: syscon@19180000 {
> >>>>> + compatible = "mediatek,mt8183-ipu_core0", "syscon";
> >>>>> + reg = <0 0x19180000 0 0x1000>;
> >>>>> + #clock-cells = <1>;
> >>>>> + };
> >>>>> +
> >>>>> + ipu_core1: syscon@19280000 {
> >>>>> + compatible = "mediatek,mt8183-ipu_core1", "syscon";
> >>>>> + reg = <0 0x19280000 0 0x1000>;
> >>>>> + #clock-cells = <1>;
> >>>>> + };
> >>>>> +
> >>>>> + camsys: syscon@1a000000 {
> >>>>> + compatible = "mediatek,mt8183-camsys", "syscon";
> >>>>> + reg = <0 0x1a000000 0 0x1000>;
> >>>>> + #clock-cells = <1>;
> >>>>> + };
> >>>>> +};
> >>>>>
> >>>>
> >>>> _______________________________________________
> >>>> Linux-mediatek mailing list
> >>>> Linux-mediatek@lists.infradead.org
> >>>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
> >>>
> >>>
> >>
> >> _______________________________________________
> >> Linux-mediatek mailing list
> >> Linux-mediatek@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-mediatek
> >
> >
^ permalink raw reply
* Re: [PATCH v10 3/3] dt-bindings: dma: uart: rename binding
From: Matthias Brugger @ 2019-02-14 10:13 UTC (permalink / raw)
To: Long Cheng, Vinod Koul, Randy Dunlap, Rob Herring, Mark Rutland,
Ryder Lee, Sean Wang, Nicolas Boichat
Cc: Dan Williams, Greg Kroah-Hartman, Jiri Slaby, Sean Wang,
dmaengine, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, linux-serial, srv_heupstream, Yingjoe Chen, YT Shen,
Zhenbao Liu
In-Reply-To: <1547781016-890-4-git-send-email-long.cheng@mediatek.com>
On 18/01/2019 04:10, Long Cheng wrote:
> The filename matches mtk-uart-apdma.c.
> So using "mtk-uart-apdma.txt" should be better.
>
> Signed-off-by: Long Cheng <long.cheng@mediatek.com>
> ---
> .../devicetree/bindings/dma/8250_mtk_dma.txt | 33 --------------------
> .../devicetree/bindings/dma/mtk-uart-apdma.txt | 33 ++++++++++++++++++++
> 2 files changed, 33 insertions(+), 33 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/dma/8250_mtk_dma.txt
> create mode 100644 Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt
>
> diff --git a/Documentation/devicetree/bindings/dma/8250_mtk_dma.txt b/Documentation/devicetree/bindings/dma/8250_mtk_dma.txt
> deleted file mode 100644
> index 3fe0961..0000000
> --- a/Documentation/devicetree/bindings/dma/8250_mtk_dma.txt
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -* Mediatek UART APDMA Controller
> -
> -Required properties:
> -- compatible should contain:
> - * "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA
> - * "mediatek,mt6577-uart-dma" for MT6577 and all of the above
> -
> -- reg: The base address of the APDMA register bank.> -
> -- interrupts: A single interrupt specifier.
One interrupt per dma-request, or 8 if no dma-requests property is present.
> -
> -- clocks : Must contain an entry for each entry in clock-names.
> - See ../clocks/clock-bindings.txt for details.
> -- clock-names: The APDMA clock for register accesses> -
> -Examples:
> -
> - apdma: dma-controller@11000380 {
> - compatible = "mediatek,mt2712-uart-dma";
> - reg = <0 0x11000380 0 0x400>;
> - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_LOW>,
> - <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>,
> - <GIC_SPI 65 IRQ_TYPE_LEVEL_LOW>,
> - <GIC_SPI 66 IRQ_TYPE_LEVEL_LOW>,
> - <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>,
> - <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>,
> - <GIC_SPI 69 IRQ_TYPE_LEVEL_LOW>,
> - <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&pericfg CLK_PERI_AP_DMA>;
> - clock-names = "apdma";
> - #dma-cells = <1>;
> - };
> -
> diff --git a/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt b/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt
> new file mode 100644
> index 0000000..3fe0961
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt
> @@ -0,0 +1,33 @@
> +* Mediatek UART APDMA Controller
> +
> +Required properties:
> +- compatible should contain:
> + * "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA
> + * "mediatek,mt6577-uart-dma" for MT6577 and all of the above
> +
> +- reg: The base address of the APDMA register bank.
> +
There is one address needed for every dma-request or 8 if dma-requests property
is not present. As already mentioned in the driver review dma-requests property
is missing.
> +- interrupts: A single interrupt specifier.
> +
> +- clocks : Must contain an entry for each entry in clock-names.
> + See ../clocks/clock-bindings.txt for details.
> +- clock-names: The APDMA clock for register accesses
> +
Missing option property dma-33bits (should be mtk,dma-33bits?).
> +Examples:
> +
> + apdma: dma-controller@11000380 {
> + compatible = "mediatek,mt2712-uart-dma";
> + reg = <0 0x11000380 0 0x400>;
We are missing the io mem areas here, right?
Regards,
Matthias
> + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 65 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 66 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 69 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&pericfg CLK_PERI_AP_DMA>;
> + clock-names = "apdma";
> + #dma-cells = <1>;
> + };
> +
>
^ permalink raw reply
* Re: [PATCH v10 1/3] dmaengine: 8250_mtk_dma: add MediaTek uart DMA support
From: Matthias Brugger @ 2019-02-14 10:08 UTC (permalink / raw)
To: Long Cheng, Vinod Koul, Randy Dunlap, Rob Herring, Mark Rutland,
Ryder Lee, Sean Wang, Nicolas Boichat
Cc: Dan Williams, Greg Kroah-Hartman, Jiri Slaby, Sean Wang,
dmaengine, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, linux-serial, srv_heupstream, Yingjoe Chen, YT Shen,
Zhenbao Liu
In-Reply-To: <1547781016-890-2-git-send-email-long.cheng@mediatek.com>
On 18/01/2019 04:10, Long Cheng wrote:
> In DMA engine framework, add 8250 uart dma to support MediaTek uart.
> If MediaTek uart enabled(SERIAL_8250_MT6577), and want to improve
> the performance, can enable the function.
>
> Signed-off-by: Long Cheng <long.cheng@mediatek.com>
> ---
> drivers/dma/mediatek/Kconfig | 11 +
> drivers/dma/mediatek/Makefile | 1 +
> drivers/dma/mediatek/mtk-uart-apdma.c | 669 +++++++++++++++++++++++++++++++++
> 3 files changed, 681 insertions(+)
> create mode 100644 drivers/dma/mediatek/mtk-uart-apdma.c
>
[...]
> +
> +static int mtk_uart_apdma_probe(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct mtk_uart_apdmadev *mtkd;
> + struct resource *res;
> + struct mtk_chan *c;
> + int bit_mask = 32, rc;
> + unsigned int i;
> +
> + mtkd = devm_kzalloc(&pdev->dev, sizeof(*mtkd), GFP_KERNEL);
> + if (!mtkd)
> + return -ENOMEM;
> +
> + mtkd->clk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(mtkd->clk)) {
> + dev_err(&pdev->dev, "No clock specified\n");
> + rc = PTR_ERR(mtkd->clk);
> + return rc;
> + }
> +
> + if (of_property_read_bool(np, "dma-33bits"))
> + mtkd->support_33bits = true;
dma-33bits not defined in the binding description.
> +
> + if (mtkd->support_33bits)
> + bit_mask = 33;
> +
> + rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(bit_mask));
> + if (rc)
> + return rc;
> +
> + dma_cap_set(DMA_SLAVE, mtkd->ddev.cap_mask);
> + mtkd->ddev.device_alloc_chan_resources =
> + mtk_uart_apdma_alloc_chan_resources;
> + mtkd->ddev.device_free_chan_resources =
> + mtk_uart_apdma_free_chan_resources;
> + mtkd->ddev.device_tx_status = mtk_uart_apdma_tx_status;
> + mtkd->ddev.device_issue_pending = mtk_uart_apdma_issue_pending;
> + mtkd->ddev.device_prep_slave_sg = mtk_uart_apdma_prep_slave_sg;
> + mtkd->ddev.device_config = mtk_uart_apdma_slave_config;
> + mtkd->ddev.device_pause = mtk_uart_apdma_device_pause;
> + mtkd->ddev.device_terminate_all = mtk_uart_apdma_terminate_all;
> + mtkd->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE);
> + mtkd->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE);
> + mtkd->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
> + mtkd->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
> + mtkd->ddev.dev = &pdev->dev;
> + INIT_LIST_HEAD(&mtkd->ddev.channels);
> +
> + mtkd->dma_requests = MTK_UART_APDMA_NR_VCHANS;
Do this if dma-requests property is not present.
> + if (of_property_read_u32(np, "dma-requests", &mtkd->dma_requests)) {
It's quite obvious what this does, but IMHO it should be reflected in the binding.
Regards,
Matthias
> + dev_info(&pdev->dev,
> + "Using %u as missing dma-requests property\n",
> + MTK_UART_APDMA_NR_VCHANS);
> + }
> +
> + mtkd->dma_irq = devm_kcalloc(&pdev->dev, mtkd->dma_requests,
> + sizeof(*mtkd->dma_irq), GFP_KERNEL);
> + if (!mtkd->dma_irq)
> + return -ENOMEM;
> +
> + for (i = 0; i < mtkd->dma_requests; i++) {
> + c = devm_kzalloc(mtkd->ddev.dev, sizeof(*c), GFP_KERNEL);
> + if (!c) {
> + rc = -ENODEV;
> + goto err_no_dma;
> + }
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, i);
> + if (!res) {
> + rc = -ENODEV;
> + goto err_no_dma;
> + }
> +
> + c->base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(c->base)) {
> + rc = PTR_ERR(c->base);
> + goto err_no_dma;
> + }
> + c->requested = false;
> + c->vc.desc_free = mtk_uart_apdma_desc_free;
> + vchan_init(&c->vc, &mtkd->ddev);
> +
> + mtkd->dma_irq[i] = platform_get_irq(pdev, i);
> + if ((int)mtkd->dma_irq[i] < 0) {
> + dev_err(&pdev->dev, "failed to get IRQ[%d]\n", i);
> + rc = -EINVAL;
> + goto err_no_dma;
> + }
> + }
> +
> + pm_runtime_enable(&pdev->dev);
> + pm_runtime_set_active(&pdev->dev);
> +
> + rc = dma_async_device_register(&mtkd->ddev);
> + if (rc)
> + goto rpm_disable;
> +
> + platform_set_drvdata(pdev, mtkd);
> +
> + /* Device-tree DMA controller registration */
> + rc = of_dma_controller_register(np, of_dma_xlate_by_chan_id, mtkd);
> + if (rc)
> + goto dma_remove;
> +
> + return rc;
> +
> +dma_remove:
> + dma_async_device_unregister(&mtkd->ddev);
> +rpm_disable:
> + pm_runtime_disable(&pdev->dev);
> +err_no_dma:
> + mtk_uart_apdma_free(mtkd);
> + return rc;
> +}
> +
> +static int mtk_uart_apdma_remove(struct platform_device *pdev)
> +{
> + struct mtk_uart_apdmadev *mtkd = platform_get_drvdata(pdev);
> +
> + if (pdev->dev.of_node)
> + of_dma_controller_free(pdev->dev.of_node);
> +
> + pm_runtime_disable(&pdev->dev);
> + pm_runtime_put_noidle(&pdev->dev);
> +
> + dma_async_device_unregister(&mtkd->ddev);
> + mtk_uart_apdma_free(mtkd);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int mtk_uart_apdma_suspend(struct device *dev)
> +{
> + struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev);
> +
> + if (!pm_runtime_suspended(dev))
> + clk_disable_unprepare(mtkd->clk);
> +
> + return 0;
> +}
> +
> +static int mtk_uart_apdma_resume(struct device *dev)
> +{
> + int ret;
> + struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev);
> +
> + if (!pm_runtime_suspended(dev)) {
> + ret = clk_prepare_enable(mtkd->clk);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +#endif /* CONFIG_PM_SLEEP */
> +
> +#ifdef CONFIG_PM
> +static int mtk_uart_apdma_runtime_suspend(struct device *dev)
> +{
> + struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(mtkd->clk);
> +
> + return 0;
> +}
> +
> +static int mtk_uart_apdma_runtime_resume(struct device *dev)
> +{
> + int ret;
> + struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev);
> +
> + ret = clk_prepare_enable(mtkd->clk);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +#endif /* CONFIG_PM */
> +
> +static const struct dev_pm_ops mtk_uart_apdma_pm_ops = {
> + SET_SYSTEM_SLEEP_PM_OPS(mtk_uart_apdma_suspend, mtk_uart_apdma_resume)
> + SET_RUNTIME_PM_OPS(mtk_uart_apdma_runtime_suspend,
> + mtk_uart_apdma_runtime_resume, NULL)
> +};
> +
> +static struct platform_driver mtk_uart_apdma_driver = {
> + .probe = mtk_uart_apdma_probe,
> + .remove = mtk_uart_apdma_remove,
> + .driver = {
> + .name = KBUILD_MODNAME,
> + .pm = &mtk_uart_apdma_pm_ops,
> + .of_match_table = of_match_ptr(mtk_uart_apdma_match),
> + },
> +};
> +
> +module_platform_driver(mtk_uart_apdma_driver);
> +
> +MODULE_DESCRIPTION("MediaTek UART APDMA Controller Driver");
> +MODULE_AUTHOR("Long Cheng <long.cheng@mediatek.com>");
> +MODULE_LICENSE("GPL v2");
> +
>
^ permalink raw reply
* Re: [PATCH v6 6/6] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile
From: Matthias Brugger @ 2019-02-14 9:01 UTC (permalink / raw)
To: Erin Lo
Cc: Mark Rutland, Ben Ho, mars.cheng, Mengqi Zhang, linux-clk,
Hsin-Hsiung Wang, Weiyi Lu, Seiya Wang, linux-serial,
yingjoe.chen, devicetree, Jason Cooper, Marc Zyngier, Rob Herring,
linux-mediatek, Thomas Gleixner, eddie.huang, linux-arm-kernel,
srv_heupstream, Greg Kroah-Hartman, Stephen Boyd, linux-kernel,
Zhiyong Tao
In-Reply-To: <1550122026.21510.6.camel@mtksdaap41>
On 14/02/2019 06:27, Erin Lo wrote:
> On Wed, 2019-02-13 at 15:54 +0100, Matthias Brugger wrote:
>>
>> On 13/02/2019 10:03, Erin Lo wrote:
>>> On Thu, 2019-02-07 at 16:30 +0100, Matthias Brugger wrote:
>>>>
>>>> On 24/01/2019 09:07, Erin Lo wrote:
>>>>> From: Ben Ho <Ben.Ho@mediatek.com>
>>>>>
>>>>> Add basic chip support for Mediatek 8183, include
>>>>> pinctrl file, uart node with correct uart clocks, pwrap device
>>>>>
>>>>> Add clock controller nodes, include topckgen, infracfg,
>>>>> apmixedsys and subsystem.
>>>>>
>>>>> Signed-off-by: Ben Ho <Ben.Ho@mediatek.com>
>>>>> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
>>>>> Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
>>>>> Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
>>>>> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
>>>>> Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
>>>>> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
>>>>> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
>>>>> ---
>>>>> arch/arm64/boot/dts/mediatek/Makefile | 1 +
>>>>> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 136 +++
>>>>> arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h | 1120 +++++++++++++++++++++++++
>>>>
>>>> Would you mind to make the pinfunc.h a seperate patch and adding the pinctrl
>>>> maintainers to the list.
>>>>
>>>> Regards,
>>>> Matthias
>>>>
>>>
>>> OK! I will take pinfunc.h out of this series.
>>
>> My take would be to somehow change this series in something like.
>> One patch which adds basic support for the SoC without any dependencies on other
>> series.
>> Every node that has a dependency on a different series should go in a separate
>> patch. In this case IMHO pinfunc.h can got with the dts node in one patch.
>>
>> Regards,
>> Matthias
>>
>
> I will separate this patch into 3 patches : basic support for the SoC,
> mt8183-pinfunc.h, and spi node.
>
> Is that OK?
> Is it ok, if pinctrl@1000b000 is included in basic node?
>
Why do you want to do that? Without the pinfunc.h I can't take it independently,
right?
Regards,
Matthias
> Best Regards.
> Erin
>
>>>
>>> Best Regards,
>>> Erin
>>>
>>>>> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 408 +++++++++
>>>>> 4 files changed, 1665 insertions(+)
>>>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts
>>>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
>>>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
>>>>> index e8f952f..458bbc4 100644
>>>>> --- a/arch/arm64/boot/dts/mediatek/Makefile
>>>>> +++ b/arch/arm64/boot/dts/mediatek/Makefile
>>>>> @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
>>>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
>>>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
>>>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
>>>>> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
>>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
>>>>> new file mode 100644
>>>>> index 0000000..b12c6ea
>>>>> --- /dev/null
>>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
>>>>> @@ -0,0 +1,136 @@
>>>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>>>> +/*
>>>>> + * Copyright (c) 2018 MediaTek Inc.
>>>>> + * Author: Ben Ho <ben.ho@mediatek.com>
>>>>> + * Erin Lo <erin.lo@mediatek.com>
>>>>> + */
>>>>> +
>>>>> +/dts-v1/;
>>>>> +#include "mt8183.dtsi"
>>>>> +
>>>>> +/ {
>>>>> + model = "MediaTek MT8183 evaluation board";
>>>>> + compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
>>>>> +
>>>>> + aliases {
>>>>> + serial0 = &uart0;
>>>>> + };
>>>>> +
>>>>> + memory@40000000 {
>>>>> + device_type = "memory";
>>>>> + reg = <0 0x40000000 0 0x80000000>;
>>>>> + };
>>>>> +
>>>>> + chosen {
>>>>> + stdout-path = "serial0:921600n8";
>>>>> + };
>>>>> +};
>>>>> +
>>>>> +&pio {
>>>>> + spi_pins_0: spi0{
>>>>> + pins_spi{
>>>>> + pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
>>>>> + <PINMUX_GPIO86__FUNC_SPI0_CSB>,
>>>>> + <PINMUX_GPIO87__FUNC_SPI0_MO>,
>>>>> + <PINMUX_GPIO88__FUNC_SPI0_CLK>;
>>>>> + bias-disable;
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + spi_pins_1: spi1{
>>>>> + pins_spi{
>>>>> + pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
>>>>> + <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
>>>>> + <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
>>>>> + <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
>>>>> + bias-disable;
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + spi_pins_2: spi2{
>>>>> + pins_spi{
>>>>> + pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
>>>>> + <PINMUX_GPIO1__FUNC_SPI2_MO>,
>>>>> + <PINMUX_GPIO2__FUNC_SPI2_CLK>,
>>>>> + <PINMUX_GPIO94__FUNC_SPI2_MI>;
>>>>> + bias-disable;
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + spi_pins_3: spi3{
>>>>> + pins_spi{
>>>>> + pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
>>>>> + <PINMUX_GPIO22__FUNC_SPI3_CSB>,
>>>>> + <PINMUX_GPIO23__FUNC_SPI3_MO>,
>>>>> + <PINMUX_GPIO24__FUNC_SPI3_CLK>;
>>>>> + bias-disable;
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + spi_pins_4: spi4{
>>>>> + pins_spi{
>>>>> + pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
>>>>> + <PINMUX_GPIO18__FUNC_SPI4_CSB>,
>>>>> + <PINMUX_GPIO19__FUNC_SPI4_MO>,
>>>>> + <PINMUX_GPIO20__FUNC_SPI4_CLK>;
>>>>> + bias-disable;
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + spi_pins_5: spi5{
>>>>> + pins_spi{
>>>>> + pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
>>>>> + <PINMUX_GPIO14__FUNC_SPI5_CSB>,
>>>>> + <PINMUX_GPIO15__FUNC_SPI5_MO>,
>>>>> + <PINMUX_GPIO16__FUNC_SPI5_CLK>;
>>>>> + bias-disable;
>>>>> + };
>>>>> + };
>>>>> +};
>>>>> +
>>>>> +&spi0 {
>>>>> + pinctrl-names = "default";
>>>>> + pinctrl-0 = <&spi_pins_0>;
>>>>> + mediatek,pad-select = <0>;
>>>>> + status = "okay";
>>>>> +};
>>>>> +
>>>>> +&spi1 {
>>>>> + pinctrl-names = "default";
>>>>> + pinctrl-0 = <&spi_pins_1>;
>>>>> + mediatek,pad-select = <0>;
>>>>> + status = "okay";
>>>>> +};
>>>>> +
>>>>> +&spi2 {
>>>>> + pinctrl-names = "default";
>>>>> + pinctrl-0 = <&spi_pins_2>;
>>>>> + mediatek,pad-select = <0>;
>>>>> + status = "okay";
>>>>> +};
>>>>> +
>>>>> +&spi3 {
>>>>> + pinctrl-names = "default";
>>>>> + pinctrl-0 = <&spi_pins_3>;
>>>>> + mediatek,pad-select = <0>;
>>>>> + status = "okay";
>>>>> +};
>>>>> +
>>>>> +&spi4 {
>>>>> + pinctrl-names = "default";
>>>>> + pinctrl-0 = <&spi_pins_4>;
>>>>> + mediatek,pad-select = <0>;
>>>>> + status = "okay";
>>>>> +};
>>>>> +
>>>>> +&spi5 {
>>>>> + pinctrl-names = "default";
>>>>> + pinctrl-0 = <&spi_pins_5>;
>>>>> + mediatek,pad-select = <0>;
>>>>> + status = "okay";
>>>>> +
>>>>> +};
>>>>> +
>>>>> +&uart0 {
>>>>> + status = "okay";
>>>>> +};
>>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
>>>>> new file mode 100644
>>>>> index 0000000..768e41e
>>>>> --- /dev/null
>>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
>>>>> @@ -0,0 +1,1120 @@
>>>>> +// SPDX-License-Identifier: GPL-2.0
>>>>> +/*
>>>>> + * Copyright (C) 2018 MediaTek Inc.
>>>>> + * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
>>>>> + *
>>>>> + */
>>>>> +
>>>>> +#ifndef __MT8183_PINFUNC_H
>>>>> +#define __MT8183_PINFUNC_H
>>>>> +
>>>>> +#include <dt-bindings/pinctrl/mt65xx.h>
>>>>> +
>>>>> +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
>>>>> +#define PINMUX_GPIO0__FUNC_MRG_SYNC (MTK_PIN_NO(0) | 1)
>>>>> +#define PINMUX_GPIO0__FUNC_PCM0_SYNC (MTK_PIN_NO(0) | 2)
>>>>> +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 3)
>>>>> +#define PINMUX_GPIO0__FUNC_SRCLKENAI0 (MTK_PIN_NO(0) | 4)
>>>>> +#define PINMUX_GPIO0__FUNC_SCP_SPI2_CS (MTK_PIN_NO(0) | 5)
>>>>> +#define PINMUX_GPIO0__FUNC_I2S3_MCK (MTK_PIN_NO(0) | 6)
>>>>> +#define PINMUX_GPIO0__FUNC_SPI2_CSB (MTK_PIN_NO(0) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
>>>>> +#define PINMUX_GPIO1__FUNC_MRG_CLK (MTK_PIN_NO(1) | 1)
>>>>> +#define PINMUX_GPIO1__FUNC_PCM0_CLK (MTK_PIN_NO(1) | 2)
>>>>> +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 3)
>>>>> +#define PINMUX_GPIO1__FUNC_CLKM3 (MTK_PIN_NO(1) | 4)
>>>>> +#define PINMUX_GPIO1__FUNC_SCP_SPI2_MO (MTK_PIN_NO(1) | 5)
>>>>> +#define PINMUX_GPIO1__FUNC_I2S3_BCK (MTK_PIN_NO(1) | 6)
>>>>> +#define PINMUX_GPIO1__FUNC_SPI2_MO (MTK_PIN_NO(1) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
>>>>> +#define PINMUX_GPIO2__FUNC_MRG_DO (MTK_PIN_NO(2) | 1)
>>>>> +#define PINMUX_GPIO2__FUNC_PCM0_DO (MTK_PIN_NO(2) | 2)
>>>>> +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 3)
>>>>> +#define PINMUX_GPIO2__FUNC_SCL6 (MTK_PIN_NO(2) | 4)
>>>>> +#define PINMUX_GPIO2__FUNC_SCP_SPI2_CK (MTK_PIN_NO(2) | 5)
>>>>> +#define PINMUX_GPIO2__FUNC_I2S3_LRCK (MTK_PIN_NO(2) | 6)
>>>>> +#define PINMUX_GPIO2__FUNC_SPI2_CLK (MTK_PIN_NO(2) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
>>>>> +#define PINMUX_GPIO3__FUNC_MRG_DI (MTK_PIN_NO(3) | 1)
>>>>> +#define PINMUX_GPIO3__FUNC_PCM0_DI (MTK_PIN_NO(3) | 2)
>>>>> +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 3)
>>>>> +#define PINMUX_GPIO3__FUNC_SDA6 (MTK_PIN_NO(3) | 4)
>>>>> +#define PINMUX_GPIO3__FUNC_TDM_MCK (MTK_PIN_NO(3) | 5)
>>>>> +#define PINMUX_GPIO3__FUNC_I2S3_DO (MTK_PIN_NO(3) | 6)
>>>>> +#define PINMUX_GPIO3__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(3) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
>>>>> +#define PINMUX_GPIO4__FUNC_PWM_B (MTK_PIN_NO(4) | 1)
>>>>> +#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2)
>>>>> +#define PINMUX_GPIO4__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(4) | 3)
>>>>> +#define PINMUX_GPIO4__FUNC_MD_URXD1 (MTK_PIN_NO(4) | 4)
>>>>> +#define PINMUX_GPIO4__FUNC_TDM_BCK (MTK_PIN_NO(4) | 5)
>>>>> +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6)
>>>>> +#define PINMUX_GPIO4__FUNC_DAP_MD32_SWD (MTK_PIN_NO(4) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
>>>>> +#define PINMUX_GPIO5__FUNC_PWM_C (MTK_PIN_NO(5) | 1)
>>>>> +#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2)
>>>>> +#define PINMUX_GPIO5__FUNC_SSPM_URXD_AO (MTK_PIN_NO(5) | 3)
>>>>> +#define PINMUX_GPIO5__FUNC_MD_UTXD1 (MTK_PIN_NO(5) | 4)
>>>>> +#define PINMUX_GPIO5__FUNC_TDM_LRCK (MTK_PIN_NO(5) | 5)
>>>>> +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6)
>>>>> +#define PINMUX_GPIO5__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(5) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
>>>>> +#define PINMUX_GPIO6__FUNC_PWM_A (MTK_PIN_NO(6) | 1)
>>>>> +#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2)
>>>>> +#define PINMUX_GPIO6__FUNC_IDDIG (MTK_PIN_NO(6) | 3)
>>>>> +#define PINMUX_GPIO6__FUNC_MD_URXD0 (MTK_PIN_NO(6) | 4)
>>>>> +#define PINMUX_GPIO6__FUNC_TDM_DATA0 (MTK_PIN_NO(6) | 5)
>>>>> +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6)
>>>>> +#define PINMUX_GPIO6__FUNC_CMFLASH (MTK_PIN_NO(6) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
>>>>> +#define PINMUX_GPIO7__FUNC_SPI1_B_MI (MTK_PIN_NO(7) | 1)
>>>>> +#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2)
>>>>> +#define PINMUX_GPIO7__FUNC_USB_DRVVBUS (MTK_PIN_NO(7) | 3)
>>>>> +#define PINMUX_GPIO7__FUNC_MD_UTXD0 (MTK_PIN_NO(7) | 4)
>>>>> +#define PINMUX_GPIO7__FUNC_TDM_DATA1 (MTK_PIN_NO(7) | 5)
>>>>> +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6)
>>>>> +#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
>>>>> +#define PINMUX_GPIO8__FUNC_SPI1_B_CSB (MTK_PIN_NO(8) | 1)
>>>>> +#define PINMUX_GPIO8__FUNC_ANT_SEL3 (MTK_PIN_NO(8) | 2)
>>>>> +#define PINMUX_GPIO8__FUNC_SCL7 (MTK_PIN_NO(8) | 3)
>>>>> +#define PINMUX_GPIO8__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(8) | 4)
>>>>> +#define PINMUX_GPIO8__FUNC_TDM_DATA2 (MTK_PIN_NO(8) | 5)
>>>>> +#define PINMUX_GPIO8__FUNC_MD_INT0 (MTK_PIN_NO(8) | 6)
>>>>> +#define PINMUX_GPIO8__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(8) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
>>>>> +#define PINMUX_GPIO9__FUNC_SPI1_B_MO (MTK_PIN_NO(9) | 1)
>>>>> +#define PINMUX_GPIO9__FUNC_ANT_SEL4 (MTK_PIN_NO(9) | 2)
>>>>> +#define PINMUX_GPIO9__FUNC_CMMCLK2 (MTK_PIN_NO(9) | 3)
>>>>> +#define PINMUX_GPIO9__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(9) | 4)
>>>>> +#define PINMUX_GPIO9__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(9) | 5)
>>>>> +#define PINMUX_GPIO9__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(9) | 6)
>>>>> +#define PINMUX_GPIO9__FUNC_DBG_MON_B10 (MTK_PIN_NO(9) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
>>>>> +#define PINMUX_GPIO10__FUNC_SPI1_B_CLK (MTK_PIN_NO(10) | 1)
>>>>> +#define PINMUX_GPIO10__FUNC_ANT_SEL5 (MTK_PIN_NO(10) | 2)
>>>>> +#define PINMUX_GPIO10__FUNC_CMMCLK3 (MTK_PIN_NO(10) | 3)
>>>>> +#define PINMUX_GPIO10__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(10) | 4)
>>>>> +#define PINMUX_GPIO10__FUNC_TDM_DATA3 (MTK_PIN_NO(10) | 5)
>>>>> +#define PINMUX_GPIO10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 6)
>>>>> +#define PINMUX_GPIO10__FUNC_DBG_MON_B11 (MTK_PIN_NO(10) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
>>>>> +#define PINMUX_GPIO11__FUNC_TP_URXD1_AO (MTK_PIN_NO(11) | 1)
>>>>> +#define PINMUX_GPIO11__FUNC_IDDIG (MTK_PIN_NO(11) | 2)
>>>>> +#define PINMUX_GPIO11__FUNC_SCL6 (MTK_PIN_NO(11) | 3)
>>>>> +#define PINMUX_GPIO11__FUNC_UCTS1 (MTK_PIN_NO(11) | 4)
>>>>> +#define PINMUX_GPIO11__FUNC_UCTS0 (MTK_PIN_NO(11) | 5)
>>>>> +#define PINMUX_GPIO11__FUNC_SRCLKENAI1 (MTK_PIN_NO(11) | 6)
>>>>> +#define PINMUX_GPIO11__FUNC_I2S5_MCK (MTK_PIN_NO(11) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
>>>>> +#define PINMUX_GPIO12__FUNC_TP_UTXD1_AO (MTK_PIN_NO(12) | 1)
>>>>> +#define PINMUX_GPIO12__FUNC_USB_DRVVBUS (MTK_PIN_NO(12) | 2)
>>>>> +#define PINMUX_GPIO12__FUNC_SDA6 (MTK_PIN_NO(12) | 3)
>>>>> +#define PINMUX_GPIO12__FUNC_URTS1 (MTK_PIN_NO(12) | 4)
>>>>> +#define PINMUX_GPIO12__FUNC_URTS0 (MTK_PIN_NO(12) | 5)
>>>>> +#define PINMUX_GPIO12__FUNC_I2S2_DI2 (MTK_PIN_NO(12) | 6)
>>>>> +#define PINMUX_GPIO12__FUNC_I2S5_BCK (MTK_PIN_NO(12) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
>>>>> +#define PINMUX_GPIO13__FUNC_DBPI_D0 (MTK_PIN_NO(13) | 1)
>>>>> +#define PINMUX_GPIO13__FUNC_SPI5_MI (MTK_PIN_NO(13) | 2)
>>>>> +#define PINMUX_GPIO13__FUNC_PCM0_SYNC (MTK_PIN_NO(13) | 3)
>>>>> +#define PINMUX_GPIO13__FUNC_MD_URXD0 (MTK_PIN_NO(13) | 4)
>>>>> +#define PINMUX_GPIO13__FUNC_ANT_SEL3 (MTK_PIN_NO(13) | 5)
>>>>> +#define PINMUX_GPIO13__FUNC_I2S0_MCK (MTK_PIN_NO(13) | 6)
>>>>> +#define PINMUX_GPIO13__FUNC_DBG_MON_B15 (MTK_PIN_NO(13) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
>>>>> +#define PINMUX_GPIO14__FUNC_DBPI_D1 (MTK_PIN_NO(14) | 1)
>>>>> +#define PINMUX_GPIO14__FUNC_SPI5_CSB (MTK_PIN_NO(14) | 2)
>>>>> +#define PINMUX_GPIO14__FUNC_PCM0_CLK (MTK_PIN_NO(14) | 3)
>>>>> +#define PINMUX_GPIO14__FUNC_MD_UTXD0 (MTK_PIN_NO(14) | 4)
>>>>> +#define PINMUX_GPIO14__FUNC_ANT_SEL4 (MTK_PIN_NO(14) | 5)
>>>>> +#define PINMUX_GPIO14__FUNC_I2S0_BCK (MTK_PIN_NO(14) | 6)
>>>>> +#define PINMUX_GPIO14__FUNC_DBG_MON_B16 (MTK_PIN_NO(14) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
>>>>> +#define PINMUX_GPIO15__FUNC_DBPI_D2 (MTK_PIN_NO(15) | 1)
>>>>> +#define PINMUX_GPIO15__FUNC_SPI5_MO (MTK_PIN_NO(15) | 2)
>>>>> +#define PINMUX_GPIO15__FUNC_PCM0_DO (MTK_PIN_NO(15) | 3)
>>>>> +#define PINMUX_GPIO15__FUNC_MD_URXD1 (MTK_PIN_NO(15) | 4)
>>>>> +#define PINMUX_GPIO15__FUNC_ANT_SEL5 (MTK_PIN_NO(15) | 5)
>>>>> +#define PINMUX_GPIO15__FUNC_I2S0_LRCK (MTK_PIN_NO(15) | 6)
>>>>> +#define PINMUX_GPIO15__FUNC_DBG_MON_B17 (MTK_PIN_NO(15) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
>>>>> +#define PINMUX_GPIO16__FUNC_DBPI_D3 (MTK_PIN_NO(16) | 1)
>>>>> +#define PINMUX_GPIO16__FUNC_SPI5_CLK (MTK_PIN_NO(16) | 2)
>>>>> +#define PINMUX_GPIO16__FUNC_PCM0_DI (MTK_PIN_NO(16) | 3)
>>>>> +#define PINMUX_GPIO16__FUNC_MD_UTXD1 (MTK_PIN_NO(16) | 4)
>>>>> +#define PINMUX_GPIO16__FUNC_ANT_SEL6 (MTK_PIN_NO(16) | 5)
>>>>> +#define PINMUX_GPIO16__FUNC_I2S0_DI (MTK_PIN_NO(16) | 6)
>>>>> +#define PINMUX_GPIO16__FUNC_DBG_MON_B23 (MTK_PIN_NO(16) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
>>>>> +#define PINMUX_GPIO17__FUNC_DBPI_D4 (MTK_PIN_NO(17) | 1)
>>>>> +#define PINMUX_GPIO17__FUNC_SPI4_MI (MTK_PIN_NO(17) | 2)
>>>>> +#define PINMUX_GPIO17__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(17) | 3)
>>>>> +#define PINMUX_GPIO17__FUNC_MD_INT0 (MTK_PIN_NO(17) | 4)
>>>>> +#define PINMUX_GPIO17__FUNC_ANT_SEL7 (MTK_PIN_NO(17) | 5)
>>>>> +#define PINMUX_GPIO17__FUNC_I2S3_MCK (MTK_PIN_NO(17) | 6)
>>>>> +#define PINMUX_GPIO17__FUNC_DBG_MON_A1 (MTK_PIN_NO(17) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
>>>>> +#define PINMUX_GPIO18__FUNC_DBPI_D5 (MTK_PIN_NO(18) | 1)
>>>>> +#define PINMUX_GPIO18__FUNC_SPI4_CSB (MTK_PIN_NO(18) | 2)
>>>>> +#define PINMUX_GPIO18__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(18) | 3)
>>>>> +#define PINMUX_GPIO18__FUNC_MD_INT0 (MTK_PIN_NO(18) | 4)
>>>>> +#define PINMUX_GPIO18__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(18) | 5)
>>>>> +#define PINMUX_GPIO18__FUNC_I2S3_BCK (MTK_PIN_NO(18) | 6)
>>>>> +#define PINMUX_GPIO18__FUNC_DBG_MON_A2 (MTK_PIN_NO(18) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
>>>>> +#define PINMUX_GPIO19__FUNC_DBPI_D6 (MTK_PIN_NO(19) | 1)
>>>>> +#define PINMUX_GPIO19__FUNC_SPI4_MO (MTK_PIN_NO(19) | 2)
>>>>> +#define PINMUX_GPIO19__FUNC_CONN_MCU_TDO (MTK_PIN_NO(19) | 3)
>>>>> +#define PINMUX_GPIO19__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(19) | 4)
>>>>> +#define PINMUX_GPIO19__FUNC_URXD1 (MTK_PIN_NO(19) | 5)
>>>>> +#define PINMUX_GPIO19__FUNC_I2S3_LRCK (MTK_PIN_NO(19) | 6)
>>>>> +#define PINMUX_GPIO19__FUNC_DBG_MON_A3 (MTK_PIN_NO(19) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
>>>>> +#define PINMUX_GPIO20__FUNC_DBPI_D7 (MTK_PIN_NO(20) | 1)
>>>>> +#define PINMUX_GPIO20__FUNC_SPI4_CLK (MTK_PIN_NO(20) | 2)
>>>>> +#define PINMUX_GPIO20__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(20) | 3)
>>>>> +#define PINMUX_GPIO20__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(20) | 4)
>>>>> +#define PINMUX_GPIO20__FUNC_UTXD1 (MTK_PIN_NO(20) | 5)
>>>>> +#define PINMUX_GPIO20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 6)
>>>>> +#define PINMUX_GPIO20__FUNC_DBG_MON_A19 (MTK_PIN_NO(20) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
>>>>> +#define PINMUX_GPIO21__FUNC_DBPI_D8 (MTK_PIN_NO(21) | 1)
>>>>> +#define PINMUX_GPIO21__FUNC_SPI3_MI (MTK_PIN_NO(21) | 2)
>>>>> +#define PINMUX_GPIO21__FUNC_CONN_MCU_TMS (MTK_PIN_NO(21) | 3)
>>>>> +#define PINMUX_GPIO21__FUNC_DAP_MD32_SWD (MTK_PIN_NO(21) | 4)
>>>>> +#define PINMUX_GPIO21__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(21) | 5)
>>>>> +#define PINMUX_GPIO21__FUNC_I2S2_MCK (MTK_PIN_NO(21) | 6)
>>>>> +#define PINMUX_GPIO21__FUNC_DBG_MON_B5 (MTK_PIN_NO(21) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
>>>>> +#define PINMUX_GPIO22__FUNC_DBPI_D9 (MTK_PIN_NO(22) | 1)
>>>>> +#define PINMUX_GPIO22__FUNC_SPI3_CSB (MTK_PIN_NO(22) | 2)
>>>>> +#define PINMUX_GPIO22__FUNC_CONN_MCU_TCK (MTK_PIN_NO(22) | 3)
>>>>> +#define PINMUX_GPIO22__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(22) | 4)
>>>>> +#define PINMUX_GPIO22__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(22) | 5)
>>>>> +#define PINMUX_GPIO22__FUNC_I2S2_BCK (MTK_PIN_NO(22) | 6)
>>>>> +#define PINMUX_GPIO22__FUNC_DBG_MON_B6 (MTK_PIN_NO(22) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
>>>>> +#define PINMUX_GPIO23__FUNC_DBPI_D10 (MTK_PIN_NO(23) | 1)
>>>>> +#define PINMUX_GPIO23__FUNC_SPI3_MO (MTK_PIN_NO(23) | 2)
>>>>> +#define PINMUX_GPIO23__FUNC_CONN_MCU_TDI (MTK_PIN_NO(23) | 3)
>>>>> +#define PINMUX_GPIO23__FUNC_UCTS1 (MTK_PIN_NO(23) | 4)
>>>>> +#define PINMUX_GPIO23__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5)
>>>>> +#define PINMUX_GPIO23__FUNC_I2S2_LRCK (MTK_PIN_NO(23) | 6)
>>>>> +#define PINMUX_GPIO23__FUNC_DBG_MON_B7 (MTK_PIN_NO(23) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
>>>>> +#define PINMUX_GPIO24__FUNC_DBPI_D11 (MTK_PIN_NO(24) | 1)
>>>>> +#define PINMUX_GPIO24__FUNC_SPI3_CLK (MTK_PIN_NO(24) | 2)
>>>>> +#define PINMUX_GPIO24__FUNC_SRCLKENAI0 (MTK_PIN_NO(24) | 3)
>>>>> +#define PINMUX_GPIO24__FUNC_URTS1 (MTK_PIN_NO(24) | 4)
>>>>> +#define PINMUX_GPIO24__FUNC_IO_JTAG_TCK (MTK_PIN_NO(24) | 5)
>>>>> +#define PINMUX_GPIO24__FUNC_I2S2_DI (MTK_PIN_NO(24) | 6)
>>>>> +#define PINMUX_GPIO24__FUNC_DBG_MON_B31 (MTK_PIN_NO(24) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
>>>>> +#define PINMUX_GPIO25__FUNC_DBPI_HSYNC (MTK_PIN_NO(25) | 1)
>>>>> +#define PINMUX_GPIO25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 2)
>>>>> +#define PINMUX_GPIO25__FUNC_SCL6 (MTK_PIN_NO(25) | 3)
>>>>> +#define PINMUX_GPIO25__FUNC_KPCOL2 (MTK_PIN_NO(25) | 4)
>>>>> +#define PINMUX_GPIO25__FUNC_IO_JTAG_TMS (MTK_PIN_NO(25) | 5)
>>>>> +#define PINMUX_GPIO25__FUNC_I2S1_MCK (MTK_PIN_NO(25) | 6)
>>>>> +#define PINMUX_GPIO25__FUNC_DBG_MON_B0 (MTK_PIN_NO(25) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
>>>>> +#define PINMUX_GPIO26__FUNC_DBPI_VSYNC (MTK_PIN_NO(26) | 1)
>>>>> +#define PINMUX_GPIO26__FUNC_ANT_SEL1 (MTK_PIN_NO(26) | 2)
>>>>> +#define PINMUX_GPIO26__FUNC_SDA6 (MTK_PIN_NO(26) | 3)
>>>>> +#define PINMUX_GPIO26__FUNC_KPROW2 (MTK_PIN_NO(26) | 4)
>>>>> +#define PINMUX_GPIO26__FUNC_IO_JTAG_TDI (MTK_PIN_NO(26) | 5)
>>>>> +#define PINMUX_GPIO26__FUNC_I2S1_BCK (MTK_PIN_NO(26) | 6)
>>>>> +#define PINMUX_GPIO26__FUNC_DBG_MON_B1 (MTK_PIN_NO(26) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
>>>>> +#define PINMUX_GPIO27__FUNC_DBPI_DE (MTK_PIN_NO(27) | 1)
>>>>> +#define PINMUX_GPIO27__FUNC_ANT_SEL2 (MTK_PIN_NO(27) | 2)
>>>>> +#define PINMUX_GPIO27__FUNC_SCL7 (MTK_PIN_NO(27) | 3)
>>>>> +#define PINMUX_GPIO27__FUNC_DMIC_CLK (MTK_PIN_NO(27) | 4)
>>>>> +#define PINMUX_GPIO27__FUNC_IO_JTAG_TDO (MTK_PIN_NO(27) | 5)
>>>>> +#define PINMUX_GPIO27__FUNC_I2S1_LRCK (MTK_PIN_NO(27) | 6)
>>>>> +#define PINMUX_GPIO27__FUNC_DBG_MON_B9 (MTK_PIN_NO(27) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
>>>>> +#define PINMUX_GPIO28__FUNC_DBPI_CK (MTK_PIN_NO(28) | 1)
>>>>> +#define PINMUX_GPIO28__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(28) | 2)
>>>>> +#define PINMUX_GPIO28__FUNC_SDA7 (MTK_PIN_NO(28) | 3)
>>>>> +#define PINMUX_GPIO28__FUNC_DMIC_DAT (MTK_PIN_NO(28) | 4)
>>>>> +#define PINMUX_GPIO28__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(28) | 5)
>>>>> +#define PINMUX_GPIO28__FUNC_I2S1_DO (MTK_PIN_NO(28) | 6)
>>>>> +#define PINMUX_GPIO28__FUNC_DBG_MON_B32 (MTK_PIN_NO(28) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
>>>>> +#define PINMUX_GPIO29__FUNC_MSDC1_CLK (MTK_PIN_NO(29) | 1)
>>>>> +#define PINMUX_GPIO29__FUNC_IO_JTAG_TCK (MTK_PIN_NO(29) | 2)
>>>>> +#define PINMUX_GPIO29__FUNC_UDI_TCK (MTK_PIN_NO(29) | 3)
>>>>> +#define PINMUX_GPIO29__FUNC_CONN_DSP_JCK (MTK_PIN_NO(29) | 4)
>>>>> +#define PINMUX_GPIO29__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(29) | 5)
>>>>> +#define PINMUX_GPIO29__FUNC_PCM1_CLK (MTK_PIN_NO(29) | 6)
>>>>> +#define PINMUX_GPIO29__FUNC_DBG_MON_A6 (MTK_PIN_NO(29) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
>>>>> +#define PINMUX_GPIO30__FUNC_MSDC1_DAT3 (MTK_PIN_NO(30) | 1)
>>>>> +#define PINMUX_GPIO30__FUNC_DAP_MD32_SWD (MTK_PIN_NO(30) | 2)
>>>>> +#define PINMUX_GPIO30__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 3)
>>>>> +#define PINMUX_GPIO30__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(30) | 4)
>>>>> +#define PINMUX_GPIO30__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(30) | 5)
>>>>> +#define PINMUX_GPIO30__FUNC_PCM1_DI (MTK_PIN_NO(30) | 6)
>>>>> +#define PINMUX_GPIO30__FUNC_DBG_MON_A7 (MTK_PIN_NO(30) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
>>>>> +#define PINMUX_GPIO31__FUNC_MSDC1_CMD (MTK_PIN_NO(31) | 1)
>>>>> +#define PINMUX_GPIO31__FUNC_IO_JTAG_TMS (MTK_PIN_NO(31) | 2)
>>>>> +#define PINMUX_GPIO31__FUNC_UDI_TMS (MTK_PIN_NO(31) | 3)
>>>>> +#define PINMUX_GPIO31__FUNC_CONN_DSP_JMS (MTK_PIN_NO(31) | 4)
>>>>> +#define PINMUX_GPIO31__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(31) | 5)
>>>>> +#define PINMUX_GPIO31__FUNC_PCM1_SYNC (MTK_PIN_NO(31) | 6)
>>>>> +#define PINMUX_GPIO31__FUNC_DBG_MON_A8 (MTK_PIN_NO(31) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
>>>>> +#define PINMUX_GPIO32__FUNC_MSDC1_DAT0 (MTK_PIN_NO(32) | 1)
>>>>> +#define PINMUX_GPIO32__FUNC_IO_JTAG_TDI (MTK_PIN_NO(32) | 2)
>>>>> +#define PINMUX_GPIO32__FUNC_UDI_TDI (MTK_PIN_NO(32) | 3)
>>>>> +#define PINMUX_GPIO32__FUNC_CONN_DSP_JDI (MTK_PIN_NO(32) | 4)
>>>>> +#define PINMUX_GPIO32__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(32) | 5)
>>>>> +#define PINMUX_GPIO32__FUNC_PCM1_DO0 (MTK_PIN_NO(32) | 6)
>>>>> +#define PINMUX_GPIO32__FUNC_DBG_MON_A9 (MTK_PIN_NO(32) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
>>>>> +#define PINMUX_GPIO33__FUNC_MSDC1_DAT2 (MTK_PIN_NO(33) | 1)
>>>>> +#define PINMUX_GPIO33__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(33) | 2)
>>>>> +#define PINMUX_GPIO33__FUNC_UDI_NTRST (MTK_PIN_NO(33) | 3)
>>>>> +#define PINMUX_GPIO33__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(33) | 4)
>>>>> +#define PINMUX_GPIO33__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(33) | 5)
>>>>> +#define PINMUX_GPIO33__FUNC_PCM1_DO2 (MTK_PIN_NO(33) | 6)
>>>>> +#define PINMUX_GPIO33__FUNC_DBG_MON_A10 (MTK_PIN_NO(33) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
>>>>> +#define PINMUX_GPIO34__FUNC_MSDC1_DAT1 (MTK_PIN_NO(34) | 1)
>>>>> +#define PINMUX_GPIO34__FUNC_IO_JTAG_TDO (MTK_PIN_NO(34) | 2)
>>>>> +#define PINMUX_GPIO34__FUNC_UDI_TDO (MTK_PIN_NO(34) | 3)
>>>>> +#define PINMUX_GPIO34__FUNC_CONN_DSP_JDO (MTK_PIN_NO(34) | 4)
>>>>> +#define PINMUX_GPIO34__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(34) | 5)
>>>>> +#define PINMUX_GPIO34__FUNC_PCM1_DO1 (MTK_PIN_NO(34) | 6)
>>>>> +#define PINMUX_GPIO34__FUNC_DBG_MON_A11 (MTK_PIN_NO(34) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
>>>>> +#define PINMUX_GPIO35__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(35) | 1)
>>>>> +#define PINMUX_GPIO35__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(35) | 2)
>>>>> +#define PINMUX_GPIO35__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(35) | 3)
>>>>> +#define PINMUX_GPIO35__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(35) | 5)
>>>>> +#define PINMUX_GPIO35__FUNC_CONN_DSP_JMS (MTK_PIN_NO(35) | 6)
>>>>> +#define PINMUX_GPIO35__FUNC_DBG_MON_A28 (MTK_PIN_NO(35) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
>>>>> +#define PINMUX_GPIO36__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(36) | 1)
>>>>> +#define PINMUX_GPIO36__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(36) | 2)
>>>>> +#define PINMUX_GPIO36__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(36) | 3)
>>>>> +#define PINMUX_GPIO36__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(36) | 4)
>>>>> +#define PINMUX_GPIO36__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(36) | 5)
>>>>> +#define PINMUX_GPIO36__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(36) | 6)
>>>>> +#define PINMUX_GPIO36__FUNC_DBG_MON_A29 (MTK_PIN_NO(36) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
>>>>> +#define PINMUX_GPIO37__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(37) | 1)
>>>>> +#define PINMUX_GPIO37__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(37) | 2)
>>>>> +#define PINMUX_GPIO37__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(37) | 3)
>>>>> +#define PINMUX_GPIO37__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(37) | 5)
>>>>> +#define PINMUX_GPIO37__FUNC_CONN_DSP_JDO (MTK_PIN_NO(37) | 6)
>>>>> +#define PINMUX_GPIO37__FUNC_DBG_MON_A30 (MTK_PIN_NO(37) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
>>>>> +#define PINMUX_GPIO38__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(38) | 1)
>>>>> +#define PINMUX_GPIO38__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(38) | 3)
>>>>> +#define PINMUX_GPIO38__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(38) | 4)
>>>>> +#define PINMUX_GPIO38__FUNC_DBG_MON_A20 (MTK_PIN_NO(38) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
>>>>> +#define PINMUX_GPIO39__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(39) | 1)
>>>>> +#define PINMUX_GPIO39__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(39) | 2)
>>>>> +#define PINMUX_GPIO39__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(39) | 3)
>>>>> +#define PINMUX_GPIO39__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(39) | 5)
>>>>> +#define PINMUX_GPIO39__FUNC_CONN_DSP_JCK (MTK_PIN_NO(39) | 6)
>>>>> +#define PINMUX_GPIO39__FUNC_DBG_MON_A31 (MTK_PIN_NO(39) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
>>>>> +#define PINMUX_GPIO40__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(40) | 1)
>>>>> +#define PINMUX_GPIO40__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(40) | 2)
>>>>> +#define PINMUX_GPIO40__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(40) | 3)
>>>>> +#define PINMUX_GPIO40__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(40) | 5)
>>>>> +#define PINMUX_GPIO40__FUNC_CONN_DSP_JDI (MTK_PIN_NO(40) | 6)
>>>>> +#define PINMUX_GPIO40__FUNC_DBG_MON_A32 (MTK_PIN_NO(40) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
>>>>> +#define PINMUX_GPIO41__FUNC_IDDIG (MTK_PIN_NO(41) | 1)
>>>>> +#define PINMUX_GPIO41__FUNC_URXD1 (MTK_PIN_NO(41) | 2)
>>>>> +#define PINMUX_GPIO41__FUNC_UCTS0 (MTK_PIN_NO(41) | 3)
>>>>> +#define PINMUX_GPIO41__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(41) | 4)
>>>>> +#define PINMUX_GPIO41__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 5)
>>>>> +#define PINMUX_GPIO41__FUNC_DMIC_CLK (MTK_PIN_NO(41) | 6)
>>>>> +
>>>>> +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
>>>>> +#define PINMUX_GPIO42__FUNC_USB_DRVVBUS (MTK_PIN_NO(42) | 1)
>>>>> +#define PINMUX_GPIO42__FUNC_UTXD1 (MTK_PIN_NO(42) | 2)
>>>>> +#define PINMUX_GPIO42__FUNC_URTS0 (MTK_PIN_NO(42) | 3)
>>>>> +#define PINMUX_GPIO42__FUNC_SSPM_URXD_AO (MTK_PIN_NO(42) | 4)
>>>>> +#define PINMUX_GPIO42__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(42) | 5)
>>>>> +#define PINMUX_GPIO42__FUNC_DMIC_DAT (MTK_PIN_NO(42) | 6)
>>>>> +
>>>>> +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
>>>>> +#define PINMUX_GPIO43__FUNC_DISP_PWM (MTK_PIN_NO(43) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
>>>>> +#define PINMUX_GPIO44__FUNC_DSI_TE (MTK_PIN_NO(44) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
>>>>> +#define PINMUX_GPIO45__FUNC_LCM_RST (MTK_PIN_NO(45) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
>>>>> +#define PINMUX_GPIO46__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(46) | 1)
>>>>> +#define PINMUX_GPIO46__FUNC_URXD1 (MTK_PIN_NO(46) | 2)
>>>>> +#define PINMUX_GPIO46__FUNC_UCTS1 (MTK_PIN_NO(46) | 3)
>>>>> +#define PINMUX_GPIO46__FUNC_CCU_UTXD_AO (MTK_PIN_NO(46) | 4)
>>>>> +#define PINMUX_GPIO46__FUNC_TP_UCTS1_AO (MTK_PIN_NO(46) | 5)
>>>>> +#define PINMUX_GPIO46__FUNC_IDDIG (MTK_PIN_NO(46) | 6)
>>>>> +#define PINMUX_GPIO46__FUNC_I2S5_LRCK (MTK_PIN_NO(46) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
>>>>> +#define PINMUX_GPIO47__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(47) | 1)
>>>>> +#define PINMUX_GPIO47__FUNC_UTXD1 (MTK_PIN_NO(47) | 2)
>>>>> +#define PINMUX_GPIO47__FUNC_URTS1 (MTK_PIN_NO(47) | 3)
>>>>> +#define PINMUX_GPIO47__FUNC_CCU_URXD_AO (MTK_PIN_NO(47) | 4)
>>>>> +#define PINMUX_GPIO47__FUNC_TP_URTS1_AO (MTK_PIN_NO(47) | 5)
>>>>> +#define PINMUX_GPIO47__FUNC_USB_DRVVBUS (MTK_PIN_NO(47) | 6)
>>>>> +#define PINMUX_GPIO47__FUNC_I2S5_DO (MTK_PIN_NO(47) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
>>>>> +#define PINMUX_GPIO48__FUNC_SCL5 (MTK_PIN_NO(48) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
>>>>> +#define PINMUX_GPIO49__FUNC_SDA5 (MTK_PIN_NO(49) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
>>>>> +#define PINMUX_GPIO50__FUNC_SCL3 (MTK_PIN_NO(50) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
>>>>> +#define PINMUX_GPIO51__FUNC_SDA3 (MTK_PIN_NO(51) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
>>>>> +#define PINMUX_GPIO52__FUNC_BPI_ANT2 (MTK_PIN_NO(52) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
>>>>> +#define PINMUX_GPIO53__FUNC_BPI_ANT0 (MTK_PIN_NO(53) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
>>>>> +#define PINMUX_GPIO54__FUNC_BPI_OLAT1 (MTK_PIN_NO(54) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
>>>>> +#define PINMUX_GPIO55__FUNC_BPI_BUS8 (MTK_PIN_NO(55) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
>>>>> +#define PINMUX_GPIO56__FUNC_BPI_BUS9 (MTK_PIN_NO(56) | 1)
>>>>> +#define PINMUX_GPIO56__FUNC_SCL_6306 (MTK_PIN_NO(56) | 2)
>>>>> +
>>>>> +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
>>>>> +#define PINMUX_GPIO57__FUNC_BPI_BUS10 (MTK_PIN_NO(57) | 1)
>>>>> +#define PINMUX_GPIO57__FUNC_SDA_6306 (MTK_PIN_NO(57) | 2)
>>>>> +
>>>>> +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
>>>>> +#define PINMUX_GPIO58__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(58) | 1)
>>>>> +#define PINMUX_GPIO58__FUNC_SPM_BSI_D2 (MTK_PIN_NO(58) | 2)
>>>>> +#define PINMUX_GPIO58__FUNC_PWM_B (MTK_PIN_NO(58) | 3)
>>>>> +
>>>>> +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
>>>>> +#define PINMUX_GPIO59__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(59) | 1)
>>>>> +#define PINMUX_GPIO59__FUNC_SPM_BSI_D1 (MTK_PIN_NO(59) | 2)
>>>>> +
>>>>> +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
>>>>> +#define PINMUX_GPIO60__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(60) | 1)
>>>>> +#define PINMUX_GPIO60__FUNC_SPM_BSI_D0 (MTK_PIN_NO(60) | 2)
>>>>> +
>>>>> +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
>>>>> +#define PINMUX_GPIO61__FUNC_MIPI1_SDATA (MTK_PIN_NO(61) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
>>>>> +#define PINMUX_GPIO62__FUNC_MIPI1_SCLK (MTK_PIN_NO(62) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
>>>>> +#define PINMUX_GPIO63__FUNC_MIPI0_SDATA (MTK_PIN_NO(63) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
>>>>> +#define PINMUX_GPIO64__FUNC_MIPI0_SCLK (MTK_PIN_NO(64) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
>>>>> +#define PINMUX_GPIO65__FUNC_MIPI3_SDATA (MTK_PIN_NO(65) | 1)
>>>>> +#define PINMUX_GPIO65__FUNC_BPI_OLAT2 (MTK_PIN_NO(65) | 2)
>>>>> +
>>>>> +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
>>>>> +#define PINMUX_GPIO66__FUNC_MIPI3_SCLK (MTK_PIN_NO(66) | 1)
>>>>> +#define PINMUX_GPIO66__FUNC_BPI_OLAT3 (MTK_PIN_NO(66) | 2)
>>>>> +
>>>>> +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
>>>>> +#define PINMUX_GPIO67__FUNC_MIPI2_SDATA (MTK_PIN_NO(67) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
>>>>> +#define PINMUX_GPIO68__FUNC_MIPI2_SCLK (MTK_PIN_NO(68) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
>>>>> +#define PINMUX_GPIO69__FUNC_BPI_BUS7 (MTK_PIN_NO(69) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
>>>>> +#define PINMUX_GPIO70__FUNC_BPI_BUS6 (MTK_PIN_NO(70) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
>>>>> +#define PINMUX_GPIO71__FUNC_BPI_BUS5 (MTK_PIN_NO(71) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
>>>>> +#define PINMUX_GPIO72__FUNC_BPI_BUS4 (MTK_PIN_NO(72) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
>>>>> +#define PINMUX_GPIO73__FUNC_BPI_BUS3 (MTK_PIN_NO(73) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
>>>>> +#define PINMUX_GPIO74__FUNC_BPI_BUS2 (MTK_PIN_NO(74) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
>>>>> +#define PINMUX_GPIO75__FUNC_BPI_BUS1 (MTK_PIN_NO(75) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
>>>>> +#define PINMUX_GPIO76__FUNC_BPI_BUS0 (MTK_PIN_NO(76) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
>>>>> +#define PINMUX_GPIO77__FUNC_BPI_ANT1 (MTK_PIN_NO(77) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
>>>>> +#define PINMUX_GPIO78__FUNC_BPI_OLAT0 (MTK_PIN_NO(78) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
>>>>> +#define PINMUX_GPIO79__FUNC_BPI_PA_VM1 (MTK_PIN_NO(79) | 1)
>>>>> +#define PINMUX_GPIO79__FUNC_MIPI4_SDATA (MTK_PIN_NO(79) | 2)
>>>>> +
>>>>> +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
>>>>> +#define PINMUX_GPIO80__FUNC_BPI_PA_VM0 (MTK_PIN_NO(80) | 1)
>>>>> +#define PINMUX_GPIO80__FUNC_MIPI4_SCLK (MTK_PIN_NO(80) | 2)
>>>>> +
>>>>> +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
>>>>> +#define PINMUX_GPIO81__FUNC_SDA1 (MTK_PIN_NO(81) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
>>>>> +#define PINMUX_GPIO82__FUNC_SDA0 (MTK_PIN_NO(82) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
>>>>> +#define PINMUX_GPIO83__FUNC_SCL0 (MTK_PIN_NO(83) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
>>>>> +#define PINMUX_GPIO84__FUNC_SCL1 (MTK_PIN_NO(84) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
>>>>> +#define PINMUX_GPIO85__FUNC_SPI0_MI (MTK_PIN_NO(85) | 1)
>>>>> +#define PINMUX_GPIO85__FUNC_SCP_SPI0_MI (MTK_PIN_NO(85) | 2)
>>>>> +#define PINMUX_GPIO85__FUNC_CLKM3 (MTK_PIN_NO(85) | 3)
>>>>> +#define PINMUX_GPIO85__FUNC_I2S1_BCK (MTK_PIN_NO(85) | 4)
>>>>> +#define PINMUX_GPIO85__FUNC_MFG_DFD_JTAG_TDO (MTK_PIN_NO(85) | 5)
>>>>> +#define PINMUX_GPIO85__FUNC_DFD_TDO (MTK_PIN_NO(85) | 6)
>>>>> +#define PINMUX_GPIO85__FUNC_JTDO_SEL1 (MTK_PIN_NO(85) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
>>>>> +#define PINMUX_GPIO86__FUNC_SPI0_CSB (MTK_PIN_NO(86) | 1)
>>>>> +#define PINMUX_GPIO86__FUNC_SCP_SPI0_CS (MTK_PIN_NO(86) | 2)
>>>>> +#define PINMUX_GPIO86__FUNC_CLKM0 (MTK_PIN_NO(86) | 3)
>>>>> +#define PINMUX_GPIO86__FUNC_I2S1_LRCK (MTK_PIN_NO(86) | 4)
>>>>> +#define PINMUX_GPIO86__FUNC_MFG_DFD_JTAG_TMS (MTK_PIN_NO(86) | 5)
>>>>> +#define PINMUX_GPIO86__FUNC_DFD_TMS (MTK_PIN_NO(86) | 6)
>>>>> +#define PINMUX_GPIO86__FUNC_JTMS_SEL1 (MTK_PIN_NO(86) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
>>>>> +#define PINMUX_GPIO87__FUNC_SPI0_MO (MTK_PIN_NO(87) | 1)
>>>>> +#define PINMUX_GPIO87__FUNC_SCP_SPI0_MO (MTK_PIN_NO(87) | 2)
>>>>> +#define PINMUX_GPIO87__FUNC_SDA1 (MTK_PIN_NO(87) | 3)
>>>>> +#define PINMUX_GPIO87__FUNC_I2S1_DO (MTK_PIN_NO(87) | 4)
>>>>> +#define PINMUX_GPIO87__FUNC_MFG_DFD_JTAG_TDI (MTK_PIN_NO(87) | 5)
>>>>> +#define PINMUX_GPIO87__FUNC_DFD_TDI (MTK_PIN_NO(87) | 6)
>>>>> +#define PINMUX_GPIO87__FUNC_JTDI_SEL1 (MTK_PIN_NO(87) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
>>>>> +#define PINMUX_GPIO88__FUNC_SPI0_CLK (MTK_PIN_NO(88) | 1)
>>>>> +#define PINMUX_GPIO88__FUNC_SCP_SPI0_CK (MTK_PIN_NO(88) | 2)
>>>>> +#define PINMUX_GPIO88__FUNC_SCL1 (MTK_PIN_NO(88) | 3)
>>>>> +#define PINMUX_GPIO88__FUNC_I2S1_MCK (MTK_PIN_NO(88) | 4)
>>>>> +#define PINMUX_GPIO88__FUNC_MFG_DFD_JTAG_TCK (MTK_PIN_NO(88) | 5)
>>>>> +#define PINMUX_GPIO88__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 6)
>>>>> +#define PINMUX_GPIO88__FUNC_JTCK_SEL1 (MTK_PIN_NO(88) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
>>>>> +#define PINMUX_GPIO89__FUNC_SRCLKENAI0 (MTK_PIN_NO(89) | 1)
>>>>> +#define PINMUX_GPIO89__FUNC_PWM_C (MTK_PIN_NO(89) | 2)
>>>>> +#define PINMUX_GPIO89__FUNC_I2S5_BCK (MTK_PIN_NO(89) | 3)
>>>>> +#define PINMUX_GPIO89__FUNC_ANT_SEL6 (MTK_PIN_NO(89) | 4)
>>>>> +#define PINMUX_GPIO89__FUNC_SDA8 (MTK_PIN_NO(89) | 5)
>>>>> +#define PINMUX_GPIO89__FUNC_CMVREF0 (MTK_PIN_NO(89) | 6)
>>>>> +#define PINMUX_GPIO89__FUNC_DBG_MON_A21 (MTK_PIN_NO(89) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
>>>>> +#define PINMUX_GPIO90__FUNC_PWM_A (MTK_PIN_NO(90) | 1)
>>>>> +#define PINMUX_GPIO90__FUNC_CMMCLK2 (MTK_PIN_NO(90) | 2)
>>>>> +#define PINMUX_GPIO90__FUNC_I2S5_LRCK (MTK_PIN_NO(90) | 3)
>>>>> +#define PINMUX_GPIO90__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(90) | 4)
>>>>> +#define PINMUX_GPIO90__FUNC_SCL8 (MTK_PIN_NO(90) | 5)
>>>>> +#define PINMUX_GPIO90__FUNC_PTA_RXD (MTK_PIN_NO(90) | 6)
>>>>> +#define PINMUX_GPIO90__FUNC_DBG_MON_A22 (MTK_PIN_NO(90) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
>>>>> +#define PINMUX_GPIO91__FUNC_KPROW1 (MTK_PIN_NO(91) | 1)
>>>>> +#define PINMUX_GPIO91__FUNC_PWM_B (MTK_PIN_NO(91) | 2)
>>>>> +#define PINMUX_GPIO91__FUNC_I2S5_DO (MTK_PIN_NO(91) | 3)
>>>>> +#define PINMUX_GPIO91__FUNC_ANT_SEL7 (MTK_PIN_NO(91) | 4)
>>>>> +#define PINMUX_GPIO91__FUNC_CMMCLK3 (MTK_PIN_NO(91) | 5)
>>>>> +#define PINMUX_GPIO91__FUNC_PTA_TXD (MTK_PIN_NO(91) | 6)
>>>>> +
>>>>> +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
>>>>> +#define PINMUX_GPIO92__FUNC_KPROW0 (MTK_PIN_NO(92) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
>>>>> +#define PINMUX_GPIO93__FUNC_KPCOL0 (MTK_PIN_NO(93) | 1)
>>>>> +#define PINMUX_GPIO93__FUNC_DBG_MON_B27 (MTK_PIN_NO(93) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
>>>>> +#define PINMUX_GPIO94__FUNC_KPCOL1 (MTK_PIN_NO(94) | 1)
>>>>> +#define PINMUX_GPIO94__FUNC_I2S2_DI2 (MTK_PIN_NO(94) | 2)
>>>>> +#define PINMUX_GPIO94__FUNC_I2S5_MCK (MTK_PIN_NO(94) | 3)
>>>>> +#define PINMUX_GPIO94__FUNC_CMMCLK2 (MTK_PIN_NO(94) | 4)
>>>>> +#define PINMUX_GPIO94__FUNC_SCP_SPI2_MI (MTK_PIN_NO(94) | 5)
>>>>> +#define PINMUX_GPIO94__FUNC_SRCLKENAI1 (MTK_PIN_NO(94) | 6)
>>>>> +#define PINMUX_GPIO94__FUNC_SPI2_MI (MTK_PIN_NO(94) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
>>>>> +#define PINMUX_GPIO95__FUNC_URXD0 (MTK_PIN_NO(95) | 1)
>>>>> +#define PINMUX_GPIO95__FUNC_UTXD0 (MTK_PIN_NO(95) | 2)
>>>>> +#define PINMUX_GPIO95__FUNC_MD_URXD0 (MTK_PIN_NO(95) | 3)
>>>>> +#define PINMUX_GPIO95__FUNC_MD_URXD1 (MTK_PIN_NO(95) | 4)
>>>>> +#define PINMUX_GPIO95__FUNC_SSPM_URXD_AO (MTK_PIN_NO(95) | 5)
>>>>> +#define PINMUX_GPIO95__FUNC_CCU_URXD_AO (MTK_PIN_NO(95) | 6)
>>>>> +
>>>>> +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
>>>>> +#define PINMUX_GPIO96__FUNC_UTXD0 (MTK_PIN_NO(96) | 1)
>>>>> +#define PINMUX_GPIO96__FUNC_URXD0 (MTK_PIN_NO(96) | 2)
>>>>> +#define PINMUX_GPIO96__FUNC_MD_UTXD0 (MTK_PIN_NO(96) | 3)
>>>>> +#define PINMUX_GPIO96__FUNC_MD_UTXD1 (MTK_PIN_NO(96) | 4)
>>>>> +#define PINMUX_GPIO96__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(96) | 5)
>>>>> +#define PINMUX_GPIO96__FUNC_CCU_UTXD_AO (MTK_PIN_NO(96) | 6)
>>>>> +#define PINMUX_GPIO96__FUNC_DBG_MON_B2 (MTK_PIN_NO(96) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
>>>>> +#define PINMUX_GPIO97__FUNC_UCTS0 (MTK_PIN_NO(97) | 1)
>>>>> +#define PINMUX_GPIO97__FUNC_I2S2_MCK (MTK_PIN_NO(97) | 2)
>>>>> +#define PINMUX_GPIO97__FUNC_IDDIG (MTK_PIN_NO(97) | 3)
>>>>> +#define PINMUX_GPIO97__FUNC_CONN_MCU_TDO (MTK_PIN_NO(97) | 4)
>>>>> +#define PINMUX_GPIO97__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(97) | 5)
>>>>> +#define PINMUX_GPIO97__FUNC_IO_JTAG_TDO (MTK_PIN_NO(97) | 6)
>>>>> +#define PINMUX_GPIO97__FUNC_DBG_MON_B3 (MTK_PIN_NO(97) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
>>>>> +#define PINMUX_GPIO98__FUNC_URTS0 (MTK_PIN_NO(98) | 1)
>>>>> +#define PINMUX_GPIO98__FUNC_I2S2_BCK (MTK_PIN_NO(98) | 2)
>>>>> +#define PINMUX_GPIO98__FUNC_USB_DRVVBUS (MTK_PIN_NO(98) | 3)
>>>>> +#define PINMUX_GPIO98__FUNC_CONN_MCU_TMS (MTK_PIN_NO(98) | 4)
>>>>> +#define PINMUX_GPIO98__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(98) | 5)
>>>>> +#define PINMUX_GPIO98__FUNC_IO_JTAG_TMS (MTK_PIN_NO(98) | 6)
>>>>> +#define PINMUX_GPIO98__FUNC_DBG_MON_B4 (MTK_PIN_NO(98) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
>>>>> +#define PINMUX_GPIO99__FUNC_CMMCLK0 (MTK_PIN_NO(99) | 1)
>>>>> +#define PINMUX_GPIO99__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(99) | 4)
>>>>> +#define PINMUX_GPIO99__FUNC_DBG_MON_B28 (MTK_PIN_NO(99) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
>>>>> +#define PINMUX_GPIO100__FUNC_CMMCLK1 (MTK_PIN_NO(100) | 1)
>>>>> +#define PINMUX_GPIO100__FUNC_PWM_C (MTK_PIN_NO(100) | 2)
>>>>> +#define PINMUX_GPIO100__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(100) | 3)
>>>>> +#define PINMUX_GPIO100__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(100) | 4)
>>>>> +#define PINMUX_GPIO100__FUNC_DBG_MON_B29 (MTK_PIN_NO(100) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
>>>>> +#define PINMUX_GPIO101__FUNC_CLKM2 (MTK_PIN_NO(101) | 1)
>>>>> +#define PINMUX_GPIO101__FUNC_I2S2_LRCK (MTK_PIN_NO(101) | 2)
>>>>> +#define PINMUX_GPIO101__FUNC_CMVREF1 (MTK_PIN_NO(101) | 3)
>>>>> +#define PINMUX_GPIO101__FUNC_CONN_MCU_TCK (MTK_PIN_NO(101) | 4)
>>>>> +#define PINMUX_GPIO101__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(101) | 5)
>>>>> +#define PINMUX_GPIO101__FUNC_IO_JTAG_TCK (MTK_PIN_NO(101) | 6)
>>>>> +
>>>>> +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
>>>>> +#define PINMUX_GPIO102__FUNC_CLKM1 (MTK_PIN_NO(102) | 1)
>>>>> +#define PINMUX_GPIO102__FUNC_I2S2_DI (MTK_PIN_NO(102) | 2)
>>>>> +#define PINMUX_GPIO102__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(102) | 3)
>>>>> +#define PINMUX_GPIO102__FUNC_CONN_MCU_TDI (MTK_PIN_NO(102) | 4)
>>>>> +#define PINMUX_GPIO102__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(102) | 5)
>>>>> +#define PINMUX_GPIO102__FUNC_IO_JTAG_TDI (MTK_PIN_NO(102) | 6)
>>>>> +#define PINMUX_GPIO102__FUNC_DBG_MON_B8 (MTK_PIN_NO(102) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
>>>>> +#define PINMUX_GPIO103__FUNC_SCL2 (MTK_PIN_NO(103) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
>>>>> +#define PINMUX_GPIO104__FUNC_SDA2 (MTK_PIN_NO(104) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
>>>>> +#define PINMUX_GPIO105__FUNC_SCL4 (MTK_PIN_NO(105) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
>>>>> +#define PINMUX_GPIO106__FUNC_SDA4 (MTK_PIN_NO(106) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
>>>>> +#define PINMUX_GPIO107__FUNC_DMIC_CLK (MTK_PIN_NO(107) | 1)
>>>>> +#define PINMUX_GPIO107__FUNC_ANT_SEL0 (MTK_PIN_NO(107) | 2)
>>>>> +#define PINMUX_GPIO107__FUNC_CLKM0 (MTK_PIN_NO(107) | 3)
>>>>> +#define PINMUX_GPIO107__FUNC_SDA7 (MTK_PIN_NO(107) | 4)
>>>>> +#define PINMUX_GPIO107__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(107) | 5)
>>>>> +#define PINMUX_GPIO107__FUNC_PWM_A (MTK_PIN_NO(107) | 6)
>>>>> +#define PINMUX_GPIO107__FUNC_DBG_MON_B12 (MTK_PIN_NO(107) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
>>>>> +#define PINMUX_GPIO108__FUNC_CMMCLK2 (MTK_PIN_NO(108) | 1)
>>>>> +#define PINMUX_GPIO108__FUNC_ANT_SEL1 (MTK_PIN_NO(108) | 2)
>>>>> +#define PINMUX_GPIO108__FUNC_CLKM1 (MTK_PIN_NO(108) | 3)
>>>>> +#define PINMUX_GPIO108__FUNC_SCL8 (MTK_PIN_NO(108) | 4)
>>>>> +#define PINMUX_GPIO108__FUNC_DAP_MD32_SWD (MTK_PIN_NO(108) | 5)
>>>>> +#define PINMUX_GPIO108__FUNC_PWM_B (MTK_PIN_NO(108) | 6)
>>>>> +#define PINMUX_GPIO108__FUNC_DBG_MON_B13 (MTK_PIN_NO(108) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
>>>>> +#define PINMUX_GPIO109__FUNC_DMIC_DAT (MTK_PIN_NO(109) | 1)
>>>>> +#define PINMUX_GPIO109__FUNC_ANT_SEL2 (MTK_PIN_NO(109) | 2)
>>>>> +#define PINMUX_GPIO109__FUNC_CLKM2 (MTK_PIN_NO(109) | 3)
>>>>> +#define PINMUX_GPIO109__FUNC_SDA8 (MTK_PIN_NO(109) | 4)
>>>>> +#define PINMUX_GPIO109__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(109) | 5)
>>>>> +#define PINMUX_GPIO109__FUNC_PWM_C (MTK_PIN_NO(109) | 6)
>>>>> +#define PINMUX_GPIO109__FUNC_DBG_MON_B14 (MTK_PIN_NO(109) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
>>>>> +#define PINMUX_GPIO110__FUNC_SCL7 (MTK_PIN_NO(110) | 1)
>>>>> +#define PINMUX_GPIO110__FUNC_ANT_SEL0 (MTK_PIN_NO(110) | 2)
>>>>> +#define PINMUX_GPIO110__FUNC_TP_URXD1_AO (MTK_PIN_NO(110) | 3)
>>>>> +#define PINMUX_GPIO110__FUNC_USB_DRVVBUS (MTK_PIN_NO(110) | 4)
>>>>> +#define PINMUX_GPIO110__FUNC_SRCLKENAI1 (MTK_PIN_NO(110) | 5)
>>>>> +#define PINMUX_GPIO110__FUNC_KPCOL2 (MTK_PIN_NO(110) | 6)
>>>>> +#define PINMUX_GPIO110__FUNC_URXD1 (MTK_PIN_NO(110) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
>>>>> +#define PINMUX_GPIO111__FUNC_CMMCLK3 (MTK_PIN_NO(111) | 1)
>>>>> +#define PINMUX_GPIO111__FUNC_ANT_SEL1 (MTK_PIN_NO(111) | 2)
>>>>> +#define PINMUX_GPIO111__FUNC_SRCLKENAI0 (MTK_PIN_NO(111) | 3)
>>>>> +#define PINMUX_GPIO111__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(111) | 4)
>>>>> +#define PINMUX_GPIO111__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(111) | 5)
>>>>> +#define PINMUX_GPIO111__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(111) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
>>>>> +#define PINMUX_GPIO112__FUNC_SDA7 (MTK_PIN_NO(112) | 1)
>>>>> +#define PINMUX_GPIO112__FUNC_ANT_SEL2 (MTK_PIN_NO(112) | 2)
>>>>> +#define PINMUX_GPIO112__FUNC_TP_UTXD1_AO (MTK_PIN_NO(112) | 3)
>>>>> +#define PINMUX_GPIO112__FUNC_IDDIG (MTK_PIN_NO(112) | 4)
>>>>> +#define PINMUX_GPIO112__FUNC_AGPS_SYNC (MTK_PIN_NO(112) | 5)
>>>>> +#define PINMUX_GPIO112__FUNC_KPROW2 (MTK_PIN_NO(112) | 6)
>>>>> +#define PINMUX_GPIO112__FUNC_UTXD1 (MTK_PIN_NO(112) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
>>>>> +#define PINMUX_GPIO113__FUNC_CONN_TOP_CLK (MTK_PIN_NO(113) | 1)
>>>>> +#define PINMUX_GPIO113__FUNC_SCL6 (MTK_PIN_NO(113) | 3)
>>>>> +#define PINMUX_GPIO113__FUNC_AUXIF_CLK0 (MTK_PIN_NO(113) | 4)
>>>>> +#define PINMUX_GPIO113__FUNC_TP_UCTS1_AO (MTK_PIN_NO(113) | 6)
>>>>> +
>>>>> +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
>>>>> +#define PINMUX_GPIO114__FUNC_CONN_TOP_DATA (MTK_PIN_NO(114) | 1)
>>>>> +#define PINMUX_GPIO114__FUNC_SDA6 (MTK_PIN_NO(114) | 3)
>>>>> +#define PINMUX_GPIO114__FUNC_AUXIF_ST0 (MTK_PIN_NO(114) | 4)
>>>>> +#define PINMUX_GPIO114__FUNC_TP_URTS1_AO (MTK_PIN_NO(114) | 6)
>>>>> +
>>>>> +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
>>>>> +#define PINMUX_GPIO115__FUNC_CONN_BT_CLK (MTK_PIN_NO(115) | 1)
>>>>> +#define PINMUX_GPIO115__FUNC_UTXD1 (MTK_PIN_NO(115) | 2)
>>>>> +#define PINMUX_GPIO115__FUNC_PTA_TXD (MTK_PIN_NO(115) | 3)
>>>>> +#define PINMUX_GPIO115__FUNC_AUXIF_CLK1 (MTK_PIN_NO(115) | 4)
>>>>> +#define PINMUX_GPIO115__FUNC_DAP_MD32_SWD (MTK_PIN_NO(115) | 5)
>>>>> +#define PINMUX_GPIO115__FUNC_TP_UTXD1_AO (MTK_PIN_NO(115) | 6)
>>>>> +
>>>>> +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
>>>>> +#define PINMUX_GPIO116__FUNC_CONN_BT_DATA (MTK_PIN_NO(116) | 1)
>>>>> +#define PINMUX_GPIO116__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(116) | 2)
>>>>> +#define PINMUX_GPIO116__FUNC_AUXIF_ST1 (MTK_PIN_NO(116) | 4)
>>>>> +#define PINMUX_GPIO116__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(116) | 5)
>>>>> +#define PINMUX_GPIO116__FUNC_TP_URXD2_AO (MTK_PIN_NO(116) | 6)
>>>>> +#define PINMUX_GPIO116__FUNC_DBG_MON_A0 (MTK_PIN_NO(116) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
>>>>> +#define PINMUX_GPIO117__FUNC_CONN_WF_HB0 (MTK_PIN_NO(117) | 1)
>>>>> +#define PINMUX_GPIO117__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(117) | 2)
>>>>> +#define PINMUX_GPIO117__FUNC_TP_UTXD2_AO (MTK_PIN_NO(117) | 6)
>>>>> +#define PINMUX_GPIO117__FUNC_DBG_MON_A4 (MTK_PIN_NO(117) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
>>>>> +#define PINMUX_GPIO118__FUNC_CONN_WF_HB1 (MTK_PIN_NO(118) | 1)
>>>>> +#define PINMUX_GPIO118__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(118) | 2)
>>>>> +#define PINMUX_GPIO118__FUNC_SSPM_URXD_AO (MTK_PIN_NO(118) | 5)
>>>>> +#define PINMUX_GPIO118__FUNC_TP_UCTS2_AO (MTK_PIN_NO(118) | 6)
>>>>> +#define PINMUX_GPIO118__FUNC_DBG_MON_A5 (MTK_PIN_NO(118) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
>>>>> +#define PINMUX_GPIO119__FUNC_CONN_WF_HB2 (MTK_PIN_NO(119) | 1)
>>>>> +#define PINMUX_GPIO119__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(119) | 2)
>>>>> +#define PINMUX_GPIO119__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(119) | 5)
>>>>> +#define PINMUX_GPIO119__FUNC_TP_URTS2_AO (MTK_PIN_NO(119) | 6)
>>>>> +
>>>>> +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
>>>>> +#define PINMUX_GPIO120__FUNC_CONN_WB_PTA (MTK_PIN_NO(120) | 1)
>>>>> +#define PINMUX_GPIO120__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(120) | 2)
>>>>> +#define PINMUX_GPIO120__FUNC_CCU_URXD_AO (MTK_PIN_NO(120) | 5)
>>>>> +
>>>>> +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
>>>>> +#define PINMUX_GPIO121__FUNC_CONN_HRST_B (MTK_PIN_NO(121) | 1)
>>>>> +#define PINMUX_GPIO121__FUNC_URXD1 (MTK_PIN_NO(121) | 2)
>>>>> +#define PINMUX_GPIO121__FUNC_PTA_RXD (MTK_PIN_NO(121) | 3)
>>>>> +#define PINMUX_GPIO121__FUNC_CCU_UTXD_AO (MTK_PIN_NO(121) | 5)
>>>>> +#define PINMUX_GPIO121__FUNC_TP_URXD1_AO (MTK_PIN_NO(121) | 6)
>>>>> +
>>>>> +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
>>>>> +#define PINMUX_GPIO122__FUNC_MSDC0_CMD (MTK_PIN_NO(122) | 1)
>>>>> +#define PINMUX_GPIO122__FUNC_SSPM_URXD2_AO (MTK_PIN_NO(122) | 2)
>>>>> +#define PINMUX_GPIO122__FUNC_ANT_SEL1 (MTK_PIN_NO(122) | 3)
>>>>> +#define PINMUX_GPIO122__FUNC_DBG_MON_A12 (MTK_PIN_NO(122) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
>>>>> +#define PINMUX_GPIO123__FUNC_MSDC0_DAT0 (MTK_PIN_NO(123) | 1)
>>>>> +#define PINMUX_GPIO123__FUNC_ANT_SEL0 (MTK_PIN_NO(123) | 3)
>>>>> +#define PINMUX_GPIO123__FUNC_DBG_MON_A13 (MTK_PIN_NO(123) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
>>>>> +#define PINMUX_GPIO124__FUNC_MSDC0_CLK (MTK_PIN_NO(124) | 1)
>>>>> +#define PINMUX_GPIO124__FUNC_DBG_MON_A14 (MTK_PIN_NO(124) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
>>>>> +#define PINMUX_GPIO125__FUNC_MSDC0_DAT2 (MTK_PIN_NO(125) | 1)
>>>>> +#define PINMUX_GPIO125__FUNC_MRG_CLK (MTK_PIN_NO(125) | 3)
>>>>> +#define PINMUX_GPIO125__FUNC_DBG_MON_A15 (MTK_PIN_NO(125) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
>>>>> +#define PINMUX_GPIO126__FUNC_MSDC0_DAT4 (MTK_PIN_NO(126) | 1)
>>>>> +#define PINMUX_GPIO126__FUNC_ANT_SEL5 (MTK_PIN_NO(126) | 3)
>>>>> +#define PINMUX_GPIO126__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(126) | 6)
>>>>> +#define PINMUX_GPIO126__FUNC_DBG_MON_A16 (MTK_PIN_NO(126) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
>>>>> +#define PINMUX_GPIO127__FUNC_MSDC0_DAT6 (MTK_PIN_NO(127) | 1)
>>>>> +#define PINMUX_GPIO127__FUNC_ANT_SEL4 (MTK_PIN_NO(127) | 3)
>>>>> +#define PINMUX_GPIO127__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(127) | 6)
>>>>> +#define PINMUX_GPIO127__FUNC_DBG_MON_A17 (MTK_PIN_NO(127) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
>>>>> +#define PINMUX_GPIO128__FUNC_MSDC0_DAT1 (MTK_PIN_NO(128) | 1)
>>>>> +#define PINMUX_GPIO128__FUNC_ANT_SEL2 (MTK_PIN_NO(128) | 3)
>>>>> +#define PINMUX_GPIO128__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(128) | 6)
>>>>> +#define PINMUX_GPIO128__FUNC_DBG_MON_A18 (MTK_PIN_NO(128) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
>>>>> +#define PINMUX_GPIO129__FUNC_MSDC0_DAT5 (MTK_PIN_NO(129) | 1)
>>>>> +#define PINMUX_GPIO129__FUNC_ANT_SEL3 (MTK_PIN_NO(129) | 3)
>>>>> +#define PINMUX_GPIO129__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(129) | 6)
>>>>> +#define PINMUX_GPIO129__FUNC_DBG_MON_A23 (MTK_PIN_NO(129) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
>>>>> +#define PINMUX_GPIO130__FUNC_MSDC0_DAT7 (MTK_PIN_NO(130) | 1)
>>>>> +#define PINMUX_GPIO130__FUNC_MRG_DO (MTK_PIN_NO(130) | 3)
>>>>> +#define PINMUX_GPIO130__FUNC_DBG_MON_A24 (MTK_PIN_NO(130) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
>>>>> +#define PINMUX_GPIO131__FUNC_MSDC0_DSL (MTK_PIN_NO(131) | 1)
>>>>> +#define PINMUX_GPIO131__FUNC_MRG_SYNC (MTK_PIN_NO(131) | 3)
>>>>> +#define PINMUX_GPIO131__FUNC_DBG_MON_A25 (MTK_PIN_NO(131) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
>>>>> +#define PINMUX_GPIO132__FUNC_MSDC0_DAT3 (MTK_PIN_NO(132) | 1)
>>>>> +#define PINMUX_GPIO132__FUNC_MRG_DI (MTK_PIN_NO(132) | 3)
>>>>> +#define PINMUX_GPIO132__FUNC_DBG_MON_A26 (MTK_PIN_NO(132) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
>>>>> +#define PINMUX_GPIO133__FUNC_MSDC0_RSTB (MTK_PIN_NO(133) | 1)
>>>>> +#define PINMUX_GPIO133__FUNC_AGPS_SYNC (MTK_PIN_NO(133) | 3)
>>>>> +#define PINMUX_GPIO133__FUNC_DBG_MON_A27 (MTK_PIN_NO(133) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
>>>>> +#define PINMUX_GPIO134__FUNC_RTC32K_CK (MTK_PIN_NO(134) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
>>>>> +#define PINMUX_GPIO135__FUNC_WATCHDOG (MTK_PIN_NO(135) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
>>>>> +#define PINMUX_GPIO136__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(136) | 1)
>>>>> +#define PINMUX_GPIO136__FUNC_AUD_CLK_MISO (MTK_PIN_NO(136) | 2)
>>>>> +#define PINMUX_GPIO136__FUNC_I2S1_MCK (MTK_PIN_NO(136) | 3)
>>>>> +#define PINMUX_GPIO136__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(136) | 6)
>>>>> +
>>>>> +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
>>>>> +#define PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(137) | 1)
>>>>> +#define PINMUX_GPIO137__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(137) | 2)
>>>>> +#define PINMUX_GPIO137__FUNC_I2S1_BCK (MTK_PIN_NO(137) | 3)
>>>>> +
>>>>> +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
>>>>> +#define PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(138) | 1)
>>>>> +#define PINMUX_GPIO138__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(138) | 2)
>>>>> +#define PINMUX_GPIO138__FUNC_I2S1_LRCK (MTK_PIN_NO(138) | 3)
>>>>> +#define PINMUX_GPIO138__FUNC_DBG_MON_B24 (MTK_PIN_NO(138) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
>>>>> +#define PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(139) | 1)
>>>>> +#define PINMUX_GPIO139__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(139) | 2)
>>>>> +#define PINMUX_GPIO139__FUNC_I2S1_DO (MTK_PIN_NO(139) | 3)
>>>>> +#define PINMUX_GPIO139__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(139) | 6)
>>>>> +
>>>>> +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
>>>>> +#define PINMUX_GPIO140__FUNC_AUD_CLK_MISO (MTK_PIN_NO(140) | 1)
>>>>> +#define PINMUX_GPIO140__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(140) | 2)
>>>>> +#define PINMUX_GPIO140__FUNC_I2S0_MCK (MTK_PIN_NO(140) | 3)
>>>>> +#define PINMUX_GPIO140__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(140) | 6)
>>>>> +
>>>>> +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
>>>>> +#define PINMUX_GPIO141__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(141) | 1)
>>>>> +#define PINMUX_GPIO141__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(141) | 2)
>>>>> +#define PINMUX_GPIO141__FUNC_I2S0_BCK (MTK_PIN_NO(141) | 3)
>>>>> +
>>>>> +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
>>>>> +#define PINMUX_GPIO142__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(142) | 1)
>>>>> +#define PINMUX_GPIO142__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(142) | 2)
>>>>> +#define PINMUX_GPIO142__FUNC_I2S0_LRCK (MTK_PIN_NO(142) | 3)
>>>>> +#define PINMUX_GPIO142__FUNC_VOW_DAT_MISO (MTK_PIN_NO(142) | 4)
>>>>> +#define PINMUX_GPIO142__FUNC_DBG_MON_B25 (MTK_PIN_NO(142) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
>>>>> +#define PINMUX_GPIO143__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(143) | 1)
>>>>> +#define PINMUX_GPIO143__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(143) | 2)
>>>>> +#define PINMUX_GPIO143__FUNC_I2S0_DI (MTK_PIN_NO(143) | 3)
>>>>> +#define PINMUX_GPIO143__FUNC_VOW_CLK_MISO (MTK_PIN_NO(143) | 4)
>>>>> +#define PINMUX_GPIO143__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(143) | 6)
>>>>> +#define PINMUX_GPIO143__FUNC_DBG_MON_B26 (MTK_PIN_NO(143) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
>>>>> +#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(144) | 1)
>>>>> +#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(144) | 2)
>>>>> +
>>>>> +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
>>>>> +#define PINMUX_GPIO145__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(145) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
>>>>> +#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(146) | 1)
>>>>> +#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(146) | 2)
>>>>> +
>>>>> +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
>>>>> +#define PINMUX_GPIO147__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(147) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
>>>>> +#define PINMUX_GPIO148__FUNC_SRCLKENA0 (MTK_PIN_NO(148) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
>>>>> +#define PINMUX_GPIO149__FUNC_SRCLKENA1 (MTK_PIN_NO(149) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
>>>>> +#define PINMUX_GPIO150__FUNC_PWM_A (MTK_PIN_NO(150) | 1)
>>>>> +#define PINMUX_GPIO150__FUNC_CMFLASH (MTK_PIN_NO(150) | 2)
>>>>> +#define PINMUX_GPIO150__FUNC_CLKM0 (MTK_PIN_NO(150) | 3)
>>>>> +#define PINMUX_GPIO150__FUNC_DBG_MON_B30 (MTK_PIN_NO(150) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
>>>>> +#define PINMUX_GPIO151__FUNC_PWM_B (MTK_PIN_NO(151) | 1)
>>>>> +#define PINMUX_GPIO151__FUNC_CMVREF0 (MTK_PIN_NO(151) | 2)
>>>>> +#define PINMUX_GPIO151__FUNC_CLKM1 (MTK_PIN_NO(151) | 3)
>>>>> +#define PINMUX_GPIO151__FUNC_DBG_MON_B20 (MTK_PIN_NO(151) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
>>>>> +#define PINMUX_GPIO152__FUNC_PWM_C (MTK_PIN_NO(152) | 1)
>>>>> +#define PINMUX_GPIO152__FUNC_CMFLASH (MTK_PIN_NO(152) | 2)
>>>>> +#define PINMUX_GPIO152__FUNC_CLKM2 (MTK_PIN_NO(152) | 3)
>>>>> +#define PINMUX_GPIO152__FUNC_DBG_MON_B21 (MTK_PIN_NO(152) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
>>>>> +#define PINMUX_GPIO153__FUNC_PWM_A (MTK_PIN_NO(153) | 1)
>>>>> +#define PINMUX_GPIO153__FUNC_CMVREF0 (MTK_PIN_NO(153) | 2)
>>>>> +#define PINMUX_GPIO153__FUNC_CLKM3 (MTK_PIN_NO(153) | 3)
>>>>> +#define PINMUX_GPIO153__FUNC_DBG_MON_B22 (MTK_PIN_NO(153) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
>>>>> +#define PINMUX_GPIO154__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(154) | 1)
>>>>> +#define PINMUX_GPIO154__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(154) | 2)
>>>>> +#define PINMUX_GPIO154__FUNC_DBG_MON_B18 (MTK_PIN_NO(154) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
>>>>> +#define PINMUX_GPIO155__FUNC_ANT_SEL0 (MTK_PIN_NO(155) | 1)
>>>>> +#define PINMUX_GPIO155__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(155) | 2)
>>>>> +#define PINMUX_GPIO155__FUNC_CMVREF1 (MTK_PIN_NO(155) | 3)
>>>>> +#define PINMUX_GPIO155__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(155) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
>>>>> +#define PINMUX_GPIO156__FUNC_ANT_SEL1 (MTK_PIN_NO(156) | 1)
>>>>> +#define PINMUX_GPIO156__FUNC_SRCLKENAI0 (MTK_PIN_NO(156) | 2)
>>>>> +#define PINMUX_GPIO156__FUNC_SCL6 (MTK_PIN_NO(156) | 3)
>>>>> +#define PINMUX_GPIO156__FUNC_KPCOL2 (MTK_PIN_NO(156) | 4)
>>>>> +#define PINMUX_GPIO156__FUNC_IDDIG (MTK_PIN_NO(156) | 5)
>>>>> +#define PINMUX_GPIO156__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(156) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
>>>>> +#define PINMUX_GPIO157__FUNC_ANT_SEL2 (MTK_PIN_NO(157) | 1)
>>>>> +#define PINMUX_GPIO157__FUNC_SRCLKENAI1 (MTK_PIN_NO(157) | 2)
>>>>> +#define PINMUX_GPIO157__FUNC_SDA6 (MTK_PIN_NO(157) | 3)
>>>>> +#define PINMUX_GPIO157__FUNC_KPROW2 (MTK_PIN_NO(157) | 4)
>>>>> +#define PINMUX_GPIO157__FUNC_USB_DRVVBUS (MTK_PIN_NO(157) | 5)
>>>>> +#define PINMUX_GPIO157__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(157) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
>>>>> +#define PINMUX_GPIO158__FUNC_ANT_SEL3 (MTK_PIN_NO(158) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
>>>>> +#define PINMUX_GPIO159__FUNC_ANT_SEL4 (MTK_PIN_NO(159) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
>>>>> +#define PINMUX_GPIO160__FUNC_ANT_SEL5 (MTK_PIN_NO(160) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
>>>>> +#define PINMUX_GPIO161__FUNC_SPI1_A_MI (MTK_PIN_NO(161) | 1)
>>>>> +#define PINMUX_GPIO161__FUNC_SCP_SPI1_MI (MTK_PIN_NO(161) | 2)
>>>>> +#define PINMUX_GPIO161__FUNC_IDDIG (MTK_PIN_NO(161) | 3)
>>>>> +#define PINMUX_GPIO161__FUNC_ANT_SEL6 (MTK_PIN_NO(161) | 4)
>>>>> +#define PINMUX_GPIO161__FUNC_KPCOL2 (MTK_PIN_NO(161) | 5)
>>>>> +#define PINMUX_GPIO161__FUNC_PTA_RXD (MTK_PIN_NO(161) | 6)
>>>>> +#define PINMUX_GPIO161__FUNC_DBG_MON_B19 (MTK_PIN_NO(161) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
>>>>> +#define PINMUX_GPIO162__FUNC_SPI1_A_CSB (MTK_PIN_NO(162) | 1)
>>>>> +#define PINMUX_GPIO162__FUNC_SCP_SPI1_CS (MTK_PIN_NO(162) | 2)
>>>>> +#define PINMUX_GPIO162__FUNC_USB_DRVVBUS (MTK_PIN_NO(162) | 3)
>>>>> +#define PINMUX_GPIO162__FUNC_ANT_SEL5 (MTK_PIN_NO(162) | 4)
>>>>> +#define PINMUX_GPIO162__FUNC_KPROW2 (MTK_PIN_NO(162) | 5)
>>>>> +#define PINMUX_GPIO162__FUNC_PTA_TXD (MTK_PIN_NO(162) | 6)
>>>>> +
>>>>> +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
>>>>> +#define PINMUX_GPIO163__FUNC_SPI1_A_MO (MTK_PIN_NO(163) | 1)
>>>>> +#define PINMUX_GPIO163__FUNC_SCP_SPI1_MO (MTK_PIN_NO(163) | 2)
>>>>> +#define PINMUX_GPIO163__FUNC_SDA1 (MTK_PIN_NO(163) | 3)
>>>>> +#define PINMUX_GPIO163__FUNC_ANT_SEL4 (MTK_PIN_NO(163) | 4)
>>>>> +#define PINMUX_GPIO163__FUNC_CMMCLK2 (MTK_PIN_NO(163) | 5)
>>>>> +#define PINMUX_GPIO163__FUNC_DMIC_CLK (MTK_PIN_NO(163) | 6)
>>>>> +
>>>>> +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
>>>>> +#define PINMUX_GPIO164__FUNC_SPI1_A_CLK (MTK_PIN_NO(164) | 1)
>>>>> +#define PINMUX_GPIO164__FUNC_SCP_SPI1_CK (MTK_PIN_NO(164) | 2)
>>>>> +#define PINMUX_GPIO164__FUNC_SCL1 (MTK_PIN_NO(164) | 3)
>>>>> +#define PINMUX_GPIO164__FUNC_ANT_SEL3 (MTK_PIN_NO(164) | 4)
>>>>> +#define PINMUX_GPIO164__FUNC_CMMCLK3 (MTK_PIN_NO(164) | 5)
>>>>> +#define PINMUX_GPIO164__FUNC_DMIC_DAT (MTK_PIN_NO(164) | 6)
>>>>> +
>>>>> +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
>>>>> +#define PINMUX_GPIO165__FUNC_PWM_B (MTK_PIN_NO(165) | 1)
>>>>> +#define PINMUX_GPIO165__FUNC_CMMCLK2 (MTK_PIN_NO(165) | 2)
>>>>> +#define PINMUX_GPIO165__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(165) | 3)
>>>>> +#define PINMUX_GPIO165__FUNC_TDM_MCK_2ND (MTK_PIN_NO(165) | 6)
>>>>> +#define PINMUX_GPIO165__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(165) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
>>>>> +#define PINMUX_GPIO166__FUNC_ANT_SEL6 (MTK_PIN_NO(166) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
>>>>> +#define PINMUX_GPIO167__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(167) | 1)
>>>>> +#define PINMUX_GPIO167__FUNC_SPM_BSI_EN (MTK_PIN_NO(167) | 2)
>>>>> +
>>>>> +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
>>>>> +#define PINMUX_GPIO168__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(168) | 1)
>>>>> +#define PINMUX_GPIO168__FUNC_SPM_BSI_CK (MTK_PIN_NO(168) | 2)
>>>>> +
>>>>> +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
>>>>> +#define PINMUX_GPIO169__FUNC_PWM_C (MTK_PIN_NO(169) | 1)
>>>>> +#define PINMUX_GPIO169__FUNC_CMMCLK3 (MTK_PIN_NO(169) | 2)
>>>>> +#define PINMUX_GPIO169__FUNC_CMVREF1 (MTK_PIN_NO(169) | 3)
>>>>> +#define PINMUX_GPIO169__FUNC_ANT_SEL7 (MTK_PIN_NO(169) | 4)
>>>>> +#define PINMUX_GPIO169__FUNC_AGPS_SYNC (MTK_PIN_NO(169) | 5)
>>>>> +#define PINMUX_GPIO169__FUNC_TDM_BCK_2ND (MTK_PIN_NO(169) | 6)
>>>>> +#define PINMUX_GPIO169__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(169) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
>>>>> +#define PINMUX_GPIO170__FUNC_I2S1_BCK (MTK_PIN_NO(170) | 1)
>>>>> +#define PINMUX_GPIO170__FUNC_I2S3_BCK (MTK_PIN_NO(170) | 2)
>>>>> +#define PINMUX_GPIO170__FUNC_SCL7 (MTK_PIN_NO(170) | 3)
>>>>> +#define PINMUX_GPIO170__FUNC_I2S5_BCK (MTK_PIN_NO(170) | 4)
>>>>> +#define PINMUX_GPIO170__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(170) | 5)
>>>>> +#define PINMUX_GPIO170__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(170) | 6)
>>>>> +#define PINMUX_GPIO170__FUNC_ANT_SEL3 (MTK_PIN_NO(170) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
>>>>> +#define PINMUX_GPIO171__FUNC_I2S1_LRCK (MTK_PIN_NO(171) | 1)
>>>>> +#define PINMUX_GPIO171__FUNC_I2S3_LRCK (MTK_PIN_NO(171) | 2)
>>>>> +#define PINMUX_GPIO171__FUNC_SDA7 (MTK_PIN_NO(171) | 3)
>>>>> +#define PINMUX_GPIO171__FUNC_I2S5_LRCK (MTK_PIN_NO(171) | 4)
>>>>> +#define PINMUX_GPIO171__FUNC_URXD1 (MTK_PIN_NO(171) | 5)
>>>>> +#define PINMUX_GPIO171__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(171) | 6)
>>>>> +#define PINMUX_GPIO171__FUNC_ANT_SEL4 (MTK_PIN_NO(171) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
>>>>> +#define PINMUX_GPIO172__FUNC_I2S1_DO (MTK_PIN_NO(172) | 1)
>>>>> +#define PINMUX_GPIO172__FUNC_I2S3_DO (MTK_PIN_NO(172) | 2)
>>>>> +#define PINMUX_GPIO172__FUNC_SCL8 (MTK_PIN_NO(172) | 3)
>>>>> +#define PINMUX_GPIO172__FUNC_I2S5_DO (MTK_PIN_NO(172) | 4)
>>>>> +#define PINMUX_GPIO172__FUNC_UTXD1 (MTK_PIN_NO(172) | 5)
>>>>> +#define PINMUX_GPIO172__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(172) | 6)
>>>>> +#define PINMUX_GPIO172__FUNC_ANT_SEL5 (MTK_PIN_NO(172) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
>>>>> +#define PINMUX_GPIO173__FUNC_I2S1_MCK (MTK_PIN_NO(173) | 1)
>>>>> +#define PINMUX_GPIO173__FUNC_I2S3_MCK (MTK_PIN_NO(173) | 2)
>>>>> +#define PINMUX_GPIO173__FUNC_SDA8 (MTK_PIN_NO(173) | 3)
>>>>> +#define PINMUX_GPIO173__FUNC_I2S5_MCK (MTK_PIN_NO(173) | 4)
>>>>> +#define PINMUX_GPIO173__FUNC_UCTS0 (MTK_PIN_NO(173) | 5)
>>>>> +#define PINMUX_GPIO173__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(173) | 6)
>>>>> +#define PINMUX_GPIO173__FUNC_ANT_SEL6 (MTK_PIN_NO(173) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
>>>>> +#define PINMUX_GPIO174__FUNC_I2S2_DI (MTK_PIN_NO(174) | 1)
>>>>> +#define PINMUX_GPIO174__FUNC_I2S0_DI (MTK_PIN_NO(174) | 2)
>>>>> +#define PINMUX_GPIO174__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(174) | 3)
>>>>> +#define PINMUX_GPIO174__FUNC_I2S2_DI2 (MTK_PIN_NO(174) | 4)
>>>>> +#define PINMUX_GPIO174__FUNC_URTS0 (MTK_PIN_NO(174) | 5)
>>>>> +#define PINMUX_GPIO174__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(174) | 6)
>>>>> +#define PINMUX_GPIO174__FUNC_ANT_SEL7 (MTK_PIN_NO(174) | 7)
>>>>> +
>>>>> +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
>>>>> +#define PINMUX_GPIO175__FUNC_ANT_SEL7 (MTK_PIN_NO(175) | 1)
>>>>> +
>>>>> +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
>>>>> +
>>>>> +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
>>>>> +
>>>>> +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
>>>>> +
>>>>> +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
>>>>> +
>>>>> +#endif /* __MT8183-PINFUNC_H */
>>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>>> new file mode 100644
>>>>> index 0000000..63db9cc
>>>>> --- /dev/null
>>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>>> @@ -0,0 +1,408 @@
>>>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>>>> +/*
>>>>> + * Copyright (c) 2018 MediaTek Inc.
>>>>> + * Author: Ben Ho <ben.ho@mediatek.com>
>>>>> + * Erin Lo <erin.lo@mediatek.com>
>>>>> + */
>>>>> +
>>>>> +#include <dt-bindings/clock/mt8183-clk.h>
>>>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>>>> +#include "mt8183-pinfunc.h"
>>>>> +
>>>>> +/ {
>>>>> + compatible = "mediatek,mt8183";
>>>>> + interrupt-parent = <&sysirq>;
>>>>> + #address-cells = <2>;
>>>>> + #size-cells = <2>;
>>>>> +
>>>>> + cpus {
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> +
>>>>> + cpu-map {
>>>>> + cluster0 {
>>>>> + core0 {
>>>>> + cpu = <&cpu0>;
>>>>> + };
>>>>> + core1 {
>>>>> + cpu = <&cpu1>;
>>>>> + };
>>>>> + core2 {
>>>>> + cpu = <&cpu2>;
>>>>> + };
>>>>> + core3 {
>>>>> + cpu = <&cpu3>;
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + cluster1 {
>>>>> + core0 {
>>>>> + cpu = <&cpu4>;
>>>>> + };
>>>>> + core1 {
>>>>> + cpu = <&cpu5>;
>>>>> + };
>>>>> + core2 {
>>>>> + cpu = <&cpu6>;
>>>>> + };
>>>>> + core3 {
>>>>> + cpu = <&cpu7>;
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + cpu0: cpu@0 {
>>>>> + device_type = "cpu";
>>>>> + compatible = "arm,cortex-a53";
>>>>> + reg = <0x000>;
>>>>> + enable-method = "psci";
>>>>> + };
>>>>> +
>>>>> + cpu1: cpu@1 {
>>>>> + device_type = "cpu";
>>>>> + compatible = "arm,cortex-a53";
>>>>> + reg = <0x001>;
>>>>> + enable-method = "psci";
>>>>> + };
>>>>> +
>>>>> + cpu2: cpu@2 {
>>>>> + device_type = "cpu";
>>>>> + compatible = "arm,cortex-a53";
>>>>> + reg = <0x002>;
>>>>> + enable-method = "psci";
>>>>> + };
>>>>> +
>>>>> + cpu3: cpu@3 {
>>>>> + device_type = "cpu";
>>>>> + compatible = "arm,cortex-a53";
>>>>> + reg = <0x003>;
>>>>> + enable-method = "psci";
>>>>> + };
>>>>> +
>>>>> + cpu4: cpu@100 {
>>>>> + device_type = "cpu";
>>>>> + compatible = "arm,cortex-a73";
>>>>> + reg = <0x100>;
>>>>> + enable-method = "psci";
>>>>> + };
>>>>> +
>>>>> + cpu5: cpu@101 {
>>>>> + device_type = "cpu";
>>>>> + compatible = "arm,cortex-a73";
>>>>> + reg = <0x101>;
>>>>> + enable-method = "psci";
>>>>> + };
>>>>> +
>>>>> + cpu6: cpu@102 {
>>>>> + device_type = "cpu";
>>>>> + compatible = "arm,cortex-a73";
>>>>> + reg = <0x102>;
>>>>> + enable-method = "psci";
>>>>> + };
>>>>> +
>>>>> + cpu7: cpu@103 {
>>>>> + device_type = "cpu";
>>>>> + compatible = "arm,cortex-a73";
>>>>> + reg = <0x103>;
>>>>> + enable-method = "psci";
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + pmu-a53 {
>>>>> + compatible = "arm,cortex-a53-pmu";
>>>>> + interrupt-parent = <&gic>;
>>>>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
>>>>> + };
>>>>> +
>>>>> + pmu-a73 {
>>>>> + compatible = "arm,cortex-a73-pmu";
>>>>> + interrupt-parent = <&gic>;
>>>>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
>>>>> + };
>>>>> +
>>>>> + psci {
>>>>> + compatible = "arm,psci-1.0";
>>>>> + method = "smc";
>>>>> + };
>>>>> +
>>>>> + clk26m: oscillator {
>>>>> + compatible = "fixed-clock";
>>>>> + #clock-cells = <0>;
>>>>> + clock-frequency = <26000000>;
>>>>> + clock-output-names = "clk26m";
>>>>> + };
>>>>> +
>>>>> + timer {
>>>>> + compatible = "arm,armv8-timer";
>>>>> + interrupt-parent = <&gic>;
>>>>> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
>>>>> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
>>>>> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
>>>>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
>>>>> + };
>>>>> +
>>>>> + gic: interrupt-controller@c000000 {
>>>>> + compatible = "arm,gic-v3";
>>>>> + #interrupt-cells = <4>;
>>>>> + interrupt-parent = <&gic>;
>>>>> + interrupt-controller;
>>>>> + reg = <0 0x0c000000 0 0x40000>, /* GICD */
>>>>> + <0 0x0c100000 0 0x200000>, /* GICR */
>>>>> + <0 0x0c400000 0 0x2000>, /* GICC */
>>>>> + <0 0x0c410000 0 0x1000>, /* GICH */
>>>>> + <0 0x0c420000 0 0x2000>; /* GICV */
>>>>> +
>>>>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
>>>>> + ppi-partitions {
>>>>> + ppi_cluster0: interrupt-partition-0 {
>>>>> + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
>>>>> + };
>>>>> + ppi_cluster1: interrupt-partition-1 {
>>>>> + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + mcucfg: syscon@c530000 {
>>>>> + compatible = "mediatek,mt8183-mcucfg", "syscon";
>>>>> + reg = <0 0x0c530000 0 0x1000>;
>>>>> + #clock-cells = <1>;
>>>>> + };
>>>>> +
>>>>> + sysirq: intpol-controller@c530a80 {
>>>>> + compatible = "mediatek,mt8183-sysirq",
>>>>> + "mediatek,mt6577-sysirq";
>>>>> + interrupt-controller;
>>>>> + #interrupt-cells = <4>;
>>>>> + interrupt-parent = <&gic>;
>>>>> + reg = <0 0x0c530a80 0 0x50>;
>>>>> + };
>>>>> +
>>>>> + topckgen: syscon@10000000 {
>>>>> + compatible = "mediatek,mt8183-topckgen", "syscon";
>>>>> + reg = <0 0x10000000 0 0x1000>;
>>>>> + #clock-cells = <1>;
>>>>> + };
>>>>> +
>>>>> + infracfg: syscon@10001000 {
>>>>> + compatible = "mediatek,mt8183-infracfg", "syscon";
>>>>> + reg = <0 0x10001000 0 0x1000>;
>>>>> + #clock-cells = <1>;
>>>>> + };
>>>>> +
>>>>> + pio: pinctrl@1000b000 {
>>>>> + compatible = "mediatek,mt8183-pinctrl";
>>>>> + reg = <0 0x10005000 0 0x1000>,
>>>>> + <0 0x11f20000 0 0x1000>,
>>>>> + <0 0x11e80000 0 0x1000>,
>>>>> + <0 0x11e70000 0 0x1000>,
>>>>> + <0 0x11e90000 0 0x1000>,
>>>>> + <0 0x11d30000 0 0x1000>,
>>>>> + <0 0x11d20000 0 0x1000>,
>>>>> + <0 0x11c50000 0 0x1000>,
>>>>> + <0 0x11f30000 0 0x1000>,
>>>>> + <0 0x1000b000 0 0x1000>;
>>>>> + reg-names = "iocfg0", "iocfg1", "iocfg2",
>>>>> + "iocfg3", "iocfg4", "iocfg5",
>>>>> + "iocfg6", "iocfg7", "iocfg8",
>>>>> + "eint";
>>>>> + gpio-controller;
>>>>> + #gpio-cells = <2>;
>>>>> + gpio-ranges = <&pio 0 0 192>;
>>>>> + interrupt-controller;
>>>>> + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>;
>>>>> + interrupt-parent = <&gic>;
>>>>> + #interrupt-cells = <4>;
>>>>> + };
>>>>> +
>>>>> + apmixedsys: syscon@1000c000 {
>>>>> + compatible = "mediatek,mt8183-apmixedsys", "syscon";
>>>>> + reg = <0 0x1000c000 0 0x1000>;
>>>>> + #clock-cells = <1>;
>>>>> + };
>>>>> +
>>>>> + pwrap: pwrap@1000d000 {
>>>>> + compatible = "mediatek,mt8183-pwrap";
>>>>> + reg = <0 0x1000d000 0 0x1000>;
>>>>> + reg-names = "pwrap";
>>>>> + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 0>;
>>>>> + clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
>>>>> + <&infracfg CLK_INFRA_PMIC_AP>;
>>>>> + clock-names = "spi", "wrap";
>>>>> + };
>>>>> +
>>>>> + uart0: serial@11002000 {
>>>>> + compatible = "mediatek,mt8183-uart",
>>>>> + "mediatek,mt6577-uart";
>>>>> + reg = <0 0x11002000 0 0x1000>;
>>>>> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW 0>;
>>>>> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
>>>>> + clock-names = "baud", "bus";
>>>>> + status = "disabled";
>>>>> + };
>>>>> +
>>>>> + uart1: serial@11003000 {
>>>>> + compatible = "mediatek,mt8183-uart",
>>>>> + "mediatek,mt6577-uart";
>>>>> + reg = <0 0x11003000 0 0x1000>;
>>>>> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW 0>;
>>>>> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
>>>>> + clock-names = "baud", "bus";
>>>>> + status = "disabled";
>>>>> + };
>>>>> +
>>>>> + uart2: serial@11004000 {
>>>>> + compatible = "mediatek,mt8183-uart",
>>>>> + "mediatek,mt6577-uart";
>>>>> + reg = <0 0x11004000 0 0x1000>;
>>>>> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW 0>;
>>>>> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
>>>>> + clock-names = "baud", "bus";
>>>>> + status = "disabled";
>>>>> + };
>>>>> +
>>>>> + spi0: spi@1100a000 {
>>>>> + compatible = "mediatek,mt8183-spi";
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> + reg = <0 0x1100a000 0 0x1000>;
>>>>> + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW 0>;
>>>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
>>>>> + <&topckgen CLK_TOP_MUX_SPI>,
>>>>> + <&infracfg CLK_INFRA_SPI0>;
>>>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
>>>>> + status = "disabled";
>>>>> + };
>>>>> +
>>>>> + spi1: spi@11010000 {
>>>>> + compatible = "mediatek,mt8183-spi";
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> + reg = <0 0x11010000 0 0x1000>;
>>>>> + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW 0>;
>>>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
>>>>> + <&topckgen CLK_TOP_MUX_SPI>,
>>>>> + <&infracfg CLK_INFRA_SPI1>;
>>>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
>>>>> + status = "disabled";
>>>>> + };
>>>>> +
>>>>> + spi2: spi@11012000 {
>>>>> + compatible = "mediatek,mt8183-spi";
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> + reg = <0 0x11012000 0 0x1000>;
>>>>> + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW 0>;
>>>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
>>>>> + <&topckgen CLK_TOP_MUX_SPI>,
>>>>> + <&infracfg CLK_INFRA_SPI2>;
>>>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
>>>>> + status = "disabled";
>>>>> + };
>>>>> +
>>>>> + spi3: spi@11013000 {
>>>>> + compatible = "mediatek,mt8183-spi";
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> + reg = <0 0x11013000 0 0x1000>;
>>>>> + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW 0>;
>>>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
>>>>> + <&topckgen CLK_TOP_MUX_SPI>,
>>>>> + <&infracfg CLK_INFRA_SPI3>;
>>>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
>>>>> + status = "disabled";
>>>>> + };
>>>>> +
>>>>> + spi4: spi@11018000 {
>>>>> + compatible = "mediatek,mt8183-spi";
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> + reg = <0 0x11018000 0 0x1000>;
>>>>> + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW 0>;
>>>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
>>>>> + <&topckgen CLK_TOP_MUX_SPI>,
>>>>> + <&infracfg CLK_INFRA_SPI4>;
>>>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
>>>>> + status = "disabled";
>>>>> + };
>>>>> +
>>>>> + spi5: spi@11019000 {
>>>>> + compatible = "mediatek,mt8183-spi";
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> + reg = <0 0x11019000 0 0x1000>;
>>>>> + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW 0>;
>>>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
>>>>> + <&topckgen CLK_TOP_MUX_SPI>,
>>>>> + <&infracfg CLK_INFRA_SPI5>;
>>>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
>>>>> + status = "disabled";
>>>>> + };
>>>>> +
>>>>> + audiosys: syscon@11220000 {
>>>>> + compatible = "mediatek,mt8183-audiosys", "syscon";
>>>>> + reg = <0 0x11220000 0 0x1000>;
>>>>> + #clock-cells = <1>;
>>>>> + };
>>>>> +
>>>>> + mfgcfg: syscon@13000000 {
>>>>> + compatible = "mediatek,mt8183-mfgcfg", "syscon";
>>>>> + reg = <0 0x13000000 0 0x1000>;
>>>>> + #clock-cells = <1>;
>>>>> + };
>>>>> +
>>>>> + mmsys: syscon@14000000 {
>>>>> + compatible = "mediatek,mt8183-mmsys", "syscon";
>>>>> + reg = <0 0x14000000 0 0x1000>;
>>>>> + #clock-cells = <1>;
>>>>> + };
>>>>> +
>>>>> + imgsys: syscon@15020000 {
>>>>> + compatible = "mediatek,mt8183-imgsys", "syscon";
>>>>> + reg = <0 0x15020000 0 0x1000>;
>>>>> + #clock-cells = <1>;
>>>>> + };
>>>>> +
>>>>> + vdecsys: syscon@16000000 {
>>>>> + compatible = "mediatek,mt8183-vdecsys", "syscon";
>>>>> + reg = <0 0x16000000 0 0x1000>;
>>>>> + #clock-cells = <1>;
>>>>> + };
>>>>> +
>>>>> + vencsys: syscon@17000000 {
>>>>> + compatible = "mediatek,mt8183-vencsys", "syscon";
>>>>> + reg = <0 0x17000000 0 0x1000>;
>>>>> + #clock-cells = <1>;
>>>>> + };
>>>>> +
>>>>> + ipu_conn: syscon@19000000 {
>>>>> + compatible = "mediatek,mt8183-ipu_conn", "syscon";
>>>>> + reg = <0 0x19000000 0 0x1000>;
>>>>> + #clock-cells = <1>;
>>>>> + };
>>>>> +
>>>>> + ipu_adl: syscon@19010000 {
>>>>> + compatible = "mediatek,mt8183-ipu_adl", "syscon";
>>>>> + reg = <0 0x19010000 0 0x1000>;
>>>>> + #clock-cells = <1>;
>>>>> + };
>>>>> +
>>>>> + ipu_core0: syscon@19180000 {
>>>>> + compatible = "mediatek,mt8183-ipu_core0", "syscon";
>>>>> + reg = <0 0x19180000 0 0x1000>;
>>>>> + #clock-cells = <1>;
>>>>> + };
>>>>> +
>>>>> + ipu_core1: syscon@19280000 {
>>>>> + compatible = "mediatek,mt8183-ipu_core1", "syscon";
>>>>> + reg = <0 0x19280000 0 0x1000>;
>>>>> + #clock-cells = <1>;
>>>>> + };
>>>>> +
>>>>> + camsys: syscon@1a000000 {
>>>>> + compatible = "mediatek,mt8183-camsys", "syscon";
>>>>> + reg = <0 0x1a000000 0 0x1000>;
>>>>> + #clock-cells = <1>;
>>>>> + };
>>>>> +};
>>>>>
>>>>
>>>> _______________________________________________
>>>> Linux-mediatek mailing list
>>>> Linux-mediatek@lists.infradead.org
>>>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
>>>
>>>
>>
>> _______________________________________________
>> Linux-mediatek mailing list
>> Linux-mediatek@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
>
>
^ permalink raw reply
* RE: [PATCH] serial: uartps: Fix stuck ISR if RX disabled with non-empty FIFO
From: Shubhrajyoti Datta @ 2019-02-14 6:46 UTC (permalink / raw)
To: Michal Simek, Anssi Hannula
Cc: Jiri Slaby, linux-serial@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org,
Shubhrajyoti Datta
In-Reply-To: <d58d8b99-71ee-d9d4-7217-767cc09989ac@xilinx.com>
Hi Anssi,
Thanks for the patch.
Minor nit below.
The call to the cdns_uart_handle_rx could be prevented in cdns_uart_isr
> -----Original Message-----
> From: Michal Simek [mailto:michal.simek@xilinx.com]
> Sent: Thursday, February 14, 2019 12:06 PM
> To: Anssi Hannula <anssi.hannula@bitwise.fi>; Michal Simek
> <michals@xilinx.com>; Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: Jiri Slaby <jslaby@suse.com>; linux-serial@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; stable@vger.kernel.org; Shubhrajyoti Datta
> <shubhraj@xilinx.com>
> Subject: Re: [PATCH] serial: uartps: Fix stuck ISR if RX disabled with non-
> empty FIFO
>
> + Shubhrajyoti
>
> On 06. 02. 19 15:08, Anssi Hannula wrote:
> > If RX is disabled while there are still unprocessed bytes in RX FIFO,
> > cdns_uart_handle_rx() called from interrupt handler will get stuck in
> > the receive loop as read bytes will not get removed from the RX FIFO
> > and CDNS_UART_SR_RXEMPTY bit will never get set.
> >
> > Avoid the stuck handler by checking first if RX is disabled.
> > port->lock protects against race with RX-disabling functions.
> >
> > This HW behavior was mentioned by Nathan Rossi in 43e98facc4a3 ("tty:
> > xuartps: Fix RX hang, and TX corruption in termios call") which fixed
> > a similar issue in cdns_uart_set_termios().
> > The behavior can also be easily verified by e.g. setting
> > CDNS_UART_CR_RX_DIS at the beginning of cdns_uart_handle_rx() - the
> > following loop will then get stuck.
> >
> > Resetting the FIFO using RXRST would not set RXEMPTY either so simply
> > issuing a reset after RX-disable would not work.
> >
> > I observe this frequently on a ZynqMP board during heavy RX load at 1M
> > baudrate when the reader process exits and thus RX gets disabled.
> >
Reviewed-by: Shubhrajyoti Datta <shubhrajyori.datta@xilinx.com>
> > Fixes: 61ec9016988f ("tty/serial: add support for Xilinx PS UART")
> > Signed-off-by: Anssi Hannula <anssi.hannula@bitwise.fi>
> > Cc: stable@vger.kernel.org
> > ---
> > drivers/tty/serial/xilinx_uartps.c | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/tty/serial/xilinx_uartps.c
> > b/drivers/tty/serial/xilinx_uartps.c
> > index 094f2958cb2b..f0c4f59d9314 100644
> > --- a/drivers/tty/serial/xilinx_uartps.c
> > +++ b/drivers/tty/serial/xilinx_uartps.c
> > @@ -219,6 +219,13 @@ static void cdns_uart_handle_rx(void *dev_id,
> > unsigned int isrstatus)
> >
> > is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
> >
> > + /*
> > + * RXEMPTY will never be set if RX is disabled as read bytes
> > + * will not be removed from the FIFO
> > + */
> > + if (readl(port->membase + CDNS_UART_CR) &
> CDNS_UART_CR_RX_DIS)
> > + return;
> > +
> > while ((readl(port->membase + CDNS_UART_SR) &
> > CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
> > if (is_rxbs_support)
> >
>
>
> Please review.
> M
^ permalink raw reply
* Re: [PATCH] serial: uartps: Fix stuck ISR if RX disabled with non-empty FIFO
From: Michal Simek @ 2019-02-14 6:35 UTC (permalink / raw)
To: Anssi Hannula, Michal Simek, Greg Kroah-Hartman
Cc: Jiri Slaby, linux-serial, linux-arm-kernel, stable,
Shubhrajyoti Datta
In-Reply-To: <20190206140813.15349-1-anssi.hannula@bitwise.fi>
+ Shubhrajyoti
On 06. 02. 19 15:08, Anssi Hannula wrote:
> If RX is disabled while there are still unprocessed bytes in RX FIFO,
> cdns_uart_handle_rx() called from interrupt handler will get stuck in
> the receive loop as read bytes will not get removed from the RX FIFO
> and CDNS_UART_SR_RXEMPTY bit will never get set.
>
> Avoid the stuck handler by checking first if RX is disabled. port->lock
> protects against race with RX-disabling functions.
>
> This HW behavior was mentioned by Nathan Rossi in 43e98facc4a3 ("tty:
> xuartps: Fix RX hang, and TX corruption in termios call") which fixed a
> similar issue in cdns_uart_set_termios().
> The behavior can also be easily verified by e.g. setting
> CDNS_UART_CR_RX_DIS at the beginning of cdns_uart_handle_rx() - the
> following loop will then get stuck.
>
> Resetting the FIFO using RXRST would not set RXEMPTY either so simply
> issuing a reset after RX-disable would not work.
>
> I observe this frequently on a ZynqMP board during heavy RX load at 1M
> baudrate when the reader process exits and thus RX gets disabled.
>
> Fixes: 61ec9016988f ("tty/serial: add support for Xilinx PS UART")
> Signed-off-by: Anssi Hannula <anssi.hannula@bitwise.fi>
> Cc: stable@vger.kernel.org
> ---
> drivers/tty/serial/xilinx_uartps.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c
> index 094f2958cb2b..f0c4f59d9314 100644
> --- a/drivers/tty/serial/xilinx_uartps.c
> +++ b/drivers/tty/serial/xilinx_uartps.c
> @@ -219,6 +219,13 @@ static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
>
> is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
>
> + /*
> + * RXEMPTY will never be set if RX is disabled as read bytes
> + * will not be removed from the FIFO
> + */
> + if (readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS)
> + return;
> +
> while ((readl(port->membase + CDNS_UART_SR) &
> CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
> if (is_rxbs_support)
>
Please review.
M
^ permalink raw reply
* Re: [PATCH v6 6/6] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile
From: Erin Lo @ 2019-02-14 5:27 UTC (permalink / raw)
To: Matthias Brugger
Cc: Mark Rutland, Ben Ho, mars.cheng, Mengqi Zhang, linux-clk,
Hsin-Hsiung Wang, Weiyi Lu, Seiya Wang, linux-serial,
yingjoe.chen, devicetree, Jason Cooper, Marc Zyngier, Rob Herring,
linux-mediatek, Thomas Gleixner, eddie.huang, linux-arm-kernel,
srv_heupstream, Greg Kroah-Hartman, Stephen Boyd, linux-kernel,
Zhiyong Tao
In-Reply-To: <458fd525-3f53-fcd8-2466-4c8046400c5a@gmail.com>
On Wed, 2019-02-13 at 15:54 +0100, Matthias Brugger wrote:
>
> On 13/02/2019 10:03, Erin Lo wrote:
> > On Thu, 2019-02-07 at 16:30 +0100, Matthias Brugger wrote:
> >>
> >> On 24/01/2019 09:07, Erin Lo wrote:
> >>> From: Ben Ho <Ben.Ho@mediatek.com>
> >>>
> >>> Add basic chip support for Mediatek 8183, include
> >>> pinctrl file, uart node with correct uart clocks, pwrap device
> >>>
> >>> Add clock controller nodes, include topckgen, infracfg,
> >>> apmixedsys and subsystem.
> >>>
> >>> Signed-off-by: Ben Ho <Ben.Ho@mediatek.com>
> >>> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> >>> Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
> >>> Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
> >>> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> >>> Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
> >>> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> >>> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
> >>> ---
> >>> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> >>> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 136 +++
> >>> arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h | 1120 +++++++++++++++++++++++++
> >>
> >> Would you mind to make the pinfunc.h a seperate patch and adding the pinctrl
> >> maintainers to the list.
> >>
> >> Regards,
> >> Matthias
> >>
> >
> > OK! I will take pinfunc.h out of this series.
>
> My take would be to somehow change this series in something like.
> One patch which adds basic support for the SoC without any dependencies on other
> series.
> Every node that has a dependency on a different series should go in a separate
> patch. In this case IMHO pinfunc.h can got with the dts node in one patch.
>
> Regards,
> Matthias
>
I will separate this patch into 3 patches : basic support for the SoC,
mt8183-pinfunc.h, and spi node.
Is that OK?
Is it ok, if pinctrl@1000b000 is included in basic node?
Best Regards.
Erin
> >
> > Best Regards,
> > Erin
> >
> >>> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 408 +++++++++
> >>> 4 files changed, 1665 insertions(+)
> >>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> >>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
> >>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >>>
> >>> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> >>> index e8f952f..458bbc4 100644
> >>> --- a/arch/arm64/boot/dts/mediatek/Makefile
> >>> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> >>> @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
> >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
> >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
> >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> >>> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
> >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> >>> new file mode 100644
> >>> index 0000000..b12c6ea
> >>> --- /dev/null
> >>> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> >>> @@ -0,0 +1,136 @@
> >>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >>> +/*
> >>> + * Copyright (c) 2018 MediaTek Inc.
> >>> + * Author: Ben Ho <ben.ho@mediatek.com>
> >>> + * Erin Lo <erin.lo@mediatek.com>
> >>> + */
> >>> +
> >>> +/dts-v1/;
> >>> +#include "mt8183.dtsi"
> >>> +
> >>> +/ {
> >>> + model = "MediaTek MT8183 evaluation board";
> >>> + compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
> >>> +
> >>> + aliases {
> >>> + serial0 = &uart0;
> >>> + };
> >>> +
> >>> + memory@40000000 {
> >>> + device_type = "memory";
> >>> + reg = <0 0x40000000 0 0x80000000>;
> >>> + };
> >>> +
> >>> + chosen {
> >>> + stdout-path = "serial0:921600n8";
> >>> + };
> >>> +};
> >>> +
> >>> +&pio {
> >>> + spi_pins_0: spi0{
> >>> + pins_spi{
> >>> + pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
> >>> + <PINMUX_GPIO86__FUNC_SPI0_CSB>,
> >>> + <PINMUX_GPIO87__FUNC_SPI0_MO>,
> >>> + <PINMUX_GPIO88__FUNC_SPI0_CLK>;
> >>> + bias-disable;
> >>> + };
> >>> + };
> >>> +
> >>> + spi_pins_1: spi1{
> >>> + pins_spi{
> >>> + pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
> >>> + <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
> >>> + <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
> >>> + <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
> >>> + bias-disable;
> >>> + };
> >>> + };
> >>> +
> >>> + spi_pins_2: spi2{
> >>> + pins_spi{
> >>> + pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
> >>> + <PINMUX_GPIO1__FUNC_SPI2_MO>,
> >>> + <PINMUX_GPIO2__FUNC_SPI2_CLK>,
> >>> + <PINMUX_GPIO94__FUNC_SPI2_MI>;
> >>> + bias-disable;
> >>> + };
> >>> + };
> >>> +
> >>> + spi_pins_3: spi3{
> >>> + pins_spi{
> >>> + pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
> >>> + <PINMUX_GPIO22__FUNC_SPI3_CSB>,
> >>> + <PINMUX_GPIO23__FUNC_SPI3_MO>,
> >>> + <PINMUX_GPIO24__FUNC_SPI3_CLK>;
> >>> + bias-disable;
> >>> + };
> >>> + };
> >>> +
> >>> + spi_pins_4: spi4{
> >>> + pins_spi{
> >>> + pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
> >>> + <PINMUX_GPIO18__FUNC_SPI4_CSB>,
> >>> + <PINMUX_GPIO19__FUNC_SPI4_MO>,
> >>> + <PINMUX_GPIO20__FUNC_SPI4_CLK>;
> >>> + bias-disable;
> >>> + };
> >>> + };
> >>> +
> >>> + spi_pins_5: spi5{
> >>> + pins_spi{
> >>> + pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
> >>> + <PINMUX_GPIO14__FUNC_SPI5_CSB>,
> >>> + <PINMUX_GPIO15__FUNC_SPI5_MO>,
> >>> + <PINMUX_GPIO16__FUNC_SPI5_CLK>;
> >>> + bias-disable;
> >>> + };
> >>> + };
> >>> +};
> >>> +
> >>> +&spi0 {
> >>> + pinctrl-names = "default";
> >>> + pinctrl-0 = <&spi_pins_0>;
> >>> + mediatek,pad-select = <0>;
> >>> + status = "okay";
> >>> +};
> >>> +
> >>> +&spi1 {
> >>> + pinctrl-names = "default";
> >>> + pinctrl-0 = <&spi_pins_1>;
> >>> + mediatek,pad-select = <0>;
> >>> + status = "okay";
> >>> +};
> >>> +
> >>> +&spi2 {
> >>> + pinctrl-names = "default";
> >>> + pinctrl-0 = <&spi_pins_2>;
> >>> + mediatek,pad-select = <0>;
> >>> + status = "okay";
> >>> +};
> >>> +
> >>> +&spi3 {
> >>> + pinctrl-names = "default";
> >>> + pinctrl-0 = <&spi_pins_3>;
> >>> + mediatek,pad-select = <0>;
> >>> + status = "okay";
> >>> +};
> >>> +
> >>> +&spi4 {
> >>> + pinctrl-names = "default";
> >>> + pinctrl-0 = <&spi_pins_4>;
> >>> + mediatek,pad-select = <0>;
> >>> + status = "okay";
> >>> +};
> >>> +
> >>> +&spi5 {
> >>> + pinctrl-names = "default";
> >>> + pinctrl-0 = <&spi_pins_5>;
> >>> + mediatek,pad-select = <0>;
> >>> + status = "okay";
> >>> +
> >>> +};
> >>> +
> >>> +&uart0 {
> >>> + status = "okay";
> >>> +};
> >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
> >>> new file mode 100644
> >>> index 0000000..768e41e
> >>> --- /dev/null
> >>> +++ b/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
> >>> @@ -0,0 +1,1120 @@
> >>> +// SPDX-License-Identifier: GPL-2.0
> >>> +/*
> >>> + * Copyright (C) 2018 MediaTek Inc.
> >>> + * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
> >>> + *
> >>> + */
> >>> +
> >>> +#ifndef __MT8183_PINFUNC_H
> >>> +#define __MT8183_PINFUNC_H
> >>> +
> >>> +#include <dt-bindings/pinctrl/mt65xx.h>
> >>> +
> >>> +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
> >>> +#define PINMUX_GPIO0__FUNC_MRG_SYNC (MTK_PIN_NO(0) | 1)
> >>> +#define PINMUX_GPIO0__FUNC_PCM0_SYNC (MTK_PIN_NO(0) | 2)
> >>> +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 3)
> >>> +#define PINMUX_GPIO0__FUNC_SRCLKENAI0 (MTK_PIN_NO(0) | 4)
> >>> +#define PINMUX_GPIO0__FUNC_SCP_SPI2_CS (MTK_PIN_NO(0) | 5)
> >>> +#define PINMUX_GPIO0__FUNC_I2S3_MCK (MTK_PIN_NO(0) | 6)
> >>> +#define PINMUX_GPIO0__FUNC_SPI2_CSB (MTK_PIN_NO(0) | 7)
> >>> +
> >>> +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
> >>> +#define PINMUX_GPIO1__FUNC_MRG_CLK (MTK_PIN_NO(1) | 1)
> >>> +#define PINMUX_GPIO1__FUNC_PCM0_CLK (MTK_PIN_NO(1) | 2)
> >>> +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 3)
> >>> +#define PINMUX_GPIO1__FUNC_CLKM3 (MTK_PIN_NO(1) | 4)
> >>> +#define PINMUX_GPIO1__FUNC_SCP_SPI2_MO (MTK_PIN_NO(1) | 5)
> >>> +#define PINMUX_GPIO1__FUNC_I2S3_BCK (MTK_PIN_NO(1) | 6)
> >>> +#define PINMUX_GPIO1__FUNC_SPI2_MO (MTK_PIN_NO(1) | 7)
> >>> +
> >>> +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
> >>> +#define PINMUX_GPIO2__FUNC_MRG_DO (MTK_PIN_NO(2) | 1)
> >>> +#define PINMUX_GPIO2__FUNC_PCM0_DO (MTK_PIN_NO(2) | 2)
> >>> +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 3)
> >>> +#define PINMUX_GPIO2__FUNC_SCL6 (MTK_PIN_NO(2) | 4)
> >>> +#define PINMUX_GPIO2__FUNC_SCP_SPI2_CK (MTK_PIN_NO(2) | 5)
> >>> +#define PINMUX_GPIO2__FUNC_I2S3_LRCK (MTK_PIN_NO(2) | 6)
> >>> +#define PINMUX_GPIO2__FUNC_SPI2_CLK (MTK_PIN_NO(2) | 7)
> >>> +
> >>> +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
> >>> +#define PINMUX_GPIO3__FUNC_MRG_DI (MTK_PIN_NO(3) | 1)
> >>> +#define PINMUX_GPIO3__FUNC_PCM0_DI (MTK_PIN_NO(3) | 2)
> >>> +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 3)
> >>> +#define PINMUX_GPIO3__FUNC_SDA6 (MTK_PIN_NO(3) | 4)
> >>> +#define PINMUX_GPIO3__FUNC_TDM_MCK (MTK_PIN_NO(3) | 5)
> >>> +#define PINMUX_GPIO3__FUNC_I2S3_DO (MTK_PIN_NO(3) | 6)
> >>> +#define PINMUX_GPIO3__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(3) | 7)
> >>> +
> >>> +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
> >>> +#define PINMUX_GPIO4__FUNC_PWM_B (MTK_PIN_NO(4) | 1)
> >>> +#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2)
> >>> +#define PINMUX_GPIO4__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(4) | 3)
> >>> +#define PINMUX_GPIO4__FUNC_MD_URXD1 (MTK_PIN_NO(4) | 4)
> >>> +#define PINMUX_GPIO4__FUNC_TDM_BCK (MTK_PIN_NO(4) | 5)
> >>> +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6)
> >>> +#define PINMUX_GPIO4__FUNC_DAP_MD32_SWD (MTK_PIN_NO(4) | 7)
> >>> +
> >>> +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
> >>> +#define PINMUX_GPIO5__FUNC_PWM_C (MTK_PIN_NO(5) | 1)
> >>> +#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2)
> >>> +#define PINMUX_GPIO5__FUNC_SSPM_URXD_AO (MTK_PIN_NO(5) | 3)
> >>> +#define PINMUX_GPIO5__FUNC_MD_UTXD1 (MTK_PIN_NO(5) | 4)
> >>> +#define PINMUX_GPIO5__FUNC_TDM_LRCK (MTK_PIN_NO(5) | 5)
> >>> +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6)
> >>> +#define PINMUX_GPIO5__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(5) | 7)
> >>> +
> >>> +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
> >>> +#define PINMUX_GPIO6__FUNC_PWM_A (MTK_PIN_NO(6) | 1)
> >>> +#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2)
> >>> +#define PINMUX_GPIO6__FUNC_IDDIG (MTK_PIN_NO(6) | 3)
> >>> +#define PINMUX_GPIO6__FUNC_MD_URXD0 (MTK_PIN_NO(6) | 4)
> >>> +#define PINMUX_GPIO6__FUNC_TDM_DATA0 (MTK_PIN_NO(6) | 5)
> >>> +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6)
> >>> +#define PINMUX_GPIO6__FUNC_CMFLASH (MTK_PIN_NO(6) | 7)
> >>> +
> >>> +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
> >>> +#define PINMUX_GPIO7__FUNC_SPI1_B_MI (MTK_PIN_NO(7) | 1)
> >>> +#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2)
> >>> +#define PINMUX_GPIO7__FUNC_USB_DRVVBUS (MTK_PIN_NO(7) | 3)
> >>> +#define PINMUX_GPIO7__FUNC_MD_UTXD0 (MTK_PIN_NO(7) | 4)
> >>> +#define PINMUX_GPIO7__FUNC_TDM_DATA1 (MTK_PIN_NO(7) | 5)
> >>> +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6)
> >>> +#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 7)
> >>> +
> >>> +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
> >>> +#define PINMUX_GPIO8__FUNC_SPI1_B_CSB (MTK_PIN_NO(8) | 1)
> >>> +#define PINMUX_GPIO8__FUNC_ANT_SEL3 (MTK_PIN_NO(8) | 2)
> >>> +#define PINMUX_GPIO8__FUNC_SCL7 (MTK_PIN_NO(8) | 3)
> >>> +#define PINMUX_GPIO8__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(8) | 4)
> >>> +#define PINMUX_GPIO8__FUNC_TDM_DATA2 (MTK_PIN_NO(8) | 5)
> >>> +#define PINMUX_GPIO8__FUNC_MD_INT0 (MTK_PIN_NO(8) | 6)
> >>> +#define PINMUX_GPIO8__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(8) | 7)
> >>> +
> >>> +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
> >>> +#define PINMUX_GPIO9__FUNC_SPI1_B_MO (MTK_PIN_NO(9) | 1)
> >>> +#define PINMUX_GPIO9__FUNC_ANT_SEL4 (MTK_PIN_NO(9) | 2)
> >>> +#define PINMUX_GPIO9__FUNC_CMMCLK2 (MTK_PIN_NO(9) | 3)
> >>> +#define PINMUX_GPIO9__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(9) | 4)
> >>> +#define PINMUX_GPIO9__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(9) | 5)
> >>> +#define PINMUX_GPIO9__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(9) | 6)
> >>> +#define PINMUX_GPIO9__FUNC_DBG_MON_B10 (MTK_PIN_NO(9) | 7)
> >>> +
> >>> +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
> >>> +#define PINMUX_GPIO10__FUNC_SPI1_B_CLK (MTK_PIN_NO(10) | 1)
> >>> +#define PINMUX_GPIO10__FUNC_ANT_SEL5 (MTK_PIN_NO(10) | 2)
> >>> +#define PINMUX_GPIO10__FUNC_CMMCLK3 (MTK_PIN_NO(10) | 3)
> >>> +#define PINMUX_GPIO10__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(10) | 4)
> >>> +#define PINMUX_GPIO10__FUNC_TDM_DATA3 (MTK_PIN_NO(10) | 5)
> >>> +#define PINMUX_GPIO10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 6)
> >>> +#define PINMUX_GPIO10__FUNC_DBG_MON_B11 (MTK_PIN_NO(10) | 7)
> >>> +
> >>> +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
> >>> +#define PINMUX_GPIO11__FUNC_TP_URXD1_AO (MTK_PIN_NO(11) | 1)
> >>> +#define PINMUX_GPIO11__FUNC_IDDIG (MTK_PIN_NO(11) | 2)
> >>> +#define PINMUX_GPIO11__FUNC_SCL6 (MTK_PIN_NO(11) | 3)
> >>> +#define PINMUX_GPIO11__FUNC_UCTS1 (MTK_PIN_NO(11) | 4)
> >>> +#define PINMUX_GPIO11__FUNC_UCTS0 (MTK_PIN_NO(11) | 5)
> >>> +#define PINMUX_GPIO11__FUNC_SRCLKENAI1 (MTK_PIN_NO(11) | 6)
> >>> +#define PINMUX_GPIO11__FUNC_I2S5_MCK (MTK_PIN_NO(11) | 7)
> >>> +
> >>> +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
> >>> +#define PINMUX_GPIO12__FUNC_TP_UTXD1_AO (MTK_PIN_NO(12) | 1)
> >>> +#define PINMUX_GPIO12__FUNC_USB_DRVVBUS (MTK_PIN_NO(12) | 2)
> >>> +#define PINMUX_GPIO12__FUNC_SDA6 (MTK_PIN_NO(12) | 3)
> >>> +#define PINMUX_GPIO12__FUNC_URTS1 (MTK_PIN_NO(12) | 4)
> >>> +#define PINMUX_GPIO12__FUNC_URTS0 (MTK_PIN_NO(12) | 5)
> >>> +#define PINMUX_GPIO12__FUNC_I2S2_DI2 (MTK_PIN_NO(12) | 6)
> >>> +#define PINMUX_GPIO12__FUNC_I2S5_BCK (MTK_PIN_NO(12) | 7)
> >>> +
> >>> +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
> >>> +#define PINMUX_GPIO13__FUNC_DBPI_D0 (MTK_PIN_NO(13) | 1)
> >>> +#define PINMUX_GPIO13__FUNC_SPI5_MI (MTK_PIN_NO(13) | 2)
> >>> +#define PINMUX_GPIO13__FUNC_PCM0_SYNC (MTK_PIN_NO(13) | 3)
> >>> +#define PINMUX_GPIO13__FUNC_MD_URXD0 (MTK_PIN_NO(13) | 4)
> >>> +#define PINMUX_GPIO13__FUNC_ANT_SEL3 (MTK_PIN_NO(13) | 5)
> >>> +#define PINMUX_GPIO13__FUNC_I2S0_MCK (MTK_PIN_NO(13) | 6)
> >>> +#define PINMUX_GPIO13__FUNC_DBG_MON_B15 (MTK_PIN_NO(13) | 7)
> >>> +
> >>> +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
> >>> +#define PINMUX_GPIO14__FUNC_DBPI_D1 (MTK_PIN_NO(14) | 1)
> >>> +#define PINMUX_GPIO14__FUNC_SPI5_CSB (MTK_PIN_NO(14) | 2)
> >>> +#define PINMUX_GPIO14__FUNC_PCM0_CLK (MTK_PIN_NO(14) | 3)
> >>> +#define PINMUX_GPIO14__FUNC_MD_UTXD0 (MTK_PIN_NO(14) | 4)
> >>> +#define PINMUX_GPIO14__FUNC_ANT_SEL4 (MTK_PIN_NO(14) | 5)
> >>> +#define PINMUX_GPIO14__FUNC_I2S0_BCK (MTK_PIN_NO(14) | 6)
> >>> +#define PINMUX_GPIO14__FUNC_DBG_MON_B16 (MTK_PIN_NO(14) | 7)
> >>> +
> >>> +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
> >>> +#define PINMUX_GPIO15__FUNC_DBPI_D2 (MTK_PIN_NO(15) | 1)
> >>> +#define PINMUX_GPIO15__FUNC_SPI5_MO (MTK_PIN_NO(15) | 2)
> >>> +#define PINMUX_GPIO15__FUNC_PCM0_DO (MTK_PIN_NO(15) | 3)
> >>> +#define PINMUX_GPIO15__FUNC_MD_URXD1 (MTK_PIN_NO(15) | 4)
> >>> +#define PINMUX_GPIO15__FUNC_ANT_SEL5 (MTK_PIN_NO(15) | 5)
> >>> +#define PINMUX_GPIO15__FUNC_I2S0_LRCK (MTK_PIN_NO(15) | 6)
> >>> +#define PINMUX_GPIO15__FUNC_DBG_MON_B17 (MTK_PIN_NO(15) | 7)
> >>> +
> >>> +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
> >>> +#define PINMUX_GPIO16__FUNC_DBPI_D3 (MTK_PIN_NO(16) | 1)
> >>> +#define PINMUX_GPIO16__FUNC_SPI5_CLK (MTK_PIN_NO(16) | 2)
> >>> +#define PINMUX_GPIO16__FUNC_PCM0_DI (MTK_PIN_NO(16) | 3)
> >>> +#define PINMUX_GPIO16__FUNC_MD_UTXD1 (MTK_PIN_NO(16) | 4)
> >>> +#define PINMUX_GPIO16__FUNC_ANT_SEL6 (MTK_PIN_NO(16) | 5)
> >>> +#define PINMUX_GPIO16__FUNC_I2S0_DI (MTK_PIN_NO(16) | 6)
> >>> +#define PINMUX_GPIO16__FUNC_DBG_MON_B23 (MTK_PIN_NO(16) | 7)
> >>> +
> >>> +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
> >>> +#define PINMUX_GPIO17__FUNC_DBPI_D4 (MTK_PIN_NO(17) | 1)
> >>> +#define PINMUX_GPIO17__FUNC_SPI4_MI (MTK_PIN_NO(17) | 2)
> >>> +#define PINMUX_GPIO17__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(17) | 3)
> >>> +#define PINMUX_GPIO17__FUNC_MD_INT0 (MTK_PIN_NO(17) | 4)
> >>> +#define PINMUX_GPIO17__FUNC_ANT_SEL7 (MTK_PIN_NO(17) | 5)
> >>> +#define PINMUX_GPIO17__FUNC_I2S3_MCK (MTK_PIN_NO(17) | 6)
> >>> +#define PINMUX_GPIO17__FUNC_DBG_MON_A1 (MTK_PIN_NO(17) | 7)
> >>> +
> >>> +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
> >>> +#define PINMUX_GPIO18__FUNC_DBPI_D5 (MTK_PIN_NO(18) | 1)
> >>> +#define PINMUX_GPIO18__FUNC_SPI4_CSB (MTK_PIN_NO(18) | 2)
> >>> +#define PINMUX_GPIO18__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(18) | 3)
> >>> +#define PINMUX_GPIO18__FUNC_MD_INT0 (MTK_PIN_NO(18) | 4)
> >>> +#define PINMUX_GPIO18__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(18) | 5)
> >>> +#define PINMUX_GPIO18__FUNC_I2S3_BCK (MTK_PIN_NO(18) | 6)
> >>> +#define PINMUX_GPIO18__FUNC_DBG_MON_A2 (MTK_PIN_NO(18) | 7)
> >>> +
> >>> +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
> >>> +#define PINMUX_GPIO19__FUNC_DBPI_D6 (MTK_PIN_NO(19) | 1)
> >>> +#define PINMUX_GPIO19__FUNC_SPI4_MO (MTK_PIN_NO(19) | 2)
> >>> +#define PINMUX_GPIO19__FUNC_CONN_MCU_TDO (MTK_PIN_NO(19) | 3)
> >>> +#define PINMUX_GPIO19__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(19) | 4)
> >>> +#define PINMUX_GPIO19__FUNC_URXD1 (MTK_PIN_NO(19) | 5)
> >>> +#define PINMUX_GPIO19__FUNC_I2S3_LRCK (MTK_PIN_NO(19) | 6)
> >>> +#define PINMUX_GPIO19__FUNC_DBG_MON_A3 (MTK_PIN_NO(19) | 7)
> >>> +
> >>> +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
> >>> +#define PINMUX_GPIO20__FUNC_DBPI_D7 (MTK_PIN_NO(20) | 1)
> >>> +#define PINMUX_GPIO20__FUNC_SPI4_CLK (MTK_PIN_NO(20) | 2)
> >>> +#define PINMUX_GPIO20__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(20) | 3)
> >>> +#define PINMUX_GPIO20__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(20) | 4)
> >>> +#define PINMUX_GPIO20__FUNC_UTXD1 (MTK_PIN_NO(20) | 5)
> >>> +#define PINMUX_GPIO20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 6)
> >>> +#define PINMUX_GPIO20__FUNC_DBG_MON_A19 (MTK_PIN_NO(20) | 7)
> >>> +
> >>> +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
> >>> +#define PINMUX_GPIO21__FUNC_DBPI_D8 (MTK_PIN_NO(21) | 1)
> >>> +#define PINMUX_GPIO21__FUNC_SPI3_MI (MTK_PIN_NO(21) | 2)
> >>> +#define PINMUX_GPIO21__FUNC_CONN_MCU_TMS (MTK_PIN_NO(21) | 3)
> >>> +#define PINMUX_GPIO21__FUNC_DAP_MD32_SWD (MTK_PIN_NO(21) | 4)
> >>> +#define PINMUX_GPIO21__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(21) | 5)
> >>> +#define PINMUX_GPIO21__FUNC_I2S2_MCK (MTK_PIN_NO(21) | 6)
> >>> +#define PINMUX_GPIO21__FUNC_DBG_MON_B5 (MTK_PIN_NO(21) | 7)
> >>> +
> >>> +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
> >>> +#define PINMUX_GPIO22__FUNC_DBPI_D9 (MTK_PIN_NO(22) | 1)
> >>> +#define PINMUX_GPIO22__FUNC_SPI3_CSB (MTK_PIN_NO(22) | 2)
> >>> +#define PINMUX_GPIO22__FUNC_CONN_MCU_TCK (MTK_PIN_NO(22) | 3)
> >>> +#define PINMUX_GPIO22__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(22) | 4)
> >>> +#define PINMUX_GPIO22__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(22) | 5)
> >>> +#define PINMUX_GPIO22__FUNC_I2S2_BCK (MTK_PIN_NO(22) | 6)
> >>> +#define PINMUX_GPIO22__FUNC_DBG_MON_B6 (MTK_PIN_NO(22) | 7)
> >>> +
> >>> +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
> >>> +#define PINMUX_GPIO23__FUNC_DBPI_D10 (MTK_PIN_NO(23) | 1)
> >>> +#define PINMUX_GPIO23__FUNC_SPI3_MO (MTK_PIN_NO(23) | 2)
> >>> +#define PINMUX_GPIO23__FUNC_CONN_MCU_TDI (MTK_PIN_NO(23) | 3)
> >>> +#define PINMUX_GPIO23__FUNC_UCTS1 (MTK_PIN_NO(23) | 4)
> >>> +#define PINMUX_GPIO23__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5)
> >>> +#define PINMUX_GPIO23__FUNC_I2S2_LRCK (MTK_PIN_NO(23) | 6)
> >>> +#define PINMUX_GPIO23__FUNC_DBG_MON_B7 (MTK_PIN_NO(23) | 7)
> >>> +
> >>> +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
> >>> +#define PINMUX_GPIO24__FUNC_DBPI_D11 (MTK_PIN_NO(24) | 1)
> >>> +#define PINMUX_GPIO24__FUNC_SPI3_CLK (MTK_PIN_NO(24) | 2)
> >>> +#define PINMUX_GPIO24__FUNC_SRCLKENAI0 (MTK_PIN_NO(24) | 3)
> >>> +#define PINMUX_GPIO24__FUNC_URTS1 (MTK_PIN_NO(24) | 4)
> >>> +#define PINMUX_GPIO24__FUNC_IO_JTAG_TCK (MTK_PIN_NO(24) | 5)
> >>> +#define PINMUX_GPIO24__FUNC_I2S2_DI (MTK_PIN_NO(24) | 6)
> >>> +#define PINMUX_GPIO24__FUNC_DBG_MON_B31 (MTK_PIN_NO(24) | 7)
> >>> +
> >>> +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
> >>> +#define PINMUX_GPIO25__FUNC_DBPI_HSYNC (MTK_PIN_NO(25) | 1)
> >>> +#define PINMUX_GPIO25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 2)
> >>> +#define PINMUX_GPIO25__FUNC_SCL6 (MTK_PIN_NO(25) | 3)
> >>> +#define PINMUX_GPIO25__FUNC_KPCOL2 (MTK_PIN_NO(25) | 4)
> >>> +#define PINMUX_GPIO25__FUNC_IO_JTAG_TMS (MTK_PIN_NO(25) | 5)
> >>> +#define PINMUX_GPIO25__FUNC_I2S1_MCK (MTK_PIN_NO(25) | 6)
> >>> +#define PINMUX_GPIO25__FUNC_DBG_MON_B0 (MTK_PIN_NO(25) | 7)
> >>> +
> >>> +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
> >>> +#define PINMUX_GPIO26__FUNC_DBPI_VSYNC (MTK_PIN_NO(26) | 1)
> >>> +#define PINMUX_GPIO26__FUNC_ANT_SEL1 (MTK_PIN_NO(26) | 2)
> >>> +#define PINMUX_GPIO26__FUNC_SDA6 (MTK_PIN_NO(26) | 3)
> >>> +#define PINMUX_GPIO26__FUNC_KPROW2 (MTK_PIN_NO(26) | 4)
> >>> +#define PINMUX_GPIO26__FUNC_IO_JTAG_TDI (MTK_PIN_NO(26) | 5)
> >>> +#define PINMUX_GPIO26__FUNC_I2S1_BCK (MTK_PIN_NO(26) | 6)
> >>> +#define PINMUX_GPIO26__FUNC_DBG_MON_B1 (MTK_PIN_NO(26) | 7)
> >>> +
> >>> +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
> >>> +#define PINMUX_GPIO27__FUNC_DBPI_DE (MTK_PIN_NO(27) | 1)
> >>> +#define PINMUX_GPIO27__FUNC_ANT_SEL2 (MTK_PIN_NO(27) | 2)
> >>> +#define PINMUX_GPIO27__FUNC_SCL7 (MTK_PIN_NO(27) | 3)
> >>> +#define PINMUX_GPIO27__FUNC_DMIC_CLK (MTK_PIN_NO(27) | 4)
> >>> +#define PINMUX_GPIO27__FUNC_IO_JTAG_TDO (MTK_PIN_NO(27) | 5)
> >>> +#define PINMUX_GPIO27__FUNC_I2S1_LRCK (MTK_PIN_NO(27) | 6)
> >>> +#define PINMUX_GPIO27__FUNC_DBG_MON_B9 (MTK_PIN_NO(27) | 7)
> >>> +
> >>> +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
> >>> +#define PINMUX_GPIO28__FUNC_DBPI_CK (MTK_PIN_NO(28) | 1)
> >>> +#define PINMUX_GPIO28__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(28) | 2)
> >>> +#define PINMUX_GPIO28__FUNC_SDA7 (MTK_PIN_NO(28) | 3)
> >>> +#define PINMUX_GPIO28__FUNC_DMIC_DAT (MTK_PIN_NO(28) | 4)
> >>> +#define PINMUX_GPIO28__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(28) | 5)
> >>> +#define PINMUX_GPIO28__FUNC_I2S1_DO (MTK_PIN_NO(28) | 6)
> >>> +#define PINMUX_GPIO28__FUNC_DBG_MON_B32 (MTK_PIN_NO(28) | 7)
> >>> +
> >>> +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
> >>> +#define PINMUX_GPIO29__FUNC_MSDC1_CLK (MTK_PIN_NO(29) | 1)
> >>> +#define PINMUX_GPIO29__FUNC_IO_JTAG_TCK (MTK_PIN_NO(29) | 2)
> >>> +#define PINMUX_GPIO29__FUNC_UDI_TCK (MTK_PIN_NO(29) | 3)
> >>> +#define PINMUX_GPIO29__FUNC_CONN_DSP_JCK (MTK_PIN_NO(29) | 4)
> >>> +#define PINMUX_GPIO29__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(29) | 5)
> >>> +#define PINMUX_GPIO29__FUNC_PCM1_CLK (MTK_PIN_NO(29) | 6)
> >>> +#define PINMUX_GPIO29__FUNC_DBG_MON_A6 (MTK_PIN_NO(29) | 7)
> >>> +
> >>> +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
> >>> +#define PINMUX_GPIO30__FUNC_MSDC1_DAT3 (MTK_PIN_NO(30) | 1)
> >>> +#define PINMUX_GPIO30__FUNC_DAP_MD32_SWD (MTK_PIN_NO(30) | 2)
> >>> +#define PINMUX_GPIO30__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 3)
> >>> +#define PINMUX_GPIO30__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(30) | 4)
> >>> +#define PINMUX_GPIO30__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(30) | 5)
> >>> +#define PINMUX_GPIO30__FUNC_PCM1_DI (MTK_PIN_NO(30) | 6)
> >>> +#define PINMUX_GPIO30__FUNC_DBG_MON_A7 (MTK_PIN_NO(30) | 7)
> >>> +
> >>> +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
> >>> +#define PINMUX_GPIO31__FUNC_MSDC1_CMD (MTK_PIN_NO(31) | 1)
> >>> +#define PINMUX_GPIO31__FUNC_IO_JTAG_TMS (MTK_PIN_NO(31) | 2)
> >>> +#define PINMUX_GPIO31__FUNC_UDI_TMS (MTK_PIN_NO(31) | 3)
> >>> +#define PINMUX_GPIO31__FUNC_CONN_DSP_JMS (MTK_PIN_NO(31) | 4)
> >>> +#define PINMUX_GPIO31__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(31) | 5)
> >>> +#define PINMUX_GPIO31__FUNC_PCM1_SYNC (MTK_PIN_NO(31) | 6)
> >>> +#define PINMUX_GPIO31__FUNC_DBG_MON_A8 (MTK_PIN_NO(31) | 7)
> >>> +
> >>> +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
> >>> +#define PINMUX_GPIO32__FUNC_MSDC1_DAT0 (MTK_PIN_NO(32) | 1)
> >>> +#define PINMUX_GPIO32__FUNC_IO_JTAG_TDI (MTK_PIN_NO(32) | 2)
> >>> +#define PINMUX_GPIO32__FUNC_UDI_TDI (MTK_PIN_NO(32) | 3)
> >>> +#define PINMUX_GPIO32__FUNC_CONN_DSP_JDI (MTK_PIN_NO(32) | 4)
> >>> +#define PINMUX_GPIO32__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(32) | 5)
> >>> +#define PINMUX_GPIO32__FUNC_PCM1_DO0 (MTK_PIN_NO(32) | 6)
> >>> +#define PINMUX_GPIO32__FUNC_DBG_MON_A9 (MTK_PIN_NO(32) | 7)
> >>> +
> >>> +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
> >>> +#define PINMUX_GPIO33__FUNC_MSDC1_DAT2 (MTK_PIN_NO(33) | 1)
> >>> +#define PINMUX_GPIO33__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(33) | 2)
> >>> +#define PINMUX_GPIO33__FUNC_UDI_NTRST (MTK_PIN_NO(33) | 3)
> >>> +#define PINMUX_GPIO33__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(33) | 4)
> >>> +#define PINMUX_GPIO33__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(33) | 5)
> >>> +#define PINMUX_GPIO33__FUNC_PCM1_DO2 (MTK_PIN_NO(33) | 6)
> >>> +#define PINMUX_GPIO33__FUNC_DBG_MON_A10 (MTK_PIN_NO(33) | 7)
> >>> +
> >>> +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
> >>> +#define PINMUX_GPIO34__FUNC_MSDC1_DAT1 (MTK_PIN_NO(34) | 1)
> >>> +#define PINMUX_GPIO34__FUNC_IO_JTAG_TDO (MTK_PIN_NO(34) | 2)
> >>> +#define PINMUX_GPIO34__FUNC_UDI_TDO (MTK_PIN_NO(34) | 3)
> >>> +#define PINMUX_GPIO34__FUNC_CONN_DSP_JDO (MTK_PIN_NO(34) | 4)
> >>> +#define PINMUX_GPIO34__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(34) | 5)
> >>> +#define PINMUX_GPIO34__FUNC_PCM1_DO1 (MTK_PIN_NO(34) | 6)
> >>> +#define PINMUX_GPIO34__FUNC_DBG_MON_A11 (MTK_PIN_NO(34) | 7)
> >>> +
> >>> +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
> >>> +#define PINMUX_GPIO35__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(35) | 1)
> >>> +#define PINMUX_GPIO35__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(35) | 2)
> >>> +#define PINMUX_GPIO35__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(35) | 3)
> >>> +#define PINMUX_GPIO35__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(35) | 5)
> >>> +#define PINMUX_GPIO35__FUNC_CONN_DSP_JMS (MTK_PIN_NO(35) | 6)
> >>> +#define PINMUX_GPIO35__FUNC_DBG_MON_A28 (MTK_PIN_NO(35) | 7)
> >>> +
> >>> +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
> >>> +#define PINMUX_GPIO36__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(36) | 1)
> >>> +#define PINMUX_GPIO36__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(36) | 2)
> >>> +#define PINMUX_GPIO36__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(36) | 3)
> >>> +#define PINMUX_GPIO36__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(36) | 4)
> >>> +#define PINMUX_GPIO36__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(36) | 5)
> >>> +#define PINMUX_GPIO36__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(36) | 6)
> >>> +#define PINMUX_GPIO36__FUNC_DBG_MON_A29 (MTK_PIN_NO(36) | 7)
> >>> +
> >>> +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
> >>> +#define PINMUX_GPIO37__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(37) | 1)
> >>> +#define PINMUX_GPIO37__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(37) | 2)
> >>> +#define PINMUX_GPIO37__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(37) | 3)
> >>> +#define PINMUX_GPIO37__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(37) | 5)
> >>> +#define PINMUX_GPIO37__FUNC_CONN_DSP_JDO (MTK_PIN_NO(37) | 6)
> >>> +#define PINMUX_GPIO37__FUNC_DBG_MON_A30 (MTK_PIN_NO(37) | 7)
> >>> +
> >>> +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
> >>> +#define PINMUX_GPIO38__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(38) | 1)
> >>> +#define PINMUX_GPIO38__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(38) | 3)
> >>> +#define PINMUX_GPIO38__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(38) | 4)
> >>> +#define PINMUX_GPIO38__FUNC_DBG_MON_A20 (MTK_PIN_NO(38) | 7)
> >>> +
> >>> +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
> >>> +#define PINMUX_GPIO39__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(39) | 1)
> >>> +#define PINMUX_GPIO39__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(39) | 2)
> >>> +#define PINMUX_GPIO39__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(39) | 3)
> >>> +#define PINMUX_GPIO39__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(39) | 5)
> >>> +#define PINMUX_GPIO39__FUNC_CONN_DSP_JCK (MTK_PIN_NO(39) | 6)
> >>> +#define PINMUX_GPIO39__FUNC_DBG_MON_A31 (MTK_PIN_NO(39) | 7)
> >>> +
> >>> +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
> >>> +#define PINMUX_GPIO40__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(40) | 1)
> >>> +#define PINMUX_GPIO40__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(40) | 2)
> >>> +#define PINMUX_GPIO40__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(40) | 3)
> >>> +#define PINMUX_GPIO40__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(40) | 5)
> >>> +#define PINMUX_GPIO40__FUNC_CONN_DSP_JDI (MTK_PIN_NO(40) | 6)
> >>> +#define PINMUX_GPIO40__FUNC_DBG_MON_A32 (MTK_PIN_NO(40) | 7)
> >>> +
> >>> +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
> >>> +#define PINMUX_GPIO41__FUNC_IDDIG (MTK_PIN_NO(41) | 1)
> >>> +#define PINMUX_GPIO41__FUNC_URXD1 (MTK_PIN_NO(41) | 2)
> >>> +#define PINMUX_GPIO41__FUNC_UCTS0 (MTK_PIN_NO(41) | 3)
> >>> +#define PINMUX_GPIO41__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(41) | 4)
> >>> +#define PINMUX_GPIO41__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 5)
> >>> +#define PINMUX_GPIO41__FUNC_DMIC_CLK (MTK_PIN_NO(41) | 6)
> >>> +
> >>> +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
> >>> +#define PINMUX_GPIO42__FUNC_USB_DRVVBUS (MTK_PIN_NO(42) | 1)
> >>> +#define PINMUX_GPIO42__FUNC_UTXD1 (MTK_PIN_NO(42) | 2)
> >>> +#define PINMUX_GPIO42__FUNC_URTS0 (MTK_PIN_NO(42) | 3)
> >>> +#define PINMUX_GPIO42__FUNC_SSPM_URXD_AO (MTK_PIN_NO(42) | 4)
> >>> +#define PINMUX_GPIO42__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(42) | 5)
> >>> +#define PINMUX_GPIO42__FUNC_DMIC_DAT (MTK_PIN_NO(42) | 6)
> >>> +
> >>> +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
> >>> +#define PINMUX_GPIO43__FUNC_DISP_PWM (MTK_PIN_NO(43) | 1)
> >>> +
> >>> +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
> >>> +#define PINMUX_GPIO44__FUNC_DSI_TE (MTK_PIN_NO(44) | 1)
> >>> +
> >>> +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
> >>> +#define PINMUX_GPIO45__FUNC_LCM_RST (MTK_PIN_NO(45) | 1)
> >>> +
> >>> +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
> >>> +#define PINMUX_GPIO46__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(46) | 1)
> >>> +#define PINMUX_GPIO46__FUNC_URXD1 (MTK_PIN_NO(46) | 2)
> >>> +#define PINMUX_GPIO46__FUNC_UCTS1 (MTK_PIN_NO(46) | 3)
> >>> +#define PINMUX_GPIO46__FUNC_CCU_UTXD_AO (MTK_PIN_NO(46) | 4)
> >>> +#define PINMUX_GPIO46__FUNC_TP_UCTS1_AO (MTK_PIN_NO(46) | 5)
> >>> +#define PINMUX_GPIO46__FUNC_IDDIG (MTK_PIN_NO(46) | 6)
> >>> +#define PINMUX_GPIO46__FUNC_I2S5_LRCK (MTK_PIN_NO(46) | 7)
> >>> +
> >>> +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
> >>> +#define PINMUX_GPIO47__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(47) | 1)
> >>> +#define PINMUX_GPIO47__FUNC_UTXD1 (MTK_PIN_NO(47) | 2)
> >>> +#define PINMUX_GPIO47__FUNC_URTS1 (MTK_PIN_NO(47) | 3)
> >>> +#define PINMUX_GPIO47__FUNC_CCU_URXD_AO (MTK_PIN_NO(47) | 4)
> >>> +#define PINMUX_GPIO47__FUNC_TP_URTS1_AO (MTK_PIN_NO(47) | 5)
> >>> +#define PINMUX_GPIO47__FUNC_USB_DRVVBUS (MTK_PIN_NO(47) | 6)
> >>> +#define PINMUX_GPIO47__FUNC_I2S5_DO (MTK_PIN_NO(47) | 7)
> >>> +
> >>> +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
> >>> +#define PINMUX_GPIO48__FUNC_SCL5 (MTK_PIN_NO(48) | 1)
> >>> +
> >>> +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
> >>> +#define PINMUX_GPIO49__FUNC_SDA5 (MTK_PIN_NO(49) | 1)
> >>> +
> >>> +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
> >>> +#define PINMUX_GPIO50__FUNC_SCL3 (MTK_PIN_NO(50) | 1)
> >>> +
> >>> +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
> >>> +#define PINMUX_GPIO51__FUNC_SDA3 (MTK_PIN_NO(51) | 1)
> >>> +
> >>> +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
> >>> +#define PINMUX_GPIO52__FUNC_BPI_ANT2 (MTK_PIN_NO(52) | 1)
> >>> +
> >>> +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
> >>> +#define PINMUX_GPIO53__FUNC_BPI_ANT0 (MTK_PIN_NO(53) | 1)
> >>> +
> >>> +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
> >>> +#define PINMUX_GPIO54__FUNC_BPI_OLAT1 (MTK_PIN_NO(54) | 1)
> >>> +
> >>> +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
> >>> +#define PINMUX_GPIO55__FUNC_BPI_BUS8 (MTK_PIN_NO(55) | 1)
> >>> +
> >>> +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
> >>> +#define PINMUX_GPIO56__FUNC_BPI_BUS9 (MTK_PIN_NO(56) | 1)
> >>> +#define PINMUX_GPIO56__FUNC_SCL_6306 (MTK_PIN_NO(56) | 2)
> >>> +
> >>> +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
> >>> +#define PINMUX_GPIO57__FUNC_BPI_BUS10 (MTK_PIN_NO(57) | 1)
> >>> +#define PINMUX_GPIO57__FUNC_SDA_6306 (MTK_PIN_NO(57) | 2)
> >>> +
> >>> +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
> >>> +#define PINMUX_GPIO58__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(58) | 1)
> >>> +#define PINMUX_GPIO58__FUNC_SPM_BSI_D2 (MTK_PIN_NO(58) | 2)
> >>> +#define PINMUX_GPIO58__FUNC_PWM_B (MTK_PIN_NO(58) | 3)
> >>> +
> >>> +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
> >>> +#define PINMUX_GPIO59__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(59) | 1)
> >>> +#define PINMUX_GPIO59__FUNC_SPM_BSI_D1 (MTK_PIN_NO(59) | 2)
> >>> +
> >>> +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
> >>> +#define PINMUX_GPIO60__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(60) | 1)
> >>> +#define PINMUX_GPIO60__FUNC_SPM_BSI_D0 (MTK_PIN_NO(60) | 2)
> >>> +
> >>> +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
> >>> +#define PINMUX_GPIO61__FUNC_MIPI1_SDATA (MTK_PIN_NO(61) | 1)
> >>> +
> >>> +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
> >>> +#define PINMUX_GPIO62__FUNC_MIPI1_SCLK (MTK_PIN_NO(62) | 1)
> >>> +
> >>> +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
> >>> +#define PINMUX_GPIO63__FUNC_MIPI0_SDATA (MTK_PIN_NO(63) | 1)
> >>> +
> >>> +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
> >>> +#define PINMUX_GPIO64__FUNC_MIPI0_SCLK (MTK_PIN_NO(64) | 1)
> >>> +
> >>> +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
> >>> +#define PINMUX_GPIO65__FUNC_MIPI3_SDATA (MTK_PIN_NO(65) | 1)
> >>> +#define PINMUX_GPIO65__FUNC_BPI_OLAT2 (MTK_PIN_NO(65) | 2)
> >>> +
> >>> +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
> >>> +#define PINMUX_GPIO66__FUNC_MIPI3_SCLK (MTK_PIN_NO(66) | 1)
> >>> +#define PINMUX_GPIO66__FUNC_BPI_OLAT3 (MTK_PIN_NO(66) | 2)
> >>> +
> >>> +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
> >>> +#define PINMUX_GPIO67__FUNC_MIPI2_SDATA (MTK_PIN_NO(67) | 1)
> >>> +
> >>> +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
> >>> +#define PINMUX_GPIO68__FUNC_MIPI2_SCLK (MTK_PIN_NO(68) | 1)
> >>> +
> >>> +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
> >>> +#define PINMUX_GPIO69__FUNC_BPI_BUS7 (MTK_PIN_NO(69) | 1)
> >>> +
> >>> +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
> >>> +#define PINMUX_GPIO70__FUNC_BPI_BUS6 (MTK_PIN_NO(70) | 1)
> >>> +
> >>> +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
> >>> +#define PINMUX_GPIO71__FUNC_BPI_BUS5 (MTK_PIN_NO(71) | 1)
> >>> +
> >>> +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
> >>> +#define PINMUX_GPIO72__FUNC_BPI_BUS4 (MTK_PIN_NO(72) | 1)
> >>> +
> >>> +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
> >>> +#define PINMUX_GPIO73__FUNC_BPI_BUS3 (MTK_PIN_NO(73) | 1)
> >>> +
> >>> +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
> >>> +#define PINMUX_GPIO74__FUNC_BPI_BUS2 (MTK_PIN_NO(74) | 1)
> >>> +
> >>> +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
> >>> +#define PINMUX_GPIO75__FUNC_BPI_BUS1 (MTK_PIN_NO(75) | 1)
> >>> +
> >>> +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
> >>> +#define PINMUX_GPIO76__FUNC_BPI_BUS0 (MTK_PIN_NO(76) | 1)
> >>> +
> >>> +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
> >>> +#define PINMUX_GPIO77__FUNC_BPI_ANT1 (MTK_PIN_NO(77) | 1)
> >>> +
> >>> +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
> >>> +#define PINMUX_GPIO78__FUNC_BPI_OLAT0 (MTK_PIN_NO(78) | 1)
> >>> +
> >>> +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
> >>> +#define PINMUX_GPIO79__FUNC_BPI_PA_VM1 (MTK_PIN_NO(79) | 1)
> >>> +#define PINMUX_GPIO79__FUNC_MIPI4_SDATA (MTK_PIN_NO(79) | 2)
> >>> +
> >>> +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
> >>> +#define PINMUX_GPIO80__FUNC_BPI_PA_VM0 (MTK_PIN_NO(80) | 1)
> >>> +#define PINMUX_GPIO80__FUNC_MIPI4_SCLK (MTK_PIN_NO(80) | 2)
> >>> +
> >>> +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
> >>> +#define PINMUX_GPIO81__FUNC_SDA1 (MTK_PIN_NO(81) | 1)
> >>> +
> >>> +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
> >>> +#define PINMUX_GPIO82__FUNC_SDA0 (MTK_PIN_NO(82) | 1)
> >>> +
> >>> +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
> >>> +#define PINMUX_GPIO83__FUNC_SCL0 (MTK_PIN_NO(83) | 1)
> >>> +
> >>> +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
> >>> +#define PINMUX_GPIO84__FUNC_SCL1 (MTK_PIN_NO(84) | 1)
> >>> +
> >>> +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
> >>> +#define PINMUX_GPIO85__FUNC_SPI0_MI (MTK_PIN_NO(85) | 1)
> >>> +#define PINMUX_GPIO85__FUNC_SCP_SPI0_MI (MTK_PIN_NO(85) | 2)
> >>> +#define PINMUX_GPIO85__FUNC_CLKM3 (MTK_PIN_NO(85) | 3)
> >>> +#define PINMUX_GPIO85__FUNC_I2S1_BCK (MTK_PIN_NO(85) | 4)
> >>> +#define PINMUX_GPIO85__FUNC_MFG_DFD_JTAG_TDO (MTK_PIN_NO(85) | 5)
> >>> +#define PINMUX_GPIO85__FUNC_DFD_TDO (MTK_PIN_NO(85) | 6)
> >>> +#define PINMUX_GPIO85__FUNC_JTDO_SEL1 (MTK_PIN_NO(85) | 7)
> >>> +
> >>> +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
> >>> +#define PINMUX_GPIO86__FUNC_SPI0_CSB (MTK_PIN_NO(86) | 1)
> >>> +#define PINMUX_GPIO86__FUNC_SCP_SPI0_CS (MTK_PIN_NO(86) | 2)
> >>> +#define PINMUX_GPIO86__FUNC_CLKM0 (MTK_PIN_NO(86) | 3)
> >>> +#define PINMUX_GPIO86__FUNC_I2S1_LRCK (MTK_PIN_NO(86) | 4)
> >>> +#define PINMUX_GPIO86__FUNC_MFG_DFD_JTAG_TMS (MTK_PIN_NO(86) | 5)
> >>> +#define PINMUX_GPIO86__FUNC_DFD_TMS (MTK_PIN_NO(86) | 6)
> >>> +#define PINMUX_GPIO86__FUNC_JTMS_SEL1 (MTK_PIN_NO(86) | 7)
> >>> +
> >>> +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
> >>> +#define PINMUX_GPIO87__FUNC_SPI0_MO (MTK_PIN_NO(87) | 1)
> >>> +#define PINMUX_GPIO87__FUNC_SCP_SPI0_MO (MTK_PIN_NO(87) | 2)
> >>> +#define PINMUX_GPIO87__FUNC_SDA1 (MTK_PIN_NO(87) | 3)
> >>> +#define PINMUX_GPIO87__FUNC_I2S1_DO (MTK_PIN_NO(87) | 4)
> >>> +#define PINMUX_GPIO87__FUNC_MFG_DFD_JTAG_TDI (MTK_PIN_NO(87) | 5)
> >>> +#define PINMUX_GPIO87__FUNC_DFD_TDI (MTK_PIN_NO(87) | 6)
> >>> +#define PINMUX_GPIO87__FUNC_JTDI_SEL1 (MTK_PIN_NO(87) | 7)
> >>> +
> >>> +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
> >>> +#define PINMUX_GPIO88__FUNC_SPI0_CLK (MTK_PIN_NO(88) | 1)
> >>> +#define PINMUX_GPIO88__FUNC_SCP_SPI0_CK (MTK_PIN_NO(88) | 2)
> >>> +#define PINMUX_GPIO88__FUNC_SCL1 (MTK_PIN_NO(88) | 3)
> >>> +#define PINMUX_GPIO88__FUNC_I2S1_MCK (MTK_PIN_NO(88) | 4)
> >>> +#define PINMUX_GPIO88__FUNC_MFG_DFD_JTAG_TCK (MTK_PIN_NO(88) | 5)
> >>> +#define PINMUX_GPIO88__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 6)
> >>> +#define PINMUX_GPIO88__FUNC_JTCK_SEL1 (MTK_PIN_NO(88) | 7)
> >>> +
> >>> +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
> >>> +#define PINMUX_GPIO89__FUNC_SRCLKENAI0 (MTK_PIN_NO(89) | 1)
> >>> +#define PINMUX_GPIO89__FUNC_PWM_C (MTK_PIN_NO(89) | 2)
> >>> +#define PINMUX_GPIO89__FUNC_I2S5_BCK (MTK_PIN_NO(89) | 3)
> >>> +#define PINMUX_GPIO89__FUNC_ANT_SEL6 (MTK_PIN_NO(89) | 4)
> >>> +#define PINMUX_GPIO89__FUNC_SDA8 (MTK_PIN_NO(89) | 5)
> >>> +#define PINMUX_GPIO89__FUNC_CMVREF0 (MTK_PIN_NO(89) | 6)
> >>> +#define PINMUX_GPIO89__FUNC_DBG_MON_A21 (MTK_PIN_NO(89) | 7)
> >>> +
> >>> +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
> >>> +#define PINMUX_GPIO90__FUNC_PWM_A (MTK_PIN_NO(90) | 1)
> >>> +#define PINMUX_GPIO90__FUNC_CMMCLK2 (MTK_PIN_NO(90) | 2)
> >>> +#define PINMUX_GPIO90__FUNC_I2S5_LRCK (MTK_PIN_NO(90) | 3)
> >>> +#define PINMUX_GPIO90__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(90) | 4)
> >>> +#define PINMUX_GPIO90__FUNC_SCL8 (MTK_PIN_NO(90) | 5)
> >>> +#define PINMUX_GPIO90__FUNC_PTA_RXD (MTK_PIN_NO(90) | 6)
> >>> +#define PINMUX_GPIO90__FUNC_DBG_MON_A22 (MTK_PIN_NO(90) | 7)
> >>> +
> >>> +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
> >>> +#define PINMUX_GPIO91__FUNC_KPROW1 (MTK_PIN_NO(91) | 1)
> >>> +#define PINMUX_GPIO91__FUNC_PWM_B (MTK_PIN_NO(91) | 2)
> >>> +#define PINMUX_GPIO91__FUNC_I2S5_DO (MTK_PIN_NO(91) | 3)
> >>> +#define PINMUX_GPIO91__FUNC_ANT_SEL7 (MTK_PIN_NO(91) | 4)
> >>> +#define PINMUX_GPIO91__FUNC_CMMCLK3 (MTK_PIN_NO(91) | 5)
> >>> +#define PINMUX_GPIO91__FUNC_PTA_TXD (MTK_PIN_NO(91) | 6)
> >>> +
> >>> +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
> >>> +#define PINMUX_GPIO92__FUNC_KPROW0 (MTK_PIN_NO(92) | 1)
> >>> +
> >>> +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
> >>> +#define PINMUX_GPIO93__FUNC_KPCOL0 (MTK_PIN_NO(93) | 1)
> >>> +#define PINMUX_GPIO93__FUNC_DBG_MON_B27 (MTK_PIN_NO(93) | 7)
> >>> +
> >>> +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
> >>> +#define PINMUX_GPIO94__FUNC_KPCOL1 (MTK_PIN_NO(94) | 1)
> >>> +#define PINMUX_GPIO94__FUNC_I2S2_DI2 (MTK_PIN_NO(94) | 2)
> >>> +#define PINMUX_GPIO94__FUNC_I2S5_MCK (MTK_PIN_NO(94) | 3)
> >>> +#define PINMUX_GPIO94__FUNC_CMMCLK2 (MTK_PIN_NO(94) | 4)
> >>> +#define PINMUX_GPIO94__FUNC_SCP_SPI2_MI (MTK_PIN_NO(94) | 5)
> >>> +#define PINMUX_GPIO94__FUNC_SRCLKENAI1 (MTK_PIN_NO(94) | 6)
> >>> +#define PINMUX_GPIO94__FUNC_SPI2_MI (MTK_PIN_NO(94) | 7)
> >>> +
> >>> +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
> >>> +#define PINMUX_GPIO95__FUNC_URXD0 (MTK_PIN_NO(95) | 1)
> >>> +#define PINMUX_GPIO95__FUNC_UTXD0 (MTK_PIN_NO(95) | 2)
> >>> +#define PINMUX_GPIO95__FUNC_MD_URXD0 (MTK_PIN_NO(95) | 3)
> >>> +#define PINMUX_GPIO95__FUNC_MD_URXD1 (MTK_PIN_NO(95) | 4)
> >>> +#define PINMUX_GPIO95__FUNC_SSPM_URXD_AO (MTK_PIN_NO(95) | 5)
> >>> +#define PINMUX_GPIO95__FUNC_CCU_URXD_AO (MTK_PIN_NO(95) | 6)
> >>> +
> >>> +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
> >>> +#define PINMUX_GPIO96__FUNC_UTXD0 (MTK_PIN_NO(96) | 1)
> >>> +#define PINMUX_GPIO96__FUNC_URXD0 (MTK_PIN_NO(96) | 2)
> >>> +#define PINMUX_GPIO96__FUNC_MD_UTXD0 (MTK_PIN_NO(96) | 3)
> >>> +#define PINMUX_GPIO96__FUNC_MD_UTXD1 (MTK_PIN_NO(96) | 4)
> >>> +#define PINMUX_GPIO96__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(96) | 5)
> >>> +#define PINMUX_GPIO96__FUNC_CCU_UTXD_AO (MTK_PIN_NO(96) | 6)
> >>> +#define PINMUX_GPIO96__FUNC_DBG_MON_B2 (MTK_PIN_NO(96) | 7)
> >>> +
> >>> +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
> >>> +#define PINMUX_GPIO97__FUNC_UCTS0 (MTK_PIN_NO(97) | 1)
> >>> +#define PINMUX_GPIO97__FUNC_I2S2_MCK (MTK_PIN_NO(97) | 2)
> >>> +#define PINMUX_GPIO97__FUNC_IDDIG (MTK_PIN_NO(97) | 3)
> >>> +#define PINMUX_GPIO97__FUNC_CONN_MCU_TDO (MTK_PIN_NO(97) | 4)
> >>> +#define PINMUX_GPIO97__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(97) | 5)
> >>> +#define PINMUX_GPIO97__FUNC_IO_JTAG_TDO (MTK_PIN_NO(97) | 6)
> >>> +#define PINMUX_GPIO97__FUNC_DBG_MON_B3 (MTK_PIN_NO(97) | 7)
> >>> +
> >>> +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
> >>> +#define PINMUX_GPIO98__FUNC_URTS0 (MTK_PIN_NO(98) | 1)
> >>> +#define PINMUX_GPIO98__FUNC_I2S2_BCK (MTK_PIN_NO(98) | 2)
> >>> +#define PINMUX_GPIO98__FUNC_USB_DRVVBUS (MTK_PIN_NO(98) | 3)
> >>> +#define PINMUX_GPIO98__FUNC_CONN_MCU_TMS (MTK_PIN_NO(98) | 4)
> >>> +#define PINMUX_GPIO98__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(98) | 5)
> >>> +#define PINMUX_GPIO98__FUNC_IO_JTAG_TMS (MTK_PIN_NO(98) | 6)
> >>> +#define PINMUX_GPIO98__FUNC_DBG_MON_B4 (MTK_PIN_NO(98) | 7)
> >>> +
> >>> +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
> >>> +#define PINMUX_GPIO99__FUNC_CMMCLK0 (MTK_PIN_NO(99) | 1)
> >>> +#define PINMUX_GPIO99__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(99) | 4)
> >>> +#define PINMUX_GPIO99__FUNC_DBG_MON_B28 (MTK_PIN_NO(99) | 7)
> >>> +
> >>> +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
> >>> +#define PINMUX_GPIO100__FUNC_CMMCLK1 (MTK_PIN_NO(100) | 1)
> >>> +#define PINMUX_GPIO100__FUNC_PWM_C (MTK_PIN_NO(100) | 2)
> >>> +#define PINMUX_GPIO100__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(100) | 3)
> >>> +#define PINMUX_GPIO100__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(100) | 4)
> >>> +#define PINMUX_GPIO100__FUNC_DBG_MON_B29 (MTK_PIN_NO(100) | 7)
> >>> +
> >>> +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
> >>> +#define PINMUX_GPIO101__FUNC_CLKM2 (MTK_PIN_NO(101) | 1)
> >>> +#define PINMUX_GPIO101__FUNC_I2S2_LRCK (MTK_PIN_NO(101) | 2)
> >>> +#define PINMUX_GPIO101__FUNC_CMVREF1 (MTK_PIN_NO(101) | 3)
> >>> +#define PINMUX_GPIO101__FUNC_CONN_MCU_TCK (MTK_PIN_NO(101) | 4)
> >>> +#define PINMUX_GPIO101__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(101) | 5)
> >>> +#define PINMUX_GPIO101__FUNC_IO_JTAG_TCK (MTK_PIN_NO(101) | 6)
> >>> +
> >>> +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
> >>> +#define PINMUX_GPIO102__FUNC_CLKM1 (MTK_PIN_NO(102) | 1)
> >>> +#define PINMUX_GPIO102__FUNC_I2S2_DI (MTK_PIN_NO(102) | 2)
> >>> +#define PINMUX_GPIO102__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(102) | 3)
> >>> +#define PINMUX_GPIO102__FUNC_CONN_MCU_TDI (MTK_PIN_NO(102) | 4)
> >>> +#define PINMUX_GPIO102__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(102) | 5)
> >>> +#define PINMUX_GPIO102__FUNC_IO_JTAG_TDI (MTK_PIN_NO(102) | 6)
> >>> +#define PINMUX_GPIO102__FUNC_DBG_MON_B8 (MTK_PIN_NO(102) | 7)
> >>> +
> >>> +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
> >>> +#define PINMUX_GPIO103__FUNC_SCL2 (MTK_PIN_NO(103) | 1)
> >>> +
> >>> +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
> >>> +#define PINMUX_GPIO104__FUNC_SDA2 (MTK_PIN_NO(104) | 1)
> >>> +
> >>> +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
> >>> +#define PINMUX_GPIO105__FUNC_SCL4 (MTK_PIN_NO(105) | 1)
> >>> +
> >>> +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
> >>> +#define PINMUX_GPIO106__FUNC_SDA4 (MTK_PIN_NO(106) | 1)
> >>> +
> >>> +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
> >>> +#define PINMUX_GPIO107__FUNC_DMIC_CLK (MTK_PIN_NO(107) | 1)
> >>> +#define PINMUX_GPIO107__FUNC_ANT_SEL0 (MTK_PIN_NO(107) | 2)
> >>> +#define PINMUX_GPIO107__FUNC_CLKM0 (MTK_PIN_NO(107) | 3)
> >>> +#define PINMUX_GPIO107__FUNC_SDA7 (MTK_PIN_NO(107) | 4)
> >>> +#define PINMUX_GPIO107__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(107) | 5)
> >>> +#define PINMUX_GPIO107__FUNC_PWM_A (MTK_PIN_NO(107) | 6)
> >>> +#define PINMUX_GPIO107__FUNC_DBG_MON_B12 (MTK_PIN_NO(107) | 7)
> >>> +
> >>> +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
> >>> +#define PINMUX_GPIO108__FUNC_CMMCLK2 (MTK_PIN_NO(108) | 1)
> >>> +#define PINMUX_GPIO108__FUNC_ANT_SEL1 (MTK_PIN_NO(108) | 2)
> >>> +#define PINMUX_GPIO108__FUNC_CLKM1 (MTK_PIN_NO(108) | 3)
> >>> +#define PINMUX_GPIO108__FUNC_SCL8 (MTK_PIN_NO(108) | 4)
> >>> +#define PINMUX_GPIO108__FUNC_DAP_MD32_SWD (MTK_PIN_NO(108) | 5)
> >>> +#define PINMUX_GPIO108__FUNC_PWM_B (MTK_PIN_NO(108) | 6)
> >>> +#define PINMUX_GPIO108__FUNC_DBG_MON_B13 (MTK_PIN_NO(108) | 7)
> >>> +
> >>> +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
> >>> +#define PINMUX_GPIO109__FUNC_DMIC_DAT (MTK_PIN_NO(109) | 1)
> >>> +#define PINMUX_GPIO109__FUNC_ANT_SEL2 (MTK_PIN_NO(109) | 2)
> >>> +#define PINMUX_GPIO109__FUNC_CLKM2 (MTK_PIN_NO(109) | 3)
> >>> +#define PINMUX_GPIO109__FUNC_SDA8 (MTK_PIN_NO(109) | 4)
> >>> +#define PINMUX_GPIO109__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(109) | 5)
> >>> +#define PINMUX_GPIO109__FUNC_PWM_C (MTK_PIN_NO(109) | 6)
> >>> +#define PINMUX_GPIO109__FUNC_DBG_MON_B14 (MTK_PIN_NO(109) | 7)
> >>> +
> >>> +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
> >>> +#define PINMUX_GPIO110__FUNC_SCL7 (MTK_PIN_NO(110) | 1)
> >>> +#define PINMUX_GPIO110__FUNC_ANT_SEL0 (MTK_PIN_NO(110) | 2)
> >>> +#define PINMUX_GPIO110__FUNC_TP_URXD1_AO (MTK_PIN_NO(110) | 3)
> >>> +#define PINMUX_GPIO110__FUNC_USB_DRVVBUS (MTK_PIN_NO(110) | 4)
> >>> +#define PINMUX_GPIO110__FUNC_SRCLKENAI1 (MTK_PIN_NO(110) | 5)
> >>> +#define PINMUX_GPIO110__FUNC_KPCOL2 (MTK_PIN_NO(110) | 6)
> >>> +#define PINMUX_GPIO110__FUNC_URXD1 (MTK_PIN_NO(110) | 7)
> >>> +
> >>> +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
> >>> +#define PINMUX_GPIO111__FUNC_CMMCLK3 (MTK_PIN_NO(111) | 1)
> >>> +#define PINMUX_GPIO111__FUNC_ANT_SEL1 (MTK_PIN_NO(111) | 2)
> >>> +#define PINMUX_GPIO111__FUNC_SRCLKENAI0 (MTK_PIN_NO(111) | 3)
> >>> +#define PINMUX_GPIO111__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(111) | 4)
> >>> +#define PINMUX_GPIO111__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(111) | 5)
> >>> +#define PINMUX_GPIO111__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(111) | 7)
> >>> +
> >>> +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
> >>> +#define PINMUX_GPIO112__FUNC_SDA7 (MTK_PIN_NO(112) | 1)
> >>> +#define PINMUX_GPIO112__FUNC_ANT_SEL2 (MTK_PIN_NO(112) | 2)
> >>> +#define PINMUX_GPIO112__FUNC_TP_UTXD1_AO (MTK_PIN_NO(112) | 3)
> >>> +#define PINMUX_GPIO112__FUNC_IDDIG (MTK_PIN_NO(112) | 4)
> >>> +#define PINMUX_GPIO112__FUNC_AGPS_SYNC (MTK_PIN_NO(112) | 5)
> >>> +#define PINMUX_GPIO112__FUNC_KPROW2 (MTK_PIN_NO(112) | 6)
> >>> +#define PINMUX_GPIO112__FUNC_UTXD1 (MTK_PIN_NO(112) | 7)
> >>> +
> >>> +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
> >>> +#define PINMUX_GPIO113__FUNC_CONN_TOP_CLK (MTK_PIN_NO(113) | 1)
> >>> +#define PINMUX_GPIO113__FUNC_SCL6 (MTK_PIN_NO(113) | 3)
> >>> +#define PINMUX_GPIO113__FUNC_AUXIF_CLK0 (MTK_PIN_NO(113) | 4)
> >>> +#define PINMUX_GPIO113__FUNC_TP_UCTS1_AO (MTK_PIN_NO(113) | 6)
> >>> +
> >>> +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
> >>> +#define PINMUX_GPIO114__FUNC_CONN_TOP_DATA (MTK_PIN_NO(114) | 1)
> >>> +#define PINMUX_GPIO114__FUNC_SDA6 (MTK_PIN_NO(114) | 3)
> >>> +#define PINMUX_GPIO114__FUNC_AUXIF_ST0 (MTK_PIN_NO(114) | 4)
> >>> +#define PINMUX_GPIO114__FUNC_TP_URTS1_AO (MTK_PIN_NO(114) | 6)
> >>> +
> >>> +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
> >>> +#define PINMUX_GPIO115__FUNC_CONN_BT_CLK (MTK_PIN_NO(115) | 1)
> >>> +#define PINMUX_GPIO115__FUNC_UTXD1 (MTK_PIN_NO(115) | 2)
> >>> +#define PINMUX_GPIO115__FUNC_PTA_TXD (MTK_PIN_NO(115) | 3)
> >>> +#define PINMUX_GPIO115__FUNC_AUXIF_CLK1 (MTK_PIN_NO(115) | 4)
> >>> +#define PINMUX_GPIO115__FUNC_DAP_MD32_SWD (MTK_PIN_NO(115) | 5)
> >>> +#define PINMUX_GPIO115__FUNC_TP_UTXD1_AO (MTK_PIN_NO(115) | 6)
> >>> +
> >>> +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
> >>> +#define PINMUX_GPIO116__FUNC_CONN_BT_DATA (MTK_PIN_NO(116) | 1)
> >>> +#define PINMUX_GPIO116__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(116) | 2)
> >>> +#define PINMUX_GPIO116__FUNC_AUXIF_ST1 (MTK_PIN_NO(116) | 4)
> >>> +#define PINMUX_GPIO116__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(116) | 5)
> >>> +#define PINMUX_GPIO116__FUNC_TP_URXD2_AO (MTK_PIN_NO(116) | 6)
> >>> +#define PINMUX_GPIO116__FUNC_DBG_MON_A0 (MTK_PIN_NO(116) | 7)
> >>> +
> >>> +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
> >>> +#define PINMUX_GPIO117__FUNC_CONN_WF_HB0 (MTK_PIN_NO(117) | 1)
> >>> +#define PINMUX_GPIO117__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(117) | 2)
> >>> +#define PINMUX_GPIO117__FUNC_TP_UTXD2_AO (MTK_PIN_NO(117) | 6)
> >>> +#define PINMUX_GPIO117__FUNC_DBG_MON_A4 (MTK_PIN_NO(117) | 7)
> >>> +
> >>> +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
> >>> +#define PINMUX_GPIO118__FUNC_CONN_WF_HB1 (MTK_PIN_NO(118) | 1)
> >>> +#define PINMUX_GPIO118__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(118) | 2)
> >>> +#define PINMUX_GPIO118__FUNC_SSPM_URXD_AO (MTK_PIN_NO(118) | 5)
> >>> +#define PINMUX_GPIO118__FUNC_TP_UCTS2_AO (MTK_PIN_NO(118) | 6)
> >>> +#define PINMUX_GPIO118__FUNC_DBG_MON_A5 (MTK_PIN_NO(118) | 7)
> >>> +
> >>> +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
> >>> +#define PINMUX_GPIO119__FUNC_CONN_WF_HB2 (MTK_PIN_NO(119) | 1)
> >>> +#define PINMUX_GPIO119__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(119) | 2)
> >>> +#define PINMUX_GPIO119__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(119) | 5)
> >>> +#define PINMUX_GPIO119__FUNC_TP_URTS2_AO (MTK_PIN_NO(119) | 6)
> >>> +
> >>> +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
> >>> +#define PINMUX_GPIO120__FUNC_CONN_WB_PTA (MTK_PIN_NO(120) | 1)
> >>> +#define PINMUX_GPIO120__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(120) | 2)
> >>> +#define PINMUX_GPIO120__FUNC_CCU_URXD_AO (MTK_PIN_NO(120) | 5)
> >>> +
> >>> +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
> >>> +#define PINMUX_GPIO121__FUNC_CONN_HRST_B (MTK_PIN_NO(121) | 1)
> >>> +#define PINMUX_GPIO121__FUNC_URXD1 (MTK_PIN_NO(121) | 2)
> >>> +#define PINMUX_GPIO121__FUNC_PTA_RXD (MTK_PIN_NO(121) | 3)
> >>> +#define PINMUX_GPIO121__FUNC_CCU_UTXD_AO (MTK_PIN_NO(121) | 5)
> >>> +#define PINMUX_GPIO121__FUNC_TP_URXD1_AO (MTK_PIN_NO(121) | 6)
> >>> +
> >>> +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
> >>> +#define PINMUX_GPIO122__FUNC_MSDC0_CMD (MTK_PIN_NO(122) | 1)
> >>> +#define PINMUX_GPIO122__FUNC_SSPM_URXD2_AO (MTK_PIN_NO(122) | 2)
> >>> +#define PINMUX_GPIO122__FUNC_ANT_SEL1 (MTK_PIN_NO(122) | 3)
> >>> +#define PINMUX_GPIO122__FUNC_DBG_MON_A12 (MTK_PIN_NO(122) | 7)
> >>> +
> >>> +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
> >>> +#define PINMUX_GPIO123__FUNC_MSDC0_DAT0 (MTK_PIN_NO(123) | 1)
> >>> +#define PINMUX_GPIO123__FUNC_ANT_SEL0 (MTK_PIN_NO(123) | 3)
> >>> +#define PINMUX_GPIO123__FUNC_DBG_MON_A13 (MTK_PIN_NO(123) | 7)
> >>> +
> >>> +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
> >>> +#define PINMUX_GPIO124__FUNC_MSDC0_CLK (MTK_PIN_NO(124) | 1)
> >>> +#define PINMUX_GPIO124__FUNC_DBG_MON_A14 (MTK_PIN_NO(124) | 7)
> >>> +
> >>> +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
> >>> +#define PINMUX_GPIO125__FUNC_MSDC0_DAT2 (MTK_PIN_NO(125) | 1)
> >>> +#define PINMUX_GPIO125__FUNC_MRG_CLK (MTK_PIN_NO(125) | 3)
> >>> +#define PINMUX_GPIO125__FUNC_DBG_MON_A15 (MTK_PIN_NO(125) | 7)
> >>> +
> >>> +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
> >>> +#define PINMUX_GPIO126__FUNC_MSDC0_DAT4 (MTK_PIN_NO(126) | 1)
> >>> +#define PINMUX_GPIO126__FUNC_ANT_SEL5 (MTK_PIN_NO(126) | 3)
> >>> +#define PINMUX_GPIO126__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(126) | 6)
> >>> +#define PINMUX_GPIO126__FUNC_DBG_MON_A16 (MTK_PIN_NO(126) | 7)
> >>> +
> >>> +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
> >>> +#define PINMUX_GPIO127__FUNC_MSDC0_DAT6 (MTK_PIN_NO(127) | 1)
> >>> +#define PINMUX_GPIO127__FUNC_ANT_SEL4 (MTK_PIN_NO(127) | 3)
> >>> +#define PINMUX_GPIO127__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(127) | 6)
> >>> +#define PINMUX_GPIO127__FUNC_DBG_MON_A17 (MTK_PIN_NO(127) | 7)
> >>> +
> >>> +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
> >>> +#define PINMUX_GPIO128__FUNC_MSDC0_DAT1 (MTK_PIN_NO(128) | 1)
> >>> +#define PINMUX_GPIO128__FUNC_ANT_SEL2 (MTK_PIN_NO(128) | 3)
> >>> +#define PINMUX_GPIO128__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(128) | 6)
> >>> +#define PINMUX_GPIO128__FUNC_DBG_MON_A18 (MTK_PIN_NO(128) | 7)
> >>> +
> >>> +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
> >>> +#define PINMUX_GPIO129__FUNC_MSDC0_DAT5 (MTK_PIN_NO(129) | 1)
> >>> +#define PINMUX_GPIO129__FUNC_ANT_SEL3 (MTK_PIN_NO(129) | 3)
> >>> +#define PINMUX_GPIO129__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(129) | 6)
> >>> +#define PINMUX_GPIO129__FUNC_DBG_MON_A23 (MTK_PIN_NO(129) | 7)
> >>> +
> >>> +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
> >>> +#define PINMUX_GPIO130__FUNC_MSDC0_DAT7 (MTK_PIN_NO(130) | 1)
> >>> +#define PINMUX_GPIO130__FUNC_MRG_DO (MTK_PIN_NO(130) | 3)
> >>> +#define PINMUX_GPIO130__FUNC_DBG_MON_A24 (MTK_PIN_NO(130) | 7)
> >>> +
> >>> +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
> >>> +#define PINMUX_GPIO131__FUNC_MSDC0_DSL (MTK_PIN_NO(131) | 1)
> >>> +#define PINMUX_GPIO131__FUNC_MRG_SYNC (MTK_PIN_NO(131) | 3)
> >>> +#define PINMUX_GPIO131__FUNC_DBG_MON_A25 (MTK_PIN_NO(131) | 7)
> >>> +
> >>> +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
> >>> +#define PINMUX_GPIO132__FUNC_MSDC0_DAT3 (MTK_PIN_NO(132) | 1)
> >>> +#define PINMUX_GPIO132__FUNC_MRG_DI (MTK_PIN_NO(132) | 3)
> >>> +#define PINMUX_GPIO132__FUNC_DBG_MON_A26 (MTK_PIN_NO(132) | 7)
> >>> +
> >>> +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
> >>> +#define PINMUX_GPIO133__FUNC_MSDC0_RSTB (MTK_PIN_NO(133) | 1)
> >>> +#define PINMUX_GPIO133__FUNC_AGPS_SYNC (MTK_PIN_NO(133) | 3)
> >>> +#define PINMUX_GPIO133__FUNC_DBG_MON_A27 (MTK_PIN_NO(133) | 7)
> >>> +
> >>> +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
> >>> +#define PINMUX_GPIO134__FUNC_RTC32K_CK (MTK_PIN_NO(134) | 1)
> >>> +
> >>> +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
> >>> +#define PINMUX_GPIO135__FUNC_WATCHDOG (MTK_PIN_NO(135) | 1)
> >>> +
> >>> +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
> >>> +#define PINMUX_GPIO136__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(136) | 1)
> >>> +#define PINMUX_GPIO136__FUNC_AUD_CLK_MISO (MTK_PIN_NO(136) | 2)
> >>> +#define PINMUX_GPIO136__FUNC_I2S1_MCK (MTK_PIN_NO(136) | 3)
> >>> +#define PINMUX_GPIO136__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(136) | 6)
> >>> +
> >>> +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
> >>> +#define PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(137) | 1)
> >>> +#define PINMUX_GPIO137__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(137) | 2)
> >>> +#define PINMUX_GPIO137__FUNC_I2S1_BCK (MTK_PIN_NO(137) | 3)
> >>> +
> >>> +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
> >>> +#define PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(138) | 1)
> >>> +#define PINMUX_GPIO138__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(138) | 2)
> >>> +#define PINMUX_GPIO138__FUNC_I2S1_LRCK (MTK_PIN_NO(138) | 3)
> >>> +#define PINMUX_GPIO138__FUNC_DBG_MON_B24 (MTK_PIN_NO(138) | 7)
> >>> +
> >>> +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
> >>> +#define PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(139) | 1)
> >>> +#define PINMUX_GPIO139__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(139) | 2)
> >>> +#define PINMUX_GPIO139__FUNC_I2S1_DO (MTK_PIN_NO(139) | 3)
> >>> +#define PINMUX_GPIO139__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(139) | 6)
> >>> +
> >>> +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
> >>> +#define PINMUX_GPIO140__FUNC_AUD_CLK_MISO (MTK_PIN_NO(140) | 1)
> >>> +#define PINMUX_GPIO140__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(140) | 2)
> >>> +#define PINMUX_GPIO140__FUNC_I2S0_MCK (MTK_PIN_NO(140) | 3)
> >>> +#define PINMUX_GPIO140__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(140) | 6)
> >>> +
> >>> +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
> >>> +#define PINMUX_GPIO141__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(141) | 1)
> >>> +#define PINMUX_GPIO141__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(141) | 2)
> >>> +#define PINMUX_GPIO141__FUNC_I2S0_BCK (MTK_PIN_NO(141) | 3)
> >>> +
> >>> +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
> >>> +#define PINMUX_GPIO142__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(142) | 1)
> >>> +#define PINMUX_GPIO142__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(142) | 2)
> >>> +#define PINMUX_GPIO142__FUNC_I2S0_LRCK (MTK_PIN_NO(142) | 3)
> >>> +#define PINMUX_GPIO142__FUNC_VOW_DAT_MISO (MTK_PIN_NO(142) | 4)
> >>> +#define PINMUX_GPIO142__FUNC_DBG_MON_B25 (MTK_PIN_NO(142) | 7)
> >>> +
> >>> +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
> >>> +#define PINMUX_GPIO143__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(143) | 1)
> >>> +#define PINMUX_GPIO143__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(143) | 2)
> >>> +#define PINMUX_GPIO143__FUNC_I2S0_DI (MTK_PIN_NO(143) | 3)
> >>> +#define PINMUX_GPIO143__FUNC_VOW_CLK_MISO (MTK_PIN_NO(143) | 4)
> >>> +#define PINMUX_GPIO143__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(143) | 6)
> >>> +#define PINMUX_GPIO143__FUNC_DBG_MON_B26 (MTK_PIN_NO(143) | 7)
> >>> +
> >>> +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
> >>> +#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(144) | 1)
> >>> +#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(144) | 2)
> >>> +
> >>> +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
> >>> +#define PINMUX_GPIO145__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(145) | 1)
> >>> +
> >>> +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
> >>> +#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(146) | 1)
> >>> +#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(146) | 2)
> >>> +
> >>> +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
> >>> +#define PINMUX_GPIO147__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(147) | 1)
> >>> +
> >>> +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
> >>> +#define PINMUX_GPIO148__FUNC_SRCLKENA0 (MTK_PIN_NO(148) | 1)
> >>> +
> >>> +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
> >>> +#define PINMUX_GPIO149__FUNC_SRCLKENA1 (MTK_PIN_NO(149) | 1)
> >>> +
> >>> +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
> >>> +#define PINMUX_GPIO150__FUNC_PWM_A (MTK_PIN_NO(150) | 1)
> >>> +#define PINMUX_GPIO150__FUNC_CMFLASH (MTK_PIN_NO(150) | 2)
> >>> +#define PINMUX_GPIO150__FUNC_CLKM0 (MTK_PIN_NO(150) | 3)
> >>> +#define PINMUX_GPIO150__FUNC_DBG_MON_B30 (MTK_PIN_NO(150) | 7)
> >>> +
> >>> +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
> >>> +#define PINMUX_GPIO151__FUNC_PWM_B (MTK_PIN_NO(151) | 1)
> >>> +#define PINMUX_GPIO151__FUNC_CMVREF0 (MTK_PIN_NO(151) | 2)
> >>> +#define PINMUX_GPIO151__FUNC_CLKM1 (MTK_PIN_NO(151) | 3)
> >>> +#define PINMUX_GPIO151__FUNC_DBG_MON_B20 (MTK_PIN_NO(151) | 7)
> >>> +
> >>> +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
> >>> +#define PINMUX_GPIO152__FUNC_PWM_C (MTK_PIN_NO(152) | 1)
> >>> +#define PINMUX_GPIO152__FUNC_CMFLASH (MTK_PIN_NO(152) | 2)
> >>> +#define PINMUX_GPIO152__FUNC_CLKM2 (MTK_PIN_NO(152) | 3)
> >>> +#define PINMUX_GPIO152__FUNC_DBG_MON_B21 (MTK_PIN_NO(152) | 7)
> >>> +
> >>> +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
> >>> +#define PINMUX_GPIO153__FUNC_PWM_A (MTK_PIN_NO(153) | 1)
> >>> +#define PINMUX_GPIO153__FUNC_CMVREF0 (MTK_PIN_NO(153) | 2)
> >>> +#define PINMUX_GPIO153__FUNC_CLKM3 (MTK_PIN_NO(153) | 3)
> >>> +#define PINMUX_GPIO153__FUNC_DBG_MON_B22 (MTK_PIN_NO(153) | 7)
> >>> +
> >>> +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
> >>> +#define PINMUX_GPIO154__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(154) | 1)
> >>> +#define PINMUX_GPIO154__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(154) | 2)
> >>> +#define PINMUX_GPIO154__FUNC_DBG_MON_B18 (MTK_PIN_NO(154) | 7)
> >>> +
> >>> +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
> >>> +#define PINMUX_GPIO155__FUNC_ANT_SEL0 (MTK_PIN_NO(155) | 1)
> >>> +#define PINMUX_GPIO155__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(155) | 2)
> >>> +#define PINMUX_GPIO155__FUNC_CMVREF1 (MTK_PIN_NO(155) | 3)
> >>> +#define PINMUX_GPIO155__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(155) | 7)
> >>> +
> >>> +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
> >>> +#define PINMUX_GPIO156__FUNC_ANT_SEL1 (MTK_PIN_NO(156) | 1)
> >>> +#define PINMUX_GPIO156__FUNC_SRCLKENAI0 (MTK_PIN_NO(156) | 2)
> >>> +#define PINMUX_GPIO156__FUNC_SCL6 (MTK_PIN_NO(156) | 3)
> >>> +#define PINMUX_GPIO156__FUNC_KPCOL2 (MTK_PIN_NO(156) | 4)
> >>> +#define PINMUX_GPIO156__FUNC_IDDIG (MTK_PIN_NO(156) | 5)
> >>> +#define PINMUX_GPIO156__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(156) | 7)
> >>> +
> >>> +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
> >>> +#define PINMUX_GPIO157__FUNC_ANT_SEL2 (MTK_PIN_NO(157) | 1)
> >>> +#define PINMUX_GPIO157__FUNC_SRCLKENAI1 (MTK_PIN_NO(157) | 2)
> >>> +#define PINMUX_GPIO157__FUNC_SDA6 (MTK_PIN_NO(157) | 3)
> >>> +#define PINMUX_GPIO157__FUNC_KPROW2 (MTK_PIN_NO(157) | 4)
> >>> +#define PINMUX_GPIO157__FUNC_USB_DRVVBUS (MTK_PIN_NO(157) | 5)
> >>> +#define PINMUX_GPIO157__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(157) | 7)
> >>> +
> >>> +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
> >>> +#define PINMUX_GPIO158__FUNC_ANT_SEL3 (MTK_PIN_NO(158) | 1)
> >>> +
> >>> +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
> >>> +#define PINMUX_GPIO159__FUNC_ANT_SEL4 (MTK_PIN_NO(159) | 1)
> >>> +
> >>> +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
> >>> +#define PINMUX_GPIO160__FUNC_ANT_SEL5 (MTK_PIN_NO(160) | 1)
> >>> +
> >>> +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
> >>> +#define PINMUX_GPIO161__FUNC_SPI1_A_MI (MTK_PIN_NO(161) | 1)
> >>> +#define PINMUX_GPIO161__FUNC_SCP_SPI1_MI (MTK_PIN_NO(161) | 2)
> >>> +#define PINMUX_GPIO161__FUNC_IDDIG (MTK_PIN_NO(161) | 3)
> >>> +#define PINMUX_GPIO161__FUNC_ANT_SEL6 (MTK_PIN_NO(161) | 4)
> >>> +#define PINMUX_GPIO161__FUNC_KPCOL2 (MTK_PIN_NO(161) | 5)
> >>> +#define PINMUX_GPIO161__FUNC_PTA_RXD (MTK_PIN_NO(161) | 6)
> >>> +#define PINMUX_GPIO161__FUNC_DBG_MON_B19 (MTK_PIN_NO(161) | 7)
> >>> +
> >>> +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
> >>> +#define PINMUX_GPIO162__FUNC_SPI1_A_CSB (MTK_PIN_NO(162) | 1)
> >>> +#define PINMUX_GPIO162__FUNC_SCP_SPI1_CS (MTK_PIN_NO(162) | 2)
> >>> +#define PINMUX_GPIO162__FUNC_USB_DRVVBUS (MTK_PIN_NO(162) | 3)
> >>> +#define PINMUX_GPIO162__FUNC_ANT_SEL5 (MTK_PIN_NO(162) | 4)
> >>> +#define PINMUX_GPIO162__FUNC_KPROW2 (MTK_PIN_NO(162) | 5)
> >>> +#define PINMUX_GPIO162__FUNC_PTA_TXD (MTK_PIN_NO(162) | 6)
> >>> +
> >>> +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
> >>> +#define PINMUX_GPIO163__FUNC_SPI1_A_MO (MTK_PIN_NO(163) | 1)
> >>> +#define PINMUX_GPIO163__FUNC_SCP_SPI1_MO (MTK_PIN_NO(163) | 2)
> >>> +#define PINMUX_GPIO163__FUNC_SDA1 (MTK_PIN_NO(163) | 3)
> >>> +#define PINMUX_GPIO163__FUNC_ANT_SEL4 (MTK_PIN_NO(163) | 4)
> >>> +#define PINMUX_GPIO163__FUNC_CMMCLK2 (MTK_PIN_NO(163) | 5)
> >>> +#define PINMUX_GPIO163__FUNC_DMIC_CLK (MTK_PIN_NO(163) | 6)
> >>> +
> >>> +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
> >>> +#define PINMUX_GPIO164__FUNC_SPI1_A_CLK (MTK_PIN_NO(164) | 1)
> >>> +#define PINMUX_GPIO164__FUNC_SCP_SPI1_CK (MTK_PIN_NO(164) | 2)
> >>> +#define PINMUX_GPIO164__FUNC_SCL1 (MTK_PIN_NO(164) | 3)
> >>> +#define PINMUX_GPIO164__FUNC_ANT_SEL3 (MTK_PIN_NO(164) | 4)
> >>> +#define PINMUX_GPIO164__FUNC_CMMCLK3 (MTK_PIN_NO(164) | 5)
> >>> +#define PINMUX_GPIO164__FUNC_DMIC_DAT (MTK_PIN_NO(164) | 6)
> >>> +
> >>> +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
> >>> +#define PINMUX_GPIO165__FUNC_PWM_B (MTK_PIN_NO(165) | 1)
> >>> +#define PINMUX_GPIO165__FUNC_CMMCLK2 (MTK_PIN_NO(165) | 2)
> >>> +#define PINMUX_GPIO165__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(165) | 3)
> >>> +#define PINMUX_GPIO165__FUNC_TDM_MCK_2ND (MTK_PIN_NO(165) | 6)
> >>> +#define PINMUX_GPIO165__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(165) | 7)
> >>> +
> >>> +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
> >>> +#define PINMUX_GPIO166__FUNC_ANT_SEL6 (MTK_PIN_NO(166) | 1)
> >>> +
> >>> +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
> >>> +#define PINMUX_GPIO167__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(167) | 1)
> >>> +#define PINMUX_GPIO167__FUNC_SPM_BSI_EN (MTK_PIN_NO(167) | 2)
> >>> +
> >>> +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
> >>> +#define PINMUX_GPIO168__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(168) | 1)
> >>> +#define PINMUX_GPIO168__FUNC_SPM_BSI_CK (MTK_PIN_NO(168) | 2)
> >>> +
> >>> +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
> >>> +#define PINMUX_GPIO169__FUNC_PWM_C (MTK_PIN_NO(169) | 1)
> >>> +#define PINMUX_GPIO169__FUNC_CMMCLK3 (MTK_PIN_NO(169) | 2)
> >>> +#define PINMUX_GPIO169__FUNC_CMVREF1 (MTK_PIN_NO(169) | 3)
> >>> +#define PINMUX_GPIO169__FUNC_ANT_SEL7 (MTK_PIN_NO(169) | 4)
> >>> +#define PINMUX_GPIO169__FUNC_AGPS_SYNC (MTK_PIN_NO(169) | 5)
> >>> +#define PINMUX_GPIO169__FUNC_TDM_BCK_2ND (MTK_PIN_NO(169) | 6)
> >>> +#define PINMUX_GPIO169__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(169) | 7)
> >>> +
> >>> +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
> >>> +#define PINMUX_GPIO170__FUNC_I2S1_BCK (MTK_PIN_NO(170) | 1)
> >>> +#define PINMUX_GPIO170__FUNC_I2S3_BCK (MTK_PIN_NO(170) | 2)
> >>> +#define PINMUX_GPIO170__FUNC_SCL7 (MTK_PIN_NO(170) | 3)
> >>> +#define PINMUX_GPIO170__FUNC_I2S5_BCK (MTK_PIN_NO(170) | 4)
> >>> +#define PINMUX_GPIO170__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(170) | 5)
> >>> +#define PINMUX_GPIO170__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(170) | 6)
> >>> +#define PINMUX_GPIO170__FUNC_ANT_SEL3 (MTK_PIN_NO(170) | 7)
> >>> +
> >>> +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
> >>> +#define PINMUX_GPIO171__FUNC_I2S1_LRCK (MTK_PIN_NO(171) | 1)
> >>> +#define PINMUX_GPIO171__FUNC_I2S3_LRCK (MTK_PIN_NO(171) | 2)
> >>> +#define PINMUX_GPIO171__FUNC_SDA7 (MTK_PIN_NO(171) | 3)
> >>> +#define PINMUX_GPIO171__FUNC_I2S5_LRCK (MTK_PIN_NO(171) | 4)
> >>> +#define PINMUX_GPIO171__FUNC_URXD1 (MTK_PIN_NO(171) | 5)
> >>> +#define PINMUX_GPIO171__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(171) | 6)
> >>> +#define PINMUX_GPIO171__FUNC_ANT_SEL4 (MTK_PIN_NO(171) | 7)
> >>> +
> >>> +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
> >>> +#define PINMUX_GPIO172__FUNC_I2S1_DO (MTK_PIN_NO(172) | 1)
> >>> +#define PINMUX_GPIO172__FUNC_I2S3_DO (MTK_PIN_NO(172) | 2)
> >>> +#define PINMUX_GPIO172__FUNC_SCL8 (MTK_PIN_NO(172) | 3)
> >>> +#define PINMUX_GPIO172__FUNC_I2S5_DO (MTK_PIN_NO(172) | 4)
> >>> +#define PINMUX_GPIO172__FUNC_UTXD1 (MTK_PIN_NO(172) | 5)
> >>> +#define PINMUX_GPIO172__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(172) | 6)
> >>> +#define PINMUX_GPIO172__FUNC_ANT_SEL5 (MTK_PIN_NO(172) | 7)
> >>> +
> >>> +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
> >>> +#define PINMUX_GPIO173__FUNC_I2S1_MCK (MTK_PIN_NO(173) | 1)
> >>> +#define PINMUX_GPIO173__FUNC_I2S3_MCK (MTK_PIN_NO(173) | 2)
> >>> +#define PINMUX_GPIO173__FUNC_SDA8 (MTK_PIN_NO(173) | 3)
> >>> +#define PINMUX_GPIO173__FUNC_I2S5_MCK (MTK_PIN_NO(173) | 4)
> >>> +#define PINMUX_GPIO173__FUNC_UCTS0 (MTK_PIN_NO(173) | 5)
> >>> +#define PINMUX_GPIO173__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(173) | 6)
> >>> +#define PINMUX_GPIO173__FUNC_ANT_SEL6 (MTK_PIN_NO(173) | 7)
> >>> +
> >>> +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
> >>> +#define PINMUX_GPIO174__FUNC_I2S2_DI (MTK_PIN_NO(174) | 1)
> >>> +#define PINMUX_GPIO174__FUNC_I2S0_DI (MTK_PIN_NO(174) | 2)
> >>> +#define PINMUX_GPIO174__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(174) | 3)
> >>> +#define PINMUX_GPIO174__FUNC_I2S2_DI2 (MTK_PIN_NO(174) | 4)
> >>> +#define PINMUX_GPIO174__FUNC_URTS0 (MTK_PIN_NO(174) | 5)
> >>> +#define PINMUX_GPIO174__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(174) | 6)
> >>> +#define PINMUX_GPIO174__FUNC_ANT_SEL7 (MTK_PIN_NO(174) | 7)
> >>> +
> >>> +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
> >>> +#define PINMUX_GPIO175__FUNC_ANT_SEL7 (MTK_PIN_NO(175) | 1)
> >>> +
> >>> +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
> >>> +
> >>> +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
> >>> +
> >>> +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
> >>> +
> >>> +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
> >>> +
> >>> +#endif /* __MT8183-PINFUNC_H */
> >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >>> new file mode 100644
> >>> index 0000000..63db9cc
> >>> --- /dev/null
> >>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >>> @@ -0,0 +1,408 @@
> >>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >>> +/*
> >>> + * Copyright (c) 2018 MediaTek Inc.
> >>> + * Author: Ben Ho <ben.ho@mediatek.com>
> >>> + * Erin Lo <erin.lo@mediatek.com>
> >>> + */
> >>> +
> >>> +#include <dt-bindings/clock/mt8183-clk.h>
> >>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> >>> +#include <dt-bindings/interrupt-controller/irq.h>
> >>> +#include "mt8183-pinfunc.h"
> >>> +
> >>> +/ {
> >>> + compatible = "mediatek,mt8183";
> >>> + interrupt-parent = <&sysirq>;
> >>> + #address-cells = <2>;
> >>> + #size-cells = <2>;
> >>> +
> >>> + cpus {
> >>> + #address-cells = <1>;
> >>> + #size-cells = <0>;
> >>> +
> >>> + cpu-map {
> >>> + cluster0 {
> >>> + core0 {
> >>> + cpu = <&cpu0>;
> >>> + };
> >>> + core1 {
> >>> + cpu = <&cpu1>;
> >>> + };
> >>> + core2 {
> >>> + cpu = <&cpu2>;
> >>> + };
> >>> + core3 {
> >>> + cpu = <&cpu3>;
> >>> + };
> >>> + };
> >>> +
> >>> + cluster1 {
> >>> + core0 {
> >>> + cpu = <&cpu4>;
> >>> + };
> >>> + core1 {
> >>> + cpu = <&cpu5>;
> >>> + };
> >>> + core2 {
> >>> + cpu = <&cpu6>;
> >>> + };
> >>> + core3 {
> >>> + cpu = <&cpu7>;
> >>> + };
> >>> + };
> >>> + };
> >>> +
> >>> + cpu0: cpu@0 {
> >>> + device_type = "cpu";
> >>> + compatible = "arm,cortex-a53";
> >>> + reg = <0x000>;
> >>> + enable-method = "psci";
> >>> + };
> >>> +
> >>> + cpu1: cpu@1 {
> >>> + device_type = "cpu";
> >>> + compatible = "arm,cortex-a53";
> >>> + reg = <0x001>;
> >>> + enable-method = "psci";
> >>> + };
> >>> +
> >>> + cpu2: cpu@2 {
> >>> + device_type = "cpu";
> >>> + compatible = "arm,cortex-a53";
> >>> + reg = <0x002>;
> >>> + enable-method = "psci";
> >>> + };
> >>> +
> >>> + cpu3: cpu@3 {
> >>> + device_type = "cpu";
> >>> + compatible = "arm,cortex-a53";
> >>> + reg = <0x003>;
> >>> + enable-method = "psci";
> >>> + };
> >>> +
> >>> + cpu4: cpu@100 {
> >>> + device_type = "cpu";
> >>> + compatible = "arm,cortex-a73";
> >>> + reg = <0x100>;
> >>> + enable-method = "psci";
> >>> + };
> >>> +
> >>> + cpu5: cpu@101 {
> >>> + device_type = "cpu";
> >>> + compatible = "arm,cortex-a73";
> >>> + reg = <0x101>;
> >>> + enable-method = "psci";
> >>> + };
> >>> +
> >>> + cpu6: cpu@102 {
> >>> + device_type = "cpu";
> >>> + compatible = "arm,cortex-a73";
> >>> + reg = <0x102>;
> >>> + enable-method = "psci";
> >>> + };
> >>> +
> >>> + cpu7: cpu@103 {
> >>> + device_type = "cpu";
> >>> + compatible = "arm,cortex-a73";
> >>> + reg = <0x103>;
> >>> + enable-method = "psci";
> >>> + };
> >>> + };
> >>> +
> >>> + pmu-a53 {
> >>> + compatible = "arm,cortex-a53-pmu";
> >>> + interrupt-parent = <&gic>;
> >>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
> >>> + };
> >>> +
> >>> + pmu-a73 {
> >>> + compatible = "arm,cortex-a73-pmu";
> >>> + interrupt-parent = <&gic>;
> >>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
> >>> + };
> >>> +
> >>> + psci {
> >>> + compatible = "arm,psci-1.0";
> >>> + method = "smc";
> >>> + };
> >>> +
> >>> + clk26m: oscillator {
> >>> + compatible = "fixed-clock";
> >>> + #clock-cells = <0>;
> >>> + clock-frequency = <26000000>;
> >>> + clock-output-names = "clk26m";
> >>> + };
> >>> +
> >>> + timer {
> >>> + compatible = "arm,armv8-timer";
> >>> + interrupt-parent = <&gic>;
> >>> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
> >>> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
> >>> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
> >>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
> >>> + };
> >>> +
> >>> + gic: interrupt-controller@c000000 {
> >>> + compatible = "arm,gic-v3";
> >>> + #interrupt-cells = <4>;
> >>> + interrupt-parent = <&gic>;
> >>> + interrupt-controller;
> >>> + reg = <0 0x0c000000 0 0x40000>, /* GICD */
> >>> + <0 0x0c100000 0 0x200000>, /* GICR */
> >>> + <0 0x0c400000 0 0x2000>, /* GICC */
> >>> + <0 0x0c410000 0 0x1000>, /* GICH */
> >>> + <0 0x0c420000 0 0x2000>; /* GICV */
> >>> +
> >>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> >>> + ppi-partitions {
> >>> + ppi_cluster0: interrupt-partition-0 {
> >>> + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
> >>> + };
> >>> + ppi_cluster1: interrupt-partition-1 {
> >>> + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
> >>> + };
> >>> + };
> >>> + };
> >>> +
> >>> + mcucfg: syscon@c530000 {
> >>> + compatible = "mediatek,mt8183-mcucfg", "syscon";
> >>> + reg = <0 0x0c530000 0 0x1000>;
> >>> + #clock-cells = <1>;
> >>> + };
> >>> +
> >>> + sysirq: intpol-controller@c530a80 {
> >>> + compatible = "mediatek,mt8183-sysirq",
> >>> + "mediatek,mt6577-sysirq";
> >>> + interrupt-controller;
> >>> + #interrupt-cells = <4>;
> >>> + interrupt-parent = <&gic>;
> >>> + reg = <0 0x0c530a80 0 0x50>;
> >>> + };
> >>> +
> >>> + topckgen: syscon@10000000 {
> >>> + compatible = "mediatek,mt8183-topckgen", "syscon";
> >>> + reg = <0 0x10000000 0 0x1000>;
> >>> + #clock-cells = <1>;
> >>> + };
> >>> +
> >>> + infracfg: syscon@10001000 {
> >>> + compatible = "mediatek,mt8183-infracfg", "syscon";
> >>> + reg = <0 0x10001000 0 0x1000>;
> >>> + #clock-cells = <1>;
> >>> + };
> >>> +
> >>> + pio: pinctrl@1000b000 {
> >>> + compatible = "mediatek,mt8183-pinctrl";
> >>> + reg = <0 0x10005000 0 0x1000>,
> >>> + <0 0x11f20000 0 0x1000>,
> >>> + <0 0x11e80000 0 0x1000>,
> >>> + <0 0x11e70000 0 0x1000>,
> >>> + <0 0x11e90000 0 0x1000>,
> >>> + <0 0x11d30000 0 0x1000>,
> >>> + <0 0x11d20000 0 0x1000>,
> >>> + <0 0x11c50000 0 0x1000>,
> >>> + <0 0x11f30000 0 0x1000>,
> >>> + <0 0x1000b000 0 0x1000>;
> >>> + reg-names = "iocfg0", "iocfg1", "iocfg2",
> >>> + "iocfg3", "iocfg4", "iocfg5",
> >>> + "iocfg6", "iocfg7", "iocfg8",
> >>> + "eint";
> >>> + gpio-controller;
> >>> + #gpio-cells = <2>;
> >>> + gpio-ranges = <&pio 0 0 192>;
> >>> + interrupt-controller;
> >>> + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>;
> >>> + interrupt-parent = <&gic>;
> >>> + #interrupt-cells = <4>;
> >>> + };
> >>> +
> >>> + apmixedsys: syscon@1000c000 {
> >>> + compatible = "mediatek,mt8183-apmixedsys", "syscon";
> >>> + reg = <0 0x1000c000 0 0x1000>;
> >>> + #clock-cells = <1>;
> >>> + };
> >>> +
> >>> + pwrap: pwrap@1000d000 {
> >>> + compatible = "mediatek,mt8183-pwrap";
> >>> + reg = <0 0x1000d000 0 0x1000>;
> >>> + reg-names = "pwrap";
> >>> + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 0>;
> >>> + clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
> >>> + <&infracfg CLK_INFRA_PMIC_AP>;
> >>> + clock-names = "spi", "wrap";
> >>> + };
> >>> +
> >>> + uart0: serial@11002000 {
> >>> + compatible = "mediatek,mt8183-uart",
> >>> + "mediatek,mt6577-uart";
> >>> + reg = <0 0x11002000 0 0x1000>;
> >>> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW 0>;
> >>> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
> >>> + clock-names = "baud", "bus";
> >>> + status = "disabled";
> >>> + };
> >>> +
> >>> + uart1: serial@11003000 {
> >>> + compatible = "mediatek,mt8183-uart",
> >>> + "mediatek,mt6577-uart";
> >>> + reg = <0 0x11003000 0 0x1000>;
> >>> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW 0>;
> >>> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
> >>> + clock-names = "baud", "bus";
> >>> + status = "disabled";
> >>> + };
> >>> +
> >>> + uart2: serial@11004000 {
> >>> + compatible = "mediatek,mt8183-uart",
> >>> + "mediatek,mt6577-uart";
> >>> + reg = <0 0x11004000 0 0x1000>;
> >>> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW 0>;
> >>> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
> >>> + clock-names = "baud", "bus";
> >>> + status = "disabled";
> >>> + };
> >>> +
> >>> + spi0: spi@1100a000 {
> >>> + compatible = "mediatek,mt8183-spi";
> >>> + #address-cells = <1>;
> >>> + #size-cells = <0>;
> >>> + reg = <0 0x1100a000 0 0x1000>;
> >>> + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW 0>;
> >>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> >>> + <&topckgen CLK_TOP_MUX_SPI>,
> >>> + <&infracfg CLK_INFRA_SPI0>;
> >>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> >>> + status = "disabled";
> >>> + };
> >>> +
> >>> + spi1: spi@11010000 {
> >>> + compatible = "mediatek,mt8183-spi";
> >>> + #address-cells = <1>;
> >>> + #size-cells = <0>;
> >>> + reg = <0 0x11010000 0 0x1000>;
> >>> + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW 0>;
> >>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> >>> + <&topckgen CLK_TOP_MUX_SPI>,
> >>> + <&infracfg CLK_INFRA_SPI1>;
> >>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> >>> + status = "disabled";
> >>> + };
> >>> +
> >>> + spi2: spi@11012000 {
> >>> + compatible = "mediatek,mt8183-spi";
> >>> + #address-cells = <1>;
> >>> + #size-cells = <0>;
> >>> + reg = <0 0x11012000 0 0x1000>;
> >>> + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW 0>;
> >>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> >>> + <&topckgen CLK_TOP_MUX_SPI>,
> >>> + <&infracfg CLK_INFRA_SPI2>;
> >>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> >>> + status = "disabled";
> >>> + };
> >>> +
> >>> + spi3: spi@11013000 {
> >>> + compatible = "mediatek,mt8183-spi";
> >>> + #address-cells = <1>;
> >>> + #size-cells = <0>;
> >>> + reg = <0 0x11013000 0 0x1000>;
> >>> + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW 0>;
> >>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> >>> + <&topckgen CLK_TOP_MUX_SPI>,
> >>> + <&infracfg CLK_INFRA_SPI3>;
> >>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> >>> + status = "disabled";
> >>> + };
> >>> +
> >>> + spi4: spi@11018000 {
> >>> + compatible = "mediatek,mt8183-spi";
> >>> + #address-cells = <1>;
> >>> + #size-cells = <0>;
> >>> + reg = <0 0x11018000 0 0x1000>;
> >>> + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW 0>;
> >>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> >>> + <&topckgen CLK_TOP_MUX_SPI>,
> >>> + <&infracfg CLK_INFRA_SPI4>;
> >>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> >>> + status = "disabled";
> >>> + };
> >>> +
> >>> + spi5: spi@11019000 {
> >>> + compatible = "mediatek,mt8183-spi";
> >>> + #address-cells = <1>;
> >>> + #size-cells = <0>;
> >>> + reg = <0 0x11019000 0 0x1000>;
> >>> + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW 0>;
> >>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
> >>> + <&topckgen CLK_TOP_MUX_SPI>,
> >>> + <&infracfg CLK_INFRA_SPI5>;
> >>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> >>> + status = "disabled";
> >>> + };
> >>> +
> >>> + audiosys: syscon@11220000 {
> >>> + compatible = "mediatek,mt8183-audiosys", "syscon";
> >>> + reg = <0 0x11220000 0 0x1000>;
> >>> + #clock-cells = <1>;
> >>> + };
> >>> +
> >>> + mfgcfg: syscon@13000000 {
> >>> + compatible = "mediatek,mt8183-mfgcfg", "syscon";
> >>> + reg = <0 0x13000000 0 0x1000>;
> >>> + #clock-cells = <1>;
> >>> + };
> >>> +
> >>> + mmsys: syscon@14000000 {
> >>> + compatible = "mediatek,mt8183-mmsys", "syscon";
> >>> + reg = <0 0x14000000 0 0x1000>;
> >>> + #clock-cells = <1>;
> >>> + };
> >>> +
> >>> + imgsys: syscon@15020000 {
> >>> + compatible = "mediatek,mt8183-imgsys", "syscon";
> >>> + reg = <0 0x15020000 0 0x1000>;
> >>> + #clock-cells = <1>;
> >>> + };
> >>> +
> >>> + vdecsys: syscon@16000000 {
> >>> + compatible = "mediatek,mt8183-vdecsys", "syscon";
> >>> + reg = <0 0x16000000 0 0x1000>;
> >>> + #clock-cells = <1>;
> >>> + };
> >>> +
> >>> + vencsys: syscon@17000000 {
> >>> + compatible = "mediatek,mt8183-vencsys", "syscon";
> >>> + reg = <0 0x17000000 0 0x1000>;
> >>> + #clock-cells = <1>;
> >>> + };
> >>> +
> >>> + ipu_conn: syscon@19000000 {
> >>> + compatible = "mediatek,mt8183-ipu_conn", "syscon";
> >>> + reg = <0 0x19000000 0 0x1000>;
> >>> + #clock-cells = <1>;
> >>> + };
> >>> +
> >>> + ipu_adl: syscon@19010000 {
> >>> + compatible = "mediatek,mt8183-ipu_adl", "syscon";
> >>> + reg = <0 0x19010000 0 0x1000>;
> >>> + #clock-cells = <1>;
> >>> + };
> >>> +
> >>> + ipu_core0: syscon@19180000 {
> >>> + compatible = "mediatek,mt8183-ipu_core0", "syscon";
> >>> + reg = <0 0x19180000 0 0x1000>;
> >>> + #clock-cells = <1>;
> >>> + };
> >>> +
> >>> + ipu_core1: syscon@19280000 {
> >>> + compatible = "mediatek,mt8183-ipu_core1", "syscon";
> >>> + reg = <0 0x19280000 0 0x1000>;
> >>> + #clock-cells = <1>;
> >>> + };
> >>> +
> >>> + camsys: syscon@1a000000 {
> >>> + compatible = "mediatek,mt8183-camsys", "syscon";
> >>> + reg = <0 0x1a000000 0 0x1000>;
> >>> + #clock-cells = <1>;
> >>> + };
> >>> +};
> >>>
> >>
> >> _______________________________________________
> >> Linux-mediatek mailing list
> >> Linux-mediatek@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-mediatek
> >
> >
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply
* Re: [PATCH v6 5/6] dt-bindings: pinctrl: mt8183: add binding document
From: Erin Lo @ 2019-02-14 3:29 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
Marc Zyngier, Greg Kroah-Hartman, Stephen Boyd, devicetree,
srv_heupstream, linux-kernel, linux-serial, linux-mediatek,
linux-arm-kernel, yingjoe.chen, mars.cheng, eddie.huang,
linux-clk, Zhiyong Tao
In-Reply-To: <d76bb2e8-5285-15ce-b850-6cf3065e0777@gmail.com>
On Thu, 2019-02-07 at 16:28 +0100, Matthias Brugger wrote:
>
> On 24/01/2019 09:07, Erin Lo wrote:
> > From: Zhiyong Tao <zhiyong.tao@mediatek.com>
> >
> > The commit adds mt8183 compatible node in binding document.
> >
> > Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
> > Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> > ---
>
> I'm missing Linus Walleij on the recipient list.
> Pleas make sure to add all persons from the get_maintainers script.
> IMHO it's a bit unfortunate that we got the driver merged, but no binding
> description. Please try to send driver + binding documentation together, that
> makes things easier to discuss.
>
> Thanks,
> Matthias
>
OK! I will add Linus Walleij on the recipient list.
It's right..the binding should send together with driver code.
We will pay more attention of this next time.
Thank you for your reminder.
Best Regards,
Erin
> > .../devicetree/bindings/pinctrl/pinctrl-mt8183.txt | 115 +++++++++++++++++++++
> > 1 file changed, 115 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt
> >
> > diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt
> > new file mode 100644
> > index 0000000..364e673
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt
> > @@ -0,0 +1,115 @@
> > +* Mediatek MT8183 Pin Controller
> > +
> > +The Mediatek's Pin controller is used to control SoC pins.
> > +
> > +Required properties:
> > +- compatible: value should be one of the following.
> > + "mediatek,mt8183-pinctrl", compatible with mt8183 pinctrl.
> > +- gpio-controller : Marks the device node as a gpio controller.
> > +- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
> > + binding is used, the amount of cells must be specified as 2. See the below
> > + mentioned gpio binding representation for description of particular cells.
> > +- gpio-ranges : gpio valid number range.
> > +- reg: physicall address base for gpio base registers. There are nine
> > + physicall address base in mt8183. They are 0x10005000, 0x11F20000,
> > + 0x11E80000, 0x11E70000, 0x11E90000, 0x11D30000, 0x11D20000, 0x11C50000,
> > + 0x11F30000.
> > +
> > + Eg: <&pio 6 0>
> > + <[phandle of the gpio controller node]
> > + [line number within the gpio controller]
> > + [flags]>
> > +
> > + Values for gpio specifier:
> > + - Line number: is a value between 0 to 202.
> > + - Flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
> > + Only the following flags are supported:
> > + 0 - GPIO_ACTIVE_HIGH
> > + 1 - GPIO_ACTIVE_LOW
> > +
> > +Optional properties:
> > +- reg-names: gpio base register names. There are nine gpio base register
> > + names in mt8183. They are "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4",
> > + "iocfg5", "iocfg6", "iocfg7", "iocfg8".
> > +- interrupt-controller: Marks the device node as an interrupt controller
> > +- #interrupt-cells: Should be two.
> > +- interrupts : The interrupt outputs from the controller.
> > +
> > +Please refer to pinctrl-bindings.txt in this directory for details of the
> > +common pinctrl bindings used by client devices.
> > +
> > +Subnode format
> > +A pinctrl node should contain at least one subnodes representing the
> > +pinctrl groups available on the machine. Each subnode will list the
> > +pins it needs, and how they should be configured, with regard to muxer
> > +configuration, pullups, drive strength, input enable/disable and input schmitt.
> > +
> > + node {
> > + pinmux = <PIN_NUMBER_PINMUX>;
> > + GENERIC_PINCONFIG;
> > + };
> > +
> > +Required properties:
> > +- pinmux: integer array, represents gpio pin number and mux setting.
> > + Supported pin number and mux varies for different SoCs, and are defined
> > + as macros in boot/dts/<soc>-pinfunc.h directly.
> > +
> > +Optional properties:
> > +- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
> > + bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high,
> > + input-schmitt-enable, input-schmitt-disable and drive-strength are valid.
> > +
> > + Some special pins have extra pull up strength, there are R0 and R1 pull-up
> > + resistors available, but for user, it's only need to set R1R0 as 00, 01, 10 or 11.
> > + So when config mediatek,pull-up-adv or mediatek,pull-down-adv,
> > + it support arguments for those special pins.
> > +
> > + When config drive-strength, it can support some arguments, such as
> > + MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h.
> > +
> > +Examples:
> > +
> > +#include "mt8183-pinfunc.h"
> > +
> > +...
> > +{
> > + pio: pinctrl@10005000 {
> > + compatible = "mediatek,mt8183-pinctrl";
> > + reg = <0 0x10005000 0 0x1000>,
> > + <0 0x11F20000 0 0x1000>,
> > + <0 0x11E80000 0 0x1000>,
> > + <0 0x11E70000 0 0x1000>,
> > + <0 0x11E90000 0 0x1000>,
> > + <0 0x11D30000 0 0x1000>,
> > + <0 0x11D20000 0 0x1000>,
> > + <0 0x11C50000 0 0x1000>,
> > + <0 0x11F30000 0 0x1000>;
> > + reg-names = "iocfg0", "iocfg1", "iocfg2",
> > + "iocfg3", "iocfg4", "iocfg5",
> > + "iocfg6", "iocfg7", "iocfg8";
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + gpio-ranges = <&pio 0 0 192>;
> > + interrupt-controller;
> > + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-parent = <&gic>;
> > + #interrupt-cells = <2>;
> > +
> > + i2c0_pins_a: i2c0 {
> > + pins1 {
> > + pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
> > + <PINMUX_GPIO49__FUNC_SDA5>;
> > + mediatek,pull-up-adv = <11>;
> > + };
> > + };
> > +
> > + i2c1_pins_a: i2c1 {
> > + pins {
> > + pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
> > + <PINMUX_GPIO51__FUNC_SDA3>;
> > + mediatek,pull-down-adv = <10>;
> > + };
> > + };
> > + ...
> > + };
> > +};
> >
^ permalink raw reply
* Re: [PATCH v10 1/3] dmaengine: 8250_mtk_dma: add MediaTek uart DMA support
From: Long Cheng @ 2019-02-14 2:44 UTC (permalink / raw)
To: Vinod Koul
Cc: Randy Dunlap, Rob Herring, Mark Rutland, Ryder Lee, Sean Wang,
Nicolas Boichat, Matthias Brugger, Dan Williams,
Greg Kroah-Hartman, Jiri Slaby, Sean Wang, dmaengine, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, linux-serial,
srv_heupstream, Yingjoe Chen, YT Shen, Zhenbao Liu
In-Reply-To: <20190204072154.GJ4296@vkoul-mobl>
On Mon, 2019-02-04 at 12:51 +0530, Vinod Koul wrote:
Hi Vinod sir,
> On 18-01-19, 11:10, Long Cheng wrote:
> > +static enum dma_status mtk_uart_apdma_tx_status(struct dma_chan *chan,
> > + dma_cookie_t cookie,
> > + struct dma_tx_state *txstate)
> > +{
> > + struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
> > + enum dma_status ret;
> > + unsigned long flags;
> > +
> > + if (!txstate)
> > + return DMA_ERROR;
>
> Why, it is not a mandatory arg!
Next version, I will remove it.
>
> > + ret = dma_cookie_status(chan, cookie, txstate);
> > + spin_lock_irqsave(&c->vc.lock, flags);
> > + if (ret == DMA_IN_PROGRESS) {
> > + c->rx_status = mtk_uart_apdma_read(c, VFF_RPT) & VFF_RING_SIZE;
> > + dma_set_residue(txstate, c->rx_status);
> > + } else if (ret == DMA_COMPLETE && c->dir == DMA_DEV_TO_MEM) {
> > + dma_set_residue(txstate, c->rx_status);
>
> what is the point is setting residue to comleted txn, it is zero!
>
> > + } else {
> > + dma_set_residue(txstate, 0);
>
> naah that doesnt sound correct!
>
Next version, I will modify the function.
> > +static void mtk_uart_apdma_config_write(struct dma_chan *chan,
> > + struct dma_slave_config *cfg,
> > + enum dma_transfer_direction dir)
> > +{
> > + struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
> > + struct mtk_uart_apdmadev *mtkd =
> > + to_mtk_uart_apdma_dev(c->vc.chan.device);
> > + unsigned int tmp;
> > +
> > + if (mtk_uart_apdma_read(c, VFF_EN) == VFF_EN_B)
> > + return;
> > +
> > + c->dir = dir;
> > +
> > + if (dir == DMA_DEV_TO_MEM) {
> > + tmp = cfg->src_addr_width * 1024;
>
> why multiply by 1024?
>
Next version, I will modify the this, with 'src_port_window_size' &&
'dst_port_window_size'.
> > +static int mtk_uart_apdma_device_pause(struct dma_chan *chan)
> > +{
> > + /* just for check caps pass */
> > + return 0;
> > +}
>
> please remove, this is not a mandatory fn
Can't remove it. Before the mail, i had explained it. in 8250 uart
framework, will check the function..
thanks.
^ permalink raw reply
* Re: [RFC PATCH v1 17/25] printk: add processor number to output
From: John Ogness @ 2019-02-13 22:29 UTC (permalink / raw)
To: linux-kernel
Cc: Peter Zijlstra, Petr Mladek, Sergey Senozhatsky, Steven Rostedt,
Daniel Wang, Andrew Morton, Linus Torvalds, Greg Kroah-Hartman,
Alan Cox, Jiri Slaby, Peter Feiner, linux-serial,
Sergey Senozhatsky
In-Reply-To: <20190212143003.48446-18-john.ogness@linutronix.de>
On 2019-02-12, John Ogness <john.ogness@linutronix.de> wrote:
> It can be difficult to sort printk out if multiple processors are
> printing simultaneously. Add the processor number to the printk
> output to allow the messages to be sorted.
I just discovered Tetsuo's recently accepted work[0]. So obviously it
obsoletes this patch.
John Ogness
[0] http://lkml.kernel.org/r/1543045075-3008-1-git-send-email-penguin-kernel@I-love.SAKURA.ne.jp
^ permalink raw reply
* Re: [RFC PATCH v1 00/25] printk: new implementation
From: John Ogness @ 2019-02-13 22:20 UTC (permalink / raw)
To: David Laight
Cc: linux-kernel@vger.kernel.org, Peter Zijlstra, Petr Mladek,
Sergey Senozhatsky, Steven Rostedt, Daniel Wang, Andrew Morton,
Linus Torvalds, Greg Kroah-Hartman, Alan Cox, Jiri Slaby,
Peter Feiner, linux-serial@vger.kernel.org, Sergey Senozhatsky
In-Reply-To: <6f965383270d45d6ac26529fec5ad470@AcuMS.aculab.com>
On 2019-02-13, David Laight <David.Laight@ACULAB.COM> wrote:
> ...
>> - A dedicated kernel thread is created for printing to all consoles in
>> a fully preemptible context.
>>
>> - A new (optional) console operation "write_atomic" is introduced that
>> console drivers may implement. This function must be NMI-safe. An
>> implementation for the 8250 UART driver is provided.
>>
>> - The concept of "emergency messages" is introduced that allows
>> important messages (based on a new emergency loglevel threshold) to
>> be immediately written to any consoles supporting write_atomic,
>> regardless of the context.
> ...
>
> Does this address my usual 'gripe' that the output is written to the
> console by syslogd and not by the kernel itself?
If I understand it correctly, your usual 'gripe' is aimed at
distributions that are turning off the kernel writing directly to the
console. I don't see how that is a kernel issue.
> When you are trying to find out where the system is completely
> deadlocking you need the 'old fashioned' completely synchronous kernel
> printf().
Emergency messages will give you that. They differ from the current
implementation by changing printk to have the caller print only _their_
message directly without concern for past unseen non-emergency messages
or which context they are in.
John Ogness
^ permalink raw reply
* Re: [RFC PATCH v1 02/25] printk-rb: add prb locking functions
From: John Ogness @ 2019-02-13 21:39 UTC (permalink / raw)
To: Petr Mladek
Cc: linux-kernel, Peter Zijlstra, Sergey Senozhatsky, Steven Rostedt,
Daniel Wang, Andrew Morton, Linus Torvalds, Greg Kroah-Hartman,
Alan Cox, Jiri Slaby, Peter Feiner, linux-serial,
Sergey Senozhatsky
In-Reply-To: <20190213154541.wvft64nf352vghou@pathway.suse.cz>
On 2019-02-13, Petr Mladek <pmladek@suse.com> wrote:
>> Add processor-reentrant spin locking functions. These allow
>> restricting the number of possible contexts to 2, which can simplify
>> implementing code that also supports NMI interruptions.
>>
>> prb_lock();
>>
>> /*
>> * This code is synchronized with all contexts
>> * except an NMI on the same processor.
>> */
>>
>> prb_unlock();
>>
>> In order to support printk's emergency messages, a
>> processor-reentrant spin lock will be used to control raw access to
>> the emergency console. However, it must be the same
>> processor-reentrant spin lock as the one used by the ring buffer,
>> otherwise a deadlock can occur:
>>
>> CPU1: printk lock -> emergency -> serial lock
>> CPU2: serial lock -> printk lock
>>
>> By making the processor-reentrant implemtation available externally,
>> printk can use the same atomic_t for the ring buffer as for the
>> emergency console and thus avoid the above deadlock.
>
> Interesting idea. I just wonder if it might cause some problems
> when it is shared between printk() and many other consoles.
>
> It sounds like the big kernel lock or console_lock. They
> both caused many troubles.
It causes big troubles (deadlocks) if you have multiple instances of
it. Mainly because printk can be called from _any_ line of code in the
kernel. That is the reason I decided that it needs to be shared and only
used in call chains that are carefully constructed such as:
printk -> write_atomic
and NMI contexts are _never_ allowed to do things that rely on waiting
forever for other CPUs. For that reason it does kinda feel like a BKL.
If we do find some problems, we may want to switch to a ringbuffer
implementation that is fully lockless for both multi-readers and
multi-writers. I have written such a beast, but it is less efficient and
more complex than the ringbuffer in this series. Also, that only shrinks
the window since write_atomic would still need to make use of the
processor-reentrant spinlock to synchronize the console output. That's
why I decided to RFC with the simpler ringbuffer implementation.
>> diff --git a/lib/printk_ringbuffer.c b/lib/printk_ringbuffer.c
>> new file mode 100644
>> index 000000000000..28958b0cf774
>> --- /dev/null
>> +++ b/lib/printk_ringbuffer.c
>> @@ -0,0 +1,77 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +#include <linux/smp.h>
>> +#include <linux/printk_ringbuffer.h>
>> +
>> +static bool __prb_trylock(struct prb_cpulock *cpu_lock,
>> + unsigned int *cpu_store)
>> +{
>> + unsigned long *flags;
>> + unsigned int cpu;
>> +
>> + cpu = get_cpu();
>> +
>> + *cpu_store = atomic_read(&cpu_lock->owner);
>> + /* memory barrier to ensure the current lock owner is visible */
>> + smp_rmb();
>> + if (*cpu_store == -1) {
>> + flags = per_cpu_ptr(cpu_lock->irqflags, cpu);
>> + local_irq_save(*flags);
>> + if (atomic_try_cmpxchg_acquire(&cpu_lock->owner,
>> + cpu_store, cpu)) {
>> + return true;
>> + }
>> + local_irq_restore(*flags);
>> + } else if (*cpu_store == cpu) {
>> + return true;
>> + }
>> +
>> + put_cpu();
>
> Is there any reason why you get/put CPU and enable/disable
> in each iteration?
>
> It is a spin lock after all. We do busy waiting anyway. This looks like
> burning CPU power for no real gain. Simple cpu_relax() should be
> enough.
Agreed.
>> + return false;
>> +}
>> +
>> +/*
>> + * prb_lock: Perform a processor-reentrant spin lock.
>> + * @cpu_lock: A pointer to the lock object.
>> + * @cpu_store: A "flags" pointer to store lock status information.
>> + *
>> + * If no processor has the lock, the calling processor takes the lock and
>> + * becomes the owner. If the calling processor is already the owner of the
>> + * lock, this function succeeds immediately. If lock is locked by another
>> + * processor, this function spins until the calling processor becomes the
>> + * owner.
>> + *
>> + * It is safe to call this function from any context and state.
>> + */
>> +void prb_lock(struct prb_cpulock *cpu_lock, unsigned int *cpu_store)
>> +{
>> + for (;;) {
>> + if (__prb_trylock(cpu_lock, cpu_store))
>> + break;
>> + cpu_relax();
>> + }
>> +}
>> +
>> +/*
>> + * prb_unlock: Perform a processor-reentrant spin unlock.
>> + * @cpu_lock: A pointer to the lock object.
>> + * @cpu_store: A "flags" object storing lock status information.
>> + *
>> + * Release the lock. The calling processor must be the owner of the lock.
>> + *
>> + * It is safe to call this function from any context and state.
>> + */
>> +void prb_unlock(struct prb_cpulock *cpu_lock, unsigned int cpu_store)
>> +{
>> + unsigned long *flags;
>> + unsigned int cpu;
>> +
>> + cpu = atomic_read(&cpu_lock->owner);
>> + atomic_set_release(&cpu_lock->owner, cpu_store);
>> +
>> + if (cpu_store == -1) {
>> + flags = per_cpu_ptr(cpu_lock->irqflags, cpu);
>> + local_irq_restore(*flags);
>> + }
>
> cpu_store looks like an implementation detail. The caller
> needs to remember it to handle the nesting properly.
It's really no different than "flags" in irqsave/irqrestore.
> We could achieve the same with a recursion counter hidden
> in struct prb_lock.
The only way I see how that could be implemented is if the cmpxchg
encoded the cpu owner and counter into a single integer. (Upper half as
counter, lower half as cpu owner.) Both fields would need to be updated
with a single cmpxchg. The critical cmpxchg being the one where the CPU
becomes unlocked (counter goes from 1 to 0 and cpu owner goes from N to
-1).
That seems like a lot of extra code just to avoid passing a "flags"
argument.
John Ogness
^ permalink raw reply
* RE: [RFC PATCH v1 00/25] printk: new implementation
From: David Laight @ 2019-02-13 16:54 UTC (permalink / raw)
To: 'John Ogness', linux-kernel@vger.kernel.org
Cc: Peter Zijlstra, Petr Mladek, Sergey Senozhatsky, Steven Rostedt,
Daniel Wang, Andrew Morton, Linus Torvalds, Greg Kroah-Hartman,
Alan Cox, Jiri Slaby, Peter Feiner, linux-serial@vger.kernel.org,
Sergey Senozhatsky
In-Reply-To: <20190212143003.48446-1-john.ogness@linutronix.de>
From: John Ogness
> Sent: 12 February 2019 14:30
...
> - A dedicated kernel thread is created for printing to all consoles in
> a fully preemptible context.
>
> - A new (optional) console operation "write_atomic" is introduced that
> console drivers may implement. This function must be NMI-safe. An
> implementation for the 8250 UART driver is provided.
>
> - The concept of "emergency messages" is introduced that allows
> important messages (based on a new emergency loglevel threshold) to
> be immediately written to any consoles supporting write_atomic,
> regardless of the context.
...
Does this address my usual 'gripe' that the output is written to the console
by syslogd and not by the kernel itself?
When you are trying to find out where the system is completely deadlocking
you need the 'old fashioned' completely synchronous kernel printf().
David
-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)
^ permalink raw reply
* Re: [RFC PATCH v1 02/25] printk-rb: add prb locking functions
From: Petr Mladek @ 2019-02-13 15:45 UTC (permalink / raw)
To: John Ogness
Cc: linux-kernel, Peter Zijlstra, Sergey Senozhatsky, Steven Rostedt,
Daniel Wang, Andrew Morton, Linus Torvalds, Greg Kroah-Hartman,
Alan Cox, Jiri Slaby, Peter Feiner, linux-serial,
Sergey Senozhatsky
In-Reply-To: <20190212143003.48446-3-john.ogness@linutronix.de>
On Tue 2019-02-12 15:29:40, John Ogness wrote:
> Add processor-reentrant spin locking functions. These allow
> restricting the number of possible contexts to 2, which can simplify
> implementing code that also supports NMI interruptions.
>
> prb_lock();
>
> /*
> * This code is synchronized with all contexts
> * except an NMI on the same processor.
> */
>
> prb_unlock();
>
> In order to support printk's emergency messages, a
> processor-reentrant spin lock will be used to control raw access to
> the emergency console. However, it must be the same
> processor-reentrant spin lock as the one used by the ring buffer,
> otherwise a deadlock can occur:
>
> CPU1: printk lock -> emergency -> serial lock
> CPU2: serial lock -> printk lock
>
> By making the processor-reentrant implemtation available externally,
> printk can use the same atomic_t for the ring buffer as for the
> emergency console and thus avoid the above deadlock.
Interesting idea. I just wonder if it might cause some problems
when it is shared between printk() and many other consoles.
It sounds like the big kernel lock or console_lock. They
both caused many troubles.
> diff --git a/lib/printk_ringbuffer.c b/lib/printk_ringbuffer.c
> new file mode 100644
> index 000000000000..28958b0cf774
> --- /dev/null
> +++ b/lib/printk_ringbuffer.c
> @@ -0,0 +1,77 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include <linux/smp.h>
> +#include <linux/printk_ringbuffer.h>
> +
> +static bool __prb_trylock(struct prb_cpulock *cpu_lock,
> + unsigned int *cpu_store)
> +{
> + unsigned long *flags;
> + unsigned int cpu;
> +
> + cpu = get_cpu();
> +
> + *cpu_store = atomic_read(&cpu_lock->owner);
> + /* memory barrier to ensure the current lock owner is visible */
> + smp_rmb();
> + if (*cpu_store == -1) {
> + flags = per_cpu_ptr(cpu_lock->irqflags, cpu);
> + local_irq_save(*flags);
> + if (atomic_try_cmpxchg_acquire(&cpu_lock->owner,
> + cpu_store, cpu)) {
> + return true;
> + }
> + local_irq_restore(*flags);
> + } else if (*cpu_store == cpu) {
> + return true;
> + }
> +
> + put_cpu();
Is there any reason why you get/put CPU and enable/disable
in each iteration?
It is a spin lock after all. We do busy waiting anyway. This looks like
burning CPU power for no real gain. Simple cpu_relax() should be enough.
> + return false;
> +}
> +
> +/*
> + * prb_lock: Perform a processor-reentrant spin lock.
> + * @cpu_lock: A pointer to the lock object.
> + * @cpu_store: A "flags" pointer to store lock status information.
> + *
> + * If no processor has the lock, the calling processor takes the lock and
> + * becomes the owner. If the calling processor is already the owner of the
> + * lock, this function succeeds immediately. If lock is locked by another
> + * processor, this function spins until the calling processor becomes the
> + * owner.
> + *
> + * It is safe to call this function from any context and state.
> + */
> +void prb_lock(struct prb_cpulock *cpu_lock, unsigned int *cpu_store)
> +{
> + for (;;) {
> + if (__prb_trylock(cpu_lock, cpu_store))
> + break;
> + cpu_relax();
> + }
> +}
> +
> +/*
> + * prb_unlock: Perform a processor-reentrant spin unlock.
> + * @cpu_lock: A pointer to the lock object.
> + * @cpu_store: A "flags" object storing lock status information.
> + *
> + * Release the lock. The calling processor must be the owner of the lock.
> + *
> + * It is safe to call this function from any context and state.
> + */
> +void prb_unlock(struct prb_cpulock *cpu_lock, unsigned int cpu_store)
> +{
> + unsigned long *flags;
> + unsigned int cpu;
> +
> + cpu = atomic_read(&cpu_lock->owner);
> + atomic_set_release(&cpu_lock->owner, cpu_store);
> +
> + if (cpu_store == -1) {
> + flags = per_cpu_ptr(cpu_lock->irqflags, cpu);
> + local_irq_restore(*flags);
> + }
cpu_store looks like an implementation detail. The caller
needs to remember it to handle the nesting properly.
We could achieve the same with a recursion counter hidden
in struct prb_lock.
Best Regards,
Petr
PS: This is the most complex patchset that I have ever reviewed.
I am not sure what is the best approach. I am going to understand
it and comment on what touches my eye. I will comment the overall
design later after I have a better understanding.
The first feeling is that it would be nice to be able to
store messages into a single log buffer from every context.
It will depend if the new approach is safe and maintainable.
The offloading of console handling into a kthread might be
problematic. We were pushing it for years and never succeeded.
People preferred to minimize the risk that messages would never
appear on the console.
Well, I still think that it might be needed because Steven's
console waiter logic does not prevent softlockups completely.
And realtime has much bigger problems with unpredictable
random printk-console-lockups requirements. IMHO, we need
a solution for the realtime mode and normal one could just benefit
from it. We have some ideas in the drawer. And this patchset
brings some new. Let's see.
Best Regards,
Petr
^ permalink raw reply
* Re: [PATCH v6 6/6] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile
From: Matthias Brugger @ 2019-02-13 14:54 UTC (permalink / raw)
To: Erin Lo
Cc: Rob Herring, Mark Rutland, Thomas Gleixner, Jason Cooper,
Marc Zyngier, Greg Kroah-Hartman, Stephen Boyd, devicetree,
Mengqi Zhang, Weiyi Lu, srv_heupstream, Seiya Wang, Ben Ho,
mars.cheng, linux-kernel, linux-mediatek, Hsin-Hsiung Wang,
linux-serial, Zhiyong Tao, yingjoe.chen, eddie.huang
In-Reply-To: <1550048633.10019.2.camel@mtksdaap41>
On 13/02/2019 10:03, Erin Lo wrote:
> On Thu, 2019-02-07 at 16:30 +0100, Matthias Brugger wrote:
>>
>> On 24/01/2019 09:07, Erin Lo wrote:
>>> From: Ben Ho <Ben.Ho@mediatek.com>
>>>
>>> Add basic chip support for Mediatek 8183, include
>>> pinctrl file, uart node with correct uart clocks, pwrap device
>>>
>>> Add clock controller nodes, include topckgen, infracfg,
>>> apmixedsys and subsystem.
>>>
>>> Signed-off-by: Ben Ho <Ben.Ho@mediatek.com>
>>> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
>>> Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
>>> Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
>>> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
>>> Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
>>> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
>>> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
>>> ---
>>> arch/arm64/boot/dts/mediatek/Makefile | 1 +
>>> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 136 +++
>>> arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h | 1120 +++++++++++++++++++++++++
>>
>> Would you mind to make the pinfunc.h a seperate patch and adding the pinctrl
>> maintainers to the list.
>>
>> Regards,
>> Matthias
>>
>
> OK! I will take pinfunc.h out of this series.
My take would be to somehow change this series in something like.
One patch which adds basic support for the SoC without any dependencies on other
series.
Every node that has a dependency on a different series should go in a separate
patch. In this case IMHO pinfunc.h can got with the dts node in one patch.
Regards,
Matthias
>
> Best Regards,
> Erin
>
>>> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 408 +++++++++
>>> 4 files changed, 1665 insertions(+)
>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts
>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
>>> index e8f952f..458bbc4 100644
>>> --- a/arch/arm64/boot/dts/mediatek/Makefile
>>> +++ b/arch/arm64/boot/dts/mediatek/Makefile
>>> @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
>>> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
>>> new file mode 100644
>>> index 0000000..b12c6ea
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
>>> @@ -0,0 +1,136 @@
>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> +/*
>>> + * Copyright (c) 2018 MediaTek Inc.
>>> + * Author: Ben Ho <ben.ho@mediatek.com>
>>> + * Erin Lo <erin.lo@mediatek.com>
>>> + */
>>> +
>>> +/dts-v1/;
>>> +#include "mt8183.dtsi"
>>> +
>>> +/ {
>>> + model = "MediaTek MT8183 evaluation board";
>>> + compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
>>> +
>>> + aliases {
>>> + serial0 = &uart0;
>>> + };
>>> +
>>> + memory@40000000 {
>>> + device_type = "memory";
>>> + reg = <0 0x40000000 0 0x80000000>;
>>> + };
>>> +
>>> + chosen {
>>> + stdout-path = "serial0:921600n8";
>>> + };
>>> +};
>>> +
>>> +&pio {
>>> + spi_pins_0: spi0{
>>> + pins_spi{
>>> + pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
>>> + <PINMUX_GPIO86__FUNC_SPI0_CSB>,
>>> + <PINMUX_GPIO87__FUNC_SPI0_MO>,
>>> + <PINMUX_GPIO88__FUNC_SPI0_CLK>;
>>> + bias-disable;
>>> + };
>>> + };
>>> +
>>> + spi_pins_1: spi1{
>>> + pins_spi{
>>> + pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
>>> + <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
>>> + <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
>>> + <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
>>> + bias-disable;
>>> + };
>>> + };
>>> +
>>> + spi_pins_2: spi2{
>>> + pins_spi{
>>> + pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
>>> + <PINMUX_GPIO1__FUNC_SPI2_MO>,
>>> + <PINMUX_GPIO2__FUNC_SPI2_CLK>,
>>> + <PINMUX_GPIO94__FUNC_SPI2_MI>;
>>> + bias-disable;
>>> + };
>>> + };
>>> +
>>> + spi_pins_3: spi3{
>>> + pins_spi{
>>> + pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
>>> + <PINMUX_GPIO22__FUNC_SPI3_CSB>,
>>> + <PINMUX_GPIO23__FUNC_SPI3_MO>,
>>> + <PINMUX_GPIO24__FUNC_SPI3_CLK>;
>>> + bias-disable;
>>> + };
>>> + };
>>> +
>>> + spi_pins_4: spi4{
>>> + pins_spi{
>>> + pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
>>> + <PINMUX_GPIO18__FUNC_SPI4_CSB>,
>>> + <PINMUX_GPIO19__FUNC_SPI4_MO>,
>>> + <PINMUX_GPIO20__FUNC_SPI4_CLK>;
>>> + bias-disable;
>>> + };
>>> + };
>>> +
>>> + spi_pins_5: spi5{
>>> + pins_spi{
>>> + pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
>>> + <PINMUX_GPIO14__FUNC_SPI5_CSB>,
>>> + <PINMUX_GPIO15__FUNC_SPI5_MO>,
>>> + <PINMUX_GPIO16__FUNC_SPI5_CLK>;
>>> + bias-disable;
>>> + };
>>> + };
>>> +};
>>> +
>>> +&spi0 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&spi_pins_0>;
>>> + mediatek,pad-select = <0>;
>>> + status = "okay";
>>> +};
>>> +
>>> +&spi1 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&spi_pins_1>;
>>> + mediatek,pad-select = <0>;
>>> + status = "okay";
>>> +};
>>> +
>>> +&spi2 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&spi_pins_2>;
>>> + mediatek,pad-select = <0>;
>>> + status = "okay";
>>> +};
>>> +
>>> +&spi3 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&spi_pins_3>;
>>> + mediatek,pad-select = <0>;
>>> + status = "okay";
>>> +};
>>> +
>>> +&spi4 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&spi_pins_4>;
>>> + mediatek,pad-select = <0>;
>>> + status = "okay";
>>> +};
>>> +
>>> +&spi5 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&spi_pins_5>;
>>> + mediatek,pad-select = <0>;
>>> + status = "okay";
>>> +
>>> +};
>>> +
>>> +&uart0 {
>>> + status = "okay";
>>> +};
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
>>> new file mode 100644
>>> index 0000000..768e41e
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
>>> @@ -0,0 +1,1120 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Copyright (C) 2018 MediaTek Inc.
>>> + * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
>>> + *
>>> + */
>>> +
>>> +#ifndef __MT8183_PINFUNC_H
>>> +#define __MT8183_PINFUNC_H
>>> +
>>> +#include <dt-bindings/pinctrl/mt65xx.h>
>>> +
>>> +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
>>> +#define PINMUX_GPIO0__FUNC_MRG_SYNC (MTK_PIN_NO(0) | 1)
>>> +#define PINMUX_GPIO0__FUNC_PCM0_SYNC (MTK_PIN_NO(0) | 2)
>>> +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 3)
>>> +#define PINMUX_GPIO0__FUNC_SRCLKENAI0 (MTK_PIN_NO(0) | 4)
>>> +#define PINMUX_GPIO0__FUNC_SCP_SPI2_CS (MTK_PIN_NO(0) | 5)
>>> +#define PINMUX_GPIO0__FUNC_I2S3_MCK (MTK_PIN_NO(0) | 6)
>>> +#define PINMUX_GPIO0__FUNC_SPI2_CSB (MTK_PIN_NO(0) | 7)
>>> +
>>> +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
>>> +#define PINMUX_GPIO1__FUNC_MRG_CLK (MTK_PIN_NO(1) | 1)
>>> +#define PINMUX_GPIO1__FUNC_PCM0_CLK (MTK_PIN_NO(1) | 2)
>>> +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 3)
>>> +#define PINMUX_GPIO1__FUNC_CLKM3 (MTK_PIN_NO(1) | 4)
>>> +#define PINMUX_GPIO1__FUNC_SCP_SPI2_MO (MTK_PIN_NO(1) | 5)
>>> +#define PINMUX_GPIO1__FUNC_I2S3_BCK (MTK_PIN_NO(1) | 6)
>>> +#define PINMUX_GPIO1__FUNC_SPI2_MO (MTK_PIN_NO(1) | 7)
>>> +
>>> +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
>>> +#define PINMUX_GPIO2__FUNC_MRG_DO (MTK_PIN_NO(2) | 1)
>>> +#define PINMUX_GPIO2__FUNC_PCM0_DO (MTK_PIN_NO(2) | 2)
>>> +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 3)
>>> +#define PINMUX_GPIO2__FUNC_SCL6 (MTK_PIN_NO(2) | 4)
>>> +#define PINMUX_GPIO2__FUNC_SCP_SPI2_CK (MTK_PIN_NO(2) | 5)
>>> +#define PINMUX_GPIO2__FUNC_I2S3_LRCK (MTK_PIN_NO(2) | 6)
>>> +#define PINMUX_GPIO2__FUNC_SPI2_CLK (MTK_PIN_NO(2) | 7)
>>> +
>>> +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
>>> +#define PINMUX_GPIO3__FUNC_MRG_DI (MTK_PIN_NO(3) | 1)
>>> +#define PINMUX_GPIO3__FUNC_PCM0_DI (MTK_PIN_NO(3) | 2)
>>> +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 3)
>>> +#define PINMUX_GPIO3__FUNC_SDA6 (MTK_PIN_NO(3) | 4)
>>> +#define PINMUX_GPIO3__FUNC_TDM_MCK (MTK_PIN_NO(3) | 5)
>>> +#define PINMUX_GPIO3__FUNC_I2S3_DO (MTK_PIN_NO(3) | 6)
>>> +#define PINMUX_GPIO3__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(3) | 7)
>>> +
>>> +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
>>> +#define PINMUX_GPIO4__FUNC_PWM_B (MTK_PIN_NO(4) | 1)
>>> +#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2)
>>> +#define PINMUX_GPIO4__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(4) | 3)
>>> +#define PINMUX_GPIO4__FUNC_MD_URXD1 (MTK_PIN_NO(4) | 4)
>>> +#define PINMUX_GPIO4__FUNC_TDM_BCK (MTK_PIN_NO(4) | 5)
>>> +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6)
>>> +#define PINMUX_GPIO4__FUNC_DAP_MD32_SWD (MTK_PIN_NO(4) | 7)
>>> +
>>> +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
>>> +#define PINMUX_GPIO5__FUNC_PWM_C (MTK_PIN_NO(5) | 1)
>>> +#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2)
>>> +#define PINMUX_GPIO5__FUNC_SSPM_URXD_AO (MTK_PIN_NO(5) | 3)
>>> +#define PINMUX_GPIO5__FUNC_MD_UTXD1 (MTK_PIN_NO(5) | 4)
>>> +#define PINMUX_GPIO5__FUNC_TDM_LRCK (MTK_PIN_NO(5) | 5)
>>> +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6)
>>> +#define PINMUX_GPIO5__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(5) | 7)
>>> +
>>> +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
>>> +#define PINMUX_GPIO6__FUNC_PWM_A (MTK_PIN_NO(6) | 1)
>>> +#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2)
>>> +#define PINMUX_GPIO6__FUNC_IDDIG (MTK_PIN_NO(6) | 3)
>>> +#define PINMUX_GPIO6__FUNC_MD_URXD0 (MTK_PIN_NO(6) | 4)
>>> +#define PINMUX_GPIO6__FUNC_TDM_DATA0 (MTK_PIN_NO(6) | 5)
>>> +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6)
>>> +#define PINMUX_GPIO6__FUNC_CMFLASH (MTK_PIN_NO(6) | 7)
>>> +
>>> +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
>>> +#define PINMUX_GPIO7__FUNC_SPI1_B_MI (MTK_PIN_NO(7) | 1)
>>> +#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2)
>>> +#define PINMUX_GPIO7__FUNC_USB_DRVVBUS (MTK_PIN_NO(7) | 3)
>>> +#define PINMUX_GPIO7__FUNC_MD_UTXD0 (MTK_PIN_NO(7) | 4)
>>> +#define PINMUX_GPIO7__FUNC_TDM_DATA1 (MTK_PIN_NO(7) | 5)
>>> +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6)
>>> +#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 7)
>>> +
>>> +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
>>> +#define PINMUX_GPIO8__FUNC_SPI1_B_CSB (MTK_PIN_NO(8) | 1)
>>> +#define PINMUX_GPIO8__FUNC_ANT_SEL3 (MTK_PIN_NO(8) | 2)
>>> +#define PINMUX_GPIO8__FUNC_SCL7 (MTK_PIN_NO(8) | 3)
>>> +#define PINMUX_GPIO8__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(8) | 4)
>>> +#define PINMUX_GPIO8__FUNC_TDM_DATA2 (MTK_PIN_NO(8) | 5)
>>> +#define PINMUX_GPIO8__FUNC_MD_INT0 (MTK_PIN_NO(8) | 6)
>>> +#define PINMUX_GPIO8__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(8) | 7)
>>> +
>>> +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
>>> +#define PINMUX_GPIO9__FUNC_SPI1_B_MO (MTK_PIN_NO(9) | 1)
>>> +#define PINMUX_GPIO9__FUNC_ANT_SEL4 (MTK_PIN_NO(9) | 2)
>>> +#define PINMUX_GPIO9__FUNC_CMMCLK2 (MTK_PIN_NO(9) | 3)
>>> +#define PINMUX_GPIO9__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(9) | 4)
>>> +#define PINMUX_GPIO9__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(9) | 5)
>>> +#define PINMUX_GPIO9__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(9) | 6)
>>> +#define PINMUX_GPIO9__FUNC_DBG_MON_B10 (MTK_PIN_NO(9) | 7)
>>> +
>>> +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
>>> +#define PINMUX_GPIO10__FUNC_SPI1_B_CLK (MTK_PIN_NO(10) | 1)
>>> +#define PINMUX_GPIO10__FUNC_ANT_SEL5 (MTK_PIN_NO(10) | 2)
>>> +#define PINMUX_GPIO10__FUNC_CMMCLK3 (MTK_PIN_NO(10) | 3)
>>> +#define PINMUX_GPIO10__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(10) | 4)
>>> +#define PINMUX_GPIO10__FUNC_TDM_DATA3 (MTK_PIN_NO(10) | 5)
>>> +#define PINMUX_GPIO10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 6)
>>> +#define PINMUX_GPIO10__FUNC_DBG_MON_B11 (MTK_PIN_NO(10) | 7)
>>> +
>>> +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
>>> +#define PINMUX_GPIO11__FUNC_TP_URXD1_AO (MTK_PIN_NO(11) | 1)
>>> +#define PINMUX_GPIO11__FUNC_IDDIG (MTK_PIN_NO(11) | 2)
>>> +#define PINMUX_GPIO11__FUNC_SCL6 (MTK_PIN_NO(11) | 3)
>>> +#define PINMUX_GPIO11__FUNC_UCTS1 (MTK_PIN_NO(11) | 4)
>>> +#define PINMUX_GPIO11__FUNC_UCTS0 (MTK_PIN_NO(11) | 5)
>>> +#define PINMUX_GPIO11__FUNC_SRCLKENAI1 (MTK_PIN_NO(11) | 6)
>>> +#define PINMUX_GPIO11__FUNC_I2S5_MCK (MTK_PIN_NO(11) | 7)
>>> +
>>> +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
>>> +#define PINMUX_GPIO12__FUNC_TP_UTXD1_AO (MTK_PIN_NO(12) | 1)
>>> +#define PINMUX_GPIO12__FUNC_USB_DRVVBUS (MTK_PIN_NO(12) | 2)
>>> +#define PINMUX_GPIO12__FUNC_SDA6 (MTK_PIN_NO(12) | 3)
>>> +#define PINMUX_GPIO12__FUNC_URTS1 (MTK_PIN_NO(12) | 4)
>>> +#define PINMUX_GPIO12__FUNC_URTS0 (MTK_PIN_NO(12) | 5)
>>> +#define PINMUX_GPIO12__FUNC_I2S2_DI2 (MTK_PIN_NO(12) | 6)
>>> +#define PINMUX_GPIO12__FUNC_I2S5_BCK (MTK_PIN_NO(12) | 7)
>>> +
>>> +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
>>> +#define PINMUX_GPIO13__FUNC_DBPI_D0 (MTK_PIN_NO(13) | 1)
>>> +#define PINMUX_GPIO13__FUNC_SPI5_MI (MTK_PIN_NO(13) | 2)
>>> +#define PINMUX_GPIO13__FUNC_PCM0_SYNC (MTK_PIN_NO(13) | 3)
>>> +#define PINMUX_GPIO13__FUNC_MD_URXD0 (MTK_PIN_NO(13) | 4)
>>> +#define PINMUX_GPIO13__FUNC_ANT_SEL3 (MTK_PIN_NO(13) | 5)
>>> +#define PINMUX_GPIO13__FUNC_I2S0_MCK (MTK_PIN_NO(13) | 6)
>>> +#define PINMUX_GPIO13__FUNC_DBG_MON_B15 (MTK_PIN_NO(13) | 7)
>>> +
>>> +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
>>> +#define PINMUX_GPIO14__FUNC_DBPI_D1 (MTK_PIN_NO(14) | 1)
>>> +#define PINMUX_GPIO14__FUNC_SPI5_CSB (MTK_PIN_NO(14) | 2)
>>> +#define PINMUX_GPIO14__FUNC_PCM0_CLK (MTK_PIN_NO(14) | 3)
>>> +#define PINMUX_GPIO14__FUNC_MD_UTXD0 (MTK_PIN_NO(14) | 4)
>>> +#define PINMUX_GPIO14__FUNC_ANT_SEL4 (MTK_PIN_NO(14) | 5)
>>> +#define PINMUX_GPIO14__FUNC_I2S0_BCK (MTK_PIN_NO(14) | 6)
>>> +#define PINMUX_GPIO14__FUNC_DBG_MON_B16 (MTK_PIN_NO(14) | 7)
>>> +
>>> +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
>>> +#define PINMUX_GPIO15__FUNC_DBPI_D2 (MTK_PIN_NO(15) | 1)
>>> +#define PINMUX_GPIO15__FUNC_SPI5_MO (MTK_PIN_NO(15) | 2)
>>> +#define PINMUX_GPIO15__FUNC_PCM0_DO (MTK_PIN_NO(15) | 3)
>>> +#define PINMUX_GPIO15__FUNC_MD_URXD1 (MTK_PIN_NO(15) | 4)
>>> +#define PINMUX_GPIO15__FUNC_ANT_SEL5 (MTK_PIN_NO(15) | 5)
>>> +#define PINMUX_GPIO15__FUNC_I2S0_LRCK (MTK_PIN_NO(15) | 6)
>>> +#define PINMUX_GPIO15__FUNC_DBG_MON_B17 (MTK_PIN_NO(15) | 7)
>>> +
>>> +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
>>> +#define PINMUX_GPIO16__FUNC_DBPI_D3 (MTK_PIN_NO(16) | 1)
>>> +#define PINMUX_GPIO16__FUNC_SPI5_CLK (MTK_PIN_NO(16) | 2)
>>> +#define PINMUX_GPIO16__FUNC_PCM0_DI (MTK_PIN_NO(16) | 3)
>>> +#define PINMUX_GPIO16__FUNC_MD_UTXD1 (MTK_PIN_NO(16) | 4)
>>> +#define PINMUX_GPIO16__FUNC_ANT_SEL6 (MTK_PIN_NO(16) | 5)
>>> +#define PINMUX_GPIO16__FUNC_I2S0_DI (MTK_PIN_NO(16) | 6)
>>> +#define PINMUX_GPIO16__FUNC_DBG_MON_B23 (MTK_PIN_NO(16) | 7)
>>> +
>>> +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
>>> +#define PINMUX_GPIO17__FUNC_DBPI_D4 (MTK_PIN_NO(17) | 1)
>>> +#define PINMUX_GPIO17__FUNC_SPI4_MI (MTK_PIN_NO(17) | 2)
>>> +#define PINMUX_GPIO17__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(17) | 3)
>>> +#define PINMUX_GPIO17__FUNC_MD_INT0 (MTK_PIN_NO(17) | 4)
>>> +#define PINMUX_GPIO17__FUNC_ANT_SEL7 (MTK_PIN_NO(17) | 5)
>>> +#define PINMUX_GPIO17__FUNC_I2S3_MCK (MTK_PIN_NO(17) | 6)
>>> +#define PINMUX_GPIO17__FUNC_DBG_MON_A1 (MTK_PIN_NO(17) | 7)
>>> +
>>> +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
>>> +#define PINMUX_GPIO18__FUNC_DBPI_D5 (MTK_PIN_NO(18) | 1)
>>> +#define PINMUX_GPIO18__FUNC_SPI4_CSB (MTK_PIN_NO(18) | 2)
>>> +#define PINMUX_GPIO18__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(18) | 3)
>>> +#define PINMUX_GPIO18__FUNC_MD_INT0 (MTK_PIN_NO(18) | 4)
>>> +#define PINMUX_GPIO18__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(18) | 5)
>>> +#define PINMUX_GPIO18__FUNC_I2S3_BCK (MTK_PIN_NO(18) | 6)
>>> +#define PINMUX_GPIO18__FUNC_DBG_MON_A2 (MTK_PIN_NO(18) | 7)
>>> +
>>> +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
>>> +#define PINMUX_GPIO19__FUNC_DBPI_D6 (MTK_PIN_NO(19) | 1)
>>> +#define PINMUX_GPIO19__FUNC_SPI4_MO (MTK_PIN_NO(19) | 2)
>>> +#define PINMUX_GPIO19__FUNC_CONN_MCU_TDO (MTK_PIN_NO(19) | 3)
>>> +#define PINMUX_GPIO19__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(19) | 4)
>>> +#define PINMUX_GPIO19__FUNC_URXD1 (MTK_PIN_NO(19) | 5)
>>> +#define PINMUX_GPIO19__FUNC_I2S3_LRCK (MTK_PIN_NO(19) | 6)
>>> +#define PINMUX_GPIO19__FUNC_DBG_MON_A3 (MTK_PIN_NO(19) | 7)
>>> +
>>> +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
>>> +#define PINMUX_GPIO20__FUNC_DBPI_D7 (MTK_PIN_NO(20) | 1)
>>> +#define PINMUX_GPIO20__FUNC_SPI4_CLK (MTK_PIN_NO(20) | 2)
>>> +#define PINMUX_GPIO20__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(20) | 3)
>>> +#define PINMUX_GPIO20__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(20) | 4)
>>> +#define PINMUX_GPIO20__FUNC_UTXD1 (MTK_PIN_NO(20) | 5)
>>> +#define PINMUX_GPIO20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 6)
>>> +#define PINMUX_GPIO20__FUNC_DBG_MON_A19 (MTK_PIN_NO(20) | 7)
>>> +
>>> +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
>>> +#define PINMUX_GPIO21__FUNC_DBPI_D8 (MTK_PIN_NO(21) | 1)
>>> +#define PINMUX_GPIO21__FUNC_SPI3_MI (MTK_PIN_NO(21) | 2)
>>> +#define PINMUX_GPIO21__FUNC_CONN_MCU_TMS (MTK_PIN_NO(21) | 3)
>>> +#define PINMUX_GPIO21__FUNC_DAP_MD32_SWD (MTK_PIN_NO(21) | 4)
>>> +#define PINMUX_GPIO21__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(21) | 5)
>>> +#define PINMUX_GPIO21__FUNC_I2S2_MCK (MTK_PIN_NO(21) | 6)
>>> +#define PINMUX_GPIO21__FUNC_DBG_MON_B5 (MTK_PIN_NO(21) | 7)
>>> +
>>> +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
>>> +#define PINMUX_GPIO22__FUNC_DBPI_D9 (MTK_PIN_NO(22) | 1)
>>> +#define PINMUX_GPIO22__FUNC_SPI3_CSB (MTK_PIN_NO(22) | 2)
>>> +#define PINMUX_GPIO22__FUNC_CONN_MCU_TCK (MTK_PIN_NO(22) | 3)
>>> +#define PINMUX_GPIO22__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(22) | 4)
>>> +#define PINMUX_GPIO22__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(22) | 5)
>>> +#define PINMUX_GPIO22__FUNC_I2S2_BCK (MTK_PIN_NO(22) | 6)
>>> +#define PINMUX_GPIO22__FUNC_DBG_MON_B6 (MTK_PIN_NO(22) | 7)
>>> +
>>> +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
>>> +#define PINMUX_GPIO23__FUNC_DBPI_D10 (MTK_PIN_NO(23) | 1)
>>> +#define PINMUX_GPIO23__FUNC_SPI3_MO (MTK_PIN_NO(23) | 2)
>>> +#define PINMUX_GPIO23__FUNC_CONN_MCU_TDI (MTK_PIN_NO(23) | 3)
>>> +#define PINMUX_GPIO23__FUNC_UCTS1 (MTK_PIN_NO(23) | 4)
>>> +#define PINMUX_GPIO23__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5)
>>> +#define PINMUX_GPIO23__FUNC_I2S2_LRCK (MTK_PIN_NO(23) | 6)
>>> +#define PINMUX_GPIO23__FUNC_DBG_MON_B7 (MTK_PIN_NO(23) | 7)
>>> +
>>> +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
>>> +#define PINMUX_GPIO24__FUNC_DBPI_D11 (MTK_PIN_NO(24) | 1)
>>> +#define PINMUX_GPIO24__FUNC_SPI3_CLK (MTK_PIN_NO(24) | 2)
>>> +#define PINMUX_GPIO24__FUNC_SRCLKENAI0 (MTK_PIN_NO(24) | 3)
>>> +#define PINMUX_GPIO24__FUNC_URTS1 (MTK_PIN_NO(24) | 4)
>>> +#define PINMUX_GPIO24__FUNC_IO_JTAG_TCK (MTK_PIN_NO(24) | 5)
>>> +#define PINMUX_GPIO24__FUNC_I2S2_DI (MTK_PIN_NO(24) | 6)
>>> +#define PINMUX_GPIO24__FUNC_DBG_MON_B31 (MTK_PIN_NO(24) | 7)
>>> +
>>> +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
>>> +#define PINMUX_GPIO25__FUNC_DBPI_HSYNC (MTK_PIN_NO(25) | 1)
>>> +#define PINMUX_GPIO25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 2)
>>> +#define PINMUX_GPIO25__FUNC_SCL6 (MTK_PIN_NO(25) | 3)
>>> +#define PINMUX_GPIO25__FUNC_KPCOL2 (MTK_PIN_NO(25) | 4)
>>> +#define PINMUX_GPIO25__FUNC_IO_JTAG_TMS (MTK_PIN_NO(25) | 5)
>>> +#define PINMUX_GPIO25__FUNC_I2S1_MCK (MTK_PIN_NO(25) | 6)
>>> +#define PINMUX_GPIO25__FUNC_DBG_MON_B0 (MTK_PIN_NO(25) | 7)
>>> +
>>> +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
>>> +#define PINMUX_GPIO26__FUNC_DBPI_VSYNC (MTK_PIN_NO(26) | 1)
>>> +#define PINMUX_GPIO26__FUNC_ANT_SEL1 (MTK_PIN_NO(26) | 2)
>>> +#define PINMUX_GPIO26__FUNC_SDA6 (MTK_PIN_NO(26) | 3)
>>> +#define PINMUX_GPIO26__FUNC_KPROW2 (MTK_PIN_NO(26) | 4)
>>> +#define PINMUX_GPIO26__FUNC_IO_JTAG_TDI (MTK_PIN_NO(26) | 5)
>>> +#define PINMUX_GPIO26__FUNC_I2S1_BCK (MTK_PIN_NO(26) | 6)
>>> +#define PINMUX_GPIO26__FUNC_DBG_MON_B1 (MTK_PIN_NO(26) | 7)
>>> +
>>> +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
>>> +#define PINMUX_GPIO27__FUNC_DBPI_DE (MTK_PIN_NO(27) | 1)
>>> +#define PINMUX_GPIO27__FUNC_ANT_SEL2 (MTK_PIN_NO(27) | 2)
>>> +#define PINMUX_GPIO27__FUNC_SCL7 (MTK_PIN_NO(27) | 3)
>>> +#define PINMUX_GPIO27__FUNC_DMIC_CLK (MTK_PIN_NO(27) | 4)
>>> +#define PINMUX_GPIO27__FUNC_IO_JTAG_TDO (MTK_PIN_NO(27) | 5)
>>> +#define PINMUX_GPIO27__FUNC_I2S1_LRCK (MTK_PIN_NO(27) | 6)
>>> +#define PINMUX_GPIO27__FUNC_DBG_MON_B9 (MTK_PIN_NO(27) | 7)
>>> +
>>> +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
>>> +#define PINMUX_GPIO28__FUNC_DBPI_CK (MTK_PIN_NO(28) | 1)
>>> +#define PINMUX_GPIO28__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(28) | 2)
>>> +#define PINMUX_GPIO28__FUNC_SDA7 (MTK_PIN_NO(28) | 3)
>>> +#define PINMUX_GPIO28__FUNC_DMIC_DAT (MTK_PIN_NO(28) | 4)
>>> +#define PINMUX_GPIO28__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(28) | 5)
>>> +#define PINMUX_GPIO28__FUNC_I2S1_DO (MTK_PIN_NO(28) | 6)
>>> +#define PINMUX_GPIO28__FUNC_DBG_MON_B32 (MTK_PIN_NO(28) | 7)
>>> +
>>> +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
>>> +#define PINMUX_GPIO29__FUNC_MSDC1_CLK (MTK_PIN_NO(29) | 1)
>>> +#define PINMUX_GPIO29__FUNC_IO_JTAG_TCK (MTK_PIN_NO(29) | 2)
>>> +#define PINMUX_GPIO29__FUNC_UDI_TCK (MTK_PIN_NO(29) | 3)
>>> +#define PINMUX_GPIO29__FUNC_CONN_DSP_JCK (MTK_PIN_NO(29) | 4)
>>> +#define PINMUX_GPIO29__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(29) | 5)
>>> +#define PINMUX_GPIO29__FUNC_PCM1_CLK (MTK_PIN_NO(29) | 6)
>>> +#define PINMUX_GPIO29__FUNC_DBG_MON_A6 (MTK_PIN_NO(29) | 7)
>>> +
>>> +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
>>> +#define PINMUX_GPIO30__FUNC_MSDC1_DAT3 (MTK_PIN_NO(30) | 1)
>>> +#define PINMUX_GPIO30__FUNC_DAP_MD32_SWD (MTK_PIN_NO(30) | 2)
>>> +#define PINMUX_GPIO30__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 3)
>>> +#define PINMUX_GPIO30__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(30) | 4)
>>> +#define PINMUX_GPIO30__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(30) | 5)
>>> +#define PINMUX_GPIO30__FUNC_PCM1_DI (MTK_PIN_NO(30) | 6)
>>> +#define PINMUX_GPIO30__FUNC_DBG_MON_A7 (MTK_PIN_NO(30) | 7)
>>> +
>>> +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
>>> +#define PINMUX_GPIO31__FUNC_MSDC1_CMD (MTK_PIN_NO(31) | 1)
>>> +#define PINMUX_GPIO31__FUNC_IO_JTAG_TMS (MTK_PIN_NO(31) | 2)
>>> +#define PINMUX_GPIO31__FUNC_UDI_TMS (MTK_PIN_NO(31) | 3)
>>> +#define PINMUX_GPIO31__FUNC_CONN_DSP_JMS (MTK_PIN_NO(31) | 4)
>>> +#define PINMUX_GPIO31__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(31) | 5)
>>> +#define PINMUX_GPIO31__FUNC_PCM1_SYNC (MTK_PIN_NO(31) | 6)
>>> +#define PINMUX_GPIO31__FUNC_DBG_MON_A8 (MTK_PIN_NO(31) | 7)
>>> +
>>> +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
>>> +#define PINMUX_GPIO32__FUNC_MSDC1_DAT0 (MTK_PIN_NO(32) | 1)
>>> +#define PINMUX_GPIO32__FUNC_IO_JTAG_TDI (MTK_PIN_NO(32) | 2)
>>> +#define PINMUX_GPIO32__FUNC_UDI_TDI (MTK_PIN_NO(32) | 3)
>>> +#define PINMUX_GPIO32__FUNC_CONN_DSP_JDI (MTK_PIN_NO(32) | 4)
>>> +#define PINMUX_GPIO32__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(32) | 5)
>>> +#define PINMUX_GPIO32__FUNC_PCM1_DO0 (MTK_PIN_NO(32) | 6)
>>> +#define PINMUX_GPIO32__FUNC_DBG_MON_A9 (MTK_PIN_NO(32) | 7)
>>> +
>>> +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
>>> +#define PINMUX_GPIO33__FUNC_MSDC1_DAT2 (MTK_PIN_NO(33) | 1)
>>> +#define PINMUX_GPIO33__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(33) | 2)
>>> +#define PINMUX_GPIO33__FUNC_UDI_NTRST (MTK_PIN_NO(33) | 3)
>>> +#define PINMUX_GPIO33__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(33) | 4)
>>> +#define PINMUX_GPIO33__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(33) | 5)
>>> +#define PINMUX_GPIO33__FUNC_PCM1_DO2 (MTK_PIN_NO(33) | 6)
>>> +#define PINMUX_GPIO33__FUNC_DBG_MON_A10 (MTK_PIN_NO(33) | 7)
>>> +
>>> +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
>>> +#define PINMUX_GPIO34__FUNC_MSDC1_DAT1 (MTK_PIN_NO(34) | 1)
>>> +#define PINMUX_GPIO34__FUNC_IO_JTAG_TDO (MTK_PIN_NO(34) | 2)
>>> +#define PINMUX_GPIO34__FUNC_UDI_TDO (MTK_PIN_NO(34) | 3)
>>> +#define PINMUX_GPIO34__FUNC_CONN_DSP_JDO (MTK_PIN_NO(34) | 4)
>>> +#define PINMUX_GPIO34__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(34) | 5)
>>> +#define PINMUX_GPIO34__FUNC_PCM1_DO1 (MTK_PIN_NO(34) | 6)
>>> +#define PINMUX_GPIO34__FUNC_DBG_MON_A11 (MTK_PIN_NO(34) | 7)
>>> +
>>> +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
>>> +#define PINMUX_GPIO35__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(35) | 1)
>>> +#define PINMUX_GPIO35__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(35) | 2)
>>> +#define PINMUX_GPIO35__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(35) | 3)
>>> +#define PINMUX_GPIO35__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(35) | 5)
>>> +#define PINMUX_GPIO35__FUNC_CONN_DSP_JMS (MTK_PIN_NO(35) | 6)
>>> +#define PINMUX_GPIO35__FUNC_DBG_MON_A28 (MTK_PIN_NO(35) | 7)
>>> +
>>> +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
>>> +#define PINMUX_GPIO36__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(36) | 1)
>>> +#define PINMUX_GPIO36__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(36) | 2)
>>> +#define PINMUX_GPIO36__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(36) | 3)
>>> +#define PINMUX_GPIO36__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(36) | 4)
>>> +#define PINMUX_GPIO36__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(36) | 5)
>>> +#define PINMUX_GPIO36__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(36) | 6)
>>> +#define PINMUX_GPIO36__FUNC_DBG_MON_A29 (MTK_PIN_NO(36) | 7)
>>> +
>>> +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
>>> +#define PINMUX_GPIO37__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(37) | 1)
>>> +#define PINMUX_GPIO37__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(37) | 2)
>>> +#define PINMUX_GPIO37__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(37) | 3)
>>> +#define PINMUX_GPIO37__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(37) | 5)
>>> +#define PINMUX_GPIO37__FUNC_CONN_DSP_JDO (MTK_PIN_NO(37) | 6)
>>> +#define PINMUX_GPIO37__FUNC_DBG_MON_A30 (MTK_PIN_NO(37) | 7)
>>> +
>>> +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
>>> +#define PINMUX_GPIO38__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(38) | 1)
>>> +#define PINMUX_GPIO38__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(38) | 3)
>>> +#define PINMUX_GPIO38__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(38) | 4)
>>> +#define PINMUX_GPIO38__FUNC_DBG_MON_A20 (MTK_PIN_NO(38) | 7)
>>> +
>>> +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
>>> +#define PINMUX_GPIO39__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(39) | 1)
>>> +#define PINMUX_GPIO39__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(39) | 2)
>>> +#define PINMUX_GPIO39__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(39) | 3)
>>> +#define PINMUX_GPIO39__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(39) | 5)
>>> +#define PINMUX_GPIO39__FUNC_CONN_DSP_JCK (MTK_PIN_NO(39) | 6)
>>> +#define PINMUX_GPIO39__FUNC_DBG_MON_A31 (MTK_PIN_NO(39) | 7)
>>> +
>>> +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
>>> +#define PINMUX_GPIO40__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(40) | 1)
>>> +#define PINMUX_GPIO40__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(40) | 2)
>>> +#define PINMUX_GPIO40__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(40) | 3)
>>> +#define PINMUX_GPIO40__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(40) | 5)
>>> +#define PINMUX_GPIO40__FUNC_CONN_DSP_JDI (MTK_PIN_NO(40) | 6)
>>> +#define PINMUX_GPIO40__FUNC_DBG_MON_A32 (MTK_PIN_NO(40) | 7)
>>> +
>>> +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
>>> +#define PINMUX_GPIO41__FUNC_IDDIG (MTK_PIN_NO(41) | 1)
>>> +#define PINMUX_GPIO41__FUNC_URXD1 (MTK_PIN_NO(41) | 2)
>>> +#define PINMUX_GPIO41__FUNC_UCTS0 (MTK_PIN_NO(41) | 3)
>>> +#define PINMUX_GPIO41__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(41) | 4)
>>> +#define PINMUX_GPIO41__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 5)
>>> +#define PINMUX_GPIO41__FUNC_DMIC_CLK (MTK_PIN_NO(41) | 6)
>>> +
>>> +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
>>> +#define PINMUX_GPIO42__FUNC_USB_DRVVBUS (MTK_PIN_NO(42) | 1)
>>> +#define PINMUX_GPIO42__FUNC_UTXD1 (MTK_PIN_NO(42) | 2)
>>> +#define PINMUX_GPIO42__FUNC_URTS0 (MTK_PIN_NO(42) | 3)
>>> +#define PINMUX_GPIO42__FUNC_SSPM_URXD_AO (MTK_PIN_NO(42) | 4)
>>> +#define PINMUX_GPIO42__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(42) | 5)
>>> +#define PINMUX_GPIO42__FUNC_DMIC_DAT (MTK_PIN_NO(42) | 6)
>>> +
>>> +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
>>> +#define PINMUX_GPIO43__FUNC_DISP_PWM (MTK_PIN_NO(43) | 1)
>>> +
>>> +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
>>> +#define PINMUX_GPIO44__FUNC_DSI_TE (MTK_PIN_NO(44) | 1)
>>> +
>>> +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
>>> +#define PINMUX_GPIO45__FUNC_LCM_RST (MTK_PIN_NO(45) | 1)
>>> +
>>> +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
>>> +#define PINMUX_GPIO46__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(46) | 1)
>>> +#define PINMUX_GPIO46__FUNC_URXD1 (MTK_PIN_NO(46) | 2)
>>> +#define PINMUX_GPIO46__FUNC_UCTS1 (MTK_PIN_NO(46) | 3)
>>> +#define PINMUX_GPIO46__FUNC_CCU_UTXD_AO (MTK_PIN_NO(46) | 4)
>>> +#define PINMUX_GPIO46__FUNC_TP_UCTS1_AO (MTK_PIN_NO(46) | 5)
>>> +#define PINMUX_GPIO46__FUNC_IDDIG (MTK_PIN_NO(46) | 6)
>>> +#define PINMUX_GPIO46__FUNC_I2S5_LRCK (MTK_PIN_NO(46) | 7)
>>> +
>>> +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
>>> +#define PINMUX_GPIO47__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(47) | 1)
>>> +#define PINMUX_GPIO47__FUNC_UTXD1 (MTK_PIN_NO(47) | 2)
>>> +#define PINMUX_GPIO47__FUNC_URTS1 (MTK_PIN_NO(47) | 3)
>>> +#define PINMUX_GPIO47__FUNC_CCU_URXD_AO (MTK_PIN_NO(47) | 4)
>>> +#define PINMUX_GPIO47__FUNC_TP_URTS1_AO (MTK_PIN_NO(47) | 5)
>>> +#define PINMUX_GPIO47__FUNC_USB_DRVVBUS (MTK_PIN_NO(47) | 6)
>>> +#define PINMUX_GPIO47__FUNC_I2S5_DO (MTK_PIN_NO(47) | 7)
>>> +
>>> +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
>>> +#define PINMUX_GPIO48__FUNC_SCL5 (MTK_PIN_NO(48) | 1)
>>> +
>>> +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
>>> +#define PINMUX_GPIO49__FUNC_SDA5 (MTK_PIN_NO(49) | 1)
>>> +
>>> +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
>>> +#define PINMUX_GPIO50__FUNC_SCL3 (MTK_PIN_NO(50) | 1)
>>> +
>>> +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
>>> +#define PINMUX_GPIO51__FUNC_SDA3 (MTK_PIN_NO(51) | 1)
>>> +
>>> +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
>>> +#define PINMUX_GPIO52__FUNC_BPI_ANT2 (MTK_PIN_NO(52) | 1)
>>> +
>>> +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
>>> +#define PINMUX_GPIO53__FUNC_BPI_ANT0 (MTK_PIN_NO(53) | 1)
>>> +
>>> +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
>>> +#define PINMUX_GPIO54__FUNC_BPI_OLAT1 (MTK_PIN_NO(54) | 1)
>>> +
>>> +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
>>> +#define PINMUX_GPIO55__FUNC_BPI_BUS8 (MTK_PIN_NO(55) | 1)
>>> +
>>> +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
>>> +#define PINMUX_GPIO56__FUNC_BPI_BUS9 (MTK_PIN_NO(56) | 1)
>>> +#define PINMUX_GPIO56__FUNC_SCL_6306 (MTK_PIN_NO(56) | 2)
>>> +
>>> +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
>>> +#define PINMUX_GPIO57__FUNC_BPI_BUS10 (MTK_PIN_NO(57) | 1)
>>> +#define PINMUX_GPIO57__FUNC_SDA_6306 (MTK_PIN_NO(57) | 2)
>>> +
>>> +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
>>> +#define PINMUX_GPIO58__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(58) | 1)
>>> +#define PINMUX_GPIO58__FUNC_SPM_BSI_D2 (MTK_PIN_NO(58) | 2)
>>> +#define PINMUX_GPIO58__FUNC_PWM_B (MTK_PIN_NO(58) | 3)
>>> +
>>> +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
>>> +#define PINMUX_GPIO59__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(59) | 1)
>>> +#define PINMUX_GPIO59__FUNC_SPM_BSI_D1 (MTK_PIN_NO(59) | 2)
>>> +
>>> +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
>>> +#define PINMUX_GPIO60__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(60) | 1)
>>> +#define PINMUX_GPIO60__FUNC_SPM_BSI_D0 (MTK_PIN_NO(60) | 2)
>>> +
>>> +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
>>> +#define PINMUX_GPIO61__FUNC_MIPI1_SDATA (MTK_PIN_NO(61) | 1)
>>> +
>>> +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
>>> +#define PINMUX_GPIO62__FUNC_MIPI1_SCLK (MTK_PIN_NO(62) | 1)
>>> +
>>> +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
>>> +#define PINMUX_GPIO63__FUNC_MIPI0_SDATA (MTK_PIN_NO(63) | 1)
>>> +
>>> +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
>>> +#define PINMUX_GPIO64__FUNC_MIPI0_SCLK (MTK_PIN_NO(64) | 1)
>>> +
>>> +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
>>> +#define PINMUX_GPIO65__FUNC_MIPI3_SDATA (MTK_PIN_NO(65) | 1)
>>> +#define PINMUX_GPIO65__FUNC_BPI_OLAT2 (MTK_PIN_NO(65) | 2)
>>> +
>>> +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
>>> +#define PINMUX_GPIO66__FUNC_MIPI3_SCLK (MTK_PIN_NO(66) | 1)
>>> +#define PINMUX_GPIO66__FUNC_BPI_OLAT3 (MTK_PIN_NO(66) | 2)
>>> +
>>> +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
>>> +#define PINMUX_GPIO67__FUNC_MIPI2_SDATA (MTK_PIN_NO(67) | 1)
>>> +
>>> +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
>>> +#define PINMUX_GPIO68__FUNC_MIPI2_SCLK (MTK_PIN_NO(68) | 1)
>>> +
>>> +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
>>> +#define PINMUX_GPIO69__FUNC_BPI_BUS7 (MTK_PIN_NO(69) | 1)
>>> +
>>> +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
>>> +#define PINMUX_GPIO70__FUNC_BPI_BUS6 (MTK_PIN_NO(70) | 1)
>>> +
>>> +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
>>> +#define PINMUX_GPIO71__FUNC_BPI_BUS5 (MTK_PIN_NO(71) | 1)
>>> +
>>> +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
>>> +#define PINMUX_GPIO72__FUNC_BPI_BUS4 (MTK_PIN_NO(72) | 1)
>>> +
>>> +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
>>> +#define PINMUX_GPIO73__FUNC_BPI_BUS3 (MTK_PIN_NO(73) | 1)
>>> +
>>> +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
>>> +#define PINMUX_GPIO74__FUNC_BPI_BUS2 (MTK_PIN_NO(74) | 1)
>>> +
>>> +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
>>> +#define PINMUX_GPIO75__FUNC_BPI_BUS1 (MTK_PIN_NO(75) | 1)
>>> +
>>> +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
>>> +#define PINMUX_GPIO76__FUNC_BPI_BUS0 (MTK_PIN_NO(76) | 1)
>>> +
>>> +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
>>> +#define PINMUX_GPIO77__FUNC_BPI_ANT1 (MTK_PIN_NO(77) | 1)
>>> +
>>> +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
>>> +#define PINMUX_GPIO78__FUNC_BPI_OLAT0 (MTK_PIN_NO(78) | 1)
>>> +
>>> +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
>>> +#define PINMUX_GPIO79__FUNC_BPI_PA_VM1 (MTK_PIN_NO(79) | 1)
>>> +#define PINMUX_GPIO79__FUNC_MIPI4_SDATA (MTK_PIN_NO(79) | 2)
>>> +
>>> +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
>>> +#define PINMUX_GPIO80__FUNC_BPI_PA_VM0 (MTK_PIN_NO(80) | 1)
>>> +#define PINMUX_GPIO80__FUNC_MIPI4_SCLK (MTK_PIN_NO(80) | 2)
>>> +
>>> +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
>>> +#define PINMUX_GPIO81__FUNC_SDA1 (MTK_PIN_NO(81) | 1)
>>> +
>>> +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
>>> +#define PINMUX_GPIO82__FUNC_SDA0 (MTK_PIN_NO(82) | 1)
>>> +
>>> +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
>>> +#define PINMUX_GPIO83__FUNC_SCL0 (MTK_PIN_NO(83) | 1)
>>> +
>>> +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
>>> +#define PINMUX_GPIO84__FUNC_SCL1 (MTK_PIN_NO(84) | 1)
>>> +
>>> +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
>>> +#define PINMUX_GPIO85__FUNC_SPI0_MI (MTK_PIN_NO(85) | 1)
>>> +#define PINMUX_GPIO85__FUNC_SCP_SPI0_MI (MTK_PIN_NO(85) | 2)
>>> +#define PINMUX_GPIO85__FUNC_CLKM3 (MTK_PIN_NO(85) | 3)
>>> +#define PINMUX_GPIO85__FUNC_I2S1_BCK (MTK_PIN_NO(85) | 4)
>>> +#define PINMUX_GPIO85__FUNC_MFG_DFD_JTAG_TDO (MTK_PIN_NO(85) | 5)
>>> +#define PINMUX_GPIO85__FUNC_DFD_TDO (MTK_PIN_NO(85) | 6)
>>> +#define PINMUX_GPIO85__FUNC_JTDO_SEL1 (MTK_PIN_NO(85) | 7)
>>> +
>>> +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
>>> +#define PINMUX_GPIO86__FUNC_SPI0_CSB (MTK_PIN_NO(86) | 1)
>>> +#define PINMUX_GPIO86__FUNC_SCP_SPI0_CS (MTK_PIN_NO(86) | 2)
>>> +#define PINMUX_GPIO86__FUNC_CLKM0 (MTK_PIN_NO(86) | 3)
>>> +#define PINMUX_GPIO86__FUNC_I2S1_LRCK (MTK_PIN_NO(86) | 4)
>>> +#define PINMUX_GPIO86__FUNC_MFG_DFD_JTAG_TMS (MTK_PIN_NO(86) | 5)
>>> +#define PINMUX_GPIO86__FUNC_DFD_TMS (MTK_PIN_NO(86) | 6)
>>> +#define PINMUX_GPIO86__FUNC_JTMS_SEL1 (MTK_PIN_NO(86) | 7)
>>> +
>>> +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
>>> +#define PINMUX_GPIO87__FUNC_SPI0_MO (MTK_PIN_NO(87) | 1)
>>> +#define PINMUX_GPIO87__FUNC_SCP_SPI0_MO (MTK_PIN_NO(87) | 2)
>>> +#define PINMUX_GPIO87__FUNC_SDA1 (MTK_PIN_NO(87) | 3)
>>> +#define PINMUX_GPIO87__FUNC_I2S1_DO (MTK_PIN_NO(87) | 4)
>>> +#define PINMUX_GPIO87__FUNC_MFG_DFD_JTAG_TDI (MTK_PIN_NO(87) | 5)
>>> +#define PINMUX_GPIO87__FUNC_DFD_TDI (MTK_PIN_NO(87) | 6)
>>> +#define PINMUX_GPIO87__FUNC_JTDI_SEL1 (MTK_PIN_NO(87) | 7)
>>> +
>>> +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
>>> +#define PINMUX_GPIO88__FUNC_SPI0_CLK (MTK_PIN_NO(88) | 1)
>>> +#define PINMUX_GPIO88__FUNC_SCP_SPI0_CK (MTK_PIN_NO(88) | 2)
>>> +#define PINMUX_GPIO88__FUNC_SCL1 (MTK_PIN_NO(88) | 3)
>>> +#define PINMUX_GPIO88__FUNC_I2S1_MCK (MTK_PIN_NO(88) | 4)
>>> +#define PINMUX_GPIO88__FUNC_MFG_DFD_JTAG_TCK (MTK_PIN_NO(88) | 5)
>>> +#define PINMUX_GPIO88__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 6)
>>> +#define PINMUX_GPIO88__FUNC_JTCK_SEL1 (MTK_PIN_NO(88) | 7)
>>> +
>>> +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
>>> +#define PINMUX_GPIO89__FUNC_SRCLKENAI0 (MTK_PIN_NO(89) | 1)
>>> +#define PINMUX_GPIO89__FUNC_PWM_C (MTK_PIN_NO(89) | 2)
>>> +#define PINMUX_GPIO89__FUNC_I2S5_BCK (MTK_PIN_NO(89) | 3)
>>> +#define PINMUX_GPIO89__FUNC_ANT_SEL6 (MTK_PIN_NO(89) | 4)
>>> +#define PINMUX_GPIO89__FUNC_SDA8 (MTK_PIN_NO(89) | 5)
>>> +#define PINMUX_GPIO89__FUNC_CMVREF0 (MTK_PIN_NO(89) | 6)
>>> +#define PINMUX_GPIO89__FUNC_DBG_MON_A21 (MTK_PIN_NO(89) | 7)
>>> +
>>> +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
>>> +#define PINMUX_GPIO90__FUNC_PWM_A (MTK_PIN_NO(90) | 1)
>>> +#define PINMUX_GPIO90__FUNC_CMMCLK2 (MTK_PIN_NO(90) | 2)
>>> +#define PINMUX_GPIO90__FUNC_I2S5_LRCK (MTK_PIN_NO(90) | 3)
>>> +#define PINMUX_GPIO90__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(90) | 4)
>>> +#define PINMUX_GPIO90__FUNC_SCL8 (MTK_PIN_NO(90) | 5)
>>> +#define PINMUX_GPIO90__FUNC_PTA_RXD (MTK_PIN_NO(90) | 6)
>>> +#define PINMUX_GPIO90__FUNC_DBG_MON_A22 (MTK_PIN_NO(90) | 7)
>>> +
>>> +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
>>> +#define PINMUX_GPIO91__FUNC_KPROW1 (MTK_PIN_NO(91) | 1)
>>> +#define PINMUX_GPIO91__FUNC_PWM_B (MTK_PIN_NO(91) | 2)
>>> +#define PINMUX_GPIO91__FUNC_I2S5_DO (MTK_PIN_NO(91) | 3)
>>> +#define PINMUX_GPIO91__FUNC_ANT_SEL7 (MTK_PIN_NO(91) | 4)
>>> +#define PINMUX_GPIO91__FUNC_CMMCLK3 (MTK_PIN_NO(91) | 5)
>>> +#define PINMUX_GPIO91__FUNC_PTA_TXD (MTK_PIN_NO(91) | 6)
>>> +
>>> +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
>>> +#define PINMUX_GPIO92__FUNC_KPROW0 (MTK_PIN_NO(92) | 1)
>>> +
>>> +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
>>> +#define PINMUX_GPIO93__FUNC_KPCOL0 (MTK_PIN_NO(93) | 1)
>>> +#define PINMUX_GPIO93__FUNC_DBG_MON_B27 (MTK_PIN_NO(93) | 7)
>>> +
>>> +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
>>> +#define PINMUX_GPIO94__FUNC_KPCOL1 (MTK_PIN_NO(94) | 1)
>>> +#define PINMUX_GPIO94__FUNC_I2S2_DI2 (MTK_PIN_NO(94) | 2)
>>> +#define PINMUX_GPIO94__FUNC_I2S5_MCK (MTK_PIN_NO(94) | 3)
>>> +#define PINMUX_GPIO94__FUNC_CMMCLK2 (MTK_PIN_NO(94) | 4)
>>> +#define PINMUX_GPIO94__FUNC_SCP_SPI2_MI (MTK_PIN_NO(94) | 5)
>>> +#define PINMUX_GPIO94__FUNC_SRCLKENAI1 (MTK_PIN_NO(94) | 6)
>>> +#define PINMUX_GPIO94__FUNC_SPI2_MI (MTK_PIN_NO(94) | 7)
>>> +
>>> +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
>>> +#define PINMUX_GPIO95__FUNC_URXD0 (MTK_PIN_NO(95) | 1)
>>> +#define PINMUX_GPIO95__FUNC_UTXD0 (MTK_PIN_NO(95) | 2)
>>> +#define PINMUX_GPIO95__FUNC_MD_URXD0 (MTK_PIN_NO(95) | 3)
>>> +#define PINMUX_GPIO95__FUNC_MD_URXD1 (MTK_PIN_NO(95) | 4)
>>> +#define PINMUX_GPIO95__FUNC_SSPM_URXD_AO (MTK_PIN_NO(95) | 5)
>>> +#define PINMUX_GPIO95__FUNC_CCU_URXD_AO (MTK_PIN_NO(95) | 6)
>>> +
>>> +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
>>> +#define PINMUX_GPIO96__FUNC_UTXD0 (MTK_PIN_NO(96) | 1)
>>> +#define PINMUX_GPIO96__FUNC_URXD0 (MTK_PIN_NO(96) | 2)
>>> +#define PINMUX_GPIO96__FUNC_MD_UTXD0 (MTK_PIN_NO(96) | 3)
>>> +#define PINMUX_GPIO96__FUNC_MD_UTXD1 (MTK_PIN_NO(96) | 4)
>>> +#define PINMUX_GPIO96__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(96) | 5)
>>> +#define PINMUX_GPIO96__FUNC_CCU_UTXD_AO (MTK_PIN_NO(96) | 6)
>>> +#define PINMUX_GPIO96__FUNC_DBG_MON_B2 (MTK_PIN_NO(96) | 7)
>>> +
>>> +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
>>> +#define PINMUX_GPIO97__FUNC_UCTS0 (MTK_PIN_NO(97) | 1)
>>> +#define PINMUX_GPIO97__FUNC_I2S2_MCK (MTK_PIN_NO(97) | 2)
>>> +#define PINMUX_GPIO97__FUNC_IDDIG (MTK_PIN_NO(97) | 3)
>>> +#define PINMUX_GPIO97__FUNC_CONN_MCU_TDO (MTK_PIN_NO(97) | 4)
>>> +#define PINMUX_GPIO97__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(97) | 5)
>>> +#define PINMUX_GPIO97__FUNC_IO_JTAG_TDO (MTK_PIN_NO(97) | 6)
>>> +#define PINMUX_GPIO97__FUNC_DBG_MON_B3 (MTK_PIN_NO(97) | 7)
>>> +
>>> +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
>>> +#define PINMUX_GPIO98__FUNC_URTS0 (MTK_PIN_NO(98) | 1)
>>> +#define PINMUX_GPIO98__FUNC_I2S2_BCK (MTK_PIN_NO(98) | 2)
>>> +#define PINMUX_GPIO98__FUNC_USB_DRVVBUS (MTK_PIN_NO(98) | 3)
>>> +#define PINMUX_GPIO98__FUNC_CONN_MCU_TMS (MTK_PIN_NO(98) | 4)
>>> +#define PINMUX_GPIO98__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(98) | 5)
>>> +#define PINMUX_GPIO98__FUNC_IO_JTAG_TMS (MTK_PIN_NO(98) | 6)
>>> +#define PINMUX_GPIO98__FUNC_DBG_MON_B4 (MTK_PIN_NO(98) | 7)
>>> +
>>> +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
>>> +#define PINMUX_GPIO99__FUNC_CMMCLK0 (MTK_PIN_NO(99) | 1)
>>> +#define PINMUX_GPIO99__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(99) | 4)
>>> +#define PINMUX_GPIO99__FUNC_DBG_MON_B28 (MTK_PIN_NO(99) | 7)
>>> +
>>> +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
>>> +#define PINMUX_GPIO100__FUNC_CMMCLK1 (MTK_PIN_NO(100) | 1)
>>> +#define PINMUX_GPIO100__FUNC_PWM_C (MTK_PIN_NO(100) | 2)
>>> +#define PINMUX_GPIO100__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(100) | 3)
>>> +#define PINMUX_GPIO100__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(100) | 4)
>>> +#define PINMUX_GPIO100__FUNC_DBG_MON_B29 (MTK_PIN_NO(100) | 7)
>>> +
>>> +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
>>> +#define PINMUX_GPIO101__FUNC_CLKM2 (MTK_PIN_NO(101) | 1)
>>> +#define PINMUX_GPIO101__FUNC_I2S2_LRCK (MTK_PIN_NO(101) | 2)
>>> +#define PINMUX_GPIO101__FUNC_CMVREF1 (MTK_PIN_NO(101) | 3)
>>> +#define PINMUX_GPIO101__FUNC_CONN_MCU_TCK (MTK_PIN_NO(101) | 4)
>>> +#define PINMUX_GPIO101__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(101) | 5)
>>> +#define PINMUX_GPIO101__FUNC_IO_JTAG_TCK (MTK_PIN_NO(101) | 6)
>>> +
>>> +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
>>> +#define PINMUX_GPIO102__FUNC_CLKM1 (MTK_PIN_NO(102) | 1)
>>> +#define PINMUX_GPIO102__FUNC_I2S2_DI (MTK_PIN_NO(102) | 2)
>>> +#define PINMUX_GPIO102__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(102) | 3)
>>> +#define PINMUX_GPIO102__FUNC_CONN_MCU_TDI (MTK_PIN_NO(102) | 4)
>>> +#define PINMUX_GPIO102__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(102) | 5)
>>> +#define PINMUX_GPIO102__FUNC_IO_JTAG_TDI (MTK_PIN_NO(102) | 6)
>>> +#define PINMUX_GPIO102__FUNC_DBG_MON_B8 (MTK_PIN_NO(102) | 7)
>>> +
>>> +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
>>> +#define PINMUX_GPIO103__FUNC_SCL2 (MTK_PIN_NO(103) | 1)
>>> +
>>> +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
>>> +#define PINMUX_GPIO104__FUNC_SDA2 (MTK_PIN_NO(104) | 1)
>>> +
>>> +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
>>> +#define PINMUX_GPIO105__FUNC_SCL4 (MTK_PIN_NO(105) | 1)
>>> +
>>> +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
>>> +#define PINMUX_GPIO106__FUNC_SDA4 (MTK_PIN_NO(106) | 1)
>>> +
>>> +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
>>> +#define PINMUX_GPIO107__FUNC_DMIC_CLK (MTK_PIN_NO(107) | 1)
>>> +#define PINMUX_GPIO107__FUNC_ANT_SEL0 (MTK_PIN_NO(107) | 2)
>>> +#define PINMUX_GPIO107__FUNC_CLKM0 (MTK_PIN_NO(107) | 3)
>>> +#define PINMUX_GPIO107__FUNC_SDA7 (MTK_PIN_NO(107) | 4)
>>> +#define PINMUX_GPIO107__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(107) | 5)
>>> +#define PINMUX_GPIO107__FUNC_PWM_A (MTK_PIN_NO(107) | 6)
>>> +#define PINMUX_GPIO107__FUNC_DBG_MON_B12 (MTK_PIN_NO(107) | 7)
>>> +
>>> +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
>>> +#define PINMUX_GPIO108__FUNC_CMMCLK2 (MTK_PIN_NO(108) | 1)
>>> +#define PINMUX_GPIO108__FUNC_ANT_SEL1 (MTK_PIN_NO(108) | 2)
>>> +#define PINMUX_GPIO108__FUNC_CLKM1 (MTK_PIN_NO(108) | 3)
>>> +#define PINMUX_GPIO108__FUNC_SCL8 (MTK_PIN_NO(108) | 4)
>>> +#define PINMUX_GPIO108__FUNC_DAP_MD32_SWD (MTK_PIN_NO(108) | 5)
>>> +#define PINMUX_GPIO108__FUNC_PWM_B (MTK_PIN_NO(108) | 6)
>>> +#define PINMUX_GPIO108__FUNC_DBG_MON_B13 (MTK_PIN_NO(108) | 7)
>>> +
>>> +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
>>> +#define PINMUX_GPIO109__FUNC_DMIC_DAT (MTK_PIN_NO(109) | 1)
>>> +#define PINMUX_GPIO109__FUNC_ANT_SEL2 (MTK_PIN_NO(109) | 2)
>>> +#define PINMUX_GPIO109__FUNC_CLKM2 (MTK_PIN_NO(109) | 3)
>>> +#define PINMUX_GPIO109__FUNC_SDA8 (MTK_PIN_NO(109) | 4)
>>> +#define PINMUX_GPIO109__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(109) | 5)
>>> +#define PINMUX_GPIO109__FUNC_PWM_C (MTK_PIN_NO(109) | 6)
>>> +#define PINMUX_GPIO109__FUNC_DBG_MON_B14 (MTK_PIN_NO(109) | 7)
>>> +
>>> +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
>>> +#define PINMUX_GPIO110__FUNC_SCL7 (MTK_PIN_NO(110) | 1)
>>> +#define PINMUX_GPIO110__FUNC_ANT_SEL0 (MTK_PIN_NO(110) | 2)
>>> +#define PINMUX_GPIO110__FUNC_TP_URXD1_AO (MTK_PIN_NO(110) | 3)
>>> +#define PINMUX_GPIO110__FUNC_USB_DRVVBUS (MTK_PIN_NO(110) | 4)
>>> +#define PINMUX_GPIO110__FUNC_SRCLKENAI1 (MTK_PIN_NO(110) | 5)
>>> +#define PINMUX_GPIO110__FUNC_KPCOL2 (MTK_PIN_NO(110) | 6)
>>> +#define PINMUX_GPIO110__FUNC_URXD1 (MTK_PIN_NO(110) | 7)
>>> +
>>> +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
>>> +#define PINMUX_GPIO111__FUNC_CMMCLK3 (MTK_PIN_NO(111) | 1)
>>> +#define PINMUX_GPIO111__FUNC_ANT_SEL1 (MTK_PIN_NO(111) | 2)
>>> +#define PINMUX_GPIO111__FUNC_SRCLKENAI0 (MTK_PIN_NO(111) | 3)
>>> +#define PINMUX_GPIO111__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(111) | 4)
>>> +#define PINMUX_GPIO111__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(111) | 5)
>>> +#define PINMUX_GPIO111__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(111) | 7)
>>> +
>>> +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
>>> +#define PINMUX_GPIO112__FUNC_SDA7 (MTK_PIN_NO(112) | 1)
>>> +#define PINMUX_GPIO112__FUNC_ANT_SEL2 (MTK_PIN_NO(112) | 2)
>>> +#define PINMUX_GPIO112__FUNC_TP_UTXD1_AO (MTK_PIN_NO(112) | 3)
>>> +#define PINMUX_GPIO112__FUNC_IDDIG (MTK_PIN_NO(112) | 4)
>>> +#define PINMUX_GPIO112__FUNC_AGPS_SYNC (MTK_PIN_NO(112) | 5)
>>> +#define PINMUX_GPIO112__FUNC_KPROW2 (MTK_PIN_NO(112) | 6)
>>> +#define PINMUX_GPIO112__FUNC_UTXD1 (MTK_PIN_NO(112) | 7)
>>> +
>>> +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
>>> +#define PINMUX_GPIO113__FUNC_CONN_TOP_CLK (MTK_PIN_NO(113) | 1)
>>> +#define PINMUX_GPIO113__FUNC_SCL6 (MTK_PIN_NO(113) | 3)
>>> +#define PINMUX_GPIO113__FUNC_AUXIF_CLK0 (MTK_PIN_NO(113) | 4)
>>> +#define PINMUX_GPIO113__FUNC_TP_UCTS1_AO (MTK_PIN_NO(113) | 6)
>>> +
>>> +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
>>> +#define PINMUX_GPIO114__FUNC_CONN_TOP_DATA (MTK_PIN_NO(114) | 1)
>>> +#define PINMUX_GPIO114__FUNC_SDA6 (MTK_PIN_NO(114) | 3)
>>> +#define PINMUX_GPIO114__FUNC_AUXIF_ST0 (MTK_PIN_NO(114) | 4)
>>> +#define PINMUX_GPIO114__FUNC_TP_URTS1_AO (MTK_PIN_NO(114) | 6)
>>> +
>>> +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
>>> +#define PINMUX_GPIO115__FUNC_CONN_BT_CLK (MTK_PIN_NO(115) | 1)
>>> +#define PINMUX_GPIO115__FUNC_UTXD1 (MTK_PIN_NO(115) | 2)
>>> +#define PINMUX_GPIO115__FUNC_PTA_TXD (MTK_PIN_NO(115) | 3)
>>> +#define PINMUX_GPIO115__FUNC_AUXIF_CLK1 (MTK_PIN_NO(115) | 4)
>>> +#define PINMUX_GPIO115__FUNC_DAP_MD32_SWD (MTK_PIN_NO(115) | 5)
>>> +#define PINMUX_GPIO115__FUNC_TP_UTXD1_AO (MTK_PIN_NO(115) | 6)
>>> +
>>> +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
>>> +#define PINMUX_GPIO116__FUNC_CONN_BT_DATA (MTK_PIN_NO(116) | 1)
>>> +#define PINMUX_GPIO116__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(116) | 2)
>>> +#define PINMUX_GPIO116__FUNC_AUXIF_ST1 (MTK_PIN_NO(116) | 4)
>>> +#define PINMUX_GPIO116__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(116) | 5)
>>> +#define PINMUX_GPIO116__FUNC_TP_URXD2_AO (MTK_PIN_NO(116) | 6)
>>> +#define PINMUX_GPIO116__FUNC_DBG_MON_A0 (MTK_PIN_NO(116) | 7)
>>> +
>>> +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
>>> +#define PINMUX_GPIO117__FUNC_CONN_WF_HB0 (MTK_PIN_NO(117) | 1)
>>> +#define PINMUX_GPIO117__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(117) | 2)
>>> +#define PINMUX_GPIO117__FUNC_TP_UTXD2_AO (MTK_PIN_NO(117) | 6)
>>> +#define PINMUX_GPIO117__FUNC_DBG_MON_A4 (MTK_PIN_NO(117) | 7)
>>> +
>>> +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
>>> +#define PINMUX_GPIO118__FUNC_CONN_WF_HB1 (MTK_PIN_NO(118) | 1)
>>> +#define PINMUX_GPIO118__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(118) | 2)
>>> +#define PINMUX_GPIO118__FUNC_SSPM_URXD_AO (MTK_PIN_NO(118) | 5)
>>> +#define PINMUX_GPIO118__FUNC_TP_UCTS2_AO (MTK_PIN_NO(118) | 6)
>>> +#define PINMUX_GPIO118__FUNC_DBG_MON_A5 (MTK_PIN_NO(118) | 7)
>>> +
>>> +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
>>> +#define PINMUX_GPIO119__FUNC_CONN_WF_HB2 (MTK_PIN_NO(119) | 1)
>>> +#define PINMUX_GPIO119__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(119) | 2)
>>> +#define PINMUX_GPIO119__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(119) | 5)
>>> +#define PINMUX_GPIO119__FUNC_TP_URTS2_AO (MTK_PIN_NO(119) | 6)
>>> +
>>> +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
>>> +#define PINMUX_GPIO120__FUNC_CONN_WB_PTA (MTK_PIN_NO(120) | 1)
>>> +#define PINMUX_GPIO120__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(120) | 2)
>>> +#define PINMUX_GPIO120__FUNC_CCU_URXD_AO (MTK_PIN_NO(120) | 5)
>>> +
>>> +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
>>> +#define PINMUX_GPIO121__FUNC_CONN_HRST_B (MTK_PIN_NO(121) | 1)
>>> +#define PINMUX_GPIO121__FUNC_URXD1 (MTK_PIN_NO(121) | 2)
>>> +#define PINMUX_GPIO121__FUNC_PTA_RXD (MTK_PIN_NO(121) | 3)
>>> +#define PINMUX_GPIO121__FUNC_CCU_UTXD_AO (MTK_PIN_NO(121) | 5)
>>> +#define PINMUX_GPIO121__FUNC_TP_URXD1_AO (MTK_PIN_NO(121) | 6)
>>> +
>>> +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
>>> +#define PINMUX_GPIO122__FUNC_MSDC0_CMD (MTK_PIN_NO(122) | 1)
>>> +#define PINMUX_GPIO122__FUNC_SSPM_URXD2_AO (MTK_PIN_NO(122) | 2)
>>> +#define PINMUX_GPIO122__FUNC_ANT_SEL1 (MTK_PIN_NO(122) | 3)
>>> +#define PINMUX_GPIO122__FUNC_DBG_MON_A12 (MTK_PIN_NO(122) | 7)
>>> +
>>> +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
>>> +#define PINMUX_GPIO123__FUNC_MSDC0_DAT0 (MTK_PIN_NO(123) | 1)
>>> +#define PINMUX_GPIO123__FUNC_ANT_SEL0 (MTK_PIN_NO(123) | 3)
>>> +#define PINMUX_GPIO123__FUNC_DBG_MON_A13 (MTK_PIN_NO(123) | 7)
>>> +
>>> +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
>>> +#define PINMUX_GPIO124__FUNC_MSDC0_CLK (MTK_PIN_NO(124) | 1)
>>> +#define PINMUX_GPIO124__FUNC_DBG_MON_A14 (MTK_PIN_NO(124) | 7)
>>> +
>>> +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
>>> +#define PINMUX_GPIO125__FUNC_MSDC0_DAT2 (MTK_PIN_NO(125) | 1)
>>> +#define PINMUX_GPIO125__FUNC_MRG_CLK (MTK_PIN_NO(125) | 3)
>>> +#define PINMUX_GPIO125__FUNC_DBG_MON_A15 (MTK_PIN_NO(125) | 7)
>>> +
>>> +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
>>> +#define PINMUX_GPIO126__FUNC_MSDC0_DAT4 (MTK_PIN_NO(126) | 1)
>>> +#define PINMUX_GPIO126__FUNC_ANT_SEL5 (MTK_PIN_NO(126) | 3)
>>> +#define PINMUX_GPIO126__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(126) | 6)
>>> +#define PINMUX_GPIO126__FUNC_DBG_MON_A16 (MTK_PIN_NO(126) | 7)
>>> +
>>> +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
>>> +#define PINMUX_GPIO127__FUNC_MSDC0_DAT6 (MTK_PIN_NO(127) | 1)
>>> +#define PINMUX_GPIO127__FUNC_ANT_SEL4 (MTK_PIN_NO(127) | 3)
>>> +#define PINMUX_GPIO127__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(127) | 6)
>>> +#define PINMUX_GPIO127__FUNC_DBG_MON_A17 (MTK_PIN_NO(127) | 7)
>>> +
>>> +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
>>> +#define PINMUX_GPIO128__FUNC_MSDC0_DAT1 (MTK_PIN_NO(128) | 1)
>>> +#define PINMUX_GPIO128__FUNC_ANT_SEL2 (MTK_PIN_NO(128) | 3)
>>> +#define PINMUX_GPIO128__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(128) | 6)
>>> +#define PINMUX_GPIO128__FUNC_DBG_MON_A18 (MTK_PIN_NO(128) | 7)
>>> +
>>> +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
>>> +#define PINMUX_GPIO129__FUNC_MSDC0_DAT5 (MTK_PIN_NO(129) | 1)
>>> +#define PINMUX_GPIO129__FUNC_ANT_SEL3 (MTK_PIN_NO(129) | 3)
>>> +#define PINMUX_GPIO129__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(129) | 6)
>>> +#define PINMUX_GPIO129__FUNC_DBG_MON_A23 (MTK_PIN_NO(129) | 7)
>>> +
>>> +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
>>> +#define PINMUX_GPIO130__FUNC_MSDC0_DAT7 (MTK_PIN_NO(130) | 1)
>>> +#define PINMUX_GPIO130__FUNC_MRG_DO (MTK_PIN_NO(130) | 3)
>>> +#define PINMUX_GPIO130__FUNC_DBG_MON_A24 (MTK_PIN_NO(130) | 7)
>>> +
>>> +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
>>> +#define PINMUX_GPIO131__FUNC_MSDC0_DSL (MTK_PIN_NO(131) | 1)
>>> +#define PINMUX_GPIO131__FUNC_MRG_SYNC (MTK_PIN_NO(131) | 3)
>>> +#define PINMUX_GPIO131__FUNC_DBG_MON_A25 (MTK_PIN_NO(131) | 7)
>>> +
>>> +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
>>> +#define PINMUX_GPIO132__FUNC_MSDC0_DAT3 (MTK_PIN_NO(132) | 1)
>>> +#define PINMUX_GPIO132__FUNC_MRG_DI (MTK_PIN_NO(132) | 3)
>>> +#define PINMUX_GPIO132__FUNC_DBG_MON_A26 (MTK_PIN_NO(132) | 7)
>>> +
>>> +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
>>> +#define PINMUX_GPIO133__FUNC_MSDC0_RSTB (MTK_PIN_NO(133) | 1)
>>> +#define PINMUX_GPIO133__FUNC_AGPS_SYNC (MTK_PIN_NO(133) | 3)
>>> +#define PINMUX_GPIO133__FUNC_DBG_MON_A27 (MTK_PIN_NO(133) | 7)
>>> +
>>> +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
>>> +#define PINMUX_GPIO134__FUNC_RTC32K_CK (MTK_PIN_NO(134) | 1)
>>> +
>>> +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
>>> +#define PINMUX_GPIO135__FUNC_WATCHDOG (MTK_PIN_NO(135) | 1)
>>> +
>>> +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
>>> +#define PINMUX_GPIO136__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(136) | 1)
>>> +#define PINMUX_GPIO136__FUNC_AUD_CLK_MISO (MTK_PIN_NO(136) | 2)
>>> +#define PINMUX_GPIO136__FUNC_I2S1_MCK (MTK_PIN_NO(136) | 3)
>>> +#define PINMUX_GPIO136__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(136) | 6)
>>> +
>>> +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
>>> +#define PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(137) | 1)
>>> +#define PINMUX_GPIO137__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(137) | 2)
>>> +#define PINMUX_GPIO137__FUNC_I2S1_BCK (MTK_PIN_NO(137) | 3)
>>> +
>>> +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
>>> +#define PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(138) | 1)
>>> +#define PINMUX_GPIO138__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(138) | 2)
>>> +#define PINMUX_GPIO138__FUNC_I2S1_LRCK (MTK_PIN_NO(138) | 3)
>>> +#define PINMUX_GPIO138__FUNC_DBG_MON_B24 (MTK_PIN_NO(138) | 7)
>>> +
>>> +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
>>> +#define PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(139) | 1)
>>> +#define PINMUX_GPIO139__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(139) | 2)
>>> +#define PINMUX_GPIO139__FUNC_I2S1_DO (MTK_PIN_NO(139) | 3)
>>> +#define PINMUX_GPIO139__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(139) | 6)
>>> +
>>> +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
>>> +#define PINMUX_GPIO140__FUNC_AUD_CLK_MISO (MTK_PIN_NO(140) | 1)
>>> +#define PINMUX_GPIO140__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(140) | 2)
>>> +#define PINMUX_GPIO140__FUNC_I2S0_MCK (MTK_PIN_NO(140) | 3)
>>> +#define PINMUX_GPIO140__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(140) | 6)
>>> +
>>> +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
>>> +#define PINMUX_GPIO141__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(141) | 1)
>>> +#define PINMUX_GPIO141__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(141) | 2)
>>> +#define PINMUX_GPIO141__FUNC_I2S0_BCK (MTK_PIN_NO(141) | 3)
>>> +
>>> +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
>>> +#define PINMUX_GPIO142__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(142) | 1)
>>> +#define PINMUX_GPIO142__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(142) | 2)
>>> +#define PINMUX_GPIO142__FUNC_I2S0_LRCK (MTK_PIN_NO(142) | 3)
>>> +#define PINMUX_GPIO142__FUNC_VOW_DAT_MISO (MTK_PIN_NO(142) | 4)
>>> +#define PINMUX_GPIO142__FUNC_DBG_MON_B25 (MTK_PIN_NO(142) | 7)
>>> +
>>> +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
>>> +#define PINMUX_GPIO143__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(143) | 1)
>>> +#define PINMUX_GPIO143__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(143) | 2)
>>> +#define PINMUX_GPIO143__FUNC_I2S0_DI (MTK_PIN_NO(143) | 3)
>>> +#define PINMUX_GPIO143__FUNC_VOW_CLK_MISO (MTK_PIN_NO(143) | 4)
>>> +#define PINMUX_GPIO143__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(143) | 6)
>>> +#define PINMUX_GPIO143__FUNC_DBG_MON_B26 (MTK_PIN_NO(143) | 7)
>>> +
>>> +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
>>> +#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(144) | 1)
>>> +#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(144) | 2)
>>> +
>>> +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
>>> +#define PINMUX_GPIO145__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(145) | 1)
>>> +
>>> +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
>>> +#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(146) | 1)
>>> +#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(146) | 2)
>>> +
>>> +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
>>> +#define PINMUX_GPIO147__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(147) | 1)
>>> +
>>> +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
>>> +#define PINMUX_GPIO148__FUNC_SRCLKENA0 (MTK_PIN_NO(148) | 1)
>>> +
>>> +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
>>> +#define PINMUX_GPIO149__FUNC_SRCLKENA1 (MTK_PIN_NO(149) | 1)
>>> +
>>> +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
>>> +#define PINMUX_GPIO150__FUNC_PWM_A (MTK_PIN_NO(150) | 1)
>>> +#define PINMUX_GPIO150__FUNC_CMFLASH (MTK_PIN_NO(150) | 2)
>>> +#define PINMUX_GPIO150__FUNC_CLKM0 (MTK_PIN_NO(150) | 3)
>>> +#define PINMUX_GPIO150__FUNC_DBG_MON_B30 (MTK_PIN_NO(150) | 7)
>>> +
>>> +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
>>> +#define PINMUX_GPIO151__FUNC_PWM_B (MTK_PIN_NO(151) | 1)
>>> +#define PINMUX_GPIO151__FUNC_CMVREF0 (MTK_PIN_NO(151) | 2)
>>> +#define PINMUX_GPIO151__FUNC_CLKM1 (MTK_PIN_NO(151) | 3)
>>> +#define PINMUX_GPIO151__FUNC_DBG_MON_B20 (MTK_PIN_NO(151) | 7)
>>> +
>>> +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
>>> +#define PINMUX_GPIO152__FUNC_PWM_C (MTK_PIN_NO(152) | 1)
>>> +#define PINMUX_GPIO152__FUNC_CMFLASH (MTK_PIN_NO(152) | 2)
>>> +#define PINMUX_GPIO152__FUNC_CLKM2 (MTK_PIN_NO(152) | 3)
>>> +#define PINMUX_GPIO152__FUNC_DBG_MON_B21 (MTK_PIN_NO(152) | 7)
>>> +
>>> +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
>>> +#define PINMUX_GPIO153__FUNC_PWM_A (MTK_PIN_NO(153) | 1)
>>> +#define PINMUX_GPIO153__FUNC_CMVREF0 (MTK_PIN_NO(153) | 2)
>>> +#define PINMUX_GPIO153__FUNC_CLKM3 (MTK_PIN_NO(153) | 3)
>>> +#define PINMUX_GPIO153__FUNC_DBG_MON_B22 (MTK_PIN_NO(153) | 7)
>>> +
>>> +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
>>> +#define PINMUX_GPIO154__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(154) | 1)
>>> +#define PINMUX_GPIO154__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(154) | 2)
>>> +#define PINMUX_GPIO154__FUNC_DBG_MON_B18 (MTK_PIN_NO(154) | 7)
>>> +
>>> +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
>>> +#define PINMUX_GPIO155__FUNC_ANT_SEL0 (MTK_PIN_NO(155) | 1)
>>> +#define PINMUX_GPIO155__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(155) | 2)
>>> +#define PINMUX_GPIO155__FUNC_CMVREF1 (MTK_PIN_NO(155) | 3)
>>> +#define PINMUX_GPIO155__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(155) | 7)
>>> +
>>> +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
>>> +#define PINMUX_GPIO156__FUNC_ANT_SEL1 (MTK_PIN_NO(156) | 1)
>>> +#define PINMUX_GPIO156__FUNC_SRCLKENAI0 (MTK_PIN_NO(156) | 2)
>>> +#define PINMUX_GPIO156__FUNC_SCL6 (MTK_PIN_NO(156) | 3)
>>> +#define PINMUX_GPIO156__FUNC_KPCOL2 (MTK_PIN_NO(156) | 4)
>>> +#define PINMUX_GPIO156__FUNC_IDDIG (MTK_PIN_NO(156) | 5)
>>> +#define PINMUX_GPIO156__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(156) | 7)
>>> +
>>> +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
>>> +#define PINMUX_GPIO157__FUNC_ANT_SEL2 (MTK_PIN_NO(157) | 1)
>>> +#define PINMUX_GPIO157__FUNC_SRCLKENAI1 (MTK_PIN_NO(157) | 2)
>>> +#define PINMUX_GPIO157__FUNC_SDA6 (MTK_PIN_NO(157) | 3)
>>> +#define PINMUX_GPIO157__FUNC_KPROW2 (MTK_PIN_NO(157) | 4)
>>> +#define PINMUX_GPIO157__FUNC_USB_DRVVBUS (MTK_PIN_NO(157) | 5)
>>> +#define PINMUX_GPIO157__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(157) | 7)
>>> +
>>> +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
>>> +#define PINMUX_GPIO158__FUNC_ANT_SEL3 (MTK_PIN_NO(158) | 1)
>>> +
>>> +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
>>> +#define PINMUX_GPIO159__FUNC_ANT_SEL4 (MTK_PIN_NO(159) | 1)
>>> +
>>> +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
>>> +#define PINMUX_GPIO160__FUNC_ANT_SEL5 (MTK_PIN_NO(160) | 1)
>>> +
>>> +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
>>> +#define PINMUX_GPIO161__FUNC_SPI1_A_MI (MTK_PIN_NO(161) | 1)
>>> +#define PINMUX_GPIO161__FUNC_SCP_SPI1_MI (MTK_PIN_NO(161) | 2)
>>> +#define PINMUX_GPIO161__FUNC_IDDIG (MTK_PIN_NO(161) | 3)
>>> +#define PINMUX_GPIO161__FUNC_ANT_SEL6 (MTK_PIN_NO(161) | 4)
>>> +#define PINMUX_GPIO161__FUNC_KPCOL2 (MTK_PIN_NO(161) | 5)
>>> +#define PINMUX_GPIO161__FUNC_PTA_RXD (MTK_PIN_NO(161) | 6)
>>> +#define PINMUX_GPIO161__FUNC_DBG_MON_B19 (MTK_PIN_NO(161) | 7)
>>> +
>>> +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
>>> +#define PINMUX_GPIO162__FUNC_SPI1_A_CSB (MTK_PIN_NO(162) | 1)
>>> +#define PINMUX_GPIO162__FUNC_SCP_SPI1_CS (MTK_PIN_NO(162) | 2)
>>> +#define PINMUX_GPIO162__FUNC_USB_DRVVBUS (MTK_PIN_NO(162) | 3)
>>> +#define PINMUX_GPIO162__FUNC_ANT_SEL5 (MTK_PIN_NO(162) | 4)
>>> +#define PINMUX_GPIO162__FUNC_KPROW2 (MTK_PIN_NO(162) | 5)
>>> +#define PINMUX_GPIO162__FUNC_PTA_TXD (MTK_PIN_NO(162) | 6)
>>> +
>>> +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
>>> +#define PINMUX_GPIO163__FUNC_SPI1_A_MO (MTK_PIN_NO(163) | 1)
>>> +#define PINMUX_GPIO163__FUNC_SCP_SPI1_MO (MTK_PIN_NO(163) | 2)
>>> +#define PINMUX_GPIO163__FUNC_SDA1 (MTK_PIN_NO(163) | 3)
>>> +#define PINMUX_GPIO163__FUNC_ANT_SEL4 (MTK_PIN_NO(163) | 4)
>>> +#define PINMUX_GPIO163__FUNC_CMMCLK2 (MTK_PIN_NO(163) | 5)
>>> +#define PINMUX_GPIO163__FUNC_DMIC_CLK (MTK_PIN_NO(163) | 6)
>>> +
>>> +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
>>> +#define PINMUX_GPIO164__FUNC_SPI1_A_CLK (MTK_PIN_NO(164) | 1)
>>> +#define PINMUX_GPIO164__FUNC_SCP_SPI1_CK (MTK_PIN_NO(164) | 2)
>>> +#define PINMUX_GPIO164__FUNC_SCL1 (MTK_PIN_NO(164) | 3)
>>> +#define PINMUX_GPIO164__FUNC_ANT_SEL3 (MTK_PIN_NO(164) | 4)
>>> +#define PINMUX_GPIO164__FUNC_CMMCLK3 (MTK_PIN_NO(164) | 5)
>>> +#define PINMUX_GPIO164__FUNC_DMIC_DAT (MTK_PIN_NO(164) | 6)
>>> +
>>> +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
>>> +#define PINMUX_GPIO165__FUNC_PWM_B (MTK_PIN_NO(165) | 1)
>>> +#define PINMUX_GPIO165__FUNC_CMMCLK2 (MTK_PIN_NO(165) | 2)
>>> +#define PINMUX_GPIO165__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(165) | 3)
>>> +#define PINMUX_GPIO165__FUNC_TDM_MCK_2ND (MTK_PIN_NO(165) | 6)
>>> +#define PINMUX_GPIO165__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(165) | 7)
>>> +
>>> +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
>>> +#define PINMUX_GPIO166__FUNC_ANT_SEL6 (MTK_PIN_NO(166) | 1)
>>> +
>>> +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
>>> +#define PINMUX_GPIO167__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(167) | 1)
>>> +#define PINMUX_GPIO167__FUNC_SPM_BSI_EN (MTK_PIN_NO(167) | 2)
>>> +
>>> +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
>>> +#define PINMUX_GPIO168__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(168) | 1)
>>> +#define PINMUX_GPIO168__FUNC_SPM_BSI_CK (MTK_PIN_NO(168) | 2)
>>> +
>>> +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
>>> +#define PINMUX_GPIO169__FUNC_PWM_C (MTK_PIN_NO(169) | 1)
>>> +#define PINMUX_GPIO169__FUNC_CMMCLK3 (MTK_PIN_NO(169) | 2)
>>> +#define PINMUX_GPIO169__FUNC_CMVREF1 (MTK_PIN_NO(169) | 3)
>>> +#define PINMUX_GPIO169__FUNC_ANT_SEL7 (MTK_PIN_NO(169) | 4)
>>> +#define PINMUX_GPIO169__FUNC_AGPS_SYNC (MTK_PIN_NO(169) | 5)
>>> +#define PINMUX_GPIO169__FUNC_TDM_BCK_2ND (MTK_PIN_NO(169) | 6)
>>> +#define PINMUX_GPIO169__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(169) | 7)
>>> +
>>> +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
>>> +#define PINMUX_GPIO170__FUNC_I2S1_BCK (MTK_PIN_NO(170) | 1)
>>> +#define PINMUX_GPIO170__FUNC_I2S3_BCK (MTK_PIN_NO(170) | 2)
>>> +#define PINMUX_GPIO170__FUNC_SCL7 (MTK_PIN_NO(170) | 3)
>>> +#define PINMUX_GPIO170__FUNC_I2S5_BCK (MTK_PIN_NO(170) | 4)
>>> +#define PINMUX_GPIO170__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(170) | 5)
>>> +#define PINMUX_GPIO170__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(170) | 6)
>>> +#define PINMUX_GPIO170__FUNC_ANT_SEL3 (MTK_PIN_NO(170) | 7)
>>> +
>>> +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
>>> +#define PINMUX_GPIO171__FUNC_I2S1_LRCK (MTK_PIN_NO(171) | 1)
>>> +#define PINMUX_GPIO171__FUNC_I2S3_LRCK (MTK_PIN_NO(171) | 2)
>>> +#define PINMUX_GPIO171__FUNC_SDA7 (MTK_PIN_NO(171) | 3)
>>> +#define PINMUX_GPIO171__FUNC_I2S5_LRCK (MTK_PIN_NO(171) | 4)
>>> +#define PINMUX_GPIO171__FUNC_URXD1 (MTK_PIN_NO(171) | 5)
>>> +#define PINMUX_GPIO171__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(171) | 6)
>>> +#define PINMUX_GPIO171__FUNC_ANT_SEL4 (MTK_PIN_NO(171) | 7)
>>> +
>>> +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
>>> +#define PINMUX_GPIO172__FUNC_I2S1_DO (MTK_PIN_NO(172) | 1)
>>> +#define PINMUX_GPIO172__FUNC_I2S3_DO (MTK_PIN_NO(172) | 2)
>>> +#define PINMUX_GPIO172__FUNC_SCL8 (MTK_PIN_NO(172) | 3)
>>> +#define PINMUX_GPIO172__FUNC_I2S5_DO (MTK_PIN_NO(172) | 4)
>>> +#define PINMUX_GPIO172__FUNC_UTXD1 (MTK_PIN_NO(172) | 5)
>>> +#define PINMUX_GPIO172__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(172) | 6)
>>> +#define PINMUX_GPIO172__FUNC_ANT_SEL5 (MTK_PIN_NO(172) | 7)
>>> +
>>> +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
>>> +#define PINMUX_GPIO173__FUNC_I2S1_MCK (MTK_PIN_NO(173) | 1)
>>> +#define PINMUX_GPIO173__FUNC_I2S3_MCK (MTK_PIN_NO(173) | 2)
>>> +#define PINMUX_GPIO173__FUNC_SDA8 (MTK_PIN_NO(173) | 3)
>>> +#define PINMUX_GPIO173__FUNC_I2S5_MCK (MTK_PIN_NO(173) | 4)
>>> +#define PINMUX_GPIO173__FUNC_UCTS0 (MTK_PIN_NO(173) | 5)
>>> +#define PINMUX_GPIO173__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(173) | 6)
>>> +#define PINMUX_GPIO173__FUNC_ANT_SEL6 (MTK_PIN_NO(173) | 7)
>>> +
>>> +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
>>> +#define PINMUX_GPIO174__FUNC_I2S2_DI (MTK_PIN_NO(174) | 1)
>>> +#define PINMUX_GPIO174__FUNC_I2S0_DI (MTK_PIN_NO(174) | 2)
>>> +#define PINMUX_GPIO174__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(174) | 3)
>>> +#define PINMUX_GPIO174__FUNC_I2S2_DI2 (MTK_PIN_NO(174) | 4)
>>> +#define PINMUX_GPIO174__FUNC_URTS0 (MTK_PIN_NO(174) | 5)
>>> +#define PINMUX_GPIO174__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(174) | 6)
>>> +#define PINMUX_GPIO174__FUNC_ANT_SEL7 (MTK_PIN_NO(174) | 7)
>>> +
>>> +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
>>> +#define PINMUX_GPIO175__FUNC_ANT_SEL7 (MTK_PIN_NO(175) | 1)
>>> +
>>> +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
>>> +
>>> +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
>>> +
>>> +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
>>> +
>>> +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
>>> +
>>> +#endif /* __MT8183-PINFUNC_H */
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>> new file mode 100644
>>> index 0000000..63db9cc
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>> @@ -0,0 +1,408 @@
>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> +/*
>>> + * Copyright (c) 2018 MediaTek Inc.
>>> + * Author: Ben Ho <ben.ho@mediatek.com>
>>> + * Erin Lo <erin.lo@mediatek.com>
>>> + */
>>> +
>>> +#include <dt-bindings/clock/mt8183-clk.h>
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>> +#include "mt8183-pinfunc.h"
>>> +
>>> +/ {
>>> + compatible = "mediatek,mt8183";
>>> + interrupt-parent = <&sysirq>;
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> +
>>> + cpus {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + cpu-map {
>>> + cluster0 {
>>> + core0 {
>>> + cpu = <&cpu0>;
>>> + };
>>> + core1 {
>>> + cpu = <&cpu1>;
>>> + };
>>> + core2 {
>>> + cpu = <&cpu2>;
>>> + };
>>> + core3 {
>>> + cpu = <&cpu3>;
>>> + };
>>> + };
>>> +
>>> + cluster1 {
>>> + core0 {
>>> + cpu = <&cpu4>;
>>> + };
>>> + core1 {
>>> + cpu = <&cpu5>;
>>> + };
>>> + core2 {
>>> + cpu = <&cpu6>;
>>> + };
>>> + core3 {
>>> + cpu = <&cpu7>;
>>> + };
>>> + };
>>> + };
>>> +
>>> + cpu0: cpu@0 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a53";
>>> + reg = <0x000>;
>>> + enable-method = "psci";
>>> + };
>>> +
>>> + cpu1: cpu@1 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a53";
>>> + reg = <0x001>;
>>> + enable-method = "psci";
>>> + };
>>> +
>>> + cpu2: cpu@2 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a53";
>>> + reg = <0x002>;
>>> + enable-method = "psci";
>>> + };
>>> +
>>> + cpu3: cpu@3 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a53";
>>> + reg = <0x003>;
>>> + enable-method = "psci";
>>> + };
>>> +
>>> + cpu4: cpu@100 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a73";
>>> + reg = <0x100>;
>>> + enable-method = "psci";
>>> + };
>>> +
>>> + cpu5: cpu@101 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a73";
>>> + reg = <0x101>;
>>> + enable-method = "psci";
>>> + };
>>> +
>>> + cpu6: cpu@102 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a73";
>>> + reg = <0x102>;
>>> + enable-method = "psci";
>>> + };
>>> +
>>> + cpu7: cpu@103 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a73";
>>> + reg = <0x103>;
>>> + enable-method = "psci";
>>> + };
>>> + };
>>> +
>>> + pmu-a53 {
>>> + compatible = "arm,cortex-a53-pmu";
>>> + interrupt-parent = <&gic>;
>>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
>>> + };
>>> +
>>> + pmu-a73 {
>>> + compatible = "arm,cortex-a73-pmu";
>>> + interrupt-parent = <&gic>;
>>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
>>> + };
>>> +
>>> + psci {
>>> + compatible = "arm,psci-1.0";
>>> + method = "smc";
>>> + };
>>> +
>>> + clk26m: oscillator {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <26000000>;
>>> + clock-output-names = "clk26m";
>>> + };
>>> +
>>> + timer {
>>> + compatible = "arm,armv8-timer";
>>> + interrupt-parent = <&gic>;
>>> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
>>> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
>>> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
>>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
>>> + };
>>> +
>>> + gic: interrupt-controller@c000000 {
>>> + compatible = "arm,gic-v3";
>>> + #interrupt-cells = <4>;
>>> + interrupt-parent = <&gic>;
>>> + interrupt-controller;
>>> + reg = <0 0x0c000000 0 0x40000>, /* GICD */
>>> + <0 0x0c100000 0 0x200000>, /* GICR */
>>> + <0 0x0c400000 0 0x2000>, /* GICC */
>>> + <0 0x0c410000 0 0x1000>, /* GICH */
>>> + <0 0x0c420000 0 0x2000>; /* GICV */
>>> +
>>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
>>> + ppi-partitions {
>>> + ppi_cluster0: interrupt-partition-0 {
>>> + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
>>> + };
>>> + ppi_cluster1: interrupt-partition-1 {
>>> + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
>>> + };
>>> + };
>>> + };
>>> +
>>> + mcucfg: syscon@c530000 {
>>> + compatible = "mediatek,mt8183-mcucfg", "syscon";
>>> + reg = <0 0x0c530000 0 0x1000>;
>>> + #clock-cells = <1>;
>>> + };
>>> +
>>> + sysirq: intpol-controller@c530a80 {
>>> + compatible = "mediatek,mt8183-sysirq",
>>> + "mediatek,mt6577-sysirq";
>>> + interrupt-controller;
>>> + #interrupt-cells = <4>;
>>> + interrupt-parent = <&gic>;
>>> + reg = <0 0x0c530a80 0 0x50>;
>>> + };
>>> +
>>> + topckgen: syscon@10000000 {
>>> + compatible = "mediatek,mt8183-topckgen", "syscon";
>>> + reg = <0 0x10000000 0 0x1000>;
>>> + #clock-cells = <1>;
>>> + };
>>> +
>>> + infracfg: syscon@10001000 {
>>> + compatible = "mediatek,mt8183-infracfg", "syscon";
>>> + reg = <0 0x10001000 0 0x1000>;
>>> + #clock-cells = <1>;
>>> + };
>>> +
>>> + pio: pinctrl@1000b000 {
>>> + compatible = "mediatek,mt8183-pinctrl";
>>> + reg = <0 0x10005000 0 0x1000>,
>>> + <0 0x11f20000 0 0x1000>,
>>> + <0 0x11e80000 0 0x1000>,
>>> + <0 0x11e70000 0 0x1000>,
>>> + <0 0x11e90000 0 0x1000>,
>>> + <0 0x11d30000 0 0x1000>,
>>> + <0 0x11d20000 0 0x1000>,
>>> + <0 0x11c50000 0 0x1000>,
>>> + <0 0x11f30000 0 0x1000>,
>>> + <0 0x1000b000 0 0x1000>;
>>> + reg-names = "iocfg0", "iocfg1", "iocfg2",
>>> + "iocfg3", "iocfg4", "iocfg5",
>>> + "iocfg6", "iocfg7", "iocfg8",
>>> + "eint";
>>> + gpio-controller;
>>> + #gpio-cells = <2>;
>>> + gpio-ranges = <&pio 0 0 192>;
>>> + interrupt-controller;
>>> + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>;
>>> + interrupt-parent = <&gic>;
>>> + #interrupt-cells = <4>;
>>> + };
>>> +
>>> + apmixedsys: syscon@1000c000 {
>>> + compatible = "mediatek,mt8183-apmixedsys", "syscon";
>>> + reg = <0 0x1000c000 0 0x1000>;
>>> + #clock-cells = <1>;
>>> + };
>>> +
>>> + pwrap: pwrap@1000d000 {
>>> + compatible = "mediatek,mt8183-pwrap";
>>> + reg = <0 0x1000d000 0 0x1000>;
>>> + reg-names = "pwrap";
>>> + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 0>;
>>> + clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
>>> + <&infracfg CLK_INFRA_PMIC_AP>;
>>> + clock-names = "spi", "wrap";
>>> + };
>>> +
>>> + uart0: serial@11002000 {
>>> + compatible = "mediatek,mt8183-uart",
>>> + "mediatek,mt6577-uart";
>>> + reg = <0 0x11002000 0 0x1000>;
>>> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW 0>;
>>> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
>>> + clock-names = "baud", "bus";
>>> + status = "disabled";
>>> + };
>>> +
>>> + uart1: serial@11003000 {
>>> + compatible = "mediatek,mt8183-uart",
>>> + "mediatek,mt6577-uart";
>>> + reg = <0 0x11003000 0 0x1000>;
>>> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW 0>;
>>> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
>>> + clock-names = "baud", "bus";
>>> + status = "disabled";
>>> + };
>>> +
>>> + uart2: serial@11004000 {
>>> + compatible = "mediatek,mt8183-uart",
>>> + "mediatek,mt6577-uart";
>>> + reg = <0 0x11004000 0 0x1000>;
>>> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW 0>;
>>> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
>>> + clock-names = "baud", "bus";
>>> + status = "disabled";
>>> + };
>>> +
>>> + spi0: spi@1100a000 {
>>> + compatible = "mediatek,mt8183-spi";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + reg = <0 0x1100a000 0 0x1000>;
>>> + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW 0>;
>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
>>> + <&topckgen CLK_TOP_MUX_SPI>,
>>> + <&infracfg CLK_INFRA_SPI0>;
>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
>>> + status = "disabled";
>>> + };
>>> +
>>> + spi1: spi@11010000 {
>>> + compatible = "mediatek,mt8183-spi";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + reg = <0 0x11010000 0 0x1000>;
>>> + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW 0>;
>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
>>> + <&topckgen CLK_TOP_MUX_SPI>,
>>> + <&infracfg CLK_INFRA_SPI1>;
>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
>>> + status = "disabled";
>>> + };
>>> +
>>> + spi2: spi@11012000 {
>>> + compatible = "mediatek,mt8183-spi";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + reg = <0 0x11012000 0 0x1000>;
>>> + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW 0>;
>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
>>> + <&topckgen CLK_TOP_MUX_SPI>,
>>> + <&infracfg CLK_INFRA_SPI2>;
>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
>>> + status = "disabled";
>>> + };
>>> +
>>> + spi3: spi@11013000 {
>>> + compatible = "mediatek,mt8183-spi";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + reg = <0 0x11013000 0 0x1000>;
>>> + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW 0>;
>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
>>> + <&topckgen CLK_TOP_MUX_SPI>,
>>> + <&infracfg CLK_INFRA_SPI3>;
>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
>>> + status = "disabled";
>>> + };
>>> +
>>> + spi4: spi@11018000 {
>>> + compatible = "mediatek,mt8183-spi";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + reg = <0 0x11018000 0 0x1000>;
>>> + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW 0>;
>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
>>> + <&topckgen CLK_TOP_MUX_SPI>,
>>> + <&infracfg CLK_INFRA_SPI4>;
>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
>>> + status = "disabled";
>>> + };
>>> +
>>> + spi5: spi@11019000 {
>>> + compatible = "mediatek,mt8183-spi";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + reg = <0 0x11019000 0 0x1000>;
>>> + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW 0>;
>>> + clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
>>> + <&topckgen CLK_TOP_MUX_SPI>,
>>> + <&infracfg CLK_INFRA_SPI5>;
>>> + clock-names = "parent-clk", "sel-clk", "spi-clk";
>>> + status = "disabled";
>>> + };
>>> +
>>> + audiosys: syscon@11220000 {
>>> + compatible = "mediatek,mt8183-audiosys", "syscon";
>>> + reg = <0 0x11220000 0 0x1000>;
>>> + #clock-cells = <1>;
>>> + };
>>> +
>>> + mfgcfg: syscon@13000000 {
>>> + compatible = "mediatek,mt8183-mfgcfg", "syscon";
>>> + reg = <0 0x13000000 0 0x1000>;
>>> + #clock-cells = <1>;
>>> + };
>>> +
>>> + mmsys: syscon@14000000 {
>>> + compatible = "mediatek,mt8183-mmsys", "syscon";
>>> + reg = <0 0x14000000 0 0x1000>;
>>> + #clock-cells = <1>;
>>> + };
>>> +
>>> + imgsys: syscon@15020000 {
>>> + compatible = "mediatek,mt8183-imgsys", "syscon";
>>> + reg = <0 0x15020000 0 0x1000>;
>>> + #clock-cells = <1>;
>>> + };
>>> +
>>> + vdecsys: syscon@16000000 {
>>> + compatible = "mediatek,mt8183-vdecsys", "syscon";
>>> + reg = <0 0x16000000 0 0x1000>;
>>> + #clock-cells = <1>;
>>> + };
>>> +
>>> + vencsys: syscon@17000000 {
>>> + compatible = "mediatek,mt8183-vencsys", "syscon";
>>> + reg = <0 0x17000000 0 0x1000>;
>>> + #clock-cells = <1>;
>>> + };
>>> +
>>> + ipu_conn: syscon@19000000 {
>>> + compatible = "mediatek,mt8183-ipu_conn", "syscon";
>>> + reg = <0 0x19000000 0 0x1000>;
>>> + #clock-cells = <1>;
>>> + };
>>> +
>>> + ipu_adl: syscon@19010000 {
>>> + compatible = "mediatek,mt8183-ipu_adl", "syscon";
>>> + reg = <0 0x19010000 0 0x1000>;
>>> + #clock-cells = <1>;
>>> + };
>>> +
>>> + ipu_core0: syscon@19180000 {
>>> + compatible = "mediatek,mt8183-ipu_core0", "syscon";
>>> + reg = <0 0x19180000 0 0x1000>;
>>> + #clock-cells = <1>;
>>> + };
>>> +
>>> + ipu_core1: syscon@19280000 {
>>> + compatible = "mediatek,mt8183-ipu_core1", "syscon";
>>> + reg = <0 0x19280000 0 0x1000>;
>>> + #clock-cells = <1>;
>>> + };
>>> +
>>> + camsys: syscon@1a000000 {
>>> + compatible = "mediatek,mt8183-camsys", "syscon";
>>> + reg = <0 0x1a000000 0 0x1000>;
>>> + #clock-cells = <1>;
>>> + };
>>> +};
>>>
>>
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