* Re: [PATCH 19/24] dt-bindings: spi: spi-mt65xx: add support for MT8516
From: Mark Brown @ 2019-04-16 14:28 UTC (permalink / raw)
To: Matthias Brugger
Cc: Fabien Parent, robh+dt, mark.rutland, sean.wang, ryder.lee,
hsin-hsiung.wang, wenzhen.yu, chaotian.jing, yong.mao, jjian.zhou,
devicetree, linux-kernel, linux-i2c, linux-arm-kernel,
linux-mediatek, linux-mmc, linux-gpio, linux-serial, linux-spi,
linux-watchdog, linux-clk, stephane.leprovost
In-Reply-To: <5bc3fbfa-6d7e-08d3-116c-a8f78bc680cd@gmail.com>
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On Tue, Apr 16, 2019 at 09:55:41AM +0200, Matthias Brugger wrote:
> On 23/03/2019 22:16, Fabien Parent wrote:
> > Add binding documentation of spi-mt65xx for MT8516 SoC.
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > ---
> > Documentation/devicetree/bindings/spi/spi-mt65xx.txt | 1 +
> > 1 file changed, 1 insertion(+)
> applied to v5.1-next/dts64
> Mark let me know if you want to take it through your tree and I drop the patch.
Yes, DT bindings generally get reviewed in the subsystem :(
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^ permalink raw reply
* Re: [PATCH v2 2/4] mfd: ioc3: Add driver for SGI IOC3 chip
From: Greg Kroah-Hartman @ 2019-04-16 13:16 UTC (permalink / raw)
To: Thomas Bogendoerfer
Cc: Ralf Baechle, Paul Burton, James Hogan, Dmitry Torokhov,
Lee Jones, David S. Miller, Alessandro Zummo, Alexandre Belloni,
Jiri Slaby, linux-mips, linux-kernel, linux-input, netdev,
linux-rtc, linux-serial
In-Reply-To: <20190409154610.6735-3-tbogendoerfer@suse.de>
On Tue, Apr 09, 2019 at 05:46:06PM +0200, Thomas Bogendoerfer wrote:
> SGI IOC3 chip has integrated ethernet, keyboard and mouse interface.
> It also supports connecting a SuperIO chip for serial and parallel
> interfaces. IOC3 is used inside various SGI systemboards and add-on
> cards with different equipped external interfaces.
>
> Support for ethernet and serial interfaces were implemented inside
> the network driver. This patchset moves out the not network related
> parts to a new MFD driver, which takes care of card detection,
> setup of platform devices and interrupt distribution for the subdevices.
>
> Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de>
> ---
> arch/mips/include/asm/sn/ioc3.h | 345 +++---
> arch/mips/sgi-ip27/ip27-timer.c | 20 -
> drivers/mfd/Kconfig | 13 +
> drivers/mfd/Makefile | 1 +
> drivers/mfd/ioc3.c | 802 ++++++++++++++
> drivers/net/ethernet/sgi/Kconfig | 4 +-
> drivers/net/ethernet/sgi/ioc3-eth.c | 1867 ++++++++++++---------------------
> drivers/tty/serial/8250/8250_ioc3.c | 98 ++
> drivers/tty/serial/8250/Kconfig | 11 +
> drivers/tty/serial/8250/Makefile | 1 +
> include/linux/platform_data/ioc3eth.h | 15 +
> 11 files changed, 1762 insertions(+), 1415 deletions(-)
> create mode 100644 drivers/mfd/ioc3.c
> create mode 100644 drivers/tty/serial/8250/8250_ioc3.c
> create mode 100644 include/linux/platform_data/ioc3eth.h
Serial portion:
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
^ permalink raw reply
* Re: [PATCH] serial: sc16is7xx: fix unused label warning
From: Greg Kroah-Hartman @ 2019-04-16 13:11 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Jiri Slaby, Phil Elwell, Gustavo A. R. Silva, Stefan Potyra,
Mao Wenan, linux-serial, linux-kernel
In-Reply-To: <20190416123321.3577638-1-arnd@arndb.de>
On Tue, Apr 16, 2019 at 02:33:14PM +0200, Arnd Bergmann wrote:
> A bugfix introduced a harmless warning:
>
> drivers/tty/serial/sc16is7xx.c:1523:1: error: unused label 'err_spi' [-Werror,-Wunused-label]
>
> Move each label inside the correct #ifdef.
>
> Fixes: ac0cdb3d9901 ("sc16is7xx: missing unregister/delete driver on error in sc16is7xx_init()")
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> drivers/tty/serial/sc16is7xx.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Someone sent this same patch a week earlier. I'll merge yours into
it...
thanks,
greg k-h
^ permalink raw reply
* [PATCH] serial: sc16is7xx: fix unused label warning
From: Arnd Bergmann @ 2019-04-16 12:33 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: Arnd Bergmann, Phil Elwell, Gustavo A. R. Silva, Stefan Potyra,
Mao Wenan, linux-serial, linux-kernel
A bugfix introduced a harmless warning:
drivers/tty/serial/sc16is7xx.c:1523:1: error: unused label 'err_spi' [-Werror,-Wunused-label]
Move each label inside the correct #ifdef.
Fixes: ac0cdb3d9901 ("sc16is7xx: missing unregister/delete driver on error in sc16is7xx_init()")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/tty/serial/sc16is7xx.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c
index 09a183dfc526..a31db15cd7c0 100644
--- a/drivers/tty/serial/sc16is7xx.c
+++ b/drivers/tty/serial/sc16is7xx.c
@@ -1520,11 +1520,13 @@ static int __init sc16is7xx_init(void)
#endif
return ret;
+#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
err_spi:
+#endif
#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
i2c_del_driver(&sc16is7xx_i2c_uart_driver);
-#endif
err_i2c:
+#endif
uart_unregister_driver(&sc16is7xx_uart);
return ret;
}
--
2.20.0
^ permalink raw reply related
* Re: [PATCH 22/24] dt-bindings: i2c: i2c-mtk: add support for MT8516
From: Wolfram Sang @ 2019-04-16 11:05 UTC (permalink / raw)
To: Fabien Parent
Cc: matthias.bgg, robh+dt, mark.rutland, sean.wang, ryder.lee,
hsin-hsiung.wang, wenzhen.yu, chaotian.jing, yong.mao, jjian.zhou,
devicetree, linux-kernel, linux-i2c, linux-arm-kernel,
linux-mediatek, linux-mmc, linux-gpio, linux-serial, linux-spi,
linux-watchdog, linux-clk, stephane.leprovost
In-Reply-To: <20190323211612.860-23-fparent@baylibre.com>
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On Sat, Mar 23, 2019 at 10:16:10PM +0100, Fabien Parent wrote:
> Add binding documentation of i2c-mtk for MT8516 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
Applied to for-next, thanks!
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^ permalink raw reply
* Re: [PATCH v9] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile
From: Matthias Brugger @ 2019-04-16 10:35 UTC (permalink / raw)
To: Erin Lo
Cc: Rob Herring, Mark Rutland, devicetree, srv_heupstream,
linux-kernel, linux-serial, linux-mediatek, linux-arm-kernel,
mars.cheng, eddie.huang, Ben Ho, Seiya Wang, Weiyi Lu,
Hsin-Hsiung Wang, Stephen Boyd
In-Reply-To: <1555406836.27018.10.camel@mtksdaap41>
On 16/04/2019 11:27, Erin Lo wrote:
> On Tue, 2019-04-16 at 10:29 +0200, Matthias Brugger wrote:
>>
>> On 18/03/2019 19:42, kbuild test robot wrote:
>>> Hi Erin,
>>>
>>> Thank you for the patch! Yet something to improve:
>>>
>>> [auto build test ERROR on robh/for-next]
>>> [also build test ERROR on v5.1-rc1 next-20190318]
>>> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
>>>
>>> url: https://github.com/0day-ci/linux/commits/Erin-Lo/arm64-dts-Add-Mediatek-SoC-MT8183-and-evaluation-board-dts-and-Makefile/20190318-170422
>>> base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
>>> config: arm64-allyesconfig (attached as .config)
>>> compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
>>> reproduce:
>>> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
>>> chmod +x ~/bin/make.cross
>>> # save the attached .config to linux build tree
>>> GCC_VERSION=7.2.0 make.cross ARCH=arm64
>>>
>>> All errors (new ones prefixed by >>):
>>>
>>> In file included from arch/arm64/boot/dts/mediatek/mt8183-evb.dts:9:0:
>>>>> arch/arm64/boot/dts/mediatek/mt8183.dtsi:8:10: fatal error: dt-bindings/clock/mt8183-clk.h: No such file or directory
>>> #include <dt-bindings/clock/mt8183-clk.h>
>>> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>> compilation terminated.
>>>
>>> vim +8 arch/arm64/boot/dts/mediatek/mt8183.dtsi
>>>
>>> > 8 #include <dt-bindings/clock/mt8183-clk.h>
>>> 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> 10 #include <dt-bindings/interrupt-controller/irq.h>
>>> 11
>>>
>>
>> Stephen queued the corresponding patch for v5.2.
>> I propose we wait for v5.2-rc1 and then apply the basic support and the others
>> based on this one.
>>
>> Erin: There are may mt8183 dts patches floating around that depend on this or
>> more patches. Can you coordinate with your colleagues to resend them as a
>> series? Then it will be easier for me to take them for v5.3, as some have
>> dependencies on other series etc.
>>
>> Thanks a lot.
>> Matthias
>
> OK, I will coordinate with my colleagues to resend mt8183 dts patches as
> a series base on v5.2-rc1 when v5.2-rc1 release.
> Since we want to send this series more confident so they still send
> separate patch in v5.1 just for review in advance. Is that ok for you?
>
Sure no problem. Thanks for helping!
^ permalink raw reply
* Re: [PATCH v9] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile
From: Erin Lo @ 2019-04-16 9:27 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, Mark Rutland, devicetree, srv_heupstream,
linux-kernel, linux-serial, linux-mediatek, linux-arm-kernel,
mars.cheng, eddie.huang, Ben Ho, Seiya Wang, Weiyi Lu,
Hsin-Hsiung Wang, Stephen Boyd
In-Reply-To: <135d7e3a-d5a3-0f13-05c9-4a8ec0524256@gmail.com>
On Tue, 2019-04-16 at 10:29 +0200, Matthias Brugger wrote:
>
> On 18/03/2019 19:42, kbuild test robot wrote:
> > Hi Erin,
> >
> > Thank you for the patch! Yet something to improve:
> >
> > [auto build test ERROR on robh/for-next]
> > [also build test ERROR on v5.1-rc1 next-20190318]
> > [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
> >
> > url: https://github.com/0day-ci/linux/commits/Erin-Lo/arm64-dts-Add-Mediatek-SoC-MT8183-and-evaluation-board-dts-and-Makefile/20190318-170422
> > base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
> > config: arm64-allyesconfig (attached as .config)
> > compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
> > reproduce:
> > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> > chmod +x ~/bin/make.cross
> > # save the attached .config to linux build tree
> > GCC_VERSION=7.2.0 make.cross ARCH=arm64
> >
> > All errors (new ones prefixed by >>):
> >
> > In file included from arch/arm64/boot/dts/mediatek/mt8183-evb.dts:9:0:
> >>> arch/arm64/boot/dts/mediatek/mt8183.dtsi:8:10: fatal error: dt-bindings/clock/mt8183-clk.h: No such file or directory
> > #include <dt-bindings/clock/mt8183-clk.h>
> > ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > compilation terminated.
> >
> > vim +8 arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >
> > > 8 #include <dt-bindings/clock/mt8183-clk.h>
> > 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
> > 10 #include <dt-bindings/interrupt-controller/irq.h>
> > 11
> >
>
> Stephen queued the corresponding patch for v5.2.
> I propose we wait for v5.2-rc1 and then apply the basic support and the others
> based on this one.
>
> Erin: There are may mt8183 dts patches floating around that depend on this or
> more patches. Can you coordinate with your colleagues to resend them as a
> series? Then it will be easier for me to take them for v5.3, as some have
> dependencies on other series etc.
>
> Thanks a lot.
> Matthias
OK, I will coordinate with my colleagues to resend mt8183 dts patches as
a series base on v5.2-rc1 when v5.2-rc1 release.
Since we want to send this series more confident so they still send
separate patch in v5.1 just for review in advance. Is that ok for you?
^ permalink raw reply
* Re: [PATCH 15/24] dt-bindings: pinctrl: pinctrl-mt65xx: add support for MT8516
From: Matthias Brugger @ 2019-04-16 9:12 UTC (permalink / raw)
To: Linus Walleij, Fabien Parent
Cc: Rob Herring, Mark Rutland, Sean Wang, Ryder Lee, hsin-hsiung.wang,
wenzhen.yu, Chaotian Jing, Yong Mao, jjian.zhou,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org, linux-i2c, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-mmc,
open list:GPIO SUBSYSTEM, linux-serial, linux-spi <linux-spi@
In-Reply-To: <CACRpkdZZ6-+MVdK4bOP4SHxQ8uQ8zENcir7DSteHy4g+B5uySQ@mail.gmail.com>
Hi Linus,
On 08/04/2019 22:44, Linus Walleij wrote:
> On Sat, Mar 23, 2019 at 10:17 PM Fabien Parent <fparent@baylibre.com> wrote:
>
>> Add binding documentation of pinctrl-mt65xx for MT8516 SoC.
>>
>> Signed-off-by: Fabien Parent <fparent@baylibre.com>
>
> Patch applied with Rob's ACK.
>
I don't see this in your for-next branch. Did the patch got lost?
Regards,
Matthias
^ permalink raw reply
* Re: [PATCH 22/24] dt-bindings: i2c: i2c-mtk: add support for MT8516
From: Matthias Brugger @ 2019-04-16 8:53 UTC (permalink / raw)
To: Wolfram Sang
Cc: Fabien Parent, robh+dt, mark.rutland, sean.wang, ryder.lee,
hsin-hsiung.wang, wenzhen.yu, chaotian.jing, yong.mao, jjian.zhou,
devicetree, linux-kernel, linux-i2c, linux-arm-kernel,
linux-mediatek, linux-mmc, linux-gpio, linux-serial, linux-spi,
linux-watchdog, linux-clk, stephane.leprovost
In-Reply-To: <20190416081433.GA1012@kunai>
On 16/04/2019 10:14, Wolfram Sang wrote:
> On Tue, Apr 16, 2019 at 09:58:09AM +0200, Matthias Brugger wrote:
>>
>>
>> On 23/03/2019 22:16, Fabien Parent wrote:
>>> Add binding documentation of i2c-mtk for MT8516 SoC.
>>>
>>> Signed-off-by: Fabien Parent <fparent@baylibre.com> ---
>>> Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 1 + 1 file changed,
>>> 1 insertion(+)
>>>
>>
>>
>> applied to v5.1-next/dts64
>>
>> Wolfram let me know if you want to take it through your tree and I drop
>> the patch.
>
> I'd like to take it via my tree to reduce conflicts. It already needs
> rebasing on top of i2c/for-next because of Qii's MT8183 patches.
>
Ok, dropped, the patch is all yours :)
^ permalink raw reply
* Re: [PATCH 19/24] dt-bindings: spi: spi-mt65xx: add support for MT8516
From: Matthias Brugger @ 2019-04-16 8:52 UTC (permalink / raw)
To: lei liu
Cc: Fabien Parent, robh+dt, mark.rutland, Mark Brown,
linux-arm-kernel, devicetree, ryder.lee, linux-watchdog,
jjian.zhou, wenzhen.yu, stephane.leprovost, sean.wang, linux-mmc,
linux-kernel, yong.mao, linux-spi, linux-gpio, linux-mediatek,
hsin-hsiung.wang, linux-serial, linux-clk, chaotian.jing,
linux-i2c
In-Reply-To: <1555403151.7441.4.camel@mhfsdcap03>
On 16/04/2019 10:25, lei liu wrote:
> On Tue, 2019-04-16 at 09:55 +0200, Matthias Brugger wrote:
>>
>> On 23/03/2019 22:16, Fabien Parent wrote:
>>> Add binding documentation of spi-mt65xx for MT8516 SoC.
>>>
>>> Signed-off-by: Fabien Parent <fparent@baylibre.com>
>>> ---
>>> Documentation/devicetree/bindings/spi/spi-mt65xx.txt | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>
>>
>> applied to v5.1-next/dts64
>>
>> Mark let me know if you want to take it through your tree and I drop the patch.
>>
>>> diff --git a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
>>> index 69c356767cf8..69ac5976b952 100644
>>> --- a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
>>> +++ b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
>>> @@ -10,6 +10,7 @@ Required properties:
>>> - mediatek,mt8135-spi: for mt8135 platforms
>>> - mediatek,mt8173-spi: for mt8173 platforms
>>> - mediatek,mt8183-spi: for mt8183 platforms
>>> + - "mediatek,mt8516-spi", "mediatek,mt2701-spi": for mt8516 platforms
> Hi Fabien,
> mt8516 SPI design comes from mt2712 and it's different from mt2701. Here
> it should compatible with mt2712.
>
Ok, please resend. I dropped the patch for now.
>>>
>>> - #address-cells: should be 1.
>>>
>>>
>>
>> _______________________________________________
>> Linux-mediatek mailing list
>> Linux-mediatek@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
>
>
^ permalink raw reply
* Re: [PATCH v9] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile
From: Matthias Brugger @ 2019-04-16 8:29 UTC (permalink / raw)
To: Erin Lo
Cc: Rob Herring, Mark Rutland, devicetree, srv_heupstream,
linux-kernel, linux-serial, linux-mediatek, linux-arm-kernel,
mars.cheng, eddie.huang, Ben Ho, Seiya Wang, Weiyi Lu,
Hsin-Hsiung Wang, Stephen Boyd
In-Reply-To: <201903190247.QZDwfpLQ%lkp@intel.com>
On 18/03/2019 19:42, kbuild test robot wrote:
> Hi Erin,
>
> Thank you for the patch! Yet something to improve:
>
> [auto build test ERROR on robh/for-next]
> [also build test ERROR on v5.1-rc1 next-20190318]
> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
>
> url: https://github.com/0day-ci/linux/commits/Erin-Lo/arm64-dts-Add-Mediatek-SoC-MT8183-and-evaluation-board-dts-and-Makefile/20190318-170422
> base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
> config: arm64-allyesconfig (attached as .config)
> compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
> reproduce:
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # save the attached .config to linux build tree
> GCC_VERSION=7.2.0 make.cross ARCH=arm64
>
> All errors (new ones prefixed by >>):
>
> In file included from arch/arm64/boot/dts/mediatek/mt8183-evb.dts:9:0:
>>> arch/arm64/boot/dts/mediatek/mt8183.dtsi:8:10: fatal error: dt-bindings/clock/mt8183-clk.h: No such file or directory
> #include <dt-bindings/clock/mt8183-clk.h>
> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> compilation terminated.
>
> vim +8 arch/arm64/boot/dts/mediatek/mt8183.dtsi
>
> > 8 #include <dt-bindings/clock/mt8183-clk.h>
> 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
> 10 #include <dt-bindings/interrupt-controller/irq.h>
> 11
>
Stephen queued the corresponding patch for v5.2.
I propose we wait for v5.2-rc1 and then apply the basic support and the others
based on this one.
Erin: There are may mt8183 dts patches floating around that depend on this or
more patches. Can you coordinate with your colleagues to resend them as a
series? Then it will be easier for me to take them for v5.3, as some have
dependencies on other series etc.
Thanks a lot.
Matthias
^ permalink raw reply
* Re: [PATCH 19/24] dt-bindings: spi: spi-mt65xx: add support for MT8516
From: lei liu @ 2019-04-16 8:25 UTC (permalink / raw)
To: Matthias Brugger
Cc: Fabien Parent, robh+dt, mark.rutland, Mark Brown,
linux-arm-kernel, devicetree, ryder.lee, linux-watchdog,
jjian.zhou, wenzhen.yu, stephane.leprovost, sean.wang, linux-mmc,
linux-kernel, yong.mao, linux-spi, linux-gpio, linux-mediatek,
hsin-hsiung.wang, linux-serial, linux-clk, chaotian.jing,
linux-i2c
In-Reply-To: <5bc3fbfa-6d7e-08d3-116c-a8f78bc680cd@gmail.com>
On Tue, 2019-04-16 at 09:55 +0200, Matthias Brugger wrote:
>
> On 23/03/2019 22:16, Fabien Parent wrote:
> > Add binding documentation of spi-mt65xx for MT8516 SoC.
> >
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > ---
> > Documentation/devicetree/bindings/spi/spi-mt65xx.txt | 1 +
> > 1 file changed, 1 insertion(+)
> >
>
>
> applied to v5.1-next/dts64
>
> Mark let me know if you want to take it through your tree and I drop the patch.
>
> > diff --git a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
> > index 69c356767cf8..69ac5976b952 100644
> > --- a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
> > +++ b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
> > @@ -10,6 +10,7 @@ Required properties:
> > - mediatek,mt8135-spi: for mt8135 platforms
> > - mediatek,mt8173-spi: for mt8173 platforms
> > - mediatek,mt8183-spi: for mt8183 platforms
> > + - "mediatek,mt8516-spi", "mediatek,mt2701-spi": for mt8516 platforms
Hi Fabien,
mt8516 SPI design comes from mt2712 and it's different from mt2701. Here
it should compatible with mt2712.
> >
> > - #address-cells: should be 1.
> >
> >
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply
* Re: [PATCH 22/24] dt-bindings: i2c: i2c-mtk: add support for MT8516
From: Wolfram Sang @ 2019-04-16 8:14 UTC (permalink / raw)
To: Matthias Brugger
Cc: Fabien Parent, robh+dt, mark.rutland, sean.wang, ryder.lee,
hsin-hsiung.wang, wenzhen.yu, chaotian.jing, yong.mao, jjian.zhou,
devicetree, linux-kernel, linux-i2c, linux-arm-kernel,
linux-mediatek, linux-mmc, linux-gpio, linux-serial, linux-spi,
linux-watchdog, linux-clk, stephane.leprovost
In-Reply-To: <2a384e4b-a23d-450b-ee37-57af8c097bae@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 624 bytes --]
On Tue, Apr 16, 2019 at 09:58:09AM +0200, Matthias Brugger wrote:
>
>
> On 23/03/2019 22:16, Fabien Parent wrote:
> > Add binding documentation of i2c-mtk for MT8516 SoC.
> >
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > ---
> > Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 1 +
> > 1 file changed, 1 insertion(+)
> >
>
>
> applied to v5.1-next/dts64
>
> Wolfram let me know if you want to take it through your tree and I drop the patch.
I'd like to take it via my tree to reduce conflicts. It already needs
rebasing on top of i2c/for-next because of Qii's MT8183 patches.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* [PATCH v10] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile
From: Erin Lo @ 2019-04-16 8:12 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Mark Rutland
Cc: devicetree, srv_heupstream, linux-kernel, linux-serial,
linux-mediatek, linux-arm-kernel, erin.lo, mars.cheng,
eddie.huang, Ben Ho, Seiya Wang, Weiyi Lu, Hsin-Hsiung Wang
In-Reply-To: <1555402331-5343-1-git-send-email-erin.lo@mediatek.com>
From: Ben Ho <Ben.Ho@mediatek.com>
Add basic chip support for Mediatek 8183, include
uart node with correct uart clocks, pwrap device
Add clock controller nodes, include topckgen, infracfg,
apmixedsys and subsystem.
Signed-off-by: Ben Ho <Ben.Ho@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
---
Based on v5.1-rc1 and
https://patchwork.kernel.org/cover/10838993/
Which already in clk-next
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git/commit/?h=clk-mtk&id=2f41cd9b13ea891e7cc1bd037b70458132a12e31
---
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 31 +++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 329 ++++++++++++++++++++++++++++
3 files changed, 361 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index e8f952f..458bbc4 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
new file mode 100644
index 0000000..9b52559
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Ben Ho <ben.ho@mediatek.com>
+ * Erin Lo <erin.lo@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt8183.dtsi"
+
+/ {
+ model = "MediaTek MT8183 evaluation board";
+ compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
new file mode 100644
index 0000000..23d1ad6
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -0,0 +1,329 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Ben Ho <ben.ho@mediatek.com>
+ * Erin Lo <erin.lo@mediatek.com>
+ */
+
+#include <dt-bindings/clock/mt8183-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "mediatek,mt8183";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ next-level-cache = <&a53_l2>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ next-level-cache = <&a53_l2>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x002>;
+ enable-method = "psci";
+ next-level-cache = <&a53_l2>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x003>;
+ enable-method = "psci";
+ next-level-cache = <&a53_l2>;
+ };
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x100>;
+ enable-method = "psci";
+ next-level-cache = <&a73_l2>;
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x101>;
+ enable-method = "psci";
+ next-level-cache = <&a73_l2>;
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x102>;
+ enable-method = "psci";
+ next-level-cache = <&a73_l2>;
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x103>;
+ enable-method = "psci";
+ next-level-cache = <&a73_l2>;
+ };
+
+ a53_l2: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+
+ a73_l2: l2-cache1 {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ pmu-a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
+ };
+
+ pmu-a73 {
+ compatible = "arm,cortex-a73-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ clk26m: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>, /* GICD */
+ <0 0x0c100000 0 0x200000>, /* GICR */
+ <0 0x0c400000 0 0x2000>, /* GICC */
+ <0 0x0c410000 0 0x1000>, /* GICH */
+ <0 0x0c420000 0 0x2000>; /* GICV */
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ };
+ };
+ };
+
+ mcucfg: syscon@c530000 {
+ compatible = "mediatek,mt8183-mcucfg", "syscon";
+ reg = <0 0x0c530000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ sysirq: interrupt-controller@c530a80 {
+ compatible = "mediatek,mt8183-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x0c530a80 0 0x50>;
+ };
+
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8183-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt8183-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8183-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pwrap: pwrap@1000d000 {
+ compatible = "mediatek,mt8183-pwrap";
+ reg = <0 0x1000d000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
+ <&infracfg CLK_INFRA_PMIC_AP>;
+ clock-names = "spi", "wrap";
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt8183-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x1000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt8183-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x1000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11004000 {
+ compatible = "mediatek,mt8183-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x1000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ audiosys: syscon@11220000 {
+ compatible = "mediatek,mt8183-audiosys", "syscon";
+ reg = <0 0x11220000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mfgcfg: syscon@13000000 {
+ compatible = "mediatek,mt8183-mfgcfg", "syscon";
+ reg = <0 0x13000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt8183-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys: syscon@15020000 {
+ compatible = "mediatek,mt8183-imgsys", "syscon";
+ reg = <0 0x15020000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: syscon@16000000 {
+ compatible = "mediatek,mt8183-vdecsys", "syscon";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: syscon@17000000 {
+ compatible = "mediatek,mt8183-vencsys", "syscon";
+ reg = <0 0x17000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ipu_conn: syscon@19000000 {
+ compatible = "mediatek,mt8183-ipu_conn", "syscon";
+ reg = <0 0x19000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ipu_adl: syscon@19010000 {
+ compatible = "mediatek,mt8183-ipu_adl", "syscon";
+ reg = <0 0x19010000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ipu_core0: syscon@19180000 {
+ compatible = "mediatek,mt8183-ipu_core0", "syscon";
+ reg = <0 0x19180000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ipu_core1: syscon@19280000 {
+ compatible = "mediatek,mt8183-ipu_core1", "syscon";
+ reg = <0 0x19280000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: syscon@1a000000 {
+ compatible = "mediatek,mt8183-camsys", "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related
* [PATCH v10] Add basic and clock support for Mediatek MT8183 SoC
From: Erin Lo @ 2019-04-16 8:12 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Mark Rutland
Cc: devicetree, srv_heupstream, linux-kernel, linux-serial,
linux-mediatek, linux-arm-kernel, erin.lo, mars.cheng,
eddie.huang
MT8183 is a SoC based on 64bit ARMv8 architecture.
It contains 4 CA53 and 4 CA73 cores.
MT8183 share many HW IP with MT65xx series.
This patchset was tested on MT8183 evaluation board and use correct clock to shell.
Based on v5.1-rc1 and
http://lists.infradead.org/pipermail/linux-mediatek/2019-March/017963.html
Change in v10:
Add the L2 cache node to prevent warning on unable to detect cache
hierarchy.
Change in v9:
Remove pio node since binding is not documented yet
Change in v8:
1. Fix interrupt-parent of pio node
2. Remove pinfunc.h and spi node patches
Change in v7:
1. Place all the MMIO peripherals under one or more simple-bus nodes
2. Make the pinfunc.h and spi node into seperate patch
3. Modify SPIs pamerater from 4 back to 3
and remove patch "support 4 interrupt parameters for sysirq"
4. Rename intpol-controller to interrupt-controller
5. Rename pinctrl@1000b000 to pinctrl@10005000
Change in v6:
1. Remove power and iommu nodes
2. Fix dtb build warning
3. Fix pinctrl binding doc
4. Fix '_' in node names
Change in v5:
1. Collect all device tree nodes to the last patch
2. Add PMU
3. Add Signed-off-by
4. Remove clock driver code and binding doc
5. Add pinctrl, iommu, spi, and pwrap nodes
Change in v4:
1. Correct syntax error in dtsi
2. Add MT8183 clock support
Change in v3:
1. Fill out GICC, GICH, GICV regions
2. Update Copyright to 2018
Change in v2:
1. Split dt-bindings into different patches
2. Correct bindings for supported SoCs (mtk-uart.txt)
Ben Ho (1):
arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and
Makefile
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 31 +++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 329 ++++++++++++++++++++++++++++
3 files changed, 361 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi
--
1.9.1
^ permalink raw reply
* Re: [PATCH 18/24] dt-bindings: timer: mtk-timer: add support for MT8516
From: Daniel Lezcano @ 2019-04-16 8:09 UTC (permalink / raw)
To: Matthias Brugger, Fabien Parent, robh+dt, mark.rutland
Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu, chaotian.jing,
yong.mao, jjian.zhou, devicetree, linux-kernel, linux-i2c,
linux-arm-kernel, linux-mediatek, linux-mmc, linux-gpio,
linux-serial, linux-spi, linux-watchdog, linux-clk,
stephane.leprovost
In-Reply-To: <182f1ae5-9f4f-8ef4-695f-353bbd1966c6@gmail.com>
On 16/04/2019 09:54, Matthias Brugger wrote:
>
>
> On 23/03/2019 22:16, Fabien Parent wrote:
>> Add binding documentation of mtk-timer for MT8516 SoC.
>>
>> Signed-off-by: Fabien Parent <fparent@baylibre.com>
>> ---
>> Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
>> 1 file changed, 1 insertion(+)
>
> applied to v5.1-next/dts64
>
> Daniel let me know if you want to take it through your tree and I drop the patch.
It is ok.
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
>> diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
>> index ff7c567a7972..74c3eadad844 100644
>> --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
>> +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
>> @@ -17,6 +17,7 @@ Required properties:
>> * "mediatek,mt8127-timer" for MT8127 compatible timers (GPT)
>> * "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
>> * "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
>> + * "mediatek,mt8516-timer" for MT8516 compatible timers (GPT)
>> * "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)
>>
>> For those SoCs that use SYST
>>
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* Re: [PATCH 23/24] arm64: dts: mediatek: add dtsi for MT8516
From: Matthias Brugger @ 2019-04-16 8:04 UTC (permalink / raw)
To: Rob Herring, Fabien Parent
Cc: Mark Rutland, Sean Wang, Ryder Lee, Hsin-Hsiung Wang, Wenzhen Yu,
Chaotian Jing, Yong Mao, jjian.zhou, devicetree,
linux-kernel@vger.kernel.org, Linux I2C,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
moderated list:ARM/Mediatek SoC support, linux-mmc,
open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS
In-Reply-To: <CAL_Jsq+Q06O84-MTpgTWGG312VXm_vGOkjMCjtWuS0eZ-j_0yw@mail.gmail.com>
On 28/03/2019 20:22, Rob Herring wrote:
> On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent <fparent@baylibre.com> wrote:
>>
>> The MT8516 SoC provides the following peripherals: GPIO, UART, USB2,
>> SPI, eMMC, SDIO, NAND, Flash, ADC, I2C, PWM, Timers, IR, Ethernet, and
>> Audio (I2S, SPDIF, TDM).
>>
>> This commit is adding the basic dtsi file with the support of the
>> following IOs: GPIO, UART, SPI, eMMC, I2C, Timers.
>>
>> Signed-off-by: Fabien Parent <fparent@baylibre.com>
>> ---
>> arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h | 663 ++++++++++++++++++
>> arch/arm64/boot/dts/mediatek/mt8516.dtsi | 409 +++++++++++
>> 2 files changed, 1072 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h
>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8516.dtsi
>
> Reviewed-by: Rob Herring <robh@kernel.org>
>
Fabien, before taking this through my tree, I'd like to see the drivers merged.
Can you please resubmit taking into account the outcome of get_maintainers.pl
script. From my experience it is easier to send one series per driver, as it
makes the amount of emails every maintainer gets more manageable.
Regards,
Matthias
^ permalink raw reply
* Re: [PATCH 22/24] dt-bindings: i2c: i2c-mtk: add support for MT8516
From: Matthias Brugger @ 2019-04-16 7:58 UTC (permalink / raw)
To: Fabien Parent, robh+dt, mark.rutland, Wolfram Sang
Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu, chaotian.jing,
yong.mao, jjian.zhou, devicetree, linux-kernel, linux-i2c,
linux-arm-kernel, linux-mediatek, linux-mmc, linux-gpio,
linux-serial, linux-spi, linux-watchdog, linux-clk,
stephane.leprovost
In-Reply-To: <20190323211612.860-23-fparent@baylibre.com>
On 23/03/2019 22:16, Fabien Parent wrote:
> Add binding documentation of i2c-mtk for MT8516 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
> Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 1 +
> 1 file changed, 1 insertion(+)
>
applied to v5.1-next/dts64
Wolfram let me know if you want to take it through your tree and I drop the patch.
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
> index ee4c32454198..aac7b56f251f 100644
> --- a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
> +++ b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
> @@ -12,6 +12,7 @@ Required properties:
> "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
> "mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
> "mediatek,mt8173-i2c": for MediaTek MT8173
> + "mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516
> - reg: physical base address of the controller and dma base, length of memory
> mapped region.
> - interrupts: interrupt number to the cpu.
>
^ permalink raw reply
* Re: [PATCH 21/24] dt-bindings: irq: mtk,sysirq: add support for MT8516
From: Matthias Brugger @ 2019-04-16 7:57 UTC (permalink / raw)
To: Fabien Parent, robh+dt, mark.rutland
Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu, chaotian.jing,
yong.mao, jjian.zhou, devicetree, linux-kernel, linux-i2c,
linux-arm-kernel, linux-mediatek, linux-mmc, linux-gpio,
linux-serial, linux-spi, linux-watchdog, linux-clk,
stephane.leprovost
In-Reply-To: <20190323211612.860-22-fparent@baylibre.com>
On 23/03/2019 22:16, Fabien Parent wrote:
> Add binding documentation of mediatek,sysirq for MT8516 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
> .../bindings/interrupt-controller/mediatek,sysirq.txt | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
applied to v5.1-next/dts64
Thanks
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> index c5d589108a94..deaaba70d548 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> @@ -1,10 +1,11 @@
> -+Mediatek MT65xx/MT67xx/MT81xx sysirq
> ++Mediatek MT65xx/MT67xx/MT81xx/MT85xx sysirq
>
> Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
> interrupt.
>
> Required properties:
> - compatible: should be
> + "mediatek,mt8516-sysirq", "mediatek,mt6577-sysirq": for MT8516
> "mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
> "mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
> "mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
>
^ permalink raw reply
* Re: [PATCH 20/24] dt-bindings: serial: mtk-uart: add support for MT8516
From: Matthias Brugger @ 2019-04-16 7:56 UTC (permalink / raw)
To: Fabien Parent, robh+dt, mark.rutland
Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu, chaotian.jing,
yong.mao, jjian.zhou, devicetree, linux-kernel, linux-i2c,
linux-arm-kernel, linux-mediatek, linux-mmc, linux-gpio,
linux-serial, linux-spi, linux-watchdog, linux-clk,
stephane.leprovost
In-Reply-To: <20190323211612.860-21-fparent@baylibre.com>
On 23/03/2019 22:16, Fabien Parent wrote:
> Add binding documentation of mtk-uart for MT8516 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
> Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
> 1 file changed, 1 insertion(+)
>
applied to v5.1-next/dts64
Thanks.
> diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
> index 742cb470595b..1af981f7a33b 100644
> --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
> +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
> @@ -16,6 +16,7 @@ Required properties:
> * "mediatek,mt8127-uart" for MT8127 compatible UARTS
> * "mediatek,mt8135-uart" for MT8135 compatible UARTS
> * "mediatek,mt8173-uart" for MT8173 compatible UARTS
> + * "mediatek,mt8516-uart" for MT8516 compatible UARTS
> * "mediatek,mt6577-uart" for MT6577 and all of the above
>
> - reg: The base address of the UART register bank.
>
^ permalink raw reply
* Re: [PATCH 19/24] dt-bindings: spi: spi-mt65xx: add support for MT8516
From: Matthias Brugger @ 2019-04-16 7:55 UTC (permalink / raw)
To: Fabien Parent, robh+dt, mark.rutland, Mark Brown
Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu, chaotian.jing,
yong.mao, jjian.zhou, devicetree, linux-kernel, linux-i2c,
linux-arm-kernel, linux-mediatek, linux-mmc, linux-gpio,
linux-serial, linux-spi, linux-watchdog, linux-clk,
stephane.leprovost
In-Reply-To: <20190323211612.860-20-fparent@baylibre.com>
On 23/03/2019 22:16, Fabien Parent wrote:
> Add binding documentation of spi-mt65xx for MT8516 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
> Documentation/devicetree/bindings/spi/spi-mt65xx.txt | 1 +
> 1 file changed, 1 insertion(+)
>
applied to v5.1-next/dts64
Mark let me know if you want to take it through your tree and I drop the patch.
> diff --git a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
> index 69c356767cf8..69ac5976b952 100644
> --- a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
> +++ b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
> @@ -10,6 +10,7 @@ Required properties:
> - mediatek,mt8135-spi: for mt8135 platforms
> - mediatek,mt8173-spi: for mt8173 platforms
> - mediatek,mt8183-spi: for mt8183 platforms
> + - "mediatek,mt8516-spi", "mediatek,mt2701-spi": for mt8516 platforms
>
> - #address-cells: should be 1.
>
>
^ permalink raw reply
* Re: [PATCH 18/24] dt-bindings: timer: mtk-timer: add support for MT8516
From: Matthias Brugger @ 2019-04-16 7:54 UTC (permalink / raw)
To: Fabien Parent, robh+dt, mark.rutland, Daniel Lezcano
Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu, chaotian.jing,
yong.mao, jjian.zhou, devicetree, linux-kernel, linux-i2c,
linux-arm-kernel, linux-mediatek, linux-mmc, linux-gpio,
linux-serial, linux-spi, linux-watchdog, linux-clk,
stephane.leprovost
In-Reply-To: <20190323211612.860-19-fparent@baylibre.com>
On 23/03/2019 22:16, Fabien Parent wrote:
> Add binding documentation of mtk-timer for MT8516 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
> Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
> 1 file changed, 1 insertion(+)
applied to v5.1-next/dts64
Daniel let me know if you want to take it through your tree and I drop the patch.
>
> diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
> index ff7c567a7972..74c3eadad844 100644
> --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
> +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
> @@ -17,6 +17,7 @@ Required properties:
> * "mediatek,mt8127-timer" for MT8127 compatible timers (GPT)
> * "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
> * "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
> + * "mediatek,mt8516-timer" for MT8516 compatible timers (GPT)
> * "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)
>
> For those SoCs that use SYST
>
^ permalink raw reply
* [PATCH 6/6] ARM: ks8695: split up uart register headers
From: Arnd Bergmann @ 2019-04-15 20:24 UTC (permalink / raw)
To: Greg Ungerer
Cc: Linus Walleij, arm, Arnd Bergmann, Greg Kroah-Hartman, Jiri Slaby,
linux-arm-kernel, linux-kernel, linux-serial
In-Reply-To: <20190415202501.941196-1-arnd@arndb.de>
The uart driver is tightly coupled with the platform code, without
real need. The uart registers can be moved into the driver itself
(and the uncompress code), and instead of referring to the IRQ
lines by number, we can generally use port->irq.
Finally, the initialization of the uart_port structure gets moved
into the platform code. This cannot use platform_data since we
need it before console_init(), but map_io is called very early,
and the data is all hardcoded.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/mach-ks8695/cpu.c | 15 ++-
arch/arm/mach-ks8695/devices.c | 2 +-
arch/arm/mach-ks8695/include/mach/regs-uart.h | 92 -------------
.../arm/mach-ks8695/include/mach/uncompress.h | 16 ++-
arch/arm/mach-ks8695/regs-uart.h | 19 +++
drivers/tty/serial/Kconfig | 2 +-
drivers/tty/serial/serial_ks8695.c | 123 ++++++++++++++----
include/linux/platform_data/serial-ks8695.h | 10 ++
8 files changed, 157 insertions(+), 122 deletions(-)
delete mode 100644 arch/arm/mach-ks8695/include/mach/regs-uart.h
create mode 100644 arch/arm/mach-ks8695/regs-uart.h
create mode 100644 include/linux/platform_data/serial-ks8695.h
diff --git a/arch/arm/mach-ks8695/cpu.c b/arch/arm/mach-ks8695/cpu.c
index 7eadf73c7e30..680b94641196 100644
--- a/arch/arm/mach-ks8695/cpu.c
+++ b/arch/arm/mach-ks8695/cpu.c
@@ -25,6 +25,7 @@
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/platform_data/serial-ks8695.h>
#include <mach/hardware.h>
#include <asm/mach/arch.h>
@@ -32,7 +33,7 @@
#include "regs-sys.h"
#include "regs-misc.h"
-
+#include "regs-uart.h"
static struct map_desc ks8695_io_desc[] __initdata = {
{
@@ -64,10 +65,22 @@ static void __init ks8695_clock_info(void)
sysclk[scdc] / 1000000, cpuclk[scdc] / 1000000);
}
+static void __init ks8695_serial_setup(void)
+{
+ if (!IS_ENABLED(CONFIG_SERIAL_KS8695))
+ return;
+
+ ks8695uart_ports[0].membase = KS8695_UART_VA;
+ ks8695uart_ports[0].mapbase = KS8695_UART_PA;
+ ks8695uart_ports[0].irq = KS8695_IRQ_UART_TX; /* actaully four IRQs */
+ ks8695uart_ports[0].uartclk = KS8695_CLOCK_RATE * 16;
+}
+
void __init ks8695_map_io(void)
{
iotable_init(ks8695_io_desc, ARRAY_SIZE(ks8695_io_desc));
ks8695_processor_info();
ks8695_clock_info();
+ ks8695_serial_setup();
}
diff --git a/arch/arm/mach-ks8695/devices.c b/arch/arm/mach-ks8695/devices.c
index 6bd50a8f12f9..ba9d0f0f47ac 100644
--- a/arch/arm/mach-ks8695/devices.c
+++ b/arch/arm/mach-ks8695/devices.c
@@ -29,6 +29,7 @@
#include "regs-hpna.h"
#include "regs-switch.h"
#include "regs-misc.h"
+#include "regs-uart.h"
/* --------------------------------------------------------------------
* Ethernet
@@ -191,7 +192,6 @@ static void __init ks8695_add_device_watchdog(void)
platform_device_register(&ks8695_wdt_device);
}
-
/* -------------------------------------------------------------------- */
/*
diff --git a/arch/arm/mach-ks8695/include/mach/regs-uart.h b/arch/arm/mach-ks8695/include/mach/regs-uart.h
deleted file mode 100644
index 8581fbc6245f..000000000000
--- a/arch/arm/mach-ks8695/include/mach/regs-uart.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * arch/arm/mach-ks8695/include/mach/regs-uart.h
- *
- * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
- * Copyright (C) 2006 Simtec Electronics
- *
- * KS8695 - UART register and bit definitions.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef KS8695_UART_H
-#define KS8695_UART_H
-
-#define KS8695_UART_OFFSET (0xF0000 + 0xE000)
-#define KS8695_UART_VA (KS8695_IO_VA + KS8695_UART_OFFSET)
-#define KS8695_UART_PA (KS8695_IO_PA + KS8695_UART_OFFSET)
-
-
-/*
- * UART registers
- */
-#define KS8695_URRB (0x00) /* Receive Buffer Register */
-#define KS8695_URTH (0x04) /* Transmit Holding Register */
-#define KS8695_URFC (0x08) /* FIFO Control Register */
-#define KS8695_URLC (0x0C) /* Line Control Register */
-#define KS8695_URMC (0x10) /* Modem Control Register */
-#define KS8695_URLS (0x14) /* Line Status Register */
-#define KS8695_URMS (0x18) /* Modem Status Register */
-#define KS8695_URBD (0x1C) /* Baud Rate Divisor Register */
-#define KS8695_USR (0x20) /* Status Register */
-
-
-/* FIFO Control Register */
-#define URFC_URFRT (3 << 6) /* Receive FIFO Trigger Level */
-#define URFC_URFRT_1 (0 << 6)
-#define URFC_URFRT_4 (1 << 6)
-#define URFC_URFRT_8 (2 << 6)
-#define URFC_URFRT_14 (3 << 6)
-#define URFC_URTFR (1 << 2) /* Transmit FIFO Reset */
-#define URFC_URRFR (1 << 1) /* Receive FIFO Reset */
-#define URFC_URFE (1 << 0) /* FIFO Enable */
-
-/* Line Control Register */
-#define URLC_URSBC (1 << 6) /* Set Break Condition */
-#define URLC_PARITY (7 << 3) /* Parity */
-#define URPE_NONE (0 << 3)
-#define URPE_ODD (1 << 3)
-#define URPE_EVEN (3 << 3)
-#define URPE_MARK (5 << 3)
-#define URPE_SPACE (7 << 3)
-#define URLC_URSB (1 << 2) /* Stop Bits */
-#define URLC_URCL (3 << 0) /* Character Length */
-#define URCL_5 (0 << 0)
-#define URCL_6 (1 << 0)
-#define URCL_7 (2 << 0)
-#define URCL_8 (3 << 0)
-
-/* Modem Control Register */
-#define URMC_URLB (1 << 4) /* Loop-back mode */
-#define URMC_UROUT2 (1 << 3) /* OUT2 signal */
-#define URMC_UROUT1 (1 << 2) /* OUT1 signal */
-#define URMC_URRTS (1 << 1) /* Request to Send */
-#define URMC_URDTR (1 << 0) /* Data Terminal Ready */
-
-/* Line Status Register */
-#define URLS_URRFE (1 << 7) /* Receive FIFO Error */
-#define URLS_URTE (1 << 6) /* Transmit Empty */
-#define URLS_URTHRE (1 << 5) /* Transmit Holding Register Empty */
-#define URLS_URBI (1 << 4) /* Break Interrupt */
-#define URLS_URFE (1 << 3) /* Framing Error */
-#define URLS_URPE (1 << 2) /* Parity Error */
-#define URLS_URROE (1 << 1) /* Receive Overrun Error */
-#define URLS_URDR (1 << 0) /* Receive Data Ready */
-
-/* Modem Status Register */
-#define URMS_URDCD (1 << 7) /* Data Carrier Detect */
-#define URMS_URRI (1 << 6) /* Ring Indicator */
-#define URMS_URDSR (1 << 5) /* Data Set Ready */
-#define URMS_URCTS (1 << 4) /* Clear to Send */
-#define URMS_URDDCD (1 << 3) /* Delta Data Carrier Detect */
-#define URMS_URTERI (1 << 2) /* Trailing Edge Ring Indicator */
-#define URMS_URDDST (1 << 1) /* Delta Data Set Ready */
-#define URMS_URDCTS (1 << 0) /* Delta Clear to Send */
-
-/* Status Register */
-#define USR_UTI (1 << 0) /* Timeout Indication */
-
-
-#endif
diff --git a/arch/arm/mach-ks8695/include/mach/uncompress.h b/arch/arm/mach-ks8695/include/mach/uncompress.h
index a001c7c34df2..a8ae2e82dcf1 100644
--- a/arch/arm/mach-ks8695/include/mach/uncompress.h
+++ b/arch/arm/mach-ks8695/include/mach/uncompress.h
@@ -15,7 +15,21 @@
#define __ASM_ARCH_UNCOMPRESS_H
#include <linux/io.h>
-#include <mach/regs-uart.h>
+
+#define KS8695_UART_OFFSET (0xF0000 + 0xE000)
+#define KS8695_UART_PA (KS8695_IO_PA + KS8695_UART_OFFSET)
+#define KS8695_URRB (0x00) /* Receive Buffer Register */
+#define KS8695_URTH (0x04) /* Transmit Holding Register */
+#define KS8695_URFC (0x08) /* FIFO Control Register */
+#define KS8695_URLC (0x0C) /* Line Control Register */
+#define KS8695_URMC (0x10) /* Modem Control Register */
+#define KS8695_URLS (0x14) /* Line Status Register */
+#define KS8695_URMS (0x18) /* Modem Status Register */
+#define KS8695_URBD (0x1C) /* Baud Rate Divisor Register */
+#define KS8695_USR (0x20) /* Status Register */
+
+#define URLS_URTE (1 << 6)
+#define URLS_URTHRE (1 << 5)
static inline void putc(char c)
{
diff --git a/arch/arm/mach-ks8695/regs-uart.h b/arch/arm/mach-ks8695/regs-uart.h
new file mode 100644
index 000000000000..ab6c70e8fc7a
--- /dev/null
+++ b/arch/arm/mach-ks8695/regs-uart.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
+ * Copyright (C) 2006 Simtec Electronics
+ *
+ * KS8695 - UART register and bit definitions.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef KS8695_UART_H
+#define KS8695_UART_H
+
+#define KS8695_UART_OFFSET (0xF0000 + 0xE000)
+#define KS8695_UART_VA (KS8695_IO_VA + KS8695_UART_OFFSET)
+#define KS8695_UART_PA (KS8695_IO_PA + KS8695_UART_OFFSET)
+
+#endif
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 72966bc0ac76..bdb3fc987ea2 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -198,7 +198,7 @@ config SERIAL_KGDB_NMI
config SERIAL_KS8695
bool "Micrel KS8695 (Centaur) serial port support"
- depends on ARCH_KS8695
+ depends on ARCH_KS8695 || COMPILE_TEST
select SERIAL_CORE
help
This selects the Micrel Centaur KS8695 UART. Say Y here.
diff --git a/drivers/tty/serial/serial_ks8695.c b/drivers/tty/serial/serial_ks8695.c
index 6c5e9900e69d..6caad7e5ab74 100644
--- a/drivers/tty/serial/serial_ks8695.c
+++ b/drivers/tty/serial/serial_ks8695.c
@@ -15,12 +15,11 @@
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/device.h>
+#include <linux/irq.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
+#include <linux/platform_data/serial-ks8695.h>
-#include <mach/regs-uart.h>
+#include <asm/io.h>
#if defined(CONFIG_SERIAL_KS8695_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
#define SUPPORT_SYSRQ
@@ -34,6 +33,82 @@
#define SERIAL_KS8695_DEVNAME "ttyAM"
#define SERIAL_KS8695_NR 1
+extern struct uart_port ks8695uart_ports[SERIAL_KS8695_NR];
+
+/*
+ * UART registers
+ */
+#define KS8695_URRB (0x00) /* Receive Buffer Register */
+#define KS8695_URTH (0x04) /* Transmit Holding Register */
+#define KS8695_URFC (0x08) /* FIFO Control Register */
+#define KS8695_URLC (0x0C) /* Line Control Register */
+#define KS8695_URMC (0x10) /* Modem Control Register */
+#define KS8695_URLS (0x14) /* Line Status Register */
+#define KS8695_URMS (0x18) /* Modem Status Register */
+#define KS8695_URBD (0x1C) /* Baud Rate Divisor Register */
+#define KS8695_USR (0x20) /* Status Register */
+
+
+/* FIFO Control Register */
+#define URFC_URFRT (3 << 6) /* Receive FIFO Trigger Level */
+#define URFC_URFRT_1 (0 << 6)
+#define URFC_URFRT_4 (1 << 6)
+#define URFC_URFRT_8 (2 << 6)
+#define URFC_URFRT_14 (3 << 6)
+#define URFC_URTFR (1 << 2) /* Transmit FIFO Reset */
+#define URFC_URRFR (1 << 1) /* Receive FIFO Reset */
+#define URFC_URFE (1 << 0) /* FIFO Enable */
+
+/* Line Control Register */
+#define URLC_URSBC (1 << 6) /* Set Break Condition */
+#define URLC_PARITY (7 << 3) /* Parity */
+#define URPE_NONE (0 << 3)
+#define URPE_ODD (1 << 3)
+#define URPE_EVEN (3 << 3)
+#define URPE_MARK (5 << 3)
+#define URPE_SPACE (7 << 3)
+#define URLC_URSB (1 << 2) /* Stop Bits */
+#define URLC_URCL (3 << 0) /* Character Length */
+#define URCL_5 (0 << 0)
+#define URCL_6 (1 << 0)
+#define URCL_7 (2 << 0)
+#define URCL_8 (3 << 0)
+
+/* Modem Control Register */
+#define URMC_URLB (1 << 4) /* Loop-back mode */
+#define URMC_UROUT2 (1 << 3) /* OUT2 signal */
+#define URMC_UROUT1 (1 << 2) /* OUT1 signal */
+#define URMC_URRTS (1 << 1) /* Request to Send */
+#define URMC_URDTR (1 << 0) /* Data Terminal Ready */
+
+/* Line Status Register */
+#define URLS_URRFE (1 << 7) /* Receive FIFO Error */
+#define URLS_URTE (1 << 6) /* Transmit Empty */
+#define URLS_URTHRE (1 << 5) /* Transmit Holding Register Empty */
+#define URLS_URBI (1 << 4) /* Break Interrupt */
+#define URLS_URFE (1 << 3) /* Framing Error */
+#define URLS_URPE (1 << 2) /* Parity Error */
+#define URLS_URROE (1 << 1) /* Receive Overrun Error */
+#define URLS_URDR (1 << 0) /* Receive Data Ready */
+
+/* Modem Status Register */
+#define URMS_URDCD (1 << 7) /* Data Carrier Detect */
+#define URMS_URRI (1 << 6) /* Ring Indicator */
+#define URMS_URDSR (1 << 5) /* Data Set Ready */
+#define URMS_URCTS (1 << 4) /* Clear to Send */
+#define URMS_URDDCD (1 << 3) /* Delta Data Carrier Detect */
+#define URMS_URTERI (1 << 2) /* Trailing Edge Ring Indicator */
+#define URMS_URDDST (1 << 1) /* Delta Data Set Ready */
+#define URMS_URDCTS (1 << 0) /* Delta Clear to Send */
+
+/* Status Register */
+#define USR_UTI (1 << 0) /* Timeout Indication */
+
+
+#define IRQ_TX 0
+#define IRQ_RX 1
+#define IRQ_LINE_STATUS 2
+#define IRQ_MODEM_STATUS 3
/*
* Access macros for the KS8695 UART
@@ -105,7 +180,7 @@ static void ks8695uart_stop_tx(struct uart_port *port)
* imposed deadlock by not waiting for irq handler to end,
* since this ks8695uart_stop_tx() is called from interrupt context.
*/
- disable_irq_nosync(KS8695_IRQ_UART_TX);
+ disable_irq_nosync(port->irq + IRQ_TX);
tx_enable(port, 0);
}
}
@@ -113,7 +188,7 @@ static void ks8695uart_stop_tx(struct uart_port *port)
static void ks8695uart_start_tx(struct uart_port *port)
{
if (!tx_enabled(port)) {
- enable_irq(KS8695_IRQ_UART_TX);
+ enable_irq(port->irq + IRQ_TX);
tx_enable(port, 1);
}
}
@@ -121,7 +196,7 @@ static void ks8695uart_start_tx(struct uart_port *port)
static void ks8695uart_stop_rx(struct uart_port *port)
{
if (rx_enabled(port)) {
- disable_irq(KS8695_IRQ_UART_RX);
+ disable_irq(port->irq + IRQ_RX);
rx_enable(port, 0);
}
}
@@ -129,7 +204,7 @@ static void ks8695uart_stop_rx(struct uart_port *port)
static void ks8695uart_enable_ms(struct uart_port *port)
{
if (!ms_enabled(port)) {
- enable_irq(KS8695_IRQ_UART_MODEM_STATUS);
+ enable_irq(port->irq + IRQ_MODEM_STATUS);
ms_enable(port,1);
}
}
@@ -137,7 +212,7 @@ static void ks8695uart_enable_ms(struct uart_port *port)
static void ks8695uart_disable_ms(struct uart_port *port)
{
if (ms_enabled(port)) {
- disable_irq(KS8695_IRQ_UART_MODEM_STATUS);
+ disable_irq(port->irq + IRQ_MODEM_STATUS);
ms_enable(port,0);
}
}
@@ -318,7 +393,7 @@ static int ks8695uart_startup(struct uart_port *port)
{
int retval;
- irq_modify_status(KS8695_IRQ_UART_TX, IRQ_NOREQUEST, IRQ_NOAUTOEN);
+ irq_modify_status(port->irq + IRQ_TX, IRQ_NOREQUEST, IRQ_NOAUTOEN);
tx_enable(port, 0);
rx_enable(port, 1);
ms_enable(port, 1);
@@ -326,30 +401,30 @@ static int ks8695uart_startup(struct uart_port *port)
/*
* Allocate the IRQ
*/
- retval = request_irq(KS8695_IRQ_UART_TX, ks8695uart_tx_chars, 0, "UART TX", port);
+ retval = request_irq(port->irq + IRQ_TX, ks8695uart_tx_chars, 0, "UART TX", port);
if (retval)
goto err_tx;
- retval = request_irq(KS8695_IRQ_UART_RX, ks8695uart_rx_chars, 0, "UART RX", port);
+ retval = request_irq(port->irq + IRQ_RX, ks8695uart_rx_chars, 0, "UART RX", port);
if (retval)
goto err_rx;
- retval = request_irq(KS8695_IRQ_UART_LINE_STATUS, ks8695uart_rx_chars, 0, "UART LineStatus", port);
+ retval = request_irq(port->irq + IRQ_LINE_STATUS, ks8695uart_rx_chars, 0, "UART LineStatus", port);
if (retval)
goto err_ls;
- retval = request_irq(KS8695_IRQ_UART_MODEM_STATUS, ks8695uart_modem_status, 0, "UART ModemStatus", port);
+ retval = request_irq(port->irq + IRQ_MODEM_STATUS, ks8695uart_modem_status, 0, "UART ModemStatus", port);
if (retval)
goto err_ms;
return 0;
err_ms:
- free_irq(KS8695_IRQ_UART_LINE_STATUS, port);
+ free_irq(port->irq + IRQ_LINE_STATUS, port);
err_ls:
- free_irq(KS8695_IRQ_UART_RX, port);
+ free_irq(port->irq + IRQ_RX, port);
err_rx:
- free_irq(KS8695_IRQ_UART_TX, port);
+ free_irq(port->irq + IRQ_TX, port);
err_tx:
return retval;
}
@@ -359,10 +434,10 @@ static void ks8695uart_shutdown(struct uart_port *port)
/*
* Free the interrupt
*/
- free_irq(KS8695_IRQ_UART_RX, port);
- free_irq(KS8695_IRQ_UART_TX, port);
- free_irq(KS8695_IRQ_UART_MODEM_STATUS, port);
- free_irq(KS8695_IRQ_UART_LINE_STATUS, port);
+ free_irq(port->irq + IRQ_TX, port);
+ free_irq(port->irq + IRQ_RX, port);
+ free_irq(port->irq + IRQ_MODEM_STATUS, port);
+ free_irq(port->irq + IRQ_LINE_STATUS, port);
/* disable break condition and fifos */
UART_PUT_LCR(port, UART_GET_LCR(port) & ~URLC_URSBC);
@@ -535,13 +610,9 @@ static struct uart_ops ks8695uart_pops = {
.verify_port = ks8695uart_verify_port,
};
-static struct uart_port ks8695uart_ports[SERIAL_KS8695_NR] = {
+struct uart_port ks8695uart_ports[SERIAL_KS8695_NR] = {
{
- .membase = KS8695_UART_VA,
- .mapbase = KS8695_UART_PA,
.iotype = SERIAL_IO_MEM,
- .irq = KS8695_IRQ_UART_TX,
- .uartclk = KS8695_CLOCK_RATE * 16,
.fifosize = 16,
.ops = &ks8695uart_pops,
.flags = UPF_BOOT_AUTOCONF,
diff --git a/include/linux/platform_data/serial-ks8695.h b/include/linux/platform_data/serial-ks8695.h
new file mode 100644
index 000000000000..ade3f0a03a75
--- /dev/null
+++ b/include/linux/platform_data/serial-ks8695.h
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+#ifndef _LINUX_PLATFORM_DATA_SERIAL_KS8695
+#define _LINUX_PLATFORM_DATA_SERIAL_KS8695
+
+#include <linux/serial_core.h>
+
+#define SERIAL_KS8695_NR 1
+extern struct uart_port ks8695uart_ports[SERIAL_KS8695_NR];
+
+#endif
--
2.20.0
^ permalink raw reply related
* [PATCH 5/6] ARM: ks8695, serial: skip manual tx IRQ ack
From: Arnd Bergmann @ 2019-04-15 20:24 UTC (permalink / raw)
To: Greg Ungerer
Cc: Linus Walleij, arm, Arnd Bergmann, Greg Kroah-Hartman, Jiri Slaby,
linux-serial, linux-kernel
In-Reply-To: <20190415202501.941196-1-arnd@arndb.de>
The TX interrupt is marked as edge triggered, so it will
already be acked by the top-level irq code, and does not
need the ack in the driver.
Removing this avoids a nasty dependency on the regs-irq.h
file that is otherwise reserved for the interrupt controller
driver.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/tty/serial/serial_ks8695.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/tty/serial/serial_ks8695.c b/drivers/tty/serial/serial_ks8695.c
index b461d791188c..6c5e9900e69d 100644
--- a/drivers/tty/serial/serial_ks8695.c
+++ b/drivers/tty/serial/serial_ks8695.c
@@ -21,7 +21,6 @@
#include <asm/mach/irq.h>
#include <mach/regs-uart.h>
-#include <mach/regs-irq.h>
#if defined(CONFIG_SERIAL_KS8695_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
#define SUPPORT_SYSRQ
@@ -52,8 +51,6 @@
#define UART_GET_BRDR(p) __raw_readl((p)->membase + KS8695_URBD)
#define UART_PUT_BRDR(p, c) __raw_writel((c), (p)->membase + KS8695_URBD)
-#define KS8695_CLR_TX_INT() __raw_writel(1 << KS8695_IRQ_UART_TX, KS8695_IRQ_VA + KS8695_INTST)
-
#define UART_DUMMY_LSR_RX 0x100
#define UART_PORT_SIZE (KS8695_USR - KS8695_URRB + 4)
@@ -207,7 +204,6 @@ static irqreturn_t ks8695uart_tx_chars(int irq, void *dev_id)
unsigned int count;
if (port->x_char) {
- KS8695_CLR_TX_INT();
UART_PUT_CHAR(port, port->x_char);
port->icount.tx++;
port->x_char = 0;
@@ -221,7 +217,6 @@ static irqreturn_t ks8695uart_tx_chars(int irq, void *dev_id)
count = 16; /* fifo size */
while (!uart_circ_empty(xmit) && (count-- > 0)) {
- KS8695_CLR_TX_INT();
UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
--
2.20.0
^ permalink raw reply related
* [PATCH v2] serial: Add Milbeaut serial control
From: Sugaya Taichi @ 2019-04-15 11:31 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: Arnd Bergmann, Takao Orito, Kazuhiro Kasai, Shinji Kanematsu,
Jassi Brar, Masami Hiramatsu, linux-kernel, linux-serial,
Sugaya Taichi
Add Milbeaut serial control including earlycon and console.
Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com>
---
Changes from v1:
- Add "COMPILE_TEST" dependency for coverage test.
drivers/tty/serial/Kconfig | 26 ++
drivers/tty/serial/Makefile | 1 +
drivers/tty/serial/milbeaut_usio.c | 621 +++++++++++++++++++++++++++++++++++++
include/uapi/linux/serial_core.h | 3 +
4 files changed, 651 insertions(+)
create mode 100644 drivers/tty/serial/milbeaut_usio.c
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 72966bc..d1971a8 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1582,6 +1582,32 @@ config SERIAL_RDA_CONSOLE
Say 'Y' here if you wish to use the RDA8810PL UART as the system
console. Only earlycon is implemented currently.
+config SERIAL_MILBEAUT_USIO
+ tristate "Milbeaut USIO/UART serial port support"
+ depends on ARCH_MILBEAUT || (COMPILE_TEST && OF)
+ default ARCH_MILBEAUT
+ select SERIAL_CORE
+ help
+ This selects the USIO/UART IP found in Socionext Milbeaut SoCs.
+
+config SERIAL_MILBEAUT_USIO_PORTS
+ int "Maximum number of CSIO/UART ports (1-8)"
+ range 1 8
+ depends on SERIAL_MILBEAUT_USIO
+ default "4"
+
+config SERIAL_MILBEAUT_USIO_CONSOLE
+ bool "Support for console on MILBEAUT USIO/UART serial port"
+ depends on SERIAL_MILBEAUT_USIO=y
+ default y
+ select SERIAL_CORE_CONSOLE
+ select SERIAL_EARLYCON
+ help
+ Say 'Y' here if you wish to use a USIO/UART of Socionext Milbeaut
+ SoCs as the system console (the system console is the device which
+ receives all kernel messages and warnings and which allows logins in
+ single user mode).
+
endmenu
config SERIAL_MCTRL_GPIO
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 40b702a..43ca2d0 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -92,6 +92,7 @@ obj-$(CONFIG_SERIAL_PIC32) += pic32_uart.o
obj-$(CONFIG_SERIAL_MPS2_UART) += mps2-uart.o
obj-$(CONFIG_SERIAL_OWL) += owl-uart.o
obj-$(CONFIG_SERIAL_RDA) += rda-uart.o
+obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o
# GPIOLIB helpers for modem control lines
obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o
diff --git a/drivers/tty/serial/milbeaut_usio.c b/drivers/tty/serial/milbeaut_usio.c
new file mode 100644
index 0000000..d303b7d
--- /dev/null
+++ b/drivers/tty/serial/milbeaut_usio.c
@@ -0,0 +1,621 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Socionext Inc.
+ */
+
+#if defined(CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/clk.h>
+#include <linux/console.h>
+#include <linux/module.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+
+#define USIO_NAME "mlb-usio-uart"
+#define USIO_UART_DEV_NAME "ttyUSI"
+
+static struct uart_port mlb_usio_ports[CONFIG_SERIAL_MILBEAUT_USIO_PORTS];
+
+#define RX 0
+#define TX 1
+static int mlb_usio_irq[CONFIG_SERIAL_MILBEAUT_USIO_PORTS][2];
+
+#define MLB_USIO_REG_SMR 0
+#define MLB_USIO_REG_SCR 1
+#define MLB_USIO_REG_ESCR 2
+#define MLB_USIO_REG_SSR 3
+#define MLB_USIO_REG_DR 4
+#define MLB_USIO_REG_BGR 6
+#define MLB_USIO_REG_FCR 12
+#define MLB_USIO_REG_FBYTE 14
+
+#define MLB_USIO_SMR_SOE BIT(0)
+#define MLB_USIO_SMR_SBL BIT(3)
+#define MLB_USIO_SCR_TXE BIT(0)
+#define MLB_USIO_SCR_RXE BIT(1)
+#define MLB_USIO_SCR_TBIE BIT(2)
+#define MLB_USIO_SCR_TIE BIT(3)
+#define MLB_USIO_SCR_RIE BIT(4)
+#define MLB_USIO_SCR_UPCL BIT(7)
+#define MLB_USIO_ESCR_L_8BIT 0
+#define MLB_USIO_ESCR_L_5BIT 1
+#define MLB_USIO_ESCR_L_6BIT 2
+#define MLB_USIO_ESCR_L_7BIT 3
+#define MLB_USIO_ESCR_P BIT(3)
+#define MLB_USIO_ESCR_PEN BIT(4)
+#define MLB_USIO_ESCR_FLWEN BIT(7)
+#define MLB_USIO_SSR_TBI BIT(0)
+#define MLB_USIO_SSR_TDRE BIT(1)
+#define MLB_USIO_SSR_RDRF BIT(2)
+#define MLB_USIO_SSR_ORE BIT(3)
+#define MLB_USIO_SSR_FRE BIT(4)
+#define MLB_USIO_SSR_PE BIT(5)
+#define MLB_USIO_SSR_REC BIT(7)
+#define MLB_USIO_SSR_BRK BIT(8)
+#define MLB_USIO_FCR_FE1 BIT(0)
+#define MLB_USIO_FCR_FE2 BIT(1)
+#define MLB_USIO_FCR_FCL1 BIT(2)
+#define MLB_USIO_FCR_FCL2 BIT(3)
+#define MLB_USIO_FCR_FSET BIT(4)
+#define MLB_USIO_FCR_FTIE BIT(9)
+#define MLB_USIO_FCR_FDRQ BIT(10)
+#define MLB_USIO_FCR_FRIIE BIT(11)
+
+static void mlb_usio_stop_tx(struct uart_port *port)
+{
+ writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
+ port->membase + MLB_USIO_REG_FCR);
+ writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE,
+ port->membase + MLB_USIO_REG_SCR);
+}
+
+static void mlb_usio_tx_chars(struct uart_port *port)
+{
+ struct circ_buf *xmit = &port->state->xmit;
+ int count;
+
+ writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE,
+ port->membase + MLB_USIO_REG_FCR);
+ writeb(readb(port->membase + MLB_USIO_REG_SCR) &
+ ~(MLB_USIO_SCR_TIE | MLB_USIO_SCR_TBIE),
+ port->membase + MLB_USIO_REG_SCR);
+
+ if (port->x_char) {
+ writew(port->x_char, port->membase + MLB_USIO_REG_DR);
+ port->icount.tx++;
+ port->x_char = 0;
+ return;
+ }
+ if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
+ mlb_usio_stop_tx(port);
+ return;
+ }
+
+ count = port->fifosize -
+ (readw(port->membase + MLB_USIO_REG_FBYTE) & 0xff);
+
+ do {
+ writew(xmit->buf[xmit->tail], port->membase + MLB_USIO_REG_DR);
+
+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+ port->icount.tx++;
+ if (uart_circ_empty(xmit))
+ break;
+
+ } while (--count > 0);
+
+ writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FDRQ,
+ port->membase + MLB_USIO_REG_FCR);
+
+ writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
+ port->membase + MLB_USIO_REG_SCR);
+
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ uart_write_wakeup(port);
+
+ if (uart_circ_empty(xmit))
+ mlb_usio_stop_tx(port);
+}
+
+static void mlb_usio_start_tx(struct uart_port *port)
+{
+ u16 fcr = readw(port->membase + MLB_USIO_REG_FCR);
+
+ writew(fcr | MLB_USIO_FCR_FTIE, port->membase + MLB_USIO_REG_FCR);
+ if (!(fcr & MLB_USIO_FCR_FDRQ))
+ return;
+
+ writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE,
+ port->membase + MLB_USIO_REG_SCR);
+
+ if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
+ mlb_usio_tx_chars(port);
+}
+
+static void mlb_usio_stop_rx(struct uart_port *port)
+{
+ writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_RIE,
+ port->membase + MLB_USIO_REG_SCR);
+}
+
+static void mlb_usio_enable_ms(struct uart_port *port)
+{
+ writeb(readb(port->membase + MLB_USIO_REG_SCR) |
+ MLB_USIO_SCR_RIE | MLB_USIO_SCR_RXE,
+ port->membase + MLB_USIO_REG_SCR);
+}
+
+static void mlb_usio_rx_chars(struct uart_port *port)
+{
+ struct tty_port *ttyport = &port->state->port;
+ unsigned long flag = 0;
+ char ch = 0;
+ u8 status;
+ int max_count = 2;
+
+ while (max_count--) {
+ status = readb(port->membase + MLB_USIO_REG_SSR);
+
+ if (!(status & MLB_USIO_SSR_RDRF))
+ break;
+
+ if (!(status & (MLB_USIO_SSR_ORE | MLB_USIO_SSR_FRE |
+ MLB_USIO_SSR_PE))) {
+ ch = readw(port->membase + MLB_USIO_REG_DR);
+ flag = TTY_NORMAL;
+ port->icount.rx++;
+ if (uart_handle_sysrq_char(port, ch))
+ continue;
+ uart_insert_char(port, status, MLB_USIO_SSR_ORE,
+ ch, flag);
+ continue;
+ }
+ if (status & MLB_USIO_SSR_PE)
+ port->icount.parity++;
+ if (status & MLB_USIO_SSR_ORE)
+ port->icount.overrun++;
+ status &= port->read_status_mask;
+ if (status & MLB_USIO_SSR_BRK) {
+ flag = TTY_BREAK;
+ ch = 0;
+ } else
+ if (status & MLB_USIO_SSR_PE) {
+ flag = TTY_PARITY;
+ ch = 0;
+ } else
+ if (status & MLB_USIO_SSR_FRE) {
+ flag = TTY_FRAME;
+ ch = 0;
+ }
+ if (flag)
+ uart_insert_char(port, status, MLB_USIO_SSR_ORE,
+ ch, flag);
+
+ writeb(readb(port->membase + MLB_USIO_REG_SSR) |
+ MLB_USIO_SSR_REC,
+ port->membase + MLB_USIO_REG_SSR);
+
+ max_count = readw(port->membase + MLB_USIO_REG_FBYTE) >> 8;
+ writew(readw(port->membase + MLB_USIO_REG_FCR) |
+ MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE,
+ port->membase + MLB_USIO_REG_FCR);
+ }
+
+ tty_flip_buffer_push(ttyport);
+}
+
+static irqreturn_t mlb_usio_rx_irq(int irq, void *dev_id)
+{
+ struct uart_port *port = dev_id;
+
+ spin_lock(&port->lock);
+ mlb_usio_rx_chars(port);
+ spin_unlock(&port->lock);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t mlb_usio_tx_irq(int irq, void *dev_id)
+{
+ struct uart_port *port = dev_id;
+
+ spin_lock(&port->lock);
+ if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI)
+ mlb_usio_tx_chars(port);
+ spin_unlock(&port->lock);
+
+ return IRQ_HANDLED;
+}
+
+static unsigned int mlb_usio_tx_empty(struct uart_port *port)
+{
+ return (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI) ?
+ TIOCSER_TEMT : 0;
+}
+
+static void mlb_usio_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+}
+
+static unsigned int mlb_usio_get_mctrl(struct uart_port *port)
+{
+ return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
+
+}
+
+static void mlb_usio_break_ctl(struct uart_port *port, int break_state)
+{
+}
+
+static int mlb_usio_startup(struct uart_port *port)
+{
+ const char *portname = to_platform_device(port->dev)->name;
+ unsigned long flags;
+ int ret, index = port->line;
+ unsigned char escr;
+
+ ret = request_irq(mlb_usio_irq[index][RX], mlb_usio_rx_irq,
+ 0, portname, port);
+ if (ret)
+ return ret;
+ ret = request_irq(mlb_usio_irq[index][TX], mlb_usio_tx_irq,
+ 0, portname, port);
+ if (ret) {
+ free_irq(mlb_usio_irq[index][RX], port);
+ return ret;
+ }
+
+ escr = readb(port->membase + MLB_USIO_REG_ESCR);
+ if (of_property_read_bool(port->dev->of_node, "auto-flow-control"))
+ escr |= MLB_USIO_ESCR_FLWEN;
+ spin_lock_irqsave(&port->lock, flags);
+ writeb(0, port->membase + MLB_USIO_REG_SCR);
+ writeb(escr, port->membase + MLB_USIO_REG_ESCR);
+ writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
+ writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
+ writew(0, port->membase + MLB_USIO_REG_FCR);
+ writew(MLB_USIO_FCR_FCL1 | MLB_USIO_FCR_FCL2,
+ port->membase + MLB_USIO_REG_FCR);
+ writew(MLB_USIO_FCR_FE1 | MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE,
+ port->membase + MLB_USIO_REG_FCR);
+ writew(0, port->membase + MLB_USIO_REG_FBYTE);
+ writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
+
+ writeb(MLB_USIO_SCR_TXE | MLB_USIO_SCR_RIE | MLB_USIO_SCR_TBIE |
+ MLB_USIO_SCR_RXE, port->membase + MLB_USIO_REG_SCR);
+ spin_unlock_irqrestore(&port->lock, flags);
+
+ return 0;
+}
+
+static void mlb_usio_shutdown(struct uart_port *port)
+{
+ int index = port->line;
+
+ free_irq(mlb_usio_irq[index][RX], port);
+ free_irq(mlb_usio_irq[index][TX], port);
+}
+
+static void mlb_usio_set_termios(struct uart_port *port,
+ struct ktermios *termios, struct ktermios *old)
+{
+ unsigned int escr, smr = MLB_USIO_SMR_SOE;
+ unsigned long flags, baud, quot;
+
+ switch (termios->c_cflag & CSIZE) {
+ case CS5:
+ escr = MLB_USIO_ESCR_L_5BIT;
+ break;
+ case CS6:
+ escr = MLB_USIO_ESCR_L_6BIT;
+ break;
+ case CS7:
+ escr = MLB_USIO_ESCR_L_7BIT;
+ break;
+ case CS8:
+ default:
+ escr = MLB_USIO_ESCR_L_8BIT;
+ break;
+ }
+
+ if (termios->c_cflag & CSTOPB)
+ smr |= MLB_USIO_SMR_SBL;
+
+ if (termios->c_cflag & PARENB) {
+ escr |= MLB_USIO_ESCR_PEN;
+ if (termios->c_cflag & PARODD)
+ escr |= MLB_USIO_ESCR_P;
+ }
+ /* Set hard flow control */
+ if (of_property_read_bool(port->dev->of_node, "auto-flow-control") ||
+ (termios->c_cflag & CRTSCTS))
+ escr |= MLB_USIO_ESCR_FLWEN;
+
+ baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
+ if (baud > 1)
+ quot = port->uartclk / baud - 1;
+ else
+ quot = 0;
+
+ spin_lock_irqsave(&port->lock, flags);
+ uart_update_timeout(port, termios->c_cflag, baud);
+ port->read_status_mask = MLB_USIO_SSR_ORE | MLB_USIO_SSR_RDRF |
+ MLB_USIO_SSR_TDRE;
+ if (termios->c_iflag & INPCK)
+ port->read_status_mask |= MLB_USIO_SSR_FRE | MLB_USIO_SSR_PE;
+
+ port->ignore_status_mask = 0;
+ if (termios->c_iflag & IGNPAR)
+ port->ignore_status_mask |= MLB_USIO_SSR_FRE | MLB_USIO_SSR_PE;
+ if ((termios->c_iflag & IGNBRK) && (termios->c_iflag & IGNPAR))
+ port->ignore_status_mask |= MLB_USIO_SSR_ORE;
+ if ((termios->c_cflag & CREAD) == 0)
+ port->ignore_status_mask |= MLB_USIO_SSR_RDRF;
+
+ writeb(0, port->membase + MLB_USIO_REG_SCR);
+ writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR);
+ writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR);
+ writew(0, port->membase + MLB_USIO_REG_FCR);
+ writeb(smr, port->membase + MLB_USIO_REG_SMR);
+ writeb(escr, port->membase + MLB_USIO_REG_ESCR);
+ writew(quot, port->membase + MLB_USIO_REG_BGR);
+ writew(0, port->membase + MLB_USIO_REG_FCR);
+ writew(MLB_USIO_FCR_FCL1 | MLB_USIO_FCR_FCL2 | MLB_USIO_FCR_FE1 |
+ MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE,
+ port->membase + MLB_USIO_REG_FCR);
+ writew(0, port->membase + MLB_USIO_REG_FBYTE);
+ writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE);
+ writeb(MLB_USIO_SCR_RIE | MLB_USIO_SCR_RXE | MLB_USIO_SCR_TBIE |
+ MLB_USIO_SCR_TXE, port->membase + MLB_USIO_REG_SCR);
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static const char *mlb_usio_type(struct uart_port *port)
+{
+ return ((port->type == PORT_MLB_USIO) ? USIO_NAME : NULL);
+}
+
+static void mlb_usio_config_port(struct uart_port *port, int flags)
+{
+ if (flags & UART_CONFIG_TYPE)
+ port->type = PORT_MLB_USIO;
+}
+
+static const struct uart_ops mlb_usio_ops = {
+ .tx_empty = mlb_usio_tx_empty,
+ .set_mctrl = mlb_usio_set_mctrl,
+ .get_mctrl = mlb_usio_get_mctrl,
+ .stop_tx = mlb_usio_stop_tx,
+ .start_tx = mlb_usio_start_tx,
+ .stop_rx = mlb_usio_stop_rx,
+ .enable_ms = mlb_usio_enable_ms,
+ .break_ctl = mlb_usio_break_ctl,
+ .startup = mlb_usio_startup,
+ .shutdown = mlb_usio_shutdown,
+ .set_termios = mlb_usio_set_termios,
+ .type = mlb_usio_type,
+ .config_port = mlb_usio_config_port,
+};
+
+#ifdef CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE
+
+static void mlb_usio_console_putchar(struct uart_port *port, int c)
+{
+ while (!(readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TDRE))
+ cpu_relax();
+
+ writew(c, port->membase + MLB_USIO_REG_DR);
+}
+
+static void mlb_usio_console_write(struct console *co, const char *s,
+ unsigned int count)
+{
+ struct uart_port *port = &mlb_usio_ports[co->index];
+
+ uart_console_write(port, s, count, mlb_usio_console_putchar);
+}
+
+static int __init mlb_usio_console_setup(struct console *co, char *options)
+{
+ struct uart_port *port;
+ int baud = 115200;
+ int parity = 'n';
+ int flow = 'n';
+ int bits = 8;
+
+ if (co->index >= CONFIG_SERIAL_MILBEAUT_USIO_PORTS)
+ return -ENODEV;
+
+ port = &mlb_usio_ports[co->index];
+ if (!port->membase)
+ return -ENODEV;
+
+
+ if (options)
+ uart_parse_options(options, &baud, &parity, &bits, &flow);
+
+ if (of_property_read_bool(port->dev->of_node, "auto-flow-control"))
+ flow = 'r';
+
+ return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+
+static struct uart_driver mlb_usio_uart_driver;
+static struct console mlb_usio_console = {
+ .name = USIO_UART_DEV_NAME,
+ .write = mlb_usio_console_write,
+ .device = uart_console_device,
+ .setup = mlb_usio_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+ .data = &mlb_usio_uart_driver,
+};
+
+static int __init mlb_usio_console_init(void)
+{
+ register_console(&mlb_usio_console);
+ return 0;
+}
+console_initcall(mlb_usio_console_init);
+
+
+static void mlb_usio_early_console_write(struct console *co, const char *s,
+ u_int count)
+{
+ struct earlycon_device *dev = co->data;
+
+ uart_console_write(&dev->port, s, count, mlb_usio_console_putchar);
+}
+
+static int __init mlb_usio_early_console_setup(struct earlycon_device *device,
+ const char *opt)
+{
+ if (!device->port.membase)
+ return -ENODEV;
+ device->con->write = mlb_usio_early_console_write;
+ return 0;
+}
+
+OF_EARLYCON_DECLARE(mlb_usio, "socionext,milbeaut-usio-uart",
+ mlb_usio_early_console_setup);
+
+#define USIO_CONSOLE (&mlb_usio_console)
+#else
+#define USIO_CONSOLE NULL
+#endif
+
+static struct uart_driver mlb_usio_uart_driver = {
+ .owner = THIS_MODULE,
+ .driver_name = USIO_NAME,
+ .dev_name = USIO_UART_DEV_NAME,
+ .cons = USIO_CONSOLE,
+ .nr = CONFIG_SERIAL_MILBEAUT_USIO_PORTS,
+};
+
+static int mlb_usio_probe(struct platform_device *pdev)
+{
+ struct clk *clk = devm_clk_get(&pdev->dev, 0);
+ struct uart_port *port;
+ struct resource *res;
+ int index = 0;
+ int ret;
+
+ if (IS_ERR(clk)) {
+ dev_err(&pdev->dev, "Missing clock\n");
+ return PTR_ERR(clk);
+ }
+ ret = clk_prepare_enable(clk);
+ if (ret) {
+ dev_err(&pdev->dev, "Clock enable failed: %d\n", ret);
+ return ret;
+ }
+ of_property_read_u32(pdev->dev.of_node, "index", &index);
+ port = &mlb_usio_ports[index];
+
+ port->private_data = (void *)clk;
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res == NULL) {
+ dev_err(&pdev->dev, "Missing regs\n");
+ ret = -ENODEV;
+ goto failed;
+ }
+ port->mapbase = res->start;
+ port->membase = ioremap(res->start, (res->end - res->start + 1));
+ port->membase = devm_ioremap(&pdev->dev, res->start,
+ resource_size(res));
+
+ ret = platform_get_irq_byname(pdev, "rx");
+ mlb_usio_irq[index][RX] = ret;
+
+ ret = platform_get_irq_byname(pdev, "tx");
+ mlb_usio_irq[index][TX] = ret;
+
+ port->irq = mlb_usio_irq[index][RX];
+ port->uartclk = clk_get_rate(clk);
+ port->fifosize = 128;
+ port->iotype = UPIO_MEM32;
+ port->flags = UPF_BOOT_AUTOCONF | UPF_SPD_VHI;
+ port->line = index;
+ port->ops = &mlb_usio_ops;
+ port->dev = &pdev->dev;
+
+ ret = uart_add_one_port(&mlb_usio_uart_driver, port);
+ if (ret) {
+ dev_err(&pdev->dev, "Adding port failed: %d\n", ret);
+ goto failed1;
+ }
+ return 0;
+
+failed1:
+ iounmap(port->membase);
+
+failed:
+ clk_disable_unprepare(clk);
+ clk_put(clk);
+
+ return ret;
+}
+
+static int mlb_usio_remove(struct platform_device *pdev)
+{
+ struct uart_port *port = &mlb_usio_ports[pdev->id];
+ struct clk *clk = port->private_data;
+
+ uart_remove_one_port(&mlb_usio_uart_driver, port);
+ clk_disable_unprepare(clk);
+ clk_put(clk);
+
+ return 0;
+}
+
+static const struct of_device_id mlb_usio_dt_ids[] = {
+ { .compatible = "socionext,milbeaut-usio-uart" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mlb_usio_dt_ids);
+
+static struct platform_driver mlb_usio_driver = {
+ .probe = mlb_usio_probe,
+ .remove = mlb_usio_remove,
+ .driver = {
+ .name = USIO_NAME,
+ .of_match_table = mlb_usio_dt_ids,
+ },
+};
+
+static int __init mlb_usio_init(void)
+{
+ int ret = uart_register_driver(&mlb_usio_uart_driver);
+
+ if (ret) {
+ pr_err("%s: uart registration failed: %d\n", __func__, ret);
+ return ret;
+ }
+ ret = platform_driver_register(&mlb_usio_driver);
+ if (ret) {
+ uart_unregister_driver(&mlb_usio_uart_driver);
+ pr_err("%s: drv registration failed: %d\n", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void __exit mlb_usio_exit(void)
+{
+ platform_driver_unregister(&mlb_usio_driver);
+ uart_unregister_driver(&mlb_usio_uart_driver);
+}
+
+module_init(mlb_usio_init);
+module_exit(mlb_usio_exit);
+
+MODULE_AUTHOR("SOCIONEXT");
+MODULE_DESCRIPTION("MILBEAUT_USIO/UART Driver");
+MODULE_LICENSE("GPL");
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 6009ee2..a51c747 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -287,4 +287,7 @@
/* RDA UART */
#define PORT_RDA 118
+/* Socionext Milbeaut UART */
+#define PORT_MLB_USIO 119
+
#endif /* _UAPILINUX_SERIAL_CORE_H */
--
1.9.1
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