* [PATCH v4 02/11] dt-bindings: timer: add SpacemiT K3 CLINT
From: Guodong Xu @ 2026-01-10 5:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan,
Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel,
Greg Kroah-Hartman, Jiri Slaby, Lubomir Rintel, Yangyu Chen
Cc: Paul Walmsley, Conor Dooley, Heinrich Schuchardt,
Kevin Meng Zhang, Anup Patel, Andrew Jones, devicetree,
linux-riscv, linux-kernel, spacemit, linux-serial, Guodong Xu,
Conor Dooley
In-Reply-To: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com>
Add compatible string for SpacemiT K3 CLINT.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v4: No change.
v3: No change.
v2: Add Conor's Acked-by.
---
Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index 0d3b8dc362ba..3bab40500df9 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -33,6 +33,7 @@ properties:
- eswin,eic7700-clint # ESWIN EIC7700
- sifive,fu540-c000-clint # SiFive FU540
- spacemit,k1-clint # SpacemiT K1
+ - spacemit,k3-clint # SpacemiT K3
- starfive,jh7100-clint # StarFive JH7100
- starfive,jh7110-clint # StarFive JH7110
- starfive,jh8100-clint # StarFive JH8100
--
2.43.0
^ permalink raw reply related
* [PATCH v4 01/11] dt-bindings: riscv: add SpacemiT X100 CPU compatible
From: Guodong Xu @ 2026-01-10 5:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan,
Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel,
Greg Kroah-Hartman, Jiri Slaby, Lubomir Rintel, Yangyu Chen
Cc: Paul Walmsley, Conor Dooley, Heinrich Schuchardt,
Kevin Meng Zhang, Anup Patel, Andrew Jones, devicetree,
linux-riscv, linux-kernel, spacemit, linux-serial, Guodong Xu,
Krzysztof Kozlowski, Heinrich Schuchardt
In-Reply-To: <20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com>
Add compatible string for the SpacemiT X100 core. [1]
The X100 is a 64-bit RVA23-compliant RISC-V core from SpacemiT. X100
supports the RISC-V vector and hypervisor extensions and all mandatory
extersions as required by the RVA23U64 and RVA23S64 profiles, per the
definition in 'RVA23 Profile, Version 1.0'. [2]
From a microarchieture viewpoint, the X100 features a 4-issue
out-of-order pipeline.
X100 is used in SpacemiT K3 SoC.
Link: https://www.spacemit.com/en/spacemit-x100-core/ [1]
Link: https://docs.riscv.org/reference/profiles/rva23/_attachments/rva23-profile.pdf [2]
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v4: No change.
v3: Added Acked-by from Krzysztof.
v2: Fixed alphanumeric sorting of compatible strings, put x100 before x60,
as per Krzysztof's feedback.
Added reviewed-by from Yixun and Heinrich.
Updated the commit message to provide more information about X100.
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d733c0bd534f..5feeb2203050 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -61,6 +61,7 @@ properties:
- sifive,u7
- sifive,u74
- sifive,u74-mc
+ - spacemit,x100
- spacemit,x60
- thead,c906
- thead,c908
--
2.43.0
^ permalink raw reply related
* [PATCH v4 00/11] riscv: spacemit: Add SpacemiT K3 SoC and K3 Pico-ITX board
From: Guodong Xu @ 2026-01-10 5:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan,
Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel,
Greg Kroah-Hartman, Jiri Slaby, Lubomir Rintel, Yangyu Chen
Cc: Paul Walmsley, Conor Dooley, Heinrich Schuchardt,
Kevin Meng Zhang, Anup Patel, Andrew Jones, devicetree,
linux-riscv, linux-kernel, spacemit, linux-serial, Guodong Xu,
Krzysztof Kozlowski, Heinrich Schuchardt, Conor Dooley
This series introduces basic support for the SpacemiT K3 SoC and the
K3 Pico-ITX evaluation board.
This series (starting from v2) also adds descriptions about ISA extensions
mandated by the RVA23 Profile Version 1.0 into riscv/extensions.yaml.
There are extensive discussions about how to handle these new extensions
in v2. In v3 (now v4), here is my best understading of what I think we have
reached consensus on.
At v3, Samuel Holland shared his opinion regarding how "supm" should be
handled [3]. He suggests removing "supm" from devicetrees not targeting
U-mode. I did that in Patch 10/11 of v3 with k3.dtsi. Samuel also notes
that "supm" could make sense as a binding for devicetrees targeting U-mode.
Considering there are other changes suggested in [2] and [3], I would
prefer to start a separate patchset dedicated to "supm".
Among others, major change in v4 is adding m-mode imsic and aplic nodes
into k3.dtsi (Patch 10/11) to better represent the hardware.
Hi, Conor
For the binding riscv/extensions.ymal, here's what changed in v3 (no
change in v4):
1. Dropped the patch of adding "supm" into extensions.yaml. At the same
time, I will start another patchset which implements the strategy
outlined by Conor in Link [2] and by Samuel in Link [3].
2. Dropped the dependency checks for "sha" on "h", "shcounterenw", and
6 others. "sha" implies these extensions, and it should be allowed
to be declared independently. Like "a" implies "zaamo" and "zalrsc".
3. Enchanced the dependency check of "ziccamoa" on "a". Specifically,
- added the dependency check of "ziccamoa" on "zaamo" or on "a".
- added the dependency check of "za64rs" on "zalrsc" or on "a".
- added the dependency check of "ziccrse" on "zalrsc" or "a".
The commit message of this patch is updated too, to better explain the
relationship between "ziccamoa", "za64rs", "ziccrse" and "a".
4. Enhanced checking dependency of "b" and "zba", "zbb", "zbs", making the
dependency check in both directions, as discussed in [4]. Since "b"
was ratified much later than its component extensions (zba/zbb/zbs),
existing software and kernels expect these explicit strings. This
bidirectional check ensures cores declaring "b" remain compatible
with older software that only recognizes zba/zbb/zbs.
Thank you for your review.
Because the K3 uart compatible string patch (Patch 5 in v2) has been
applied in tty.git, the entire series now rebased on top of linux-next,
tag: next-20260109.
The SpacemiT K3 is an SoC featuring 8 SpacemiT X100 RISC-V cores.
The X100 is a 4-issue, out-of-order core compliant with the RVA23
profile, targeting high-performance scenarios. [1]
The K3 Pico-ITX is an evaluation board built around the K3 SoC.
From an RVA23 profile compliance perspective, the X100 supports all
mandatory extensions required by RVA23U64 and RVA23S64.
Link: https://www.spacemit.com/en/spacemit-x100-core/ [1]
Link: https://lore.kernel.org/lkml/20260101-legume-engraved-0fae8282cfbe@spud/ [2]
Link: https://lore.kernel.org/all/4ebbe14b-2579-4ba6-808d-d50c24641d04@sifive.com/ [3]
Link: https://lore.kernel.org/all/20251230-imprison-sleet-6b5a1e26d34b@spud/#r [4]
Changes in v4:
- Patch 5:
Adjust maintainers list in alphabetic order.
Declare spacemit,k3-pico-itx as an enum, which could save future
code change when adding new boards.
- Patch 10:
Fix missing blank space after comma in simsic compatible.
Add m-mode imsic and aplic nodes, per suggestion received from Samuel
Holland.
Adjust node properties order in nodes simsic, saplic, mimsic, maplic to
follow the DTS coding style.
- Link to v3: https://lore.kernel.org/r/20260108-k3-basic-dt-v3-0-ed99eb4c3ad3@riscstar.com
Other Changes in v3 include:
- Patch 1:
Acked-by: Krzysztof Kozlowski
- Patch 4:
Acked-by: Krzysztof Kozlowski
- Dropped Patch 5 "dt-bindings: serial: 8250: add SpacemiT K3 UART compatible"
as it has been applied to tty-next.
- Link to v2: https://lore.kernel.org/r/20251222-k3-basic-dt-v2-0-3af3f3cd0f8a@riscstar.com
Changes in v2:
- Patch 1:
Fixed alphanumeric sorting order of compatible strings (swapped x100 and
x60) as per Krzysztof's feedback.
Update commit message with more information about X100 featurs per
Yixun's feedback.
- Patch 4:
Fixed the order to keep things alphabetically.
- Patch 6:
Use "one blank space" between name and email address.
- Patch 7 ~ 11:
New patches. Add description of RVA23 mandatory extensions into riscv
binding YAML file.
- Patch 12 (Patch 7 in v1):
Removed aliases node.
Updated 'riscv,isa-extensions' with new extension strings available
- Patch 13 (Patch 8 in v1):
Updated the memory address to the hardware truth.
Added aliases node in board dts.
- Patch 1,2,3,5: Add Reviewed-by and Acked-by collected.
Link to v1: https://lore.kernel.org/r/20251216-k3-basic-dt-v1-0-a0d256c9dc92@riscstar.com
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
Guodong Xu (11):
dt-bindings: riscv: add SpacemiT X100 CPU compatible
dt-bindings: timer: add SpacemiT K3 CLINT
dt-bindings: interrupt-controller: add SpacemiT K3 APLIC
dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC
dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings
dt-bindings: riscv: Add B ISA extension description
dt-bindings: riscv: Add descriptions for Za64rs, Ziccamoa, Ziccif, and Zicclsm
dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl
dt-bindings: riscv: Add Sha and its comprised extensions
riscv: dts: spacemit: add initial device tree of SpacemiT K3 SoC
riscv: dts: spacemit: add SpacemiT K3 Pico-ITX board device tree
.../bindings/interrupt-controller/riscv,aplic.yaml | 1 +
.../interrupt-controller/riscv,imsics.yaml | 1 +
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
.../devicetree/bindings/riscv/extensions.yaml | 169 ++++++
.../devicetree/bindings/riscv/spacemit.yaml | 5 +
.../devicetree/bindings/timer/sifive,clint.yaml | 1 +
arch/riscv/boot/dts/spacemit/Makefile | 1 +
arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 38 ++
arch/riscv/boot/dts/spacemit/k3.dtsi | 590 +++++++++++++++++++++
9 files changed, 807 insertions(+)
---
base-commit: 31d167f54de93f14fa8e4bc6cbc4adaf7019fd94
change-id: 20251216-k3-basic-dt-cd9540061989
Best regards,
--
Guodong Xu <guodong@riscstar.com>
^ permalink raw reply
* [PATCH 2/2] arm: dts: lpc32xx: Add ns16550a compatible value to UART device tree nodes
From: Vladimir Zapolskiy @ 2026-01-10 2:46 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Lubomir Rintel, Piotr Wojtaszczyk, devicetree, linux-serial,
linux-arm-kernel
In-Reply-To: <20260110024647.3389345-1-vz@mleia.com>
NXP LPC32xx SoC has 4 16550A compatible UARTs with a difference of minor
significance, which is expectedly handled in the 8250 serial driver.
Reflect this fact in the platform device tree file by adding the expected
compatible value.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
---
arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
index e94df78def18..8fa1848943f8 100644
--- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
@@ -263,8 +263,7 @@ i2s1: i2s@2009c000 {
/* UART5 first since it is the default console, ttyS0 */
uart5: serial@40090000 {
- /* actually, ns16550a w/ 64 byte fifos! */
- compatible = "nxp,lpc3220-uart";
+ compatible = "nxp,lpc3220-uart", "ns16550a";
reg = <0x40090000 0x1000>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
@@ -273,7 +272,7 @@ uart5: serial@40090000 {
};
uart3: serial@40080000 {
- compatible = "nxp,lpc3220-uart";
+ compatible = "nxp,lpc3220-uart", "ns16550a";
reg = <0x40080000 0x1000>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
@@ -282,7 +281,7 @@ uart3: serial@40080000 {
};
uart4: serial@40088000 {
- compatible = "nxp,lpc3220-uart";
+ compatible = "nxp,lpc3220-uart", "ns16550a";
reg = <0x40088000 0x1000>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
@@ -291,7 +290,7 @@ uart4: serial@40088000 {
};
uart6: serial@40098000 {
- compatible = "nxp,lpc3220-uart";
+ compatible = "nxp,lpc3220-uart", "ns16550a";
reg = <0x40098000 0x1000>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
--
2.43.0
^ permalink raw reply related
* [PATCH 1/2] dt-bindings: serial: 8250: Explicitly make LPC32xx UARTs compatible with 16550A
From: Vladimir Zapolskiy @ 2026-01-10 2:46 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Lubomir Rintel, Piotr Wojtaszczyk, devicetree, linux-serial,
linux-arm-kernel
In-Reply-To: <20260110024647.3389345-1-vz@mleia.com>
NXP LPC32xx SoC has 4 16550A compatible UARTs with 64 byte TX and RX FIFO
sizes, and the platform UART hardware is well supported as a standard
16550A UART.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
---
Documentation/devicetree/bindings/serial/8250.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
index 167ddcbd8800..1a5178320465 100644
--- a/Documentation/devicetree/bindings/serial/8250.yaml
+++ b/Documentation/devicetree/bindings/serial/8250.yaml
@@ -108,7 +108,6 @@ properties:
- const: nuvoton,wpcm450-uart
- const: nuvoton,npcm750-uart
- const: nvidia,tegra20-uart
- - const: nxp,lpc3220-uart
- items:
- enum:
- exar,xr16l2552
@@ -123,6 +122,7 @@ properties:
- fsl,16550-FIFO64
- andestech,uart16550
- nxp,lpc1850-uart
+ - nxp,lpc3220-uart
- opencores,uart16550-rtlsvn105
- ti,da830-uart
- loongson,ls2k0500-uart
--
2.43.0
^ permalink raw reply related
* [PATCH 0/2] arm: dts: lpc32xx: Specify compatibility of platform UARTs with 16550A
From: Vladimir Zapolskiy @ 2026-01-10 2:46 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Lubomir Rintel, Piotr Wojtaszczyk, devicetree, linux-serial,
linux-arm-kernel
NXP LPC32xx SoC has 4 16550A compatible UARTs with 64 byte TX and RX FIFO
sizes, and the platform UART hardware is well supported as a standard
16550A UART.
Vladimir Zapolskiy (2):
dt-bindings: serial: 8250: Explicitly make LPC32xx UARTs compatible with 16550A
arm: dts: lpc32xx: Add ns16550a compatible value to UART device tree nodes
Documentation/devicetree/bindings/serial/8250.yaml | 2 +-
arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 9 ++++-----
2 files changed, 5 insertions(+), 6 deletions(-)
--
2.43.0
^ permalink raw reply
* Re: [PATCH 00/13] MIPS: move pic32.h header file from asm to platform_data
From: Brian Masney @ 2026-01-09 17:14 UTC (permalink / raw)
To: Thomas Bogendoerfer, Claudiu Beznea
Cc: linux-mips, linux-kernel, Michael Turquette, Stephen Boyd,
linux-clk, Thomas Gleixner, Adrian Hunter, Ulf Hansson, linux-mmc,
Linus Walleij, linux-gpio, Alexandre Belloni, linux-rtc,
Greg Kroah-Hartman, Jiri Slaby, linux-serial, Wim Van Sebroeck,
Guenter Roeck, linux-watchdog
In-Reply-To: <20260109-mips-pic32-header-move-v1-0-99859c55783d@redhat.com>
On Fri, Jan 09, 2026 at 11:41:13AM -0500, Brian Masney wrote:
> There are currently some pic32 MIPS drivers that are in tree, and are
> only configured to be compiled on the MIPS pic32 platform. There's a
> risk of breaking some of these drivers when migrating drivers away from
> legacy APIs. It happened to me with a pic32 clk driver.
>
> Let's go ahead and move the pic32.h from the asm to the platform_data
> include directory in the tree. This will make it easier, and cleaner to
> enable COMPILE_TEST for some of these pic32 drivers.
>
> I included a patch at the end that shows enabling COMPILE_TEST for a
> pic32 clk driver.
I didn't CC everyone on patch 1 to this series that copes pic32.h from
the MIPS ASM directory to linux/platform_data/pic32.h. It's available at
the following location if you want to see it:
https://lore.kernel.org/linux-mips/20260109-mips-pic32-header-move-v1-0-99859c55783d@redhat.com/T/#m1e0e50adfe2ea4bf430025660fada7b1468d0fbf
Patch 12 of this series is where I remove the asm variant of pic32.h.
Brian
^ permalink raw reply
* [PATCH 09/13] serial: pic32_uart: update include to use pic32.h from platform_data
From: Brian Masney @ 2026-01-09 16:41 UTC (permalink / raw)
To: Thomas Bogendoerfer, Claudiu Beznea
Cc: linux-mips, linux-kernel, Brian Masney, Greg Kroah-Hartman,
Jiri Slaby, linux-serial
In-Reply-To: <20260109-mips-pic32-header-move-v1-0-99859c55783d@redhat.com>
Use the linux/platform_data/pic32.h include instead of
asm/mach-pic32/pic32.h so that the asm variant can be dropped. This
is in preparation for allowing some drivers to be compiled on other
architectures with COMPILE_TEST enabled.
Signed-off-by: Brian Masney <bmasney@redhat.com>
---
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: Jiri Slaby <jirislaby@kernel.org>
Cc: linux-kernel@vger.kernel.org
Cc: linux-serial@vger.kernel.org
---
| 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
--git a/drivers/tty/serial/pic32_uart.c b/drivers/tty/serial/pic32_uart.c
index 14d50bd7f1bd3575e60e51783bf5b2d821f9168d..8407f85776c07a7495688fc4f95b8672b1543bd0 100644
--- a/drivers/tty/serial/pic32_uart.c
+++ b/drivers/tty/serial/pic32_uart.c
@@ -22,8 +22,7 @@
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#include <linux/delay.h>
-
-#include <asm/mach-pic32/pic32.h>
+#include <linux/platform_data/pic32.h>
/* UART name and device definitions */
#define PIC32_DEV_NAME "pic32-uart"
--
2.52.0
^ permalink raw reply related
* [PATCH 00/13] MIPS: move pic32.h header file from asm to platform_data
From: Brian Masney @ 2026-01-09 16:41 UTC (permalink / raw)
To: Thomas Bogendoerfer, Claudiu Beznea
Cc: linux-mips, linux-kernel, Brian Masney, Michael Turquette,
Stephen Boyd, linux-clk, Thomas Gleixner, Adrian Hunter,
Ulf Hansson, linux-mmc, Linus Walleij, linux-gpio,
Alexandre Belloni, linux-rtc, Greg Kroah-Hartman, Jiri Slaby,
linux-serial, Wim Van Sebroeck, Guenter Roeck, linux-watchdog
There are currently some pic32 MIPS drivers that are in tree, and are
only configured to be compiled on the MIPS pic32 platform. There's a
risk of breaking some of these drivers when migrating drivers away from
legacy APIs. It happened to me with a pic32 clk driver.
Let's go ahead and move the pic32.h from the asm to the platform_data
include directory in the tree. This will make it easier, and cleaner to
enable COMPILE_TEST for some of these pic32 drivers.
I included a patch at the end that shows enabling COMPILE_TEST for a
pic32 clk driver.
Merge Strategy
==============
- Patches 1-12 can go through the MIPS tree.
- Patch 13 I can repost to Claudiu after patches 1-12 are in Linus's
tree after the next merge window. There is a separate patch set that
fixes a compiler error I unintentionally introduced via the clk tree.
https://lore.kernel.org/linux-clk/CABx5tq+eOocJ41X-GSgkGy6S+s+Am1yCS099wqP695NtwALTmg@mail.gmail.com/T/
Signed-off-by: Brian Masney <bmasney@redhat.com>
---
Brian Masney (13):
MIPS: copy pic32.h header file from asm/mach-pic32/ to include/platform-data/
MAINTAINERS: add include/linux/platform_data/pic32.h to MIPS entry
MIPS: update include to use pic32.h from platform_data
clk: microchip: core: update include to use pic32.h from platform_data
irqchip/irq-pic32-evic: update include to use pic32.h from platform_data
mmc: sdhci-pic32: update include to use pic32.h from platform_data
pinctrl: pic32: update include to use pic32.h from platform_data
rtc: pic32: update include to use pic32.h from platform_data
serial: pic32_uart: update include to use pic32.h from platform_data
watchdog: pic32-dmt: update include to use pic32.h from platform_data
watchdog: pic32-wdt: update include to use pic32.h from platform_data
MIPS: drop unused pic32.h header
clk: microchip: core: allow driver to be compiled with COMPILE_TEST
MAINTAINERS | 1 +
arch/mips/pic32/common/reset.c | 2 +-
arch/mips/pic32/pic32mzda/config.c | 3 +--
arch/mips/pic32/pic32mzda/early_clk.c | 2 +-
arch/mips/pic32/pic32mzda/early_console.c | 2 +-
drivers/clk/microchip/Kconfig | 2 +-
drivers/clk/microchip/clk-core.c | 6 +++++-
drivers/irqchip/irq-pic32-evic.c | 2 +-
drivers/mmc/host/sdhci-pic32.c | 2 +-
drivers/pinctrl/pinctrl-pic32.c | 3 +--
drivers/rtc/rtc-pic32.c | 3 +--
drivers/tty/serial/pic32_uart.c | 3 +--
drivers/watchdog/pic32-dmt.c | 3 +--
drivers/watchdog/pic32-wdt.c | 3 +--
.../mach-pic32 => include/linux/platform_data}/pic32.h | 17 +++++++++--------
15 files changed, 27 insertions(+), 27 deletions(-)
---
base-commit: f417b7ffcbef7d76b0d8860518f50dae0e7e5eda
change-id: 20260109-mips-pic32-header-move-6ac9965aa70a
Best regards,
--
Brian Masney <bmasney@redhat.com>
^ permalink raw reply
* Re: [PATCH] dt-bindings: serial: sh-sci: Fold single-entry compatibles into enum
From: Lad, Prabhakar @ 2026-01-09 14:24 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, linux-kernel, linux-serial, devicetree,
linux-renesas-soc, Biju Das, Fabrizio Castro, Lad Prabhakar
In-Reply-To: <CAMuHMdWz6_NzvjZNMLk+Bqoa0NR2CKNFwDXynfmrTZgOGsqxTA@mail.gmail.com>
Hi Geert,
Thank you for the review.
On Fri, Jan 9, 2026 at 1:28 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Fri, 9 Jan 2026 at 13:38, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Group single compatibles into enum.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> > +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> > @@ -20,6 +20,8 @@ properties:
> > - items:
>
> I the "- items:" can be dropped, reducing indentation of the block
> below.
>
Agreed.
> > - enum:
> > - renesas,scif-r7s9210 # RZ/A2
> > + - renesas,scif-r9a07g044 # RZ/G2{L,LC}
> > + - renesas,scif-r9a09g057 # RZ/V2H(P)
>
> This block now indeed contains all single compatible values, but it
> is still located in the middle of other multi-compatible entries.
> What about making it the first block in the "oneOf:"?
>
Ok, I will move it at the top and send a v2.
Cheers,
Prabhakar
>
> For the contents:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply
* Re: [PATCH] dt-bindings: serial: sh-sci: Fold single-entry compatibles into enum
From: Geert Uytterhoeven @ 2026-01-09 13:28 UTC (permalink / raw)
To: Prabhakar
Cc: Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, linux-kernel, linux-serial, devicetree,
linux-renesas-soc, Biju Das, Fabrizio Castro, Lad Prabhakar
In-Reply-To: <20260109123828.2470826-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Prabhakar,
On Fri, 9 Jan 2026 at 13:38, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Group single compatibles into enum.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> @@ -20,6 +20,8 @@ properties:
> - items:
I the "- items:" can be dropped, reducing indentation of the block
below.
> - enum:
> - renesas,scif-r7s9210 # RZ/A2
> + - renesas,scif-r9a07g044 # RZ/G2{L,LC}
> + - renesas,scif-r9a09g057 # RZ/V2H(P)
This block now indeed contains all single compatible values, but it
is still located in the middle of other multi-compatible entries.
What about making it the first block in the "oneOf:"?
For the contents:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH] dt-bindings: serial: sh-sci: Fold single-entry compatibles into enum
From: Prabhakar @ 2026-01-09 12:38 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm
Cc: linux-kernel, linux-serial, devicetree, linux-renesas-soc,
Prabhakar, Biju Das, Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Group single compatibles into enum.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../devicetree/bindings/serial/renesas,scif.yaml | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
index 72483bc3274d..d4cdbbf4c1f1 100644
--- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
@@ -20,6 +20,8 @@ properties:
- items:
- enum:
- renesas,scif-r7s9210 # RZ/A2
+ - renesas,scif-r9a07g044 # RZ/G2{L,LC}
+ - renesas,scif-r9a09g057 # RZ/V2H(P)
- items:
- enum:
@@ -76,10 +78,6 @@ properties:
- const: renesas,rcar-gen5-scif # R-Car Gen5
- const: renesas,scif # generic SCIF compatible UART
- - items:
- - enum:
- - renesas,scif-r9a07g044 # RZ/G2{L,LC}
-
- items:
- enum:
- renesas,scif-r9a07g043 # RZ/G2UL and RZ/Five
@@ -87,8 +85,6 @@ properties:
- renesas,scif-r9a08g045 # RZ/G3S
- const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback
- - const: renesas,scif-r9a09g057 # RZ/V2H(P)
-
- items:
- enum:
- renesas,scif-r9a09g047 # RZ/G3E
--
2.52.0
^ permalink raw reply related
* Re: [PATCH v3 05/11] dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings
From: Guodong Xu @ 2026-01-09 10:12 UTC (permalink / raw)
To: Yixun Lan
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Daniel Lezcano,
Thomas Gleixner, Samuel Holland, Anup Patel, Greg Kroah-Hartman,
Jiri Slaby, Lubomir Rintel, Yangyu Chen, Paul Walmsley,
Conor Dooley, Heinrich Schuchardt, Kevin Meng Zhang, Andrew Jones,
devicetree, linux-riscv, linux-kernel, spacemit, linux-serial
In-Reply-To: <20260109033608-GYA3681@gentoo.org>
Hi, Yixun
On Fri, Jan 9, 2026 at 11:36 AM Yixun Lan <dlan@gentoo.org> wrote:
>
> Hi Guodong,
>
> On 20:25 Thu 08 Jan , Guodong Xu wrote:
> > Add DT binding documentation for the SpacemiT K3 SoC and the board Pico-ITX
> > which is a 2.5-inch single-board computer.
> >
> > Signed-off-by: Guodong Xu <guodong@riscstar.com>
> > ---
> > v3: No change.
> > v2: Use one-blank-space between name and email address.
> > ---
> > Documentation/devicetree/bindings/riscv/spacemit.yaml | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml
> > index 9c49482002f768cd0cc59be6db02659a43fa31ce..fe62971c9d1f4a7470eabc0e84e8a747f84baf0d 100644
> > --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml
> > @@ -9,6 +9,7 @@ title: SpacemiT SoC-based boards
> > maintainers:
> > - Yangyu Chen <cyy@cyyself.name>
> > - Yixun Lan <dlan@gentoo.org>
> > + - Guodong Xu <guodong@riscstar.com>
> >
> sort by alphabet letter of first name?
Thanks for the review comments.
Sure, I can do that.
>
> > description:
> > SpacemiT SoC-based boards
> > @@ -26,6 +27,9 @@ properties:
> > - xunlong,orangepi-r2s
> > - xunlong,orangepi-rv2
> > - const: spacemit,k1
> > + - items:
> ..
> > + - const: spacemit,k3-pico-itx
> if DT mainainer has no objection, I'd suggest to change to enum
> - enum:
> - spacemit,k3-pico-itx
>
> although single enum is effectively equivalent to const, but easy for
> adding more boards in future (no change to previous code)..
>
Ok, I see your point. I can find there are other yaml files doing the same
style. If no other objection, I will change it to enum in next version.
BR,
Guodong Xu
> > + - const: spacemit,k3
> >
> > additionalProperties: true
> >
> >
> > --
> > 2.43.0
> >
>
> --
> Yixun Lan (dlan)
^ permalink raw reply
* Re: [PATCH v3 10/11] riscv: dts: spacemit: add initial device tree of SpacemiT K3 SoC
From: Guodong Xu @ 2026-01-09 9:58 UTC (permalink / raw)
To: Samuel Holland
Cc: Paul Walmsley, Conor Dooley, Heinrich Schuchardt,
Kevin Meng Zhang, Andrew Jones, devicetree, linux-riscv,
linux-kernel, spacemit, linux-serial, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Yixun Lan, Daniel Lezcano,
Thomas Gleixner, Anup Patel, Greg Kroah-Hartman, Jiri Slaby,
Lubomir Rintel, Yangyu Chen
In-Reply-To: <77f9a001-7f0a-4c29-abcb-501e875da117@sifive.com>
Hi, Samuel
On Fri, Jan 9, 2026 at 2:19 AM Samuel Holland <samuel.holland@sifive.com> wrote:
>
> On 2026-01-08 6:26 AM, Guodong Xu wrote:
> > SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant.
> > Add nodes of uarts, timer and interrupt-controllers.
> >
> > Signed-off-by: Guodong Xu <guodong@riscstar.com>
> > ---
> > v3: Remove "supm" from the riscv,isa-extensions list.
> > v2: Remove aliases from k3.dtsi, they should be in board DTS.
> > Updated riscv,isa-extensions with new extensions from the extensions.yaml
> > ---
> > arch/riscv/boot/dts/spacemit/k3.dtsi | 548 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 548 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..be9335fba32cb9e81915b2b91cf08c55a5e96809
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> > [...]
> > +
> > + simsic: interrupt-controller@e0400000 {
> > + compatible = "spacemit,k3-imsics","riscv,imsics";
>
> style: missing space after comma
Thanks, Samuel. I will fix that.
>
> > + reg = <0x0 0xe0400000 0x0 0x00200000>;
> > + interrupt-controller;
> > + #interrupt-cells = <0>;
> > + msi-controller;
> > + #msi-cells = <0>;
> > + interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>,
> > + <&cpu2_intc 9>, <&cpu3_intc 9>,
> > + <&cpu4_intc 9>, <&cpu5_intc 9>,
> > + <&cpu6_intc 9>, <&cpu7_intc 9>;
> > + riscv,num-ids = <511>;
> > + riscv,num-guest-ids = <511>;
> > + riscv,hart-index-bits = <4>;
> > + riscv,guest-index-bits = <6>;
> > + };
> > +
> > + saplic: interrupt-controller@e0804000 {
> > + compatible = "spacemit,k3-aplic", "riscv,aplic";
> > + reg = <0x0 0xe0804000 0x0 0x4000>;
> > + msi-parent = <&simsic>;
> > + #interrupt-cells = <2>;
> > + interrupt-controller;
> > + riscv,num-sources = <512>;
> > + };
>
> Does the chip also have M-mode IMSIC and APLIC instances? Those need to be
> represented in the devicetree as well, for M-mode firmware to access them, just
> like the CLINT below.
Yes, the K3 chip does have M-mode IMSIC and APLIC instances. Currently, the
boot firmware (U-Boot) transfers information about these nodes to OpenSBI.
However, you are correct that they should be properly described in the DT.
In the next version, I will add the M-mode APLIC (maplic) and IMSIC (mimsic)
nodes to k3.dtsi, for topology representation and potential firmware usage.
I will set their status to "disabled" because exposing them as "okay" to Linux
causes access faults during driver probing.
Please let me know if this approach (adding them but keeping them disabled)
looks okay to you.
Best regards,
Guodong Xu
>
> Regards,
> Samuel
>
> > +
> > + clint: timer@e081c000 {
> > + compatible = "spacemit,k3-clint", "sifive,clint0";
> > + reg = <0x0 0xe081c000 0x0 0x0004000>;
> > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> > + <&cpu1_intc 3>, <&cpu1_intc 7>,
> > + <&cpu2_intc 3>, <&cpu2_intc 7>,
> > + <&cpu3_intc 3>, <&cpu3_intc 7>,
> > + <&cpu4_intc 3>, <&cpu4_intc 7>,
> > + <&cpu5_intc 3>, <&cpu5_intc 7>,
> > + <&cpu6_intc 3>, <&cpu6_intc 7>,
> > + <&cpu7_intc 3>, <&cpu7_intc 7>;
> > + };
> > + };
> > +};
> >
>
^ permalink raw reply
* Re: [PATCH v2 3/6] dt-bindings: input: google,goldfish-events-keypad: Convert to DT schema
From: Krzysztof Kozlowski @ 2026-01-09 8:23 UTC (permalink / raw)
To: Kuan-Wei Chiu
Cc: airlied, simona, maarten.lankhorst, mripard, tzimmermann, robh,
krzk+dt, conor+dt, dmitry.torokhov, sre, gregkh, jirislaby,
lgirdwood, broonie, jserv, eleanor15x, dri-devel, devicetree,
linux-kernel, linux-input, linux-pm, linux-serial, linux-sound
In-Reply-To: <20260108080836.3777829-4-visitorckw@gmail.com>
On Thu, Jan 08, 2026 at 08:08:33AM +0000, Kuan-Wei Chiu wrote:
> +
> +examples:
> + - |
> + keypad@9040000 {
> + compatible = "google,goldfish-events-keypad";
> + reg = <0x9040000 0x1000>;
> + interrupts = <0x5>;
Same comment as before. It applies everywhere, btw.
> + };
> --
> 2.52.0.457.g6b5491de43-goog
>
^ permalink raw reply
* Re: [PATCH v2 1/6] dt-bindings: serial: google,goldfish-tty: Convert to DT schema
From: Krzysztof Kozlowski @ 2026-01-09 8:20 UTC (permalink / raw)
To: Kuan-Wei Chiu
Cc: airlied, simona, maarten.lankhorst, mripard, tzimmermann, robh,
krzk+dt, conor+dt, dmitry.torokhov, sre, gregkh, jirislaby,
lgirdwood, broonie, jserv, eleanor15x, dri-devel, devicetree,
linux-kernel, linux-input, linux-pm, linux-serial, linux-sound
In-Reply-To: <20260108080836.3777829-2-visitorckw@gmail.com>
On Thu, Jan 08, 2026 at 08:08:31AM +0000, Kuan-Wei Chiu wrote:
> Convert the Google Goldfish TTY binding to DT schema format.
> Move the file to the serial directory to match the subsystem.
> Update the example node name to 'serial' to comply with generic node
> naming standards.
>
> Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
> ---
> Changes in v2:
> - Add reference to serial.yaml schema.
> - Change additionalProperties to unevaluatedProperties: false.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3 05/11] dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings
From: Yixun Lan @ 2026-01-09 3:36 UTC (permalink / raw)
To: Guodong Xu
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Daniel Lezcano,
Thomas Gleixner, Samuel Holland, Anup Patel, Greg Kroah-Hartman,
Jiri Slaby, Lubomir Rintel, Yangyu Chen, Paul Walmsley,
Conor Dooley, Heinrich Schuchardt, Kevin Meng Zhang, Andrew Jones,
devicetree, linux-riscv, linux-kernel, spacemit, linux-serial
In-Reply-To: <20260108-k3-basic-dt-v3-5-ed99eb4c3ad3@riscstar.com>
Hi Guodong,
On 20:25 Thu 08 Jan , Guodong Xu wrote:
> Add DT binding documentation for the SpacemiT K3 SoC and the board Pico-ITX
> which is a 2.5-inch single-board computer.
>
> Signed-off-by: Guodong Xu <guodong@riscstar.com>
> ---
> v3: No change.
> v2: Use one-blank-space between name and email address.
> ---
> Documentation/devicetree/bindings/riscv/spacemit.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml
> index 9c49482002f768cd0cc59be6db02659a43fa31ce..fe62971c9d1f4a7470eabc0e84e8a747f84baf0d 100644
> --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml
> +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml
> @@ -9,6 +9,7 @@ title: SpacemiT SoC-based boards
> maintainers:
> - Yangyu Chen <cyy@cyyself.name>
> - Yixun Lan <dlan@gentoo.org>
> + - Guodong Xu <guodong@riscstar.com>
>
sort by alphabet letter of first name?
> description:
> SpacemiT SoC-based boards
> @@ -26,6 +27,9 @@ properties:
> - xunlong,orangepi-r2s
> - xunlong,orangepi-rv2
> - const: spacemit,k1
> + - items:
..
> + - const: spacemit,k3-pico-itx
if DT mainainer has no objection, I'd suggest to change to enum
- enum:
- spacemit,k3-pico-itx
although single enum is effectively equivalent to const, but easy for
adding more boards in future (no change to previous code)..
> + - const: spacemit,k3
>
> additionalProperties: true
>
>
> --
> 2.43.0
>
--
Yixun Lan (dlan)
^ permalink raw reply
* Re: [PATCH v2 11/13] dt-bindings: riscv: Add Supm extension description
From: Samuel Holland @ 2026-01-08 19:45 UTC (permalink / raw)
To: Conor Dooley, Heinrich Schuchardt
Cc: Rob Herring, Alex Elder, Guodong Xu, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Yixun Lan, Daniel Lezcano, Thomas Gleixner,
Anup Patel, Greg Kroah-Hartman, Jiri Slaby, Lubomir Rintel,
Yangyu Chen, Paul Walmsley, Kevin Meng Zhang, Andrew Jones,
devicetree, linux-riscv, linux-kernel, spacemit, linux-serial
In-Reply-To: <20251231-grew-abrasion-dc1a9d34e632@spud>
Hi all,
(Also replied to the v1 thread:
https://lore.kernel.org/linux-riscv/9504b2f6-12f5-46c2-ac74-826dba3fb530@sifive.com/)
On 2025-12-31 6:08 PM, Conor Dooley wrote:
>> Should supm be handled in the same way? Add it to the device-tree of
>> RVA23U64 devices. If a kernel does not support pointer masking in user
>> space, hide the extension in cpufeature.c.
>
> Perhaps.
> Samuel opted not to add supm to dt when he introduced the other relevant
> extensions, so the rationale from him would be helpful but I'd like to
> get more opinions on how to deal with supm specifically. supm doesn't
> really describe hardware capability, since the privilege specific
> instructions are what does that, which makes me question if it should be
> in dt at all. On the other hand, it could be argued that supm describes
> a combination of hardware capability at the dt consumer's privilege level
> and is valid on that basis. Some wording like Zkr will probably be needed,
> specifically mentioning that having supm in the dt means that corresponding
> version sxnpm for the privilege level that the devicetree is provided to
> is supported.
Supm describes a combination of the hardware capability (Smnpm or Ssnpm), the
consumer's privilege level (U), and the software at the next higher privilege
level (M or S).
If the DT is targeting U-mode, then I can see a case for adding Supm to the DT
either at runtime or based on the known capabilities of the
next-higher-privilege-mode software. So it could make sense to add a binding for
Supm. But we still shouldn't add Supm to this particular DT, because 1) this DT
is not targeting U-mode, and 2) this DT is not bound to a particular version of
S-mode software.
> Either way, we are going to need something in cpufeature.c to imply
> supm so that it appears to userspace if the privilege specific extension
> is detected and supm is enabled in the kernel. The kernel already does
> the implication internally it just isn't reported as an extension to
> userspace IIRC.
> If we permit supm in dt, we're also going to have to turn supm off if
> the Kconfig option is disabled, but that's relatively little effort
> since it mostly (or maybe entirely) reuses code from implying supm.
It's currently exposed to hwprobe() but not in /proc/cpuinfo. This was based on
my understanding that hwprobe() was the right way to check for availability of
extensions. I'm okay with adding it to /proc/cpuinfo if there's value in doing
so, but I would recommend that the extension in cpufeature.c is _not_ parsed
from the DT and only enabled synthetically.
Regards,
Samuel
^ permalink raw reply
* Re: [PATCH 7/8] riscv: dts: spacemit: add initial device tree of SpacemiT K3 SoC
From: Samuel Holland @ 2026-01-08 19:23 UTC (permalink / raw)
To: Conor Dooley, Heinrich Schuchardt
Cc: Guodong Xu, Paul Walmsley, Palmer Dabbelt, Kevin Meng Zhang,
devicetree, linux-riscv, linux-kernel, spacemit, linux-serial,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan,
Daniel Lezcano, Thomas Gleixner, Anup Patel, Greg Kroah-Hartman,
Jiri Slaby, Lubomir Rintel, Yangyu Chen
In-Reply-To: <20251222-dimmer-wooing-db29fe925498@spud>
Hi all,
Sorry, I wasn't following this thread.
On 2025-12-22 2:36 PM, Conor Dooley wrote:
> On Sun, Dec 21, 2025 at 01:10:15AM +0100, Heinrich Schuchardt wrote:
>> On 12/21/25 00:23, Conor Dooley wrote:
>>> On Fri, Dec 19, 2025 at 10:03:24AM +0800, Guodong Xu wrote:
>>>> Hi, Conor and Heinrich
>>>>
>>>> On Thu, Dec 18, 2025 at 8:56 AM Conor Dooley <conor@kernel.org> wrote:
>>>>>
>>>>> On Wed, Dec 17, 2025 at 09:07:14AM +0100, Heinrich Schuchardt wrote:
>>>>>> On 12/17/25 08:11, Guodong Xu wrote:
>>>>>
>>>>>>> Specifically, I must adhere to
>>>>>>> Documentation/devicetree/bindings/riscv/extensions.yaml (and cpus.yaml for
>>>>>>> properties like 'riscv,sv39' which stands for the extension Sv39). If I
>>>>>>> add extension strings that are not yet defined in these schemas, such as
>>>>>>> supm, running 'make dtbs_check W=3' fails with: 'supm' is not one of
>>>>>>> ['i', 'm', 'a', ...], followed by "Unevaluated properties are not allowed."
>>>>>>
>>>>>> If Documentation/devicetree/bindings/riscv/extensions.yaml is incomplete
>>>>>> with respect to ratified extensions, I guess the right approach is to amend
>>>>>> it and not to curtail the CPU description.
>>>>>
>>>>> Absolutely. If the cpu supports something that is not documented, then
>>>>> please document it rather than omit from the devicetree.
>>>>
>>>> Thanks for the review. May I clarify one thing? Both of you mentioned
>>>> document them, given the amount of missing extensions, is it acceptable if
>>>> I submit a prerequisite patch that only documents these strings in
>>>> riscv/extensions.yaml plus the necessary hwprobe export? Leaving the actual
>>>> usage of these extensions (named features) to the future patches.
>>>>
>>>> To provide some context on why I ask: I've investigated the commits & lkml
>>>> history of RISC-V extensions since v6.5, and I summarized the current status
>>>> regarding the RVA23 profile here:
>>>> [1] status in v6.18 (inc. v6.19-rc1):
>>>> https://docularxu.github.io/rva23/linux-kernel-coverage.html
>>>> [2] support evolution since v6.5:
>>>> https://docularxu.github.io/rva23/rva23-kernel-support-evolution.html
>>>>
>>>> Strictly describing the SpacemiT X100/K3 (or any core) as RVA23-compliant
>>>> requires adding these extensions that are currently missing from
>>>> the kernel bindings:
>>>> RVA23U64: Ziccif, Ziccamoa, Zicclsm, Za64rs
>>>> RVA23S64: Ss1p13, Ssccptr, Sstvecd, Sstvala, Sscounterenw, Ssu64xl,
>>>> Sha, Shcounterenw, Shvstvala, Shtvala, Shvstvecd, Shvsatpa, Shgatpa
>>>
>>>
>>>> Plus 'Supm', 'Zic64b', 'Ssstateen', 'B' where the kernel supports them but
>>>> they are not literally documented in yaml.
>>>
>>> I don't think Supm is suitable for devicetree, doesn't it describe
>>> what the kernel/userspace are capable of rather than hardware?
>>> Zic64b doesn't sound like hardware description (so not really suitable
>>> for devicetree either) but block size information is already represented
>>> by some existing properties (see riscv,cbo*-block-size in riscv/cpus.yaml)
>>> and duplicating that information is not really a great idea.
>>>
>>> I'll admit that I do not really understand Sxstateen and how they work,
>>> but my understanding was that knowing about Smstateen is sufficient and
>>> implied Sstateen, but having Ssstateen defined seems harmless and
>>> possible. I think kvm is the only user of this at the moment, so
>>> probably worth CCing Anup and maybe Drew Jones on the patch adding
>>> Ssstateen to make sure it makes sense.
>>
>> Supm is described in
>>
>> RISC-V Pointer Masking
>> Version 1.0, 10/2024: Ratified
>> https://raw.githubusercontent.com/riscv/riscv-j-extension/master/zjpm-spec.pdf
>>
>> The interpretation taken by QEMU has been:
>>
>> * Supm implies Ssnpm and Smnpm
This is not correct for system emulation. Supm (pointer masking visible in the
U-mode execution environment) requires exactly (S ? Ssnpm : Smnpm), not both of
them.
>> * RVA23 capable machine models display it in the device-tree
This is also not correct for system emulation. It is impossible for QEMU to know
if pointer masking is visible to the U-mode execution environment, because QEMU
does not provide the U-mode execution environment. Software inside the VM does.
>> If Supm is not shown in the device-tree, software might assume that the
>> system does not support pointer masking in user mode and is not RVA23
>> compliant.
Software shouldn't be looking for Supm in the devicetree, because the devicetree
does not describe the properties of the U-mode execution environment.
>> Hence I would suggest:
>>
>> If the X100 cores have Ssnpm and Smnpm, add Supm to the device-tree.
>>
>> If the kernel does not support user space pointer masking, the kernel should
>> filter out Supm and not announce it, neither in /proc/cpuinfo nor via
>> hwprobe.
>
> Samuel seems to have some specific thoughts on how this works, given he
> didn't blindly implement ssnpm and smnpm, but has made supm be mode
> dependent and not permitted in dt, hopefully he sees this.
>
> Personally I'm not convinced that putting supm in dt makes sense, but
> instead the kernel should imply it if the sxnpm extension matching the
> mode the kernel is operating in is present and RISCV_ISA_SUPM is set in
> Kconfig. That's effectively how it works at present, except it'd involve
> promoting RISCV_ISA_SUPM to a "real" extension instead of being a macro.
> A validate callback should easily be able to handle checking the
> mode and whether the Kconfig option is set.
> That way it would get exposed to userspace using the actual mechanisms,
> reading the devicetree itself from userspace is not a valid way of
> checking what extensions are usable after all.
We already do this for hwprobe(), so the only difference is that Supm would be
added to /proc/cpuinfo. I don't think I have a problem with this.
Regards,
Samuel
^ permalink raw reply
* Re: [PATCH v3 10/11] riscv: dts: spacemit: add initial device tree of SpacemiT K3 SoC
From: Samuel Holland @ 2026-01-08 18:19 UTC (permalink / raw)
To: Guodong Xu
Cc: Paul Walmsley, Conor Dooley, Heinrich Schuchardt,
Kevin Meng Zhang, Andrew Jones, devicetree, linux-riscv,
linux-kernel, spacemit, linux-serial, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, Yixun Lan, Daniel Lezcano,
Thomas Gleixner, Anup Patel, Greg Kroah-Hartman, Jiri Slaby,
Lubomir Rintel, Yangyu Chen
In-Reply-To: <20260108-k3-basic-dt-v3-10-ed99eb4c3ad3@riscstar.com>
On 2026-01-08 6:26 AM, Guodong Xu wrote:
> SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant.
> Add nodes of uarts, timer and interrupt-controllers.
>
> Signed-off-by: Guodong Xu <guodong@riscstar.com>
> ---
> v3: Remove "supm" from the riscv,isa-extensions list.
> v2: Remove aliases from k3.dtsi, they should be in board DTS.
> Updated riscv,isa-extensions with new extensions from the extensions.yaml
> ---
> arch/riscv/boot/dts/spacemit/k3.dtsi | 548 +++++++++++++++++++++++++++++++++++
> 1 file changed, 548 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..be9335fba32cb9e81915b2b91cf08c55a5e96809
> --- /dev/null
> +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> [...]
> +
> + simsic: interrupt-controller@e0400000 {
> + compatible = "spacemit,k3-imsics","riscv,imsics";
style: missing space after comma
> + reg = <0x0 0xe0400000 0x0 0x00200000>;
> + interrupt-controller;
> + #interrupt-cells = <0>;
> + msi-controller;
> + #msi-cells = <0>;
> + interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>,
> + <&cpu2_intc 9>, <&cpu3_intc 9>,
> + <&cpu4_intc 9>, <&cpu5_intc 9>,
> + <&cpu6_intc 9>, <&cpu7_intc 9>;
> + riscv,num-ids = <511>;
> + riscv,num-guest-ids = <511>;
> + riscv,hart-index-bits = <4>;
> + riscv,guest-index-bits = <6>;
> + };
> +
> + saplic: interrupt-controller@e0804000 {
> + compatible = "spacemit,k3-aplic", "riscv,aplic";
> + reg = <0x0 0xe0804000 0x0 0x4000>;
> + msi-parent = <&simsic>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + riscv,num-sources = <512>;
> + };
Does the chip also have M-mode IMSIC and APLIC instances? Those need to be
represented in the devicetree as well, for M-mode firmware to access them, just
like the CLINT below.
Regards,
Samuel
> +
> + clint: timer@e081c000 {
> + compatible = "spacemit,k3-clint", "sifive,clint0";
> + reg = <0x0 0xe081c000 0x0 0x0004000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> + <&cpu1_intc 3>, <&cpu1_intc 7>,
> + <&cpu2_intc 3>, <&cpu2_intc 7>,
> + <&cpu3_intc 3>, <&cpu3_intc 7>,
> + <&cpu4_intc 3>, <&cpu4_intc 7>,
> + <&cpu5_intc 3>, <&cpu5_intc 7>,
> + <&cpu6_intc 3>, <&cpu6_intc 7>,
> + <&cpu7_intc 3>, <&cpu7_intc 7>;
> + };
> + };
> +};
>
^ permalink raw reply
* [PATCH v2 1/2] serial: men_z135_uart: drop unneeded MODULE_ALIAS
From: Jose Javier Rodriguez Barbarin @ 2026-01-08 13:41 UTC (permalink / raw)
To: gregkh, jirislaby
Cc: andriy.shevchenko, dev-jorge.sanjuangarcia, linux-serial,
linux-kernel, Jose Javier Rodriguez Barbarin
In-Reply-To: <20260108134110.25278-1-dev-josejavier.rodriguez@duagon.com>
Since commit 1f4ea4838b13 ("mcb: Add missing modpost build support")
the MODULE_ALIAS() is redundant as the module alias is now
automatically generated from the MODULE_DEVICE_TABLE().
Remove the explicit alias.
No functional change intended.
Reviewed-by: Jorge Sanjuan Garcia <dev-jorge.sanjuangarcia@duagon.com>
Signed-off-by: Jose Javier Rodriguez Barbarin <dev-josejavier.rodriguez@duagon.com>
---
drivers/tty/serial/men_z135_uart.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/tty/serial/men_z135_uart.c b/drivers/tty/serial/men_z135_uart.c
index 9cc15449b673..6fad57fee912 100644
--- a/drivers/tty/serial/men_z135_uart.c
+++ b/drivers/tty/serial/men_z135_uart.c
@@ -919,5 +919,4 @@ module_exit(men_z135_exit);
MODULE_AUTHOR("Johannes Thumshirn <johannes.thumshirn@men.de>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MEN 16z135 High Speed UART");
-MODULE_ALIAS("mcb:16z135");
MODULE_IMPORT_NS("MCB");
--
2.52.0
^ permalink raw reply related
* [PATCH v2 2/2] 8250_men_mcb: drop unneeded MODULE_ALIAS
From: Jose Javier Rodriguez Barbarin @ 2026-01-08 13:41 UTC (permalink / raw)
To: gregkh, jirislaby
Cc: andriy.shevchenko, dev-jorge.sanjuangarcia, linux-serial,
linux-kernel, Jose Javier Rodriguez Barbarin
In-Reply-To: <20260108134110.25278-1-dev-josejavier.rodriguez@duagon.com>
Since commit 1f4ea4838b13 ("mcb: Add missing modpost build support")
the MODULE_ALIAS() is redundant as the module alias is now
automatically generated from the MODULE_DEVICE_TABLE().
Remove the explicit alias.
No functional change intended.
Reviewed-by: Jorge Sanjuan Garcia <dev-jorge.sanjuangarcia@duagon.com>
Signed-off-by: Jose Javier Rodriguez Barbarin <dev-josejavier.rodriguez@duagon.com>
---
drivers/tty/serial/8250/8250_men_mcb.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_men_mcb.c b/drivers/tty/serial/8250/8250_men_mcb.c
index a78ef35c8187..9774a95f2980 100644
--- a/drivers/tty/serial/8250/8250_men_mcb.c
+++ b/drivers/tty/serial/8250/8250_men_mcb.c
@@ -268,7 +268,4 @@ module_mcb_driver(mcb_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MEN 8250 UART driver");
MODULE_AUTHOR("Michael Moese <michael.moese@men.de");
-MODULE_ALIAS("mcb:16z125");
-MODULE_ALIAS("mcb:16z025");
-MODULE_ALIAS("mcb:16z057");
MODULE_IMPORT_NS("MCB");
--
2.52.0
^ permalink raw reply related
* [PATCH v2 0/2] serial: Remove MODULE_ALIAS from mcb client drivers
From: Jose Javier Rodriguez Barbarin @ 2026-01-08 13:41 UTC (permalink / raw)
To: gregkh, jirislaby
Cc: andriy.shevchenko, dev-jorge.sanjuangarcia, linux-serial,
linux-kernel, Jose Javier Rodriguez Barbarin
The first patches I sent for fixing the autoload problem encountered
on mcb device drivers were 2. The first [1] was focused on updating the
modpost process for letting kbuild to access to the data within
MODULE_DEVICE_TABLE and the second one [2] for removing the MODULE_ALIAS
on all mcb client drivers.
They were rejected and Andy suggested me to split the second patch
in a per-driver basis instead of sending all drivers' changes in a
single patch once the first patch was merged.
The first patch is already merged on Linus's Git repository for 6.19-rc4
commit 1f4ea4838b13 ("mcb: Add missing modpost build support")
So now I am sending this patch series for removing MODULE_ALIAS
on all mcb client drivers as it is no longer required. This cleanup
is being sent to each affected subsystem separately, as per the review
suggestion to ease the handling for maintainers.
[1] https://lore.kernel.org/all/20251127155452.42660-2-dev-josejavier.rodriguez@duagon.com/
[2] https://lore.kernel.org/all/20251127155452.42660-3-dev-josejavier.rodriguez@duagon.com/
changes in v2:
- Renane commit messages
Jose Javier Rodriguez Barbarin (2):
serial: men_z135_uart: drop unneeded MODULE_ALIAS
8250_men_mcb: drop unneeded MODULE_ALIAS
drivers/tty/serial/8250/8250_men_mcb.c | 3 ---
drivers/tty/serial/men_z135_uart.c | 1 -
2 files changed, 4 deletions(-)
--
2.52.0
^ permalink raw reply
* Re: [PATCH] dt-bindings: serial: renesas,rsci: Document RZ/V2H(P) and RZ/V2N SoCs
From: Geert Uytterhoeven @ 2026-01-08 12:47 UTC (permalink / raw)
To: Prabhakar
Cc: Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, linux-kernel, linux-serial, devicetree,
linux-renesas-soc, Biju Das, Fabrizio Castro, Lad Prabhakar
In-Reply-To: <20251222162909.155279-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Mon, 22 Dec 2025 at 17:29, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Document the serial communication interface (RSCI) used on the Renesas
> RZ/V2H(P) (R9A09G057) and RZ/V2N (R9A09G056) SoCs. These SoCs integrate
> the same RSCI IP block as the RZ/G3E (R9A09G047), so the RZ/G3E
> compatible is used as a fallback for both.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH v3 11/11] riscv: dts: spacemit: add SpacemiT K3 Pico-ITX board device tree
From: Guodong Xu @ 2026-01-08 12:26 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan,
Daniel Lezcano, Thomas Gleixner, Samuel Holland, Anup Patel,
Greg Kroah-Hartman, Jiri Slaby, Lubomir Rintel, Yangyu Chen
Cc: Paul Walmsley, Conor Dooley, Heinrich Schuchardt,
Kevin Meng Zhang, Anup Patel, Andrew Jones, devicetree,
linux-riscv, linux-kernel, spacemit, linux-serial, Guodong Xu
In-Reply-To: <20260108-k3-basic-dt-v3-0-ed99eb4c3ad3@riscstar.com>
K3 Pico-ITX is a 2.5-inch single-board computer equipted with a SpacemiT
K3 SoC.
This minimal device tree enables booting into a serial console with UART
output.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v3: No change.
v2: Add aliases node in this board DT.
Update the memory node to reflect the hardware truth. Address
starts at 0x100000000 (4G) boundary.
---
arch/riscv/boot/dts/spacemit/Makefile | 1 +
arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 38 ++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile
index 95889e7269d1bae679b28cd053e1b0a23ae6de68..7e2b877025718113a0e31917eadf7562f488d825 100644
--- a/arch/riscv/boot/dts/spacemit/Makefile
+++ b/arch/riscv/boot/dts/spacemit/Makefile
@@ -4,3 +4,4 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb
dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb
dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb
dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb
+dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb
diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
new file mode 100644
index 0000000000000000000000000000000000000000..037ce757e5bcae0258a326ea6265185d761f2b52
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2025 SpacemiT (Hangzhou) Technology Co. Ltd
+ * Copyright (c) 2025 Guodong Xu <guodong@riscstar.com>
+ */
+
+#include "k3.dtsi"
+
+/ {
+ model = "SpacemiT K3 Pico-ITX";
+ compatible = "spacemit,k3-pico-itx", "spacemit,k3";
+
+ aliases {
+ serial0 = &uart0;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ serial8 = &uart8;
+ serial9 = &uart9;
+ serial10 = &uart10;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ memory@100000000 {
+ device_type = "memory";
+ reg = <0x1 0x00000000 0x4 0x00000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
--
2.43.0
^ permalink raw reply related
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