* Re: [RFC PATCH v1 2/9] uaccess: Convert INLINE_COPY_{TO/FROM}_USER to kconfig and reduce ifdefery
From: Andrew Cooper @ 2026-04-28 9:36 UTC (permalink / raw)
To: Yury Norov
Cc: Andrew Cooper, Christophe Leroy (CS GROUP), Andrew Morton,
Linus Torvalds, David Laight, Thomas Gleixner, linux-alpha,
Yury Norov, linux-kernel, linux-snps-arc, linux-arm-kernel,
linux-mips, linuxppc-dev, kvm, linux-riscv, linux-s390,
sparclinux, linux-um, dmaengine, linux-efi, linux-fsi, amd-gfx,
dri-devel, intel-gfx, linux-wpan, netdev, linux-wireless,
linux-spi, linux-media, linux-staging, linux-serial, linux-usb,
xen-devel, linux-fsdevel, ocfs2-devel, bpf, kasan-dev, linux-mm,
linux-x25, rust-for-linux, linux-sound, sound-open-firmware,
linux-csky, linux-hexagon, loongarch, linux-m68k, linux-openrisc,
linux-parisc, linux-sh, linux-arch
In-Reply-To: <ae_LeSk7XDEseaZb@yury>
On 27/04/2026 9:47 pm, Yury Norov wrote:
> On Mon, Apr 27, 2026 at 09:39:33PM +0100, Andrew Cooper wrote:
>> On 27/04/2026 7:39 pm, Yury Norov wrote:
>>> On Mon, Apr 27, 2026 at 07:13:43PM +0200, Christophe Leroy (CS GROUP) wrote:
>>>> Among the 21 architectures supported by the kernel, 16 define both
>>>> INLINE_COPY_TO_USER and INLINE_COPY_FROM_USER while the 5 other ones
>>>> don't define any of the two.
>>>>
>>>> To simplify and reduce risk of mistakes, convert them to a single
>>>> kconfig item named CONFIG_ARCH_WANTS_NOINLINE_COPY which will be
>>> We've got a special word for it: outline. Can you name it
>>> CONFIG_OUTLINE_USERCOPY, or similar?
>> You can't swap the "in" for "out" like this. "out of line" is the
>> opposite of "inline" in this context, while "outline" means something
>> different and unrelated.
> Check KASAN_OUTLINE vs KASAN_INLINE for example
Then I suggest it gets corrected before more examples try to copy this
non-english.
~Andrew
^ permalink raw reply
* Re: [PATCH] serial: 8250_pci: skip WCH PCI serial devices
From: Andy Shevchenko @ 2026-04-28 9:56 UTC (permalink / raw)
To: Jiawei liu; +Cc: linux-serial, gregkh, jirislaby, linux-kernel
In-Reply-To: <CAGDm1S3mCv_7usfP0dx9jqj+mt_vBD4z8gu5wVyPbXB2Kh-mgg@mail.gmail.com>
On Tue, Apr 28, 2026 at 04:26:34PM +0800, Jiawei liu wrote:
> WCH PCI serial devices implement vendor-specific extensions
> beyond the standard 16C550 UART. These are not supported by
> the generic 8250 PCI driver, and binding them may lead to
> incorrect or suboptimal operation.
>
> Skip these devices during probe to avoid misbinding.
>
> Signed-off-by: Jiawei Liu <liujiawei4419@gmail.com>
Besides the broken way on sending patches — spend your time reading
documentation and reviewing others' code first, please, — this change
breaks the cases where it works.
100% NAK. Try again when you will have a driver that supports them including
mentioned vendor extensions, before that this patch won't ever be accepted.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* [PATCH AUTOSEL 7.0-6.12] tty: serial: samsung_tty: avoid dev_dbg deadlock
From: Sasha Levin @ 2026-04-28 10:40 UTC (permalink / raw)
To: patches, stable
Cc: Alyssa Milburn, Greg Kroah-Hartman, Sasha Levin,
krzysztof.kozlowski, jirislaby, linux-arm-kernel,
linux-samsung-soc, linux-kernel, linux-serial
In-Reply-To: <20260428104133.2858589-1-sashal@kernel.org>
From: Alyssa Milburn <amilburn@zall.org>
[ Upstream commit 43c2b86ff633c34831c8430925ba73d7c20da1ad ]
commit a05025d0ce72 ("tty: serial: samsung_tty: use standard
debugging macros") changed the debug prints to dev_dbg, which can
result in deadlocks:
s3c24xx_serial_set_termios can be called with the port lock, and then
calls dev_dbg, which needs the console mutex. At the same time,
s3c24xx_serial_console_write can be called with the console lock
(e.g., inside console_unlock), and needs the port lock.
To avoid this, move one dev_dbg call and just delete the other.
Signed-off-by: Alyssa Milburn <amilburn@zall.org>
Link: https://patch.msgid.link/aXny9km6N1v9eoXU@zall.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
LLM Generated explanations, may be completely bogus:
Now I have all the information needed. Let me write up the full
analysis:
## Complete 9-Phase Analysis
### PHASE 1: COMMIT MESSAGE FORENSICS
**Step 1.1 - Subject line parsing:**
Record: Subsystem `tty: serial: samsung_tty:`, action verb `avoid`,
summary: avoid dev_dbg deadlock between port lock and console lock.
**Step 1.2 - Commit message tags:**
Record:
- `Signed-off-by: Alyssa Milburn <amilburn@zall.org>` (author)
- `Link: https://patch.msgid.link/aXny9km6N1v9eoXU@zall.org` (original
submission)
- `Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>` (TTY
subsystem maintainer applied)
- No explicit `Fixes:` tag, but the commit body names `a05025d0ce72` as
introducing the issue
- No `Cc: stable@vger.kernel.org` (expected, as the prompt notes)
- No Reviewed-by/Acked-by/Tested-by tags
- No syzbot/Reported-by
**Step 1.3 - Commit body:**
Record: Bug description: `s3c24xx_serial_set_termios` acquires port lock
then calls `dev_dbg`, which goes through printk and can require the
console mutex. Meanwhile `s3c24xx_serial_console_write` runs with the
console lock held (e.g., from `console_unlock`) and acquires the port
lock. Classic AB-BA deadlock (port_lock ↔ console_lock). Fix: move one
`dev_dbg` before the port lock acquisition and remove the second (post-
write register-dump `dev_dbg`).
**Step 1.4 - Hidden bug fix?** Not hidden - explicit "avoid deadlock".
### PHASE 2: DIFF ANALYSIS
**Step 2.1 - Inventory:**
Record: 1 file (`drivers/tty/serial/samsung_tty.c`), +2/-8 lines total
(6 net deletion). One function modified: `s3c24xx_serial_set_termios()`.
Scope: single-file, surgical.
**Step 2.2 - Code flow change:**
Record:
- Before: `uart_port_lock_irqsave(...)` → `dev_dbg("setting ulcon ...")`
→ reg writes → `dev_dbg("uart: ulcon = ... ")` (reading registers
back)
- After: `dev_dbg("setting ulcon ...")` → `uart_port_lock_irqsave(...)`
→ reg writes → (second dev_dbg removed)
The first `dev_dbg` only prints local variables (`ulcon, quot,
udivslot`) so moving it before the lock is safe. The second `dev_dbg`
re-read registers to report actual written values - removing it loses
diagnostic info but avoids the deadlock (moving it outside the lock
would read values that could race with other writes).
**Step 2.3 - Bug mechanism:**
Record: Synchronization fix (category b): removes an AB-BA deadlock
potential between the UART port spinlock (`port->lock`) and the
printk/console locking chain.
Verified dead-lock mechanism:
- `set_termios` holds `port->lock` (uart_port_lock_irqsave)
- `dev_dbg()` expands (when dynamic debug is enabled) to a printk call
that can enter `console_unlock()` → `console->write()` →
`s3c24xx_serial_console_write()` → which calls
`uart_port_lock_irqsave(cons_uart, &flags)` = same port lock. On the
same CPU that would self-deadlock; across CPUs it forms the AB-BA
pattern with another printk path.
- Confirmed `s3c24xx_serial_console_write` does
`uart_port_lock_irqsave(cons_uart, &flags)` (samsung_tty.c lines
2280-2283 in HEAD).
**Step 2.4 - Fix quality:**
Record: Fix is obvious - debug prints are diagnostic-only; moving one
out and removing the other cannot change functional behavior. Zero risk
of regression from the fix itself. Only downside: loss of one diagnostic
print.
### PHASE 3: GIT HISTORY INVESTIGATION
**Step 3.1 - Blame/introduction:**
Record: The problematic `dev_dbg` calls were introduced by `a05025d0ce72
"tty: serial: samsung_tty: use standard debugging macros"` (Greg KH, Dec
2019). `git describe --contains a05025d0ce72` → `v5.6-rc1~139^2~130`,
i.e. first released in v5.6 (March 2020).
**Step 3.2 - Fixes target:**
Record: Named `a05025d0ce72` is present in all current LTS stable trees
(5.10.y, 5.15.y, 6.1.y, 6.6.y, 6.12.y, and 7.0.y). Before
`a05025d0ce72`, the samsung_tty driver used a custom `dbg()` macro that
routed to `printascii()` (low-level ARM debug UART write, no locking) -
that's why the original code wasn't a deadlock. After `a05025d0ce72`,
the conversion to `dev_dbg()` introduced the deadlock potential.
**Step 3.3 - File history:**
Record: Recent changes to `drivers/tty/serial/samsung_tty.c` are a small
trickle (Exynos850 earlycon, 18 port support, cast cleanup, etc.). No
churn in the set_termios area since a05025d0ce72. Standalone patch (not
part of a series) - confirmed via `b4 dig -a` showing only v1.
**Step 3.4 - Author context:**
Record: Alyssa Milburn has submitted other kernel patches (media
subsystem from previous years). Not the samsung TTY maintainer, but the
patch was applied by Greg KH (TTY maintainer) after CC'ing the proper
subsystem maintainers.
**Step 3.5 - Dependencies:**
Record: None. Fix is self-contained and touches only local code within
one function.
### PHASE 4: MAILING LIST RESEARCH
**Step 4.1 - Original thread:**
Record: `b4 dig -c 43c2b86ff633c` found match at
https://patch.msgid.link/aXny9km6N1v9eoXU@zall.org. Fetched via `b4 am`
to `/tmp/b4_samsung/`. No review replies found in the thread (the mbox
from b4 contained only the original patch - `b4 am` reported "Analyzing
0 code-review messages"). Single version - no v2/v3.
**Step 4.2 - Recipients (b4 dig -w):**
Record: Proper CC list: Krzysztof Kozlowski (samsung-soc maintainer),
Alim Akhtar (samsung platform maintainer), Greg Kroah-Hartman (TTY
maintainer), Jiri Slaby (TTY co-maintainer), Faraz Ata (samsung
contributor), linux-serial, linux-samsung-soc, linux-arm-kernel, linux-
kernel. Proper maintainer audience; Greg KH signed off, indicating the
TTY maintainer accepted it.
**Step 4.3 - Bug report:**
Record: No `Reported-by:`, no bug URL. The author appears to have
identified the issue through code review/lockdep analysis rather than
user report. Similar patterns have been found by lockdep in other serial
drivers.
**Step 4.4 - Related patches:**
Record: None (single patch).
**Step 4.5 - Stable list:**
Record: Not investigated further; lore.kernel.org fetching is blocked by
Anubis bot-protection. However, `b4` successfully retrieved the thread
without review feedback, so there was no stable-related discussion.
### PHASE 5: CODE SEMANTIC ANALYSIS
**Step 5.1 - Key functions:**
Record: `s3c24xx_serial_set_termios` is the only function modified.
**Step 5.2 - Callers of set_termios:**
Record: Called via `uport->ops->set_termios(...)` from serial_core.c at
three sites: (1) `uart_change_line_settings` (normal termios change),
(2) `uart_configure_port` (probe path), (3) `uart_resume_port` (resume).
All are triggered by common operations (open, `tcsetattr`, resume).
Confirmed `set_termios` is called WITHOUT the port_lock held by
serial_core - the driver itself acquires it internally.
**Step 5.3 - The console-write side:**
Record: `s3c24xx_serial_console_write` is registered as
`s3c24xx_serial_console.write`. Called from the printk/console subsystem
when the samsung serial is the configured console. Takes
`cons_uart->lock` via `uart_port_lock_irqsave(cons_uart, &flags)` (lines
2278-2283). This forms the second half of the AB-BA.
**Step 5.4 - Reachability:**
Record: Deadlock trigger requires: (a) dynamic debug enabled for these
specific `dev_dbg` statements in samsung_tty.c, AND (b) samsung_tty
serves as a console, AND (c) a termios change happens (user
`tcsetattr()`, getty open, resume) while another CPU/task is doing a
printk that's flushing via this console. Practical trigger is uncommon
in production (dynamic debug is off by default) but clearly reachable
from unprivileged userspace when enabled.
**Step 5.5 - Similar patterns:**
Record: Confirmed similar fixes in other serial drivers: `436c979360017
"serial: stm32: fix a deadlock in set_termios"` (same AB-BA between
`&port_lock_key` and `console_owner`), `7fd6f640f2dd1 "serial: 8250_dw:
Fix deadlock in LCR workaround"`, `62b2caef400c1 "drivers: tty: serial:
Fix deadlock in sa1100_set_termios()"`. Well-established bug-class with
accepted fixes.
### PHASE 6: STABLE TREE ANALYSIS
**Step 6.1 - Buggy code in stable:**
Record: The buggy structure (port_lock acquired before `dev_dbg`) is
present in all stable trees ≥ 5.6 (where a05025d0ce72 first appeared).
Verified in 7.0.y HEAD (stable/linux-7.0.y) - the current checkout
contains exactly the pre-patch code. Stable trees 5.10, 5.15, 6.1, 6.6,
6.12, 7.0 are affected.
**Step 6.2 - Backport difficulty:**
Record: Very low difficulty. The hunk context is stable identifiers
(`ulcon, quot, udivslot` variables, `wr_regl(port, S3C2410_ULCON,
ulcon)`). Only complication: older stable trees used
`spin_lock_irqsave(&port->lock, flags)` instead of
`uart_port_lock_irqsave(port, &flags)` (the port-lock wrappers were
introduced by 97d7a9aeba1d4 "serial: samsung_tty: Use port lock
wrappers" which went to various stable trees). Still trivial to backport
by substituting the correct lock call; git will likely auto-apply with
minor context fuzz in old trees.
**Step 6.3 - Already in stable?**
Record: No prior fix for this deadlock in stable trees (confirmed by
file history).
### PHASE 7: SUBSYSTEM CONTEXT
**Step 7.1 - Criticality:**
Record: Subsystem = tty/serial driver for Samsung SoCs (Exynos family,
Apple A7-A11, S3C). Criticality: PERIPHERAL (specific-hardware), but
used extensively on Samsung/Exynos-based embedded systems, Chromebooks,
Google Pixel/development boards, and similar ARM platforms. These
devices often use the samsung_tty as their primary console, which is
exactly the configuration where the deadlock matters.
**Step 7.2 - Activity:**
Record: Mature driver, low-churn subsystem. Active maintenance by
Krzysztof Kozlowski and Greg KH. 20 commits over the last ~2 years per
file history.
### PHASE 8: IMPACT AND RISK
**Step 8.1 - Affected users:**
Record: Users of samsung_tty on Exynos, S3C, Apple Silicon (A7-A11 via
this driver), etc. ARM/ARM64 platforms with Samsung or Apple early SoCs.
Limited to systems where dynamic debug is enabled for this file AND the
UART is a console.
**Step 8.2 - Trigger:**
Record: Requires unusual runtime config (dynamic debug on), so not
common in stock distros. However, fully reachable from userspace
(`tcsetattr()`) once dynamic debug is enabled. Developers debugging on
these platforms can hit it.
**Step 8.3 - Failure mode severity:**
Record: Hard hang (deadlock) - system becomes unresponsive. Severity if
triggered: CRITICAL (system hang). Probability: LOW in production,
HIGHER during debugging sessions.
**Step 8.4 - Benefit/risk:**
Record: BENEFIT = correctness fix for a recognized deadlock class (same
pattern fixed in stm32, 8250_dw, sa1100). RISK = essentially zero: no
functional behavior change, only debug-print placement. 2 insertions, 8
deletions, all in one function. Obviously correct on inspection.
Risk/benefit strongly favors backport.
### PHASE 9: SYNTHESIS
**Step 9.1 - Evidence:**
FOR backport:
- Fixes a real AB-BA deadlock between `port_lock` and the console
subsystem locking
- Extremely small, contained change (+2/-8 lines in a single function)
- Zero risk of behavior regression (only debug prints affected)
- Applied by the TTY subsystem maintainer (Greg KH)
- Proper maintainers and lists were CC'd
- Same bug class has been fixed in other serial drivers (stm32, sa1100,
8250_dw) and those fixes reached stable
- Buggy code has existed since v5.6 (2019), in every LTS tree
AGAINST:
- Trigger requires dynamic debug to be enabled for this file; not a
default-config hang
- No reporter, no lockdep report in the commit message (identified by
code inspection)
- Second `dev_dbg` is deleted rather than relocated (minor loss of
diagnostic info)
**Step 9.2 - Stable rules check:**
1. Obviously correct? YES - inspection-verifiable, no behavioral change
beyond debug placement
2. Fixes a real bug? YES - AB-BA deadlock (class well-documented)
3. Important issue? YES - deadlock/hang
4. Small and contained? YES - 10 lines, one function
5. No new features/APIs? YES - only relocates/removes debug prints
6. Applies to stable? YES - trivial with minor wrapper-name substitution
for older trees
**Step 9.3 - Exception category:** Not an exception case; it's a true
bug fix.
**Step 9.4 - Decision:** YES.
## Verification
- [Phase 1] Parsed tags: Link to patch.msgid.link, SOB author Alyssa
Milburn, SOB Greg KH as committer; no Fixes tag but body names
a05025d0ce72 as introducing commit.
- [Phase 2] Diff: 2 insertions, 8 deletions, single function
`s3c24xx_serial_set_termios`.
- [Phase 2] Verified `s3c24xx_serial_console_write` takes
`uart_port_lock_irqsave(cons_uart, &flags)` (samsung_tty.c lines
2278-2283), confirming the port-lock half of the AB-BA.
- [Phase 3] `git show a05025d0ce72` confirmed it replaced `dbg()` (a
`printascii`-based macro) with `dev_dbg()` - verifying the regression
introduction.
- [Phase 3] `git describe --contains a05025d0ce72` →
`v5.6-rc1~139^2~130`, so bug first appeared in v5.6.
- [Phase 3] `git log -- drivers/tty/serial/samsung_tty.c` shows no
existing fix in tree; checked the 20 recent commits.
- [Phase 3] Found related file-history commit `97d7a9aeba1d4 "serial:
samsung_tty: Use port lock wrappers"` that changed `spin_lock_irqsave`
→ `uart_port_lock_irqsave`; relevant for backport to older trees.
- [Phase 4] `b4 dig -c 43c2b86ff633c` matched the patch by patch-id to
lore thread `aXny9km6N1v9eoXU@zall.org`.
- [Phase 4] `b4 dig -c 43c2b86ff633c -a` confirmed single revision (v1
only).
- [Phase 4] `b4 dig -c 43c2b86ff633c -w` confirmed proper recipients
(Krzysztof Kozlowski, Alim Akhtar, Greg KH, Jiri Slaby, linux-serial,
linux-samsung-soc).
- [Phase 4] `b4 am` fetched the thread; only the original patch, no
review replies.
- [Phase 5] Traced `->set_termios` callers in serial_core.c: three sites
(`uart_change_line_settings`, `uart_configure_port`,
`uart_resume_port`), all reachable from common userspace operations;
confirmed serial_core does NOT hold port lock when calling
set_termios.
- [Phase 5] Found similar accepted fixes for the same deadlock class:
`436c979360017` (stm32), `7fd6f640f2dd1` (8250_dw), `62b2caef400c1`
(sa1100).
- [Phase 6] Verified current stable/linux-7.0.y HEAD contains the pre-
patch buggy structure in `s3c24xx_serial_set_termios` (samsung_tty.c
lines 1562-1595).
- [Phase 6] Upstream commit SHA in origin/master:
`43c2b86ff633c34831c8430925ba73d7c20da1ad`.
- [Phase 8] Confirmed trigger conditions require dynamic debug enabled
(`dev_dbg` is no-op otherwise) AND samsung_tty serving as console -
partially gating severity.
- UNVERIFIED: Could not fetch lore.kernel.org directly (Anubis bot-
protection). Had to rely on `b4` tooling, which reported zero review
replies - so there's likely no stable-relevant discussion I missed,
but I cannot 100% guarantee it.
- UNVERIFIED: Did not enumerate every LTS tree's exact file contents;
relied on (a) the described introduction in 2019 and (b) no file-
history fix. Minor lock-wrapper adjustments may be needed for < 6.6.y
backports (older trees use `spin_lock_irqsave(&port->lock, ...)`
pre-97d7a9aeba1d4).
## Summary
This is a small (+2/-8 lines), surgical fix for an AB-BA deadlock
between the UART port lock and the console locking chain, introduced in
v5.6 (2019) when the driver's local `dbg()` macro - which routed to a
lock-free `printascii()` - was converted to `dev_dbg()` that enters the
full printk path. The fix moves one `dev_dbg` out of the critical
section and removes another redundant one. It meets all stable-kernel
criteria: obviously correct, fixes a real deadlock, small/contained, no
new features, and applies with at most trivial context adjustment. The
same bug class has precedent backports in stm32, sa1100, and 8250_dw
serial drivers.
**YES**
drivers/tty/serial/samsung_tty.c | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
index c1fabad6ba1fa..e27806bf2cf3e 100644
--- a/drivers/tty/serial/samsung_tty.c
+++ b/drivers/tty/serial/samsung_tty.c
@@ -1562,12 +1562,12 @@ static void s3c24xx_serial_set_termios(struct uart_port *port,
ulcon |= S3C2410_LCON_PNONE;
}
- uart_port_lock_irqsave(port, &flags);
-
dev_dbg(port->dev,
"setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
ulcon, quot, udivslot);
+ uart_port_lock_irqsave(port, &flags);
+
wr_regl(port, S3C2410_ULCON, ulcon);
wr_regl(port, S3C2410_UBRDIV, quot);
@@ -1587,12 +1587,6 @@ static void s3c24xx_serial_set_termios(struct uart_port *port,
if (ourport->info->has_divslot)
wr_regl(port, S3C2443_DIVSLOT, udivslot);
- dev_dbg(port->dev,
- "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
- rd_regl(port, S3C2410_ULCON),
- rd_regl(port, S3C2410_UCON),
- rd_regl(port, S3C2410_UFCON));
-
/*
* Update the per-port timeout.
*/
--
2.53.0
^ permalink raw reply related
* [PATCH AUTOSEL 7.0-5.10] tty: serial: imx: keep dma request disabled before dma transfer setup
From: Sasha Levin @ 2026-04-28 10:40 UTC (permalink / raw)
To: patches, stable
Cc: Robin Gong, Sherry Sun, Greg Kroah-Hartman, Sasha Levin,
jirislaby, shawnguo, linux-kernel, linux-serial, linux-arm-kernel
In-Reply-To: <20260428104133.2858589-1-sashal@kernel.org>
From: Robin Gong <yibin.gong@nxp.com>
[ Upstream commit 74e0c9f0528bcd597cb1299a027d7be27d1c27d9 ]
Since sdma hardware configure postpone to transfer phase, have to
disable dma request before dma transfer setup because there is a
hardware limitation on sdma event enable(ENBLn) as below.
Refer SDMA 2.6.28 Channel Enable RAM (SDMAARMx_CHNENBLn) section:
"It is thus essential for the Arm platform to program them before any
DMA request is triggered to the SDMA, otherwise an unpredictable
combination of channels may be started."
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Link: https://patch.msgid.link/20260312094526.297348-1-sherry.sun@nxp.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
LLM Generated explanations, may be completely bogus:
Now I have enough information to provide the full analysis.
## Analysis: tty: serial: imx: keep dma request disabled before dma
transfer setup
### PHASE 1: COMMIT MESSAGE FORENSICS
**Step 1.1: Subject line**
Record: `tty: serial: imx:` subsystem, action verb "keep" (implies
correcting improper state), one-line summary: "ensure UART DMA request
stays disabled until SDMA channel is fully configured."
**Step 1.2: Tags**
Record:
- Signed-off-by: Robin Gong (author, NXP), Sherry Sun (submitter, NXP),
Greg Kroah-Hartman (tty maintainer)
- Link:
https://patch.msgid.link/20260312094526.297348-1-sherry.sun@nxp.com
- NO Fixes: tag (expected)
- NO Cc: stable tag (expected)
- NO Reported-by/Tested-by/Reviewed-by
**Step 1.3: Commit body analysis**
Record: Commit explains a hardware limitation documented in the SDMA
reference manual (section 2.6.28, "Channel Enable RAM /
SDMAARMx_CHNENBLn"). When UART asserts a DMA request before the SDMA
channel script has been properly configured, "unpredictable combination
of channels may be started." No stack trace/reproducer, but cites an
authoritative NXP/Freescale hardware reference manual. Root cause: SDMA
configuration is postponed to the transfer phase, so starting the UART
DMA request before `dma_async_issue_pending()` on the corresponding
channel is a hardware-level ordering violation.
**Step 1.4: Hidden bug fix detection**
Record: Yes — "keep disabled before setup" is a classic disguised bug
fix. This corrects an improper ordering that leads to undefined hardware
behavior.
### PHASE 2: DIFF ANALYSIS
**Step 2.1: Inventory**
Record: 1 file (`drivers/tty/serial/imx.c`), 3 lines modified + 2
comment lines changed, 1 line added net. Two functions touched:
`imx_uart_enable_dma()` and `imx_uart_startup()`. Scope: single-file
surgical fix.
**Step 2.2: Code flow change**
```1438:1451:drivers/tty/serial/imx.c
static void imx_uart_enable_dma(struct imx_port *sport)
{
u32 ucr1;
imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
/* set UCR1 */
ucr1 = imx_uart_readl(sport, UCR1);
ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
imx_uart_writel(sport, ucr1, UCR1);
sport->dma_is_enabled = 1;
}
```
Record:
- Hunk 1 (`imx_uart_enable_dma`): BEFORE sets `UCR1_RXDMAEN |
UCR1_TXDMAEN | UCR1_ATDMAEN` atomically; AFTER sets only `UCR1_RXDMAEN
| UCR1_ATDMAEN` (TXDMAEN now enabled later in `imx_uart_dma_tx`).
- Hunk 2 (`imx_uart_startup`): BEFORE calls `imx_uart_enable_dma()` THEN
`imx_uart_start_rx_dma()`; AFTER calls `imx_uart_start_rx_dma()` THEN
`imx_uart_enable_dma()`. The RX DMA channel is configured/submitted
BEFORE the UART starts asserting DMA requests.
**Step 2.3: Bug mechanism**
Record: Category (h) Hardware workaround + ordering/correctness fix. The
mechanism: UART asserting DMA requests on UCR1 before SDMA has a valid
descriptor/channel configuration can trigger an ill-defined SDMA
channel, leading to corrupted/misrouted transfers. Confirmed by
verifying that `imx_uart_dma_tx()` at line 662-664 already sets
`UCR1_TXDMAEN` just before
`dmaengine_submit()/dma_async_issue_pending()` — so removing it from
`imx_uart_enable_dma()` is safe (TXDMAEN will still be set when actually
needed).
**Step 2.4: Fix quality**
Record: Obviously correct. The fix preserves exact functionality
(TXDMAEN still ends up set before TX transfer, RX DMA still starts
before UART DMA requests flow). No regression risk in the fix itself —
just reorders two well-defined function calls and defers one register
bit. No locking changes, no API changes.
### PHASE 3: GIT HISTORY INVESTIGATION
**Step 3.1: Blame**
Record: `imx_uart_enable_dma` and UART DMA support originated from
commit `b4cdc8f61beb2` ("serial: imx: add DMA support for imx6q", July
2013). The `temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN` line was
set together from day one — the buggy ordering has been present since
2013 (kernel v3.11). All active stable trees inherit it.
**Step 3.2: Fixes: tag** — Not present. The bug is a long-standing
hardware sequencing violation.
**Step 3.3: Related file changes**
Record: Recent changes to `drivers/tty/serial/imx.c` (wake event
reporting, hrtimer, nbcon, etc.) do not touch the DMA init/enable paths
— no conflicts expected.
**Step 3.4: Author's relationship**
Record: Robin Gong is an NXP engineer and has authored the equivalent
fix in the SDMA driver itself (commit `107d06441b709` in 2018) which
changed where `sdma_event_enable()` is called. He's an authority on SDMA
hardware semantics.
**Step 3.5: Dependencies**
Record: No prerequisite commits needed. The fix depends only on
`imx_uart_dma_tx()` already containing `ucr1 |= UCR1_TXDMAEN`, which I
verified exists in v5.4, v5.10, v5.15, v6.1, v6.6, v6.12.
### PHASE 4: MAILING LIST RESEARCH
**Step 4.1: Original submission**
Record: `b4 dig -c 74e0c9f0528bc` found
https://lore.kernel.org/all/20260312094526.297348-1-sherry.sun@nxp.com/.
Single-revision v1 patch. Thread contains only the patch submission — no
review replies, no NAKs, no stable nominations. Greg KH applied it
directly.
**Step 4.2: Recipients**
Record: Sent to gregkh, jirislaby (tty maintainers), Frank.Li@nxp.com,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam, tglx, mingo.
Appropriate maintainers CC'd.
**Step 4.3: Bug report** — No explicit report linked; the fix cites the
SoC reference manual.
**Step 4.4: Related series (CRITICAL)**
Record: The SAME hardware-sequencing fix was previously applied to the
SPI driver in commit `86d57d9c07d54` ("spi: imx: keep dma request
disabled before dma transfer setup", Oct 2025). That SPI fix has already
been backported to stable branches 5.10, 5.15, 6.1, 6.6, 6.12, and 6.17
(verified via `git branch --contains`). This establishes a clear
precedent that the stable maintainers consider this exact SDMA-ordering
issue worth backporting.
**Step 4.5: Stable ML** — The SPI equivalent already flowed into stable
via AUTOSEL.
### PHASE 5: CODE SEMANTIC ANALYSIS
**Step 5.1-5.4: Call chain**
Record: `imx_uart_enable_dma()` is called exclusively from
`imx_uart_startup()`. `imx_uart_startup()` is the `uart_ops::startup`
callback, invoked every time a UART port is opened. This is a common,
user-triggerable path — every process opening `/dev/ttymxcN` hits it. So
the buggy sequencing is exercised on every UART open with DMA enabled.
**Step 5.5: Similar patterns**
Record: The same bug pattern exists in `drivers/spi/spi-imx.c` and was
fixed by commit `86d57d9c07d54`, already backported broadly. The SDMA
driver itself carries a comment "Set ENBLn earlier to make sure dma
request triggered after that" (`drivers/dma/imx-sdma.c:1859`),
corroborating that this ordering requirement is well-established
hardware lore.
### PHASE 6: STABLE TREE ANALYSIS
**Step 6.1: Buggy code exists in stable?**
Record: YES. Verified `imx_uart_enable_dma()` and the buggy
`imx_uart_enable_dma(); imx_uart_start_rx_dma();` ordering is present in
v5.4, v5.10, v5.15, v6.1, v6.6, v6.12. `imx_uart_dma_tx()` also already
contains the `ucr1 |= UCR1_TXDMAEN` statement (the dependency for the
fix).
**Step 6.2: Backport complications**
Record: Patch applies CLEANLY (`git apply --check` succeeded with no
output) against v5.4, v5.10, v5.15, v6.1, v6.6, v6.12. No backport
adjustments needed.
**Step 6.3: Related fixes already in stable**
Record: No — this particular fix has not yet flowed to stable for the
UART driver. The sibling SPI fix is already in stable trees.
### PHASE 7: SUBSYSTEM CONTEXT
Record: `drivers/tty/serial/imx.c` — IMX UART driver. Used by millions
of embedded/industrial iMX-based systems. Criticality: IMPORTANT
(driver-specific but widely deployed). Active subsystem (recent
wakeup/RXTL fixes show ongoing maintenance).
### PHASE 8: IMPACT AND RISK ASSESSMENT
**Step 8.1: Affected users**
Record: iMX SoC users (iMX6, iMX7, iMX8, iMX9 families) using UART with
DMA (typical when hardware flow control is enabled for high-throughput
serial communication).
**Step 8.2: Triggering conditions**
Record: Every time a DMA-capable iMX UART port is opened (uart startup
path). Whether the race window actually causes misbehavior depends on:
whether the TX FIFO happens to fall below the watermark immediately
after TXDMAEN is set but before a descriptor is prepared; whether the RX
line has incoming data arriving before start_rx_dma finishes. Easily
reachable on active serial links.
**Step 8.3: Failure mode**
Record: "unpredictable combination of channels may be started" per SDMA
hardware docs. In practice this can manifest as: lost/corrupted UART
data, spurious channel activation that may corrupt memory (SDMA writing
to stale addresses), or flaky DMA behavior that's hard to debug.
Severity: HIGH (data integrity + potential silent memory corruption on a
DMA engine).
**Step 8.4: Risk-benefit**
Record: BENEFIT: prevents documented hardware misbehavior on a widely-
deployed SoC family; consistency with SPI driver fix already in stable.
RISK: very low — 3-line reordering, no new locks/APIs, dependency
(TXDMAEN in dma_tx) verified present in all stable trees, patch applies
cleanly, identical fix pattern already tested in production via SPI
backport.
### PHASE 9: FINAL SYNTHESIS
**Evidence FOR:** Fixes documented SoC hardware limitation; tiny
surgical change; author is SDMA subject-matter expert; same fix pattern
already accepted into stable (5.10→6.17) for spi-imx; code path is very
common (uart_startup); patch applies cleanly to all stable trees; falls
into the "Hardware Quirk/Workaround" exception category.
**Evidence AGAINST:** No explicit Reported-by/Tested-by (but the fix
cites authoritative SoC docs); no explicit stable nomination (but
absence is expected).
**Stable rules checklist:**
1. Obviously correct and tested? YES — TXDMAEN placement verified,
reorder is semantically equivalent.
2. Fixes a real bug? YES — documented hardware sequencing violation.
3. Important issue? YES — data corruption / unpredictable DMA behavior.
4. Small and contained? YES — 3 lines of actual code change.
5. No new features? YES — pure correctness/reorder fix.
6. Applies to stable trees? YES — clean apply verified.
**Exception category:** Hardware workaround for SDMA ENBLn sequencing
requirement.
### Verification
- [Phase 1] Parsed tags: no Fixes/Cc-stable/Reported-by; Link to lore
verified
- [Phase 2] Diff shows `imx_uart_enable_dma` drops TXDMAEN;
`imx_uart_startup` swaps call order of `start_rx_dma` and `enable_dma`
- [Phase 2] Verified `imx_uart_dma_tx()` in current tree and all stable
trees contains `ucr1 |= UCR1_TXDMAEN` at lines
~658/657/666/660/682/637 respectively — the fix's dependency is met
- [Phase 3] `git log -S"imx_enable_dma"` identified original DMA commit
`b4cdc8f61beb2` (Jul 2013)
- [Phase 3] `git blame` on `sdma_event_enable` call in imx-sdma.c
corroborates the hardware ordering requirement
- [Phase 4] `b4 dig -c 74e0c9f0528bc` found lore URL; `-a` shows only
v1; mbox inspection shows no replies/NAKs
- [Phase 4] `b4 dig -c 86d57d9c07d54` for sibling SPI fix confirmed it
went through review (Frank Li, Mark Brown)
- [Phase 4] `git branch --contains` for multiple SPI backport commits
confirmed backport to 5.10/5.15/6.1/6.6/6.12/6.17
- [Phase 5] Confirmed `imx_uart_enable_dma` has a single caller
(`imx_uart_startup`) via `Grep`
- [Phase 6] `git show vX:drivers/tty/serial/imx.c` for v5.4, v5.10,
v5.15, v6.1, v6.6, v6.12 all show identical buggy ordering
- [Phase 6] `git apply --check /tmp/fix.patch` succeeded on v5.4, v5.10,
v5.15, v6.1, v6.6, v6.12 (no output = success)
- [Phase 8] Failure mode per SoC reference manual — cited directly in
commit message
- UNVERIFIED: No user bug report could be located; severity inferred
from SoC documentation only. The exact race-window probability on a
specific board is not quantified.
Small, well-contained hardware-sequencing fix; same issue already
accepted into stable trees for the sister SPI driver; dependency
verified; applies cleanly. Meets all stable criteria.
**YES**
drivers/tty/serial/imx.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index c488e5d372ffd..251a50c8aa387 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -1442,9 +1442,9 @@ static void imx_uart_enable_dma(struct imx_port *sport)
imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
- /* set UCR1 */
+ /* set UCR1 except TXDMAEN which would be enabled in imx_uart_dma_tx */
ucr1 = imx_uart_readl(sport, UCR1);
- ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
+ ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
imx_uart_writel(sport, ucr1, UCR1);
sport->dma_is_enabled = 1;
@@ -1567,8 +1567,9 @@ static int imx_uart_startup(struct uart_port *port)
imx_uart_enable_ms(&sport->port);
if (dma_is_inited) {
- imx_uart_enable_dma(sport);
+ /* Note: enable dma request after transfer start! */
imx_uart_start_rx_dma(sport);
+ imx_uart_enable_dma(sport);
} else {
ucr1 = imx_uart_readl(sport, UCR1);
ucr1 |= UCR1_RRDYEN;
--
2.53.0
^ permalink raw reply related
* [PATCH AUTOSEL 7.0-5.10] serial: qcom-geni: Fix RTS behavior with flow control
From: Sasha Levin @ 2026-04-28 10:40 UTC (permalink / raw)
To: patches, stable
Cc: Anup Kulkarni, Greg Kroah-Hartman, Sasha Levin, agross, andersson,
konrad.dybcio, jirislaby, linux-arm-msm, linux-kernel,
linux-serial
In-Reply-To: <20260428104133.2858589-1-sashal@kernel.org>
From: Anup Kulkarni <anup.kulkarni@oss.qualcomm.com>
[ Upstream commit 0b1837c04d2335ec50b9a55b0282dcde7bc12439 ]
When userspace enables flow control (CRTSCTS), the driver
deasserts RTS even when the receive buffer has space. This prevents the
peer device from transmitting, causing communication to stall.
The root cause is that the driver unconditionally uses manual RTS control
regardless of flow control mode. When CRTSCTS is set, the hardware should
automatically manage RTS based on buffer status, but the driver overrides
this by setting manual control.
Fix this by introducing port->manual_flow flag. In set_termios(), disable
manual flow when CRTSCTS is set. In set_mctrl(), only assert
SE_UART_MANUAL_RFR when manual_flow is active. Verified by enabling and
disabling hardware flow control with stty.
Signed-off-by: Anup Kulkarni <anup.kulkarni@oss.qualcomm.com>
Link: https://patch.msgid.link/20260310104155.339010-1-anup.kulkarni@oss.qualcomm.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
LLM Generated explanations, may be completely bogus:
Now I have enough information to complete the full analysis.
## Analysis
### PHASE 1: COMMIT MESSAGE FORENSICS
**Step 1.1: Subject line parse**
- Record: [serial: qcom-geni:] [fix] [RTS behavior with hardware flow
control (CRTSCTS)]
**Step 1.2: Tag inventory**
- Record: Signed-off-by: Anup Kulkarni (author, @oss.qualcomm.com),
Signed-off-by: Greg KH (applied to tty tree). Link: patch.msgid.link
URL. NO Fixes: tag, NO Cc: stable, NO Reported-by, NO Tested-by, NO
Reviewed-by, NO Acked-by. Only v1 of patch, no reviewer replies on
thread.
**Step 1.3: Commit body analysis**
- Record: Bug: "driver deasserts RTS even when the receive buffer has
space" when CRTSCTS is enabled, causing "communication to stall". Root
cause: driver unconditionally uses manual RTS control via
`UART_MANUAL_RFR_EN`, which overrides hardware's auto-flow control. No
stack trace or reproducer. Author verified fix "by enabling and
disabling hardware flow control with stty".
**Step 1.4: Hidden bug fix detection**
- Record: Not hidden - commit message explicitly says "Fix RTS behavior"
and describes the bug clearly.
### PHASE 2: DIFF ANALYSIS
**Step 2.1: Inventory**
- Record: Single file `drivers/tty/serial/qcom_geni_serial.c`. +15/-4
lines. Modifies `qcom_geni_serial_set_mctrl()` (1 line guard added)
and `qcom_geni_serial_set_termios()` (restructured CRTSCTS branch).
Adds `bool manual_flow` to `struct qcom_geni_serial_port`. Scope:
surgical single-driver fix.
**Step 2.2: Code flow change**
- Record:
- set_mctrl BEFORE: `if (!(mctrl & TIOCM_RTS) && !uport->suspended)` →
enable manual RFR (`UART_MANUAL_RFR_EN | UART_RFR_NOT_READY`) then
unconditionally write.
- set_mctrl AFTER: Only enables manual RFR when `port->manual_flow` is
true AND RTS not set AND not suspended.
- set_termios BEFORE: Only toggles `UART_CTS_MASK` bit in TX config.
- set_termios AFTER: Also sets `port->manual_flow = false` when
CRTSCTS set (HW manages), `true` otherwise.
**Step 2.3: Bug mechanism**
- Record: Category (g) Logic/correctness fix. The mechanism: when
CRTSCTS is enabled, hardware should automatically drive RTS based on
RX FIFO fullness. But any call to `set_mctrl` with `!TIOCM_RTS` (which
happens during resume: `ops->set_mctrl(uport, 0)` at
serial_core.c:2421, at B0 baud transitions serial_core.c:1685, or on
ioctl TIOCMBIC) would cause the driver to write `UART_MANUAL_RFR_EN |
UART_RFR_NOT_READY`, forcing manual RTS deassertion and preventing the
peer from transmitting.
**Step 2.4: Fix quality**
- Record: Simple, easy to verify by reading. Logic is correct: when
hardware flow control is enabled, never override with manual mode. The
`manual_flow` flag is BSS-initialized to `false`, which matches
"hardware controls RTS" default. Small regression risk: before the
first `set_termios` call, any `set_mctrl(!TIOCM_RTS)` path now writes
0 instead of enabling manual mode; this is arguably more correct but
changes initial state. No public API changes, no lock changes.
### PHASE 3: GIT HISTORY INVESTIGATION
**Step 3.1: Blame the changed lines**
- Record: The manual RFR logic in `set_mctrl` was added in
`8a8a66a1a18a1` (v4.19, July 2018) "tty: serial: qcom_geni_serial: Add
support for flow control". The early-return guard
`!uart_cts_enabled(uport)` was removed in `e8a6ca808c5ed` (v5.0) "tty:
serial: qcom_geni_serial: Allow mctrl when flow control is disabled" —
which actually made the bug more exposed (before that change, the
manual-mode code path was unreachable when CRTSCTS was off, but still
buggy when on).
**Step 3.2: Follow the Fixes: tag**
- Record: No Fixes: tag in this commit. Most likely should reference
`8a8a66a1a18a1` (v4.19) as the origin — the bug has existed since flow
control support was added to this driver.
**Step 3.3: File history for related changes**
- Record: Recent related fix `947cc4ecc06cb` "serial: qcom-geni: fix
soft lockup on sw flow control and suspend" (July 2024) was tagged
`Cc: stable # 4.17` — shows that flow-control-related bugs in this
driver have been deemed stable-worthy. Also `23f5f5debcaac` "serial:
qcom-geni: fix shutdown race" exists. No overlap/conflict with this
fix.
**Step 3.4: Author commits**
- Record: `git log --author="Anup Kulkarni"` shows only 1 other commit
(`4fcc287f3c692` "serial: qcom-geni: Enable support for half-duplex
mode"). Newer contributor but from @oss.qualcomm.com - this is the
vendor (Qualcomm) whose hardware this driver supports. Patch went
through Greg KH's tty tree.
**Step 3.5: Dependencies**
- Record: No dependencies found. The fix is self-contained and
references only symbols that exist since the original flow control
support commit (v4.19).
### PHASE 4: MAILING LIST RESEARCH
**Step 4.1: b4 dig**
- Record: Single revision (v1) at https://patch.msgid.link/2026031010415
5.339010-1-anup.kulkarni@oss.qualcomm.com. Thread mbox retrieved. Only
one message in thread - just the patch itself, no replies, no NAK, no
explicit stable nomination.
**Step 4.2: Who reviewed**
- Record: `b4 dig -w` shows to/cc: gregkh, jirislaby (tty maintainers),
praveen.talari/viken.dadhaniya/zongjian/jseerapu (Qualcomm),
bryan.odonoghue (linaro), krzk (Krzysztof Kozlowski), linux-serial,
linux-arm-msm, linux-kernel. Appropriate maintainers were CC'd but no
one publicly replied on lore before Greg applied it.
**Step 4.3: Bug report search**
- Record: No Reported-by or bug link in commit. Web search did not
surface a specific user report for this stall.
**Step 4.4: Related patches/series**
- Record: `b4 dig -a` shows v1 only; standalone single-patch submission.
**Step 4.5: Stable list history**
- Record: Nothing found discussing this specific fix on stable@.
### PHASE 5: CODE SEMANTIC ANALYSIS
**Step 5.1: Functions modified**
- Record: `qcom_geni_serial_set_mctrl`, `qcom_geni_serial_set_termios`.
**Step 5.2: Callers**
- Record: Both are `uart_ops` callbacks registered in
`qcom_geni_console_pops`/`qcom_geni_uart_pops`. Called indirectly
through `port->ops->set_mctrl(...)` and `uport->ops->set_termios(...)`
from `drivers/tty/serial/serial_core.c`. Key caller sites for
`set_mctrl`: startup/shutdown, suspend/resume (lines 2333/2421), RS485
disable path (1483), B0 transitions (1685/1692), throttle/unthrottle
(with AUTORTS — not used here). This makes the bug reachable on every
resume and on any baud change to/from B0 when CRTSCTS is active — very
common paths.
**Step 5.3: Callees**
- Record: set_mctrl only calls `writel(...)` to SE_UART_MANUAL_RFR. No
locking, no allocation. Minimal side effects.
**Step 5.4: Call chain reachability**
- Record: Reachable from any userspace UART open with CRTSCTS, stty
changes, system suspend/resume, and B0 transitions. Definitely user-
reachable, exercised on every device with hardware flow control
enabled.
**Step 5.5: Similar patterns**
- Record: Verified driver does NOT advertise `UPSTAT_AUTORTS` (no hits
for that flag) - so auto-RTS tty layer logic doesn't apply; the driver
relies entirely on hardware register-level RFR management when CRTSCTS
is on. This confirms the issue: the driver's set_mctrl was silently
overriding hardware-managed RTS.
### PHASE 6: STABLE TREE ANALYSIS
**Step 6.1: Does buggy code exist in stable?**
- Record: Verified the identical buggy `set_mctrl` body exists in stable
6.17.y, 6.12.y, 6.6.y, 6.1.y, and 5.15.y. The same CRTSCTS branch `if
(termios->c_cflag & CRTSCTS) tx_trans_cfg &= ~UART_CTS_MASK; else
tx_trans_cfg |= UART_CTS_MASK;` is present in all of them. Bug has
existed since v4.19 → affects ALL currently supported stable trees.
**Step 6.2: Backport complications**
- Record: Low complexity backport. The struct has `bool cts_rts_swap` in
every stable branch (verified). Both hunks context-match. Minor
difference: 5.15 uses legacy `to_dev_port(uport, uport)` macro
(irrelevant to the hunk). Expected: clean apply or minor context
rewrap.
**Step 6.3: Related fixes already in stable**
- Record: `947cc4ecc06cb` (flow control soft lockup fix) is already in
stable and addresses a different flow-control issue. No conflict with
this fix.
### PHASE 7: SUBSYSTEM CONTEXT
**Step 7.1: Subsystem criticality**
- Record: Subsystem: `drivers/tty/serial/` — Qualcomm GENI serial
driver. Criticality: PERIPHERAL (driver-specific) but IMPORTANT for
the affected platforms (Qualcomm SoCs used in Chromebooks, embedded
devices, Android phones, etc., where hardware flow control to
Bluetooth/GPS/modem peripherals is critical).
**Step 7.2: Subsystem activity**
- Record: Driver is actively maintained, with regular fixes going in.
This suggests real users.
### PHASE 8: IMPACT AND RISK ASSESSMENT
**Step 8.1: Who is affected**
- Record: Users of Qualcomm SoCs running Linux that use UART with
`CRTSCTS` enabled — commonly Bluetooth HCI over UART, GPS modules,
baseband modems. Affects Android devices, Chromebooks, embedded
Qualcomm platforms.
**Step 8.2: Trigger conditions**
- Record: Trigger is any invocation of set_mctrl with RTS cleared while
CRTSCTS is active. Concrete triggers:
1. System suspend/resume cycle (very common on mobile/laptop)
2. B0 baud transitions (modem hangup)
3. Any direct ioctl(TIOCMBIC, &TIOCM_RTS)
Unprivileged? Root access to the tty device is typical for the
trigger.
**Step 8.3: Failure mode severity**
- Record: Functional failure — communication stalls because RTS is stuck
deasserted and peer stops transmitting. No kernel crash, no data
corruption, no security hole. Severity: MEDIUM-HIGH — "communication
stall" is a real stability issue for devices depending on this UART
(e.g., Bluetooth dropouts, serial session lockups). Not a crash, but
noticeable and disruptive.
**Step 8.4: Risk-benefit**
- Record:
- Benefit: MEDIUM — fixes a real functional bug on actively-used
hardware (Qualcomm platforms) with a clear reproduction path,
especially after resume.
- Risk: LOW — 15 lines, single file, trivial to audit, no
locking/memory changes, no API changes. The `manual_flow` field
defaults to `false` which aligns with hardware-managed mode (safe
default).
- Ratio: Favorable for backport. Very low risk of regression for
benefit of fixing real-world stalls.
### PHASE 9: FINAL SYNTHESIS
**Step 9.1: Evidence**
- FOR: Real user-visible bug clearly described; present since v4.19 in
all stable trees; small surgical fix; touches only a driver callback;
correct logical direction (CRTSCTS means HW controls, manual mode
should be off); fix verified by author with stty; applies cleanly; no
API/feature additions; author is Qualcomm, i.e., the hardware vendor.
- AGAINST: No Fixes: tag; no Cc: stable; no reviewer Ack/Reviewed-by; no
user bug report linked; single-revision patch with no lore discussion;
reachable in common paths but severity is functional (not
crash/security/corruption).
- UNRESOLVED: Could not directly observe the reproduction trace (no
stack trace in commit).
**Step 9.2: Stable rules checklist**
1. Obviously correct? YES — straightforward logic; author tested.
2. Fixes a real bug? YES — stated reproducer via stty.
3. Important? MEDIUM — functional stall on Qualcomm platforms using flow
control (BT/GPS/modem), not a crash/security/corruption.
4. Small and contained? YES — 15 lines, 1 file, 1 driver.
5. No new features/APIs? YES — internal bool field only.
6. Applies to stable? YES — verified code exists unchanged in 5.15.y
through 6.17.y.
**Step 9.3: Exception categories**
- Not strictly an exception, but closely aligned with a hardware
workaround in a mature driver.
**Step 9.4: Decision**
This is a real, reproducible bug fix in a driver used on widely-deployed
Qualcomm hardware (Chromebooks, Android, embedded). The fix is tiny,
purely internal, doesn't introduce APIs or affect other subsystems, and
the logic is clearly correct (hardware flow control should not be
overridden by manual RTS assertion). The bug is reachable in common
operational paths (resume, B0 transitions). Backport risk is minimal.
## Verification
- [Phase 1] Parsed tags from commit: only Signed-off-by (author + Greg
KH) and Link. No Fixes:, no Cc: stable, no Reported-by, no Reviewed-
by/Acked-by.
- [Phase 2] Diff analysis confirmed on the actual patch text: 1-line
guard in set_mctrl, 2 branches expanded to set `manual_flow`, 1 new
struct field.
- [Phase 3] `git log` on file showed history; `git show 8a8a66a1a18a1`
and `git show e8a6ca808c5ed` confirmed the code origin (v4.19 via git
describe) and the removal of the CTS-enabled guard (v5.0).
- [Phase 3] `git describe --contains 8a8a66a1a18a1` →
v4.19-rc1~102^2~33; `e8a6ca808c5ed` → v5.0-rc4~20^2~1. Bug has been
present since v4.19.
- [Phase 3] `git log --author="Anup Kulkarni"` → 2 commits total (this
one plus half-duplex mode). Relatively new contributor, Qualcomm
vendor author.
- [Phase 3] `git log --grep="serial.*qcom.*flow"` → confirmed
`947cc4ecc06cb` (previous flow control fix, tagged `Cc: stable #
4.17`) is a precedent.
- [Phase 4] `b4 dig -c 0b1837c04d233` → found single lore thread, v1
only, single message, no replies.
- [Phase 4] `b4 dig -c 0b1837c04d233 -w` → recipients confirmed: gregkh,
jirislaby, Qualcomm team, bryan.odonoghue, krzk, linux-serial, linux-
arm-msm, linux-kernel.
- [Phase 4] `b4 dig -c 0b1837c04d233 -a` → only v1 exists; went direct
to Greg's tree.
- [Phase 4] Saved thread to /tmp/qcom_geni_thread.mbox; read contents -
confirmed no replies, no reviewer feedback.
- [Phase 5] Grepped `UPSTAT_AUTORTS|UPSTAT_AUTOCTS` in
qcom_geni_serial.c → no matches. Driver does NOT use UPSTAT_AUTORTS,
so throttle/unthrottle don't clear RTS through set_mctrl path.
- [Phase 5] Grepped `SE_UART_MANUAL_RFR|UART_MANUAL_RFR_EN` → only 2
writers: `qcom_geni_set_rs485_mode()` (only when RS485 enabled) and
`qcom_geni_serial_set_mctrl()` (the fixed function). No other paths
touch this register.
- [Phase 5] Read `serial_core.c:2320-2451` → confirmed
`ops->set_mctrl(uport, 0)` is called at resume (2421) with
`uport->suspended` already 0, directly triggering the bug path when
CRTSCTS is active.
- [Phase 5] Read `serial_core.c:1680-1694` → confirmed B0 transition
logic can cause set_mctrl with !TIOCM_RTS while CRTSCTS is active.
- [Phase 6] `git show stable/linux-
{6.17,6.12,6.6,6.1,5.15}.y:drivers/tty/serial/qcom_geni_serial.c` →
verified identical buggy `set_mctrl` body and identical CRTSCTS
handling in set_termios in all five stable trees. Struct has
`cts_rts_swap` in all of them, so the `manual_flow` addition will fit
cleanly.
- [Phase 8] Failure mode: communication stall (peer cannot transmit). No
crash. Severity: MEDIUM-HIGH functional. Trigger: common (resume, B0).
- UNVERIFIED: Could not obtain a literal crash/stall reproducer from
commit message; the author's claim of verification via stty is the
only direct test evidence. Did not independently reproduce the bug.
The fix is small, narrowly scoped, logically sound, and addresses a real
functional bug that is triggered on common paths (resume, B0) in a
driver used on widely-deployed hardware. It meets the stable kernel
rules.
**YES**
drivers/tty/serial/qcom_geni_serial.c | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
index e6b0a55f0cfb2..9854bb2406e3f 100644
--- a/drivers/tty/serial/qcom_geni_serial.c
+++ b/drivers/tty/serial/qcom_geni_serial.c
@@ -146,6 +146,7 @@ struct qcom_geni_serial_port {
int wakeup_irq;
bool rx_tx_swap;
bool cts_rts_swap;
+ bool manual_flow;
struct qcom_geni_private_data private_data;
const struct qcom_geni_device_data *dev_data;
@@ -250,7 +251,7 @@ static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
if (mctrl & TIOCM_LOOP)
port->loopback = RX_TX_CTS_RTS_SORTED;
- if (!(mctrl & TIOCM_RTS) && !uport->suspended)
+ if (port->manual_flow && !(mctrl & TIOCM_RTS) && !uport->suspended)
uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
}
@@ -1401,11 +1402,21 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
else
stop_bit_len = TX_STOP_BIT_LEN_1;
- /* flow control, clear the CTS_MASK bit if using flow control. */
- if (termios->c_cflag & CRTSCTS)
+ /* Configure flow control based on CRTSCTS flag.
+ * When CRTSCTS is set, use HW/auto flow control mode, where HW
+ * controls the RTS/CTS pin based FIFO state.
+ * When CRTSCTS is clear, the CTS pin value is ignored for TX
+ * path and RTS pin can be set/cleared using registers, for RX
+ * path.
+ */
+
+ if (termios->c_cflag & CRTSCTS) {
tx_trans_cfg &= ~UART_CTS_MASK;
- else
+ port->manual_flow = false;
+ } else {
tx_trans_cfg |= UART_CTS_MASK;
+ port->manual_flow = true;
+ }
if (baud) {
uart_update_timeout(uport, termios->c_cflag, baud);
--
2.53.0
^ permalink raw reply related
* Re: [PATCH v5 2/4] serial: 8250_dw: build Renesas RZN1 CPR value from DW_UART_CPR_* definitions
From: Andy Shevchenko @ 2026-04-28 10:57 UTC (permalink / raw)
To: Ilpo Järvinen
Cc: Jia Wang, Greg Kroah-Hartman, Jiri Slaby, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, LKML, linux-serial,
linux-riscv, devicetree
In-Reply-To: <23c80500-f2c1-0eb3-f640-00f7b108059b@linux.intel.com>
On Tue, Apr 28, 2026 at 11:41:27AM +0300, Ilpo Järvinen wrote:
> On Tue, 28 Apr 2026, Andy Shevchenko wrote:
> > On Tue, Apr 28, 2026 at 01:26:27PM +0800, Jia Wang wrote:
...
> > > /* Helper for FIFO size calculation */
> > > #define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16)
> >
> > > +#define DW_UART_CPR_FIFO_MODE_MAX 0x80
> >
> > You used decimal values elsewhere (id est 16), use upper limit in decimal
> > as well.
> >
> > > +#define DW_UART_CPR_FIFO_MODE_FROM_SIZE(size) \
> > > + (BUILD_BUG_ON_ZERO(!IS_ALIGNED((size), 16)) + \
> > > + BUILD_BUG_ON_ZERO(((size) / 16) > DW_UART_CPR_FIFO_MODE_MAX) + \
> > > + ((size) / 16))
> >
> > I don't see the need in having that maximum being defined separately (we don't
> > have that for 16, no need to have it for 128.
> >
> > Since some ISA:s have one assembly instruction to get both / and % divisions,
> > it's better to use that instead of IS_ALIGNED(). Can you check code generation
> > for x86_64 / x86?
>
> Do those BUILD_BUGs even generate code, especially when they are expected
> to only appear in a struct initializer?
Good question if this affects the code generation.
> > #define DW_UART_CPR_FIFO_MODE_FROM_SIZE(size) \
> > (BUILD_BUG_ON_ZERO((size) > 2048) + BUILD_BUG_ON_ZERO((size) % 16) + ((size) / 16))
> >
> > Note, I dropped first division in order to show the upper limit in a plain
> > number since 16 is also FIFO size in bytes.
> >
> > Also note, this evaluates (size) three times, which might be problematic,
> > but I think we can leave with that for now.
>
> I'd put also FIELD_PREP_CONST() into the macro itself as I don't see much
> value for this macro outside of those .cpr_value initializations.
Yep, and it would make it on par with the existing _FIFO_SIZE() that has
FIELD_GET() there.
> IMO, the entire macro would be cleaner looking as a truly multi-line
> construct. Can we use static_assert()s in struct field initialization
> (I'm not sure), something along these lines:
I believe one may put there static_assert():s.
> #define DW_UART_CPR_FIFO_MODE_FROM_SIZE(size) \
> ({ \
> typeof (size) __size = size; \
Perhaps auto ?
> \
> static_assert(IS_ALIGNED((__size), 16)); \
> static_assert(__size <= DW_UART_CPR_FIFO_MODE_MAX); \
But I still think the % and / paired are clearer (for reading and understanding)
even if they do not affect code generation. Also I think the plain number of the
maximum size is better for the same reasons we do not have it for 16.
> \
> FIELD_PREP_CONST(DW_UART_CPR_FIFO_MODE, __size / 16); \
> })
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v5 2/4] serial: 8250_dw: build Renesas RZN1 CPR value from DW_UART_CPR_* definitions
From: Andy Shevchenko @ 2026-04-28 10:58 UTC (permalink / raw)
To: Jia Wang
Cc: Ilpo Järvinen, Greg Kroah-Hartman, Jiri Slaby, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, LKML, linux-serial,
linux-riscv, devicetree
In-Reply-To: <177736726936.2886867.7725295920724488690.b4-reply@b4>
On Tue, Apr 28, 2026 at 05:07:49PM +0800, Jia Wang wrote:
> On 2026-04-28 11:41 +0300, Ilpo Järvinen wrote:
> > On Tue, 28 Apr 2026, Andy Shevchenko wrote:
> > > On Tue, Apr 28, 2026 at 01:26:27PM +0800, Jia Wang wrote:
...
> > #define DW_UART_CPR_FIFO_MODE_FROM_SIZE(size) \
> > ({ \
> > typeof (size) __size = size; \
> > \
> > static_assert(IS_ALIGNED((__size), 16)); \
> > static_assert(__size <= DW_UART_CPR_FIFO_MODE_MAX); \
> > \
> > FIELD_PREP_CONST(DW_UART_CPR_FIFO_MODE, __size / 16); \
> > })
>
> Thanks. I tried that approach, but the statement-expression form does
> not work in this case because the helper is used in static initializers.
> So I'll keep it as a plain expression macro for now, and just rework it
> into a cleaner multi-line form.
Still you can move FIELD_PREP_CONST() into it.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [RFC PATCH v1 7/9] x86: Add unsafe_copy_from_user()
From: Segher Boessenkool @ 2026-04-28 11:20 UTC (permalink / raw)
To: Yury Norov
Cc: Linus Torvalds, Christophe Leroy (CS GROUP), Andrew Morton,
David Laight, Thomas Gleixner, linux-alpha, Yury Norov,
linux-kernel, linux-snps-arc, linux-arm-kernel, linux-mips,
linuxppc-dev, kvm, linux-riscv, linux-s390, sparclinux, linux-um,
dmaengine, linux-efi, linux-fsi, amd-gfx, dri-devel, intel-gfx,
linux-wpan, netdev, linux-wireless, linux-spi, linux-media,
linux-staging, linux-serial, linux-usb, xen-devel, linux-fsdevel,
ocfs2-devel, bpf, kasan-dev, linux-mm, linux-x25, rust-for-linux,
linux-sound, sound-open-firmware, linux-csky, linux-hexagon,
loongarch, linux-m68k, linux-openrisc, linux-parisc, linux-sh,
linux-arch
In-Reply-To: <ae_jeJLlVWjJ4sOY@yury>
Hi!
On Mon, Apr 27, 2026 at 06:30:16PM -0400, Yury Norov wrote:
> On Mon, Apr 27, 2026 at 02:52:05PM -0700, Linus Torvalds wrote:
> > On Mon, 27 Apr 2026 at 12:19, Yury Norov <ynorov@nvidia.com> wrote:
> > >
> > > This is what Linus said when added x86 implementation for copy_from_user()
> > > in c512c69187197:
> >
> > Note that some things have happily changed in the six+ years since...
> >
> > > That's partly because we have no current users of it, but also partly
> > > because the copy_from_user() case is slightly different and cannot
> > > efficiently be implemented in terms of a unsafe_get_user() loop (because
> > > gcc can't do asm goto with outputs).
> >
> > now everybody can do asm goto with outputs.
> >
> > Yes, it's disabled on older versions, so it's not *always* available,
> > but all modern versions do it. And if you care about performance, you
> > won't be using an old compiler.
>
> The minimal GCC version is 8.1, and asm goto with outputs is supported
> since GCC-11. That would brake the build, if we just switch to using it
> without "CC_IS_GCC && (GCC_VERSION >= 110100)" guard.
>
> Is it worth to maintain 2 version of the function? I don't know...
GCC 11 was released five years and a day ago. The last GCC 11 release
(that of 11.5) is not even two years ago though (but there will be no
more!)
So it would be not conservative at all to require GCC 11 as minimum now,
some people might even call it a bit aggressive. But in a year (or
maybe two) the lay of the land will be rather different.
Segher
^ permalink raw reply
* Re: [RFC PATCH v1 2/9] uaccess: Convert INLINE_COPY_{TO/FROM}_USER to kconfig and reduce ifdefery
From: Segher Boessenkool @ 2026-04-28 11:34 UTC (permalink / raw)
To: Andrew Cooper
Cc: Yury Norov, Christophe Leroy (CS GROUP), Andrew Morton,
Linus Torvalds, David Laight, Thomas Gleixner, linux-alpha,
Yury Norov, linux-kernel, linux-snps-arc, linux-arm-kernel,
linux-mips, linuxppc-dev, kvm, linux-riscv, linux-s390,
sparclinux, linux-um, dmaengine, linux-efi, linux-fsi, amd-gfx,
dri-devel, intel-gfx, linux-wpan, netdev, linux-wireless,
linux-spi, linux-media, linux-staging, linux-serial, linux-usb,
xen-devel, linux-fsdevel, ocfs2-devel, bpf, kasan-dev, linux-mm,
linux-x25, rust-for-linux, linux-sound, sound-open-firmware,
linux-csky, linux-hexagon, loongarch, linux-m68k, linux-openrisc,
linux-parisc, linux-sh, linux-arch
In-Reply-To: <f54c3c2b-33da-42a0-80b7-0f6615d930ce@citrix.com>
On Mon, Apr 27, 2026 at 09:39:33PM +0100, Andrew Cooper wrote:
> On 27/04/2026 7:39 pm, Yury Norov wrote:
> > On Mon, Apr 27, 2026 at 07:13:43PM +0200, Christophe Leroy (CS GROUP) wrote:
> >> Among the 21 architectures supported by the kernel, 16 define both
> >> INLINE_COPY_TO_USER and INLINE_COPY_FROM_USER while the 5 other ones
> >> don't define any of the two.
> >>
> >> To simplify and reduce risk of mistakes, convert them to a single
> >> kconfig item named CONFIG_ARCH_WANTS_NOINLINE_COPY which will be
> > We've got a special word for it: outline. Can you name it
> > CONFIG_OUTLINE_USERCOPY, or similar?
>
> You can't swap the "in" for "out" like this. "out of line" is the
> opposite of "inline" in this context, while "outline" means something
> different and unrelated.
Yeah. Technically much more correct for it is inline vs. functional.
Not that that term won't be misunderstood as well :-)
Segher
^ permalink raw reply
* Re: [PATCH 6/8] serial: zs: Convert to use a platform device
From: Maciej W. Rozycki @ 2026-04-28 13:49 UTC (permalink / raw)
To: Thomas Bogendoerfer, Greg Kroah-Hartman, Jiri Slaby
Cc: linux-mips, linux-serial, linux-serial
In-Reply-To: <alpine.DEB.2.21.2604110034160.29980@angie.orcam.me.uk>
On Mon, 13 Apr 2026, Maciej W. Rozycki wrote:
> An unfortunate consequence of the switch to a platform device is we now
> hand the console over from the bootconsole much later in the bootstrap.
> The firmware console handler appears good enough though to work so late
> and in particular with interrupts enabled.
Additional verification revealed actual fallout from this postponement of
console switching, where the kernel hangs in the 64-bit configuration at:
pid_max: default: 32768 minimum: 301
or somewhat later, but always before:
cblist_init_generic: Setting adjustable number of callback queues.
I have tracked down the cause to be the initial console output handler now
being called from other kernel threads beyond the initial one, and unlike
the latter they have their stack allocated in 64-bit XKPHYS segment rather
than 32-bit compatibility CKSEG0 segment.
Consequently the stack pointer is no longer a 32-bit value and when the
firmware console output handler being called uses 32-bit ALU operations to
manipulate the stack pointer, the calculated result is incorrect (in fact
in the 64-bit MIPS ISA it is UB for almost all 32-bit ALU operations to
execute on 64-bit data) and control goes astray.
We already have code in the generic call_o32() 32-bit firmware call stub
for 64-bit code to do optional stack switching, so all that has to be done
is making the platform supply the stub with a pointer to an alternative
stack located in CKSEG0, such as to a chunk of initdata space. This will
be straightforward to implement; I'll yet think whether to arrange for the
stack to be switched every time or only when the incoming stack pointer is
outside the 32-bit space.
In any case I'll respin the series shortly so as to include the platform
update required and prevent an unnecessary maintenance complication from
happening that a standalone fix would cause.
The other driver never runs on 64-bit hardware, so it causes no issue.
Maciej
^ permalink raw reply
* [PATCH v3] serial: 8250_pci: Consistently define pci_device_ids using named initializers
From: Uwe Kleine-König (The Capable Hub) @ 2026-04-28 14:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: Andy Shevchenko, Markus Schneider-Pargmann, linux-serial,
linux-kernel
... and PCI device helpers.
The various struct pci_device_id were defined using a mixture of
initialization by position and by name. Some use the PCI device helpers
(like PCI_DEVICE and PCI_DEVICE_SUB) and others don't.
Consistently use named initializers, drop assignments of 0 by position
for .class and .class_mask and use the PCI device helpers. Also use
consistent line-breaks and positioning for opening and closing curly
braces.
The secret plan is to make struct pci_device_id::driver_data an
anonymous union (similar to
https://lore.kernel.org/all/cover.1776579304.git.u.kleine-koenig@baylibre.com/)
and that requires named initializers. But it's also a nice cleanup on
its own.
This patch doesn't change the compiled result; this was verified using
an allmodconfig with several things disabled that make reproducible
builds harder on x86 and arm64.
Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com>
---
Hello,
sashiko[1] found a few missing conversions in v2[2] that are addressed
here. (That happend because the formatting was different and so those
were not adapted by my semi-automatic conversion.)
I also used PCI_VDEVICE* where applicable now.
Best regards
Uwe
[1] https://sashiko.dev/#/patchset/20260427211423.2323211-2-u.kleine-koenig%40baylibre.com
[2] https://lore.kernel.org/20260427211423.2323211-2-u.kleine-koenig%40baylibre.com
drivers/tty/serial/8250/8250_pci.c | 3120 ++++++++++++++--------------
1 file changed, 1563 insertions(+), 1557 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c
index 2fbd8f2603b5..3e5bc9e8d269 100644
--- a/drivers/tty/serial/8250/8250_pci.c
+++ b/drivers/tty/serial/8250/8250_pci.c
@@ -143,16 +143,15 @@ struct serial_private {
#define PCIE_DEVICE_ID_AX99100 0x9100
static const struct pci_device_id pci_use_msi[] = {
- { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
- 0xA000, 0x1000) },
- { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
- 0xA000, 0x1000) },
- { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
- 0xA000, 0x1000) },
- { PCI_DEVICE_SUB(PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
- 0xA000, 0x1000) },
- { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
- PCI_ANY_ID, PCI_ANY_ID) },
+ { PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9900,
+ 0xA000, 0x1000) },
+ { PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9912,
+ 0xA000, 0x1000) },
+ { PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9922,
+ 0xA000, 0x1000) },
+ { PCI_VDEVICE_SUB(ASIX, PCI_DEVICE_ID_ASIX_AX99100,
+ 0xA000, 0x1000) },
+ { PCI_VDEVICE(HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL) },
{ PCI_DEVICE_SUB(PCIE_VENDOR_ID_ASIX, PCIE_DEVICE_ID_AX99100,
0xA000, 0x1000) },
{ }
@@ -4040,42 +4039,42 @@ static const struct pci_device_id blacklist[] = {
/* multi-io cards handled by parport_serial */
/* WCH CH353 2S1P */
- { PCI_VDEVICE(WCHCN, 0x7053), REPORT_CONFIG(PARPORT_SERIAL), },
+ { PCI_VDEVICE(WCHCN, 0x7053), .driver_data = REPORT_CONFIG(PARPORT_SERIAL), },
/* WCH CH353 1S1P */
- { PCI_VDEVICE(WCHCN, 0x5053), REPORT_CONFIG(PARPORT_SERIAL), },
+ { PCI_VDEVICE(WCHCN, 0x5053), .driver_data = REPORT_CONFIG(PARPORT_SERIAL), },
/* WCH CH382 2S1P */
- { PCI_VDEVICE(WCHIC, 0x3250), REPORT_CONFIG(PARPORT_SERIAL), },
+ { PCI_VDEVICE(WCHIC, 0x3250), .driver_data = REPORT_CONFIG(PARPORT_SERIAL), },
/* Intel platforms with MID UART */
- { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), },
- { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), },
- { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), },
- { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), },
- { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), },
- { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), },
+ { PCI_VDEVICE(INTEL, 0x081b), .driver_data = REPORT_8250_CONFIG(MID), },
+ { PCI_VDEVICE(INTEL, 0x081c), .driver_data = REPORT_8250_CONFIG(MID), },
+ { PCI_VDEVICE(INTEL, 0x081d), .driver_data = REPORT_8250_CONFIG(MID), },
+ { PCI_VDEVICE(INTEL, 0x1191), .driver_data = REPORT_8250_CONFIG(MID), },
+ { PCI_VDEVICE(INTEL, 0x18d8), .driver_data = REPORT_8250_CONFIG(MID), },
+ { PCI_VDEVICE(INTEL, 0x19d8), .driver_data = REPORT_8250_CONFIG(MID), },
/* Intel platforms with DesignWare UART */
- { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), },
- { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), },
- { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), },
- { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), },
- { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), },
- { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), },
- { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), },
- { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), },
- { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), },
- { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), },
- { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), },
- { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), },
- { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), },
+ { PCI_VDEVICE(INTEL, 0x0936), .driver_data = REPORT_8250_CONFIG(LPSS), },
+ { PCI_VDEVICE(INTEL, 0x0f0a), .driver_data = REPORT_8250_CONFIG(LPSS), },
+ { PCI_VDEVICE(INTEL, 0x0f0c), .driver_data = REPORT_8250_CONFIG(LPSS), },
+ { PCI_VDEVICE(INTEL, 0x228a), .driver_data = REPORT_8250_CONFIG(LPSS), },
+ { PCI_VDEVICE(INTEL, 0x228c), .driver_data = REPORT_8250_CONFIG(LPSS), },
+ { PCI_VDEVICE(INTEL, 0x4b96), .driver_data = REPORT_8250_CONFIG(LPSS), },
+ { PCI_VDEVICE(INTEL, 0x4b97), .driver_data = REPORT_8250_CONFIG(LPSS), },
+ { PCI_VDEVICE(INTEL, 0x4b98), .driver_data = REPORT_8250_CONFIG(LPSS), },
+ { PCI_VDEVICE(INTEL, 0x4b99), .driver_data = REPORT_8250_CONFIG(LPSS), },
+ { PCI_VDEVICE(INTEL, 0x4b9a), .driver_data = REPORT_8250_CONFIG(LPSS), },
+ { PCI_VDEVICE(INTEL, 0x4b9b), .driver_data = REPORT_8250_CONFIG(LPSS), },
+ { PCI_VDEVICE(INTEL, 0x9ce3), .driver_data = REPORT_8250_CONFIG(LPSS), },
+ { PCI_VDEVICE(INTEL, 0x9ce4), .driver_data = REPORT_8250_CONFIG(LPSS), },
/* Exar devices */
- { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
- { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
+ { PCI_VDEVICE(EXAR, PCI_ANY_ID), .driver_data = REPORT_8250_CONFIG(EXAR), },
+ { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), .driver_data = REPORT_8250_CONFIG(EXAR), },
/* Pericom devices */
- { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
- { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
+ { PCI_VDEVICE(PERICOM, PCI_ANY_ID), .driver_data = REPORT_8250_CONFIG(PERICOM), },
+ { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), .driver_data = REPORT_8250_CONFIG(PERICOM), },
/* End of the black list */
{ }
@@ -4448,713 +4447,753 @@ static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
pciserial_resume_one);
static const struct pci_device_id serial_pci_tbl[] = {
- { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600,
- PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0,
- pbn_b0_4_921600 },
- /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
- { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
- PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
- pbn_b2_8_921600 },
- /* Advantech also use 0x3618 and 0xf618 */
- { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
- PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
- pbn_b0_4_921600 },
- { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
- PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
- pbn_b0_4_921600 },
- { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
- PCI_SUBVENDOR_ID_CONNECT_TECH,
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
- pbn_b1_8_1382400 },
- { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
- PCI_SUBVENDOR_ID_CONNECT_TECH,
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
- pbn_b1_4_1382400 },
- { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
- PCI_SUBVENDOR_ID_CONNECT_TECH,
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
- pbn_b1_2_1382400 },
- { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
- PCI_SUBVENDOR_ID_CONNECT_TECH,
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
- pbn_b1_8_1382400 },
- { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
- PCI_SUBVENDOR_ID_CONNECT_TECH,
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
- pbn_b1_4_1382400 },
- { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
- PCI_SUBVENDOR_ID_CONNECT_TECH,
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
- pbn_b1_2_1382400 },
- { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
- PCI_SUBVENDOR_ID_CONNECT_TECH,
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
- pbn_b1_8_921600 },
- { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
- PCI_SUBVENDOR_ID_CONNECT_TECH,
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
- pbn_b1_8_921600 },
- { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
- PCI_SUBVENDOR_ID_CONNECT_TECH,
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
- pbn_b1_4_921600 },
- { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
- PCI_SUBVENDOR_ID_CONNECT_TECH,
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
- pbn_b1_4_921600 },
- { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
- PCI_SUBVENDOR_ID_CONNECT_TECH,
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
- pbn_b1_2_921600 },
- { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
- PCI_SUBVENDOR_ID_CONNECT_TECH,
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
- pbn_b1_8_921600 },
- { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
- PCI_SUBVENDOR_ID_CONNECT_TECH,
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
- pbn_b1_8_921600 },
- { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
- PCI_SUBVENDOR_ID_CONNECT_TECH,
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
- pbn_b1_4_921600 },
- { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
- PCI_SUBVENDOR_ID_CONNECT_TECH,
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
- pbn_b1_2_1250000 },
- { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
- PCI_SUBVENDOR_ID_CONNECT_TECH,
- PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
- pbn_b0_2_1843200 },
- { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
- PCI_SUBVENDOR_ID_CONNECT_TECH,
- PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
- pbn_b0_4_1843200 },
- { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
- PCI_VENDOR_ID_AFAVLAB,
- PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
- pbn_b0_4_1152000 },
- { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_bt_1_115200 },
- { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_bt_2_115200 },
- { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_bt_4_115200 },
- { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_bt_2_115200 },
- { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_bt_4_115200 },
- { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_8_115200 },
- { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_8_460800 },
- { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_8_115200 },
+ {
+ PCI_VDEVICE_SUB(ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600,
+ PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID),
+ .driver_data = pbn_b0_4_921600,
+ }, {
+ /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
+ PCI_VDEVICE_SUB(ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
+ PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001),
+ .driver_data = pbn_b2_8_921600,
+ }, {
+ /* Advantech also use 0x3618 and 0xf618 */
+ PCI_VDEVICE_SUB(ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
+ PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID),
+ .driver_data = pbn_b0_4_921600,
+ }, {
+ PCI_VDEVICE_SUB(ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
+ PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID),
+ .driver_data = pbn_b0_4_921600,
+ }, {
+ PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V960,
+ PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232),
+ .driver_data = pbn_b1_8_1382400,
+ }, {
+ PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V960,
+ PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232),
+ .driver_data = pbn_b1_4_1382400,
+ }, {
+ PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V960,
+ PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232),
+ .driver_data = pbn_b1_2_1382400,
+ }, {
+ PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351,
+ PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232),
+ .driver_data = pbn_b1_8_1382400,
+ }, {
+ PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351,
+ PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232),
+ .driver_data = pbn_b1_4_1382400,
+ }, {
+ PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351,
+ PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232),
+ .driver_data = pbn_b1_2_1382400,
+ }, {
+ PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351,
+ PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485),
+ .driver_data = pbn_b1_8_921600,
+ }, {
+ PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351,
+ PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4),
+ .driver_data = pbn_b1_8_921600,
+ }, {
+ PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351,
+ PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485),
+ .driver_data = pbn_b1_4_921600,
+ }, {
+ PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351,
+ PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2),
+ .driver_data = pbn_b1_4_921600,
+ }, {
+ PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351,
+ PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485),
+ .driver_data = pbn_b1_2_921600,
+ }, {
+ PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351,
+ PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6),
+ .driver_data = pbn_b1_8_921600,
+ }, {
+ PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351,
+ PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1),
+ .driver_data = pbn_b1_8_921600,
+ }, {
+ PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351,
+ PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1),
+ .driver_data = pbn_b1_4_921600,
+ }, {
+ PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351,
+ PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ),
+ .driver_data = pbn_b1_2_1250000,
+ }, {
+ PCI_VDEVICE_SUB(OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
+ PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2),
+ .driver_data = pbn_b0_2_1843200,
+ }, {
+ PCI_VDEVICE_SUB(OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
+ PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4),
+ .driver_data = pbn_b0_4_1843200,
+ }, {
+ PCI_VDEVICE_SUB(OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
+ PCI_VENDOR_ID_AFAVLAB, PCI_SUBDEVICE_ID_AFAVLAB_P061),
+ .driver_data = pbn_b0_4_1152000,
+ }, {
+ PCI_VDEVICE(SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530),
+ .driver_data = pbn_b2_bt_1_115200,
+ }, {
+ PCI_VDEVICE(SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2),
+ .driver_data = pbn_b2_bt_2_115200,
+ }, {
+ PCI_VDEVICE(SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422),
+ .driver_data = pbn_b2_bt_4_115200,
+ }, {
+ PCI_VDEVICE(SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232),
+ .driver_data = pbn_b2_bt_2_115200,
+ }, {
+ PCI_VDEVICE(SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4),
+ .driver_data = pbn_b2_bt_4_115200,
+ }, {
+ PCI_VDEVICE(SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8),
+ .driver_data = pbn_b2_8_115200,
+ }, {
+ PCI_VDEVICE(SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803),
+ .driver_data = pbn_b2_8_460800,
+ }, {
+ PCI_VDEVICE(SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8),
+ .driver_data = pbn_b2_8_115200,
+ }, {
+ PCI_VDEVICE(PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2),
+ .driver_data = pbn_b2_bt_2_115200,
+ }, {
+ PCI_VDEVICE(PLX, PCI_DEVICE_ID_PLX_SPCOM200),
+ .driver_data = pbn_b2_bt_2_921600,
+ }, {
+ /* VScom SPCOM800, from sl@s.pl */
+ PCI_VDEVICE(PLX, PCI_DEVICE_ID_PLX_SPCOM800),
+ .driver_data = pbn_b2_8_921600,
+ }, {
+ PCI_VDEVICE(PLX, PCI_DEVICE_ID_PLX_1077),
+ .driver_data = pbn_b2_4_921600,
+ }, {
+ /* Unknown card - subdevice 0x1584 */
+ PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050,
+ PCI_VENDOR_ID_PLX, PCI_SUBDEVICE_ID_UNKNOWN_0x1584),
+ .driver_data = pbn_b2_4_115200,
+ }, {
+ /* Unknown card - subdevice 0x1588 */
+ PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050,
+ PCI_VENDOR_ID_PLX, PCI_SUBDEVICE_ID_UNKNOWN_0x1588),
+ .driver_data = pbn_b2_8_115200,
+ }, {
+ PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050,
+ PCI_SUBVENDOR_ID_KEYSPAN, PCI_SUBDEVICE_ID_KEYSPAN_SX2),
+ .driver_data = pbn_panacom,
+ }, {
+ PCI_VDEVICE(PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM),
+ .driver_data = pbn_panacom4,
+ }, {
+ PCI_VDEVICE(PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM),
+ .driver_data = pbn_panacom2,
+ }, {
+ PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9030,
+ PCI_VENDOR_ID_ESDGMBH, PCI_DEVICE_ID_ESDGMBH_CPCIASIO4),
+ .driver_data = pbn_b2_4_115200,
+ }, {
+ PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050,
+ PCI_SUBVENDOR_ID_CHASE_PCIFAST, PCI_SUBDEVICE_ID_CHASE_PCIFAST4),
+ .driver_data = pbn_b2_4_460800,
+ }, {
+ PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050,
+ PCI_SUBVENDOR_ID_CHASE_PCIFAST, PCI_SUBDEVICE_ID_CHASE_PCIFAST8),
+ .driver_data = pbn_b2_8_460800,
+ }, {
+ PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050,
+ PCI_SUBVENDOR_ID_CHASE_PCIFAST, PCI_SUBDEVICE_ID_CHASE_PCIFAST16),
+ .driver_data = pbn_b2_16_460800,
+ }, {
+ PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050,
+ PCI_SUBVENDOR_ID_CHASE_PCIFAST, PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC),
+ .driver_data = pbn_b2_16_460800,
+ }, {
+ PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050,
+ PCI_SUBVENDOR_ID_CHASE_PCIRAS, PCI_SUBDEVICE_ID_CHASE_PCIRAS4),
+ .driver_data = pbn_b2_4_460800,
+ }, {
+ PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050,
+ PCI_SUBVENDOR_ID_CHASE_PCIRAS, PCI_SUBDEVICE_ID_CHASE_PCIRAS8),
+ .driver_data = pbn_b2_8_460800,
+ }, {
+ PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050,
+ PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4055),
+ .driver_data = pbn_b2_4_115200,
+ }, {
+ /*
+ * Megawolf Romulus PCI Serial Card, from Mike Hudson
+ * (Exoray@isys.ca)
+ */
+ PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_ROMULUS,
+ 0x10b5, 0x106a),
+ .driver_data = pbn_plx_romulus,
+ },
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_bt_2_115200 },
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_bt_2_921600 },
- /*
- * VScom SPCOM800, from sl@s.pl
- */
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_8_921600 },
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_4_921600 },
- /* Unknown card - subdevice 0x1584 */
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
- PCI_VENDOR_ID_PLX,
- PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
- pbn_b2_4_115200 },
- /* Unknown card - subdevice 0x1588 */
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
- PCI_VENDOR_ID_PLX,
- PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
- pbn_b2_8_115200 },
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
- PCI_SUBVENDOR_ID_KEYSPAN,
- PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
- pbn_panacom },
- { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_panacom4 },
- { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_panacom2 },
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
- PCI_VENDOR_ID_ESDGMBH,
- PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
- pbn_b2_4_115200 },
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
- PCI_SUBVENDOR_ID_CHASE_PCIFAST,
- PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
- pbn_b2_4_460800 },
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
- PCI_SUBVENDOR_ID_CHASE_PCIFAST,
- PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
- pbn_b2_8_460800 },
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
- PCI_SUBVENDOR_ID_CHASE_PCIFAST,
- PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
- pbn_b2_16_460800 },
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
- PCI_SUBVENDOR_ID_CHASE_PCIFAST,
- PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
- pbn_b2_16_460800 },
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
- PCI_SUBVENDOR_ID_CHASE_PCIRAS,
- PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
- pbn_b2_4_460800 },
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
- PCI_SUBVENDOR_ID_CHASE_PCIRAS,
- PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
- pbn_b2_8_460800 },
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
- PCI_SUBVENDOR_ID_EXSYS,
- PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
- pbn_b2_4_115200 },
- /*
- * Megawolf Romulus PCI Serial Card, from Mike Hudson
- * (Exoray@isys.ca)
- */
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
- 0x10b5, 0x106a, 0, 0,
- pbn_plx_romulus },
/*
* Quatech cards. These actually have configurable clocks but for
* now we just use the default.
*
* 100 series are RS232, 200 series RS422,
*/
- { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_4_115200 },
- { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_2_115200 },
- { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_2_115200 },
- { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_4_115200 },
- { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_8_115200 },
- { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_8_115200 },
- { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_4_115200 },
- { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_2_115200 },
- { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_4_115200 },
- { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_2_115200 },
- { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_4_115200 },
- { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_1_115200 },
- { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_4_115200 },
- { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_1_115200 },
- { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_8_115200 },
-
- { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
- PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
- 0, 0,
- pbn_b0_4_921600 },
- { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
- PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
- 0, 0,
- pbn_b0_4_1152000 },
- { PCI_VENDOR_ID_OXSEMI, 0x9505,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_2_921600 },
-
+ {
+ PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_QSC100),
+ .driver_data = pbn_b1_4_115200,
+ }, {
+ PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_DSC100),
+ .driver_data = pbn_b1_2_115200,
+ }, {
+ PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_DSC200),
+ .driver_data = pbn_b1_2_115200,
+ }, {
+ PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_QSC200),
+ .driver_data = pbn_b1_4_115200,
+ }, {
+ PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D),
+ .driver_data = pbn_b1_8_115200,
+ }, {
+ PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M),
+ .driver_data = pbn_b1_8_115200,
+ }, {
+ PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100),
+ .driver_data = pbn_b1_4_115200,
+ }, {
+ PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100),
+ .driver_data = pbn_b1_2_115200,
+ }, {
+ PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200),
+ .driver_data = pbn_b1_4_115200,
+ }, {
+ PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200),
+ .driver_data = pbn_b1_2_115200,
+ }, {
+ PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100),
+ .driver_data = pbn_b2_4_115200,
+ }, {
+ PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100),
+ .driver_data = pbn_b2_1_115200,
+ }, {
+ PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200),
+ .driver_data = pbn_b2_4_115200,
+ }, {
+ PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200),
+ .driver_data = pbn_b2_1_115200,
+ }, {
+ PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100),
+ .driver_data = pbn_b0_8_115200,
+ }, {
+ PCI_VDEVICE_SUB(SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
+ PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4),
+ .driver_data = pbn_b0_4_921600,
+ }, {
+ PCI_VDEVICE_SUB(OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
+ PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL),
+ .driver_data = pbn_b0_4_1152000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0x9505),
+ .driver_data = pbn_b0_bt_2_921600,
+ }, {
/*
* The below card is a little controversial since it is the
* subject of a PCI vendor/device ID clash. (See
* www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
* For now just used the hex ID 0x950a.
*/
- { PCI_VENDOR_ID_OXSEMI, 0x950a,
- PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
- 0, 0, pbn_b0_2_115200 },
- { PCI_VENDOR_ID_OXSEMI, 0x950a,
- PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
- 0, 0, pbn_b0_2_115200 },
- { PCI_VENDOR_ID_OXSEMI, 0x950a,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_2_1130000 },
- { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
- PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
- pbn_b0_1_921600 },
- { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_4_115200 },
- { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_2_921600 },
- { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_8_1152000 },
+ PCI_VDEVICE_SUB(OXSEMI, 0x950a,
+ PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00),
+ .driver_data = pbn_b0_2_115200,
+ }, {
+ PCI_VDEVICE_SUB(OXSEMI, 0x950a,
+ PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30),
+ .driver_data = pbn_b0_2_115200,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0x950a),
+ .driver_data = pbn_b0_2_1130000,
+ }, {
+ PCI_VDEVICE_SUB(OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
+ PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950),
+ .driver_data = pbn_b0_1_921600,
+ }, {
+ PCI_VDEVICE(OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954),
+ .driver_data = pbn_b0_4_115200,
+ }, {
+ PCI_VDEVICE(OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952),
+ .driver_data = pbn_b0_bt_2_921600,
+ }, {
+ PCI_VDEVICE(OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958),
+ .driver_data = pbn_b2_8_1152000,
+ },
/*
* Oxford Semiconductor Inc. Tornado PCI express device range.
*/
- { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_2_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_2_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_4_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_4_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_8_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_8_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_1_15625000 },
+ {
+ PCI_VDEVICE(OXSEMI, 0xc101), /* OXPCIe952 1 Legacy UART */
+ .driver_data = pbn_b0_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc105), /* OXPCIe952 1 Legacy UART */
+ .driver_data = pbn_b0_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc11b), /* OXPCIe952 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc11f), /* OXPCIe952 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc120), /* OXPCIe952 1 Legacy UART */
+ .driver_data = pbn_b0_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc124), /* OXPCIe952 1 Legacy UART */
+ .driver_data = pbn_b0_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc138), /* OXPCIe952 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc13d), /* OXPCIe952 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc140), /* OXPCIe952 1 Legacy UART */
+ .driver_data = pbn_b0_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc141), /* OXPCIe952 1 Legacy UART */
+ .driver_data = pbn_b0_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc144), /* OXPCIe952 1 Legacy UART */
+ .driver_data = pbn_b0_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc145), /* OXPCIe952 1 Legacy UART */
+ .driver_data = pbn_b0_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc158), /* OXPCIe952 2 Native UART */
+ .driver_data = pbn_oxsemi_2_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc15d), /* OXPCIe952 2 Native UART */
+ .driver_data = pbn_oxsemi_2_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc208), /* OXPCIe954 4 Native UART */
+ .driver_data = pbn_oxsemi_4_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc20d), /* OXPCIe954 4 Native UART */
+ .driver_data = pbn_oxsemi_4_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc308), /* OXPCIe958 8 Native UART */
+ .driver_data = pbn_oxsemi_8_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc30d), /* OXPCIe958 8 Native UART */
+ .driver_data = pbn_oxsemi_8_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc40b), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc40f), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc41b), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc41f), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc42b), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc42f), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc43b), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc43f), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc44b), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc44f), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc45b), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc45f), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc46b), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc46f), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc47b), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc47f), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc48b), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc48f), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc49b), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc49f), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc4ab), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc4af), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc4bb), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc4bf), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc4cb), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ PCI_VDEVICE(OXSEMI, 0xc4cf), /* OXPCIe200 1 Native UART */
+ .driver_data = pbn_oxsemi_1_15625000,
+ },
/*
* Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
*/
- { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
- PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
- pbn_oxsemi_1_15625000 },
- { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
- PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
- pbn_oxsemi_2_15625000 },
- { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
- PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
- pbn_oxsemi_4_15625000 },
- { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
- PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
- pbn_oxsemi_8_15625000 },
+ {
+ /* IQ Express 1 Port V.34 Super-G3 Fax */
+ PCI_VDEVICE_SUB(MAINPINE, 0x4000,
+ PCI_VENDOR_ID_MAINPINE, 0x4001),
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ /* IQ Express 2 Port V.34 Super-G3 Fax */
+ PCI_VDEVICE_SUB(MAINPINE, 0x4000,
+ PCI_VENDOR_ID_MAINPINE, 0x4002),
+ .driver_data = pbn_oxsemi_2_15625000,
+ }, {
+ /* IQ Express 4 Port V.34 Super-G3 Fax */
+ PCI_VDEVICE_SUB(MAINPINE, 0x4000,
+ PCI_VENDOR_ID_MAINPINE, 0x4004),
+ .driver_data = pbn_oxsemi_4_15625000,
+ }, {
+ /* IQ Express 8 Port V.34 Super-G3 Fax */
+ PCI_VDEVICE_SUB(MAINPINE, 0x4000,
+ PCI_VENDOR_ID_MAINPINE, 0x4008),
+ .driver_data = pbn_oxsemi_8_15625000,
+ },
/*
* Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
*/
- { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
- PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_2_15625000 },
+ {
+ PCI_VDEVICE_SUB(DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
+ PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID),
+ .driver_data = pbn_oxsemi_2_15625000,
+ },
+
/*
* EndRun Technologies. PCI express device range.
* EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952.
*/
- { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi_2_15625000 },
+ {
+ PCI_VDEVICE(ENDRUN, PCI_DEVICE_ID_ENDRUN_1588),
+ .driver_data = pbn_oxsemi_2_15625000,
+ },
/*
* SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
* from skokodyn@yahoo.com
*/
- { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
- PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
- pbn_sbsxrsio },
- { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
- PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
- pbn_sbsxrsio },
- { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
- PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
- pbn_sbsxrsio },
- { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
- PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
- pbn_sbsxrsio },
+ {
+ PCI_VDEVICE_SUB(SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
+ PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232),
+ .driver_data = pbn_sbsxrsio,
+ }, {
+ PCI_VDEVICE_SUB(SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
+ PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422),
+ .driver_data = pbn_sbsxrsio,
+ }, {
+ PCI_VDEVICE_SUB(SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
+ PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232),
+ .driver_data = pbn_sbsxrsio,
+ }, {
+ PCI_VDEVICE_SUB(SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
+ PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422),
+ .driver_data = pbn_sbsxrsio,
+ },
/*
* Digitan DS560-558, from jimd@esoft.com
*/
- { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_1_115200 },
+ {
+ PCI_VDEVICE(ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM),
+ .driver_data = pbn_b1_1_115200,
+ },
/*
* Titan Electronic cards
* The 400L and 800L have a custom setup quirk.
*/
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_1_921600 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_2_921600 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_4_921600 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_4_921600 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_1_921600 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_bt_2_921600 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_4_921600 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_8_921600 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b4_bt_2_921600 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b4_bt_4_921600 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b4_bt_8_921600 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_4_921600 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_4_921600 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_4_921600 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_titan_1_4000000 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_titan_2_4000000 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_titan_4_4000000 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_titan_8_4000000 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_titan_2_4000000 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_titan_2_4000000 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_2_921600 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_4_921600 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_4_921600 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_4_921600 },
- { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_4_921600 },
-
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_1_460800 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_1_460800 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_1_460800 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_bt_2_921600 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_bt_2_921600 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_bt_2_921600 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_bt_4_921600 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_bt_4_921600 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_bt_4_921600 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_1_921600 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_1_921600 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_1_921600 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_2_921600 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_2_921600 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_2_921600 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_4_921600 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_4_921600 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_4_921600 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_8_921600 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_8_921600 },
- { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_8_921600 },
+ {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_100),
+ .driver_data = pbn_b0_1_921600,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_200),
+ .driver_data = pbn_b0_2_921600,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_400),
+ .driver_data = pbn_b0_4_921600,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_800B),
+ .driver_data = pbn_b0_4_921600,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_100L),
+ .driver_data = pbn_b1_1_921600,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_200L),
+ .driver_data = pbn_b1_bt_2_921600,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_400L),
+ .driver_data = pbn_b0_bt_4_921600,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_800L),
+ .driver_data = pbn_b0_bt_8_921600,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_200I),
+ .driver_data = pbn_b4_bt_2_921600,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_400I),
+ .driver_data = pbn_b4_bt_4_921600,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_800I),
+ .driver_data = pbn_b4_bt_8_921600,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_400EH),
+ .driver_data = pbn_b0_4_921600,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_800EH),
+ .driver_data = pbn_b0_4_921600,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_800EHB),
+ .driver_data = pbn_b0_4_921600,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_100E),
+ .driver_data = pbn_titan_1_4000000,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_200E),
+ .driver_data = pbn_titan_2_4000000,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_400E),
+ .driver_data = pbn_titan_4_4000000,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_800E),
+ .driver_data = pbn_titan_8_4000000,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_200EI),
+ .driver_data = pbn_titan_2_4000000,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_200EISI),
+ .driver_data = pbn_titan_2_4000000,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_200V3),
+ .driver_data = pbn_b0_bt_2_921600,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_400V3),
+ .driver_data = pbn_b0_4_921600,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_410V3),
+ .driver_data = pbn_b0_4_921600,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_800V3),
+ .driver_data = pbn_b0_4_921600,
+ }, {
+ PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_800V3B),
+ .driver_data = pbn_b0_4_921600,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550),
+ .driver_data = pbn_b2_1_460800,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650),
+ .driver_data = pbn_b2_1_460800,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850),
+ .driver_data = pbn_b2_1_460800,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550),
+ .driver_data = pbn_b2_bt_2_921600,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650),
+ .driver_data = pbn_b2_bt_2_921600,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850),
+ .driver_data = pbn_b2_bt_2_921600,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550),
+ .driver_data = pbn_b2_bt_4_921600,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650),
+ .driver_data = pbn_b2_bt_4_921600,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850),
+ .driver_data = pbn_b2_bt_4_921600,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550),
+ .driver_data = pbn_b0_1_921600,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650),
+ .driver_data = pbn_b0_1_921600,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850),
+ .driver_data = pbn_b0_1_921600,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550),
+ .driver_data = pbn_b0_bt_2_921600,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650),
+ .driver_data = pbn_b0_bt_2_921600,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850),
+ .driver_data = pbn_b0_bt_2_921600,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550),
+ .driver_data = pbn_b0_bt_4_921600,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650),
+ .driver_data = pbn_b0_bt_4_921600,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850),
+ .driver_data = pbn_b0_bt_4_921600,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550),
+ .driver_data = pbn_b0_bt_8_921600,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650),
+ .driver_data = pbn_b0_bt_8_921600,
+ }, {
+ PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850),
+ .driver_data = pbn_b0_bt_8_921600,
+ },
/*
* Computone devices submitted by Doug McNash dmcnash@computone.com
*/
- { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
- PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
- 0, 0, pbn_computone_4 },
- { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
- PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
- 0, 0, pbn_computone_8 },
- { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
- PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
- 0, 0, pbn_computone_6 },
+ {
+ PCI_VDEVICE_SUB(COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
+ PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4),
+ .driver_data = pbn_computone_4,
+ }, {
+ PCI_VDEVICE_SUB(COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
+ PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8),
+ .driver_data = pbn_computone_8,
+ }, {
+ PCI_VDEVICE_SUB(COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
+ PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6),
+ .driver_data = pbn_computone_6,
+ },
- { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_oxsemi },
- { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
- PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_1_921600 },
+ {
+ PCI_VDEVICE(OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N),
+ .driver_data = pbn_oxsemi,
+ }, {
+ PCI_VDEVICE_SUB(TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
+ PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID),
+ .driver_data = pbn_b0_bt_1_921600,
+ },
/*
* Sunix PCI serial boards
*/
- { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
- PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
- pbn_sunix_pci_1s },
- { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
- PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
- pbn_sunix_pci_2s },
- { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
- PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
- pbn_sunix_pci_4s },
- { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
- PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
- pbn_sunix_pci_4s },
- { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
- PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
- pbn_sunix_pci_8s },
- { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
- PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
- pbn_sunix_pci_8s },
- { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
- PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
- pbn_sunix_pci_16s },
+ {
+ PCI_VDEVICE_SUB(SUNIX, PCI_DEVICE_ID_SUNIX_1999,
+ PCI_VENDOR_ID_SUNIX, 0x0001),
+ .driver_data = pbn_sunix_pci_1s,
+ }, {
+ PCI_VDEVICE_SUB(SUNIX, PCI_DEVICE_ID_SUNIX_1999,
+ PCI_VENDOR_ID_SUNIX, 0x0002),
+ .driver_data = pbn_sunix_pci_2s,
+ }, {
+ PCI_VDEVICE_SUB(SUNIX, PCI_DEVICE_ID_SUNIX_1999,
+ PCI_VENDOR_ID_SUNIX, 0x0004),
+ .driver_data = pbn_sunix_pci_4s,
+ }, {
+ PCI_VDEVICE_SUB(SUNIX, PCI_DEVICE_ID_SUNIX_1999,
+ PCI_VENDOR_ID_SUNIX, 0x0084),
+ .driver_data = pbn_sunix_pci_4s,
+ }, {
+ PCI_VDEVICE_SUB(SUNIX, PCI_DEVICE_ID_SUNIX_1999,
+ PCI_VENDOR_ID_SUNIX, 0x0008),
+ .driver_data = pbn_sunix_pci_8s,
+ }, {
+ PCI_VDEVICE_SUB(SUNIX, PCI_DEVICE_ID_SUNIX_1999,
+ PCI_VENDOR_ID_SUNIX, 0x0088),
+ .driver_data = pbn_sunix_pci_8s,
+ }, {
+ PCI_VDEVICE_SUB(SUNIX, PCI_DEVICE_ID_SUNIX_1999,
+ PCI_VENDOR_ID_SUNIX, 0x0010),
+ .driver_data = pbn_sunix_pci_16s,
+ },
/*
* AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
*/
- { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_8_115200 },
- { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_8_115200 },
-
- { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_2_115200 },
- { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_2_115200 },
- { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_2_115200 },
- { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_4_460800 },
- { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_4_460800 },
- { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_2_460800 },
- { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_2_460800 },
- { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_2_460800 },
- { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_1_115200 },
- { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_bt_1_460800 },
+ {
+ PCI_VDEVICE(AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028),
+ .driver_data = pbn_b0_bt_8_115200,
+ }, {
+ PCI_VDEVICE(AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030),
+ .driver_data = pbn_b0_bt_8_115200,
+ }, {
+ PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_DSERIAL),
+ .driver_data = pbn_b0_bt_2_115200,
+ }, {
+ PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A),
+ .driver_data = pbn_b0_bt_2_115200,
+ }, {
+ PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B),
+ .driver_data = pbn_b0_bt_2_115200,
+ }, {
+ PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_OCTO_A),
+ .driver_data = pbn_b0_bt_4_460800,
+ }, {
+ PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_OCTO_B),
+ .driver_data = pbn_b0_bt_4_460800,
+ }, {
+ PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS),
+ .driver_data = pbn_b0_bt_2_460800,
+ }, {
+ PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_QUAD_A),
+ .driver_data = pbn_b0_bt_2_460800,
+ }, {
+ PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_QUAD_B),
+ .driver_data = pbn_b0_bt_2_460800,
+ }, {
+ PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_SSERIAL),
+ .driver_data = pbn_b0_bt_1_115200,
+ }, {
+ PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_PORT_650),
+ .driver_data = pbn_b0_bt_1_460800,
+ },
/*
* Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
@@ -5164,560 +5203,533 @@ static const struct pci_device_id serial_pci_tbl[] = {
* Note that JC140x are RS422/485 cards which require ox950
* ACR = 0x10, and as such are not currently fully supported.
*/
- { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
- 0x1204, 0x0004, 0, 0,
- pbn_b0_4_921600 },
- { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
- 0x1208, 0x0004, 0, 0,
- pbn_b0_4_921600 },
-/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
- 0x1402, 0x0002, 0, 0,
- pbn_b0_2_921600 }, */
-/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
- 0x1404, 0x0004, 0, 0,
- pbn_b0_4_921600 }, */
- { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
- 0x1208, 0x0004, 0, 0,
- pbn_b0_4_921600 },
-
- { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
- 0x1204, 0x0004, 0, 0,
- pbn_b0_4_921600 },
- { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
- 0x1208, 0x0004, 0, 0,
- pbn_b0_4_921600 },
- { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
- 0x1208, 0x0004, 0, 0,
- pbn_b0_4_921600 },
+ {
+ PCI_VDEVICE_SUB(KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
+ 0x1204, 0x0004),
+ .driver_data = pbn_b0_4_921600,
+ }, {
+ PCI_VDEVICE_SUB(KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
+ 0x1208, 0x0004),
+ .driver_data = pbn_b0_4_921600,
+ },
+/* {
+ PCI_VDEVICE_SUB(KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
+ 0x1402, 0x0002),
+ .driver_data = pbn_b0_2_921600,
+ }, */
+/* {
+ PCI_VDEVICE_SUB(KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
+ 0x1404, 0x0004),
+ .driver_data = pbn_b0_4_921600,
+ }, */
+ {
+ PCI_VDEVICE_SUB(KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
+ 0x1208, 0x0004),
+ .driver_data = pbn_b0_4_921600,
+ }, {
+ PCI_VDEVICE_SUB(KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
+ 0x1204, 0x0004),
+ .driver_data = pbn_b0_4_921600,
+ }, {
+ PCI_VDEVICE_SUB(KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
+ 0x1208, 0x0004),
+ .driver_data = pbn_b0_4_921600,
+ }, {
+ PCI_VDEVICE_SUB(KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
+ 0x1208, 0x0004),
+ .driver_data = pbn_b0_4_921600,
+ },
/*
* Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
*/
- { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_1_1382400 },
+ {
+ PCI_VDEVICE(DELL, PCI_DEVICE_ID_DELL_RAC4),
+ .driver_data = pbn_b1_1_1382400,
+ },
/*
* Dell Remote Access Card III - Tim_T_Murphy@Dell.com
*/
- { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_1_1382400 },
+ {
+ PCI_VDEVICE(DELL, PCI_DEVICE_ID_DELL_RACIII),
+ .driver_data = pbn_b1_1_1382400,
+ },
/*
* RAStel 2 port modem, gerg@moreton.com.au
*/
- { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_bt_2_115200 },
+ {
+ PCI_VDEVICE(MORETON, PCI_DEVICE_ID_RASTEL_2PORT),
+ .driver_data = pbn_b2_bt_2_115200,
+ },
/*
* EKF addition for i960 Boards form EKF with serial port
*/
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
- 0xE4BF, PCI_ANY_ID, 0, 0,
- pbn_intel_i960 },
+ {
+ PCI_VDEVICE_SUB(INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
+ 0xE4BF, PCI_ANY_ID),
+ .driver_data = pbn_intel_i960,
+ },
/*
* Xircom Cardbus/Ethernet combos
*/
- { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_1_115200 },
+ {
+ PCI_VDEVICE(XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM),
+ .driver_data = pbn_b0_1_115200,
+ },
/*
* Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
*/
- { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_1_115200 },
+ {
+ PCI_VDEVICE(XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G),
+ .driver_data = pbn_b0_1_115200,
+ },
/*
* Untested PCI modems, sent in from various folks...
*/
- /*
- * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
- */
- { PCI_VENDOR_ID_ROCKWELL, 0x1004,
- 0x1048, 0x1500, 0, 0,
- pbn_b1_1_115200 },
-
- { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
- 0xFF00, 0, 0, 0,
- pbn_sgi_ioc3 },
+ {
+ /* Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> */
+ PCI_VDEVICE_SUB(ROCKWELL, 0x1004, 0x1048, 0x1500),
+ .driver_data = pbn_b1_1_115200,
+ }, {
+ PCI_VDEVICE_SUB(SGI, PCI_DEVICE_ID_SGI_IOC3, 0xFF00, 0),
+ .driver_data = pbn_sgi_ioc3,
+ },
/*
* HP Diva card
*/
- { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
- PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
- pbn_b1_1_115200 },
- { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_5_115200 },
- { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_1_115200 },
- /* HPE PCI serial device */
- { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_1_115200 },
-
- { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b3_2_115200 },
- { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b3_4_115200 },
- { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b3_8_115200 },
- /*
- * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
- */
- { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b0_1_115200 },
- /*
- * ITE
- */
- { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b1_bt_1_115200 },
-
- /*
- * IntaShield IS-100
- */
- { PCI_VENDOR_ID_INTASHIELD, 0x0D60,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b2_1_115200 },
- /*
- * IntaShield IS-200
- */
- { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0d80 */
- pbn_b2_2_115200 },
- /*
- * IntaShield IS-400
- */
- { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
- pbn_b2_4_115200 },
- /*
- * IntaShield IX-100
- */
- { PCI_VENDOR_ID_INTASHIELD, 0x4027,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_1_15625000 },
- /*
- * IntaShield IX-200
- */
- { PCI_VENDOR_ID_INTASHIELD, 0x4028,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_2_15625000 },
- /*
- * IntaShield IX-400
- */
- { PCI_VENDOR_ID_INTASHIELD, 0x4029,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_4_15625000 },
+ {
+ PCI_VDEVICE_SUB(HP, PCI_DEVICE_ID_HP_DIVA,
+ PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3),
+ .driver_data = pbn_b1_1_115200,
+ }, {
+ PCI_VDEVICE(HP, PCI_DEVICE_ID_HP_DIVA),
+ .driver_data = pbn_b0_5_115200,
+ }, {
+ PCI_VDEVICE(HP, PCI_DEVICE_ID_HP_DIVA_AUX),
+ .driver_data = pbn_b2_1_115200,
+ }, {
+ /* HPE PCI serial device */
+ PCI_VDEVICE(HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL),
+ .driver_data = pbn_b1_1_115200,
+ }, {
+ PCI_VDEVICE(DCI, PCI_DEVICE_ID_DCI_PCCOM2),
+ .driver_data = pbn_b3_2_115200,
+ }, {
+ PCI_VDEVICE(DCI, PCI_DEVICE_ID_DCI_PCCOM4),
+ .driver_data = pbn_b3_4_115200,
+ }, {
+ PCI_VDEVICE(DCI, PCI_DEVICE_ID_DCI_PCCOM8),
+ .driver_data = pbn_b3_8_115200,
+ }, {
+ /* Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) */
+ PCI_VDEVICE(TOPIC, PCI_DEVICE_ID_TOPIC_TP560),
+ .driver_data = pbn_b0_1_115200,
+ }, {
+ /* ITE */
+ PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8872),
+ .driver_data = pbn_b1_bt_1_115200,
+ }, {
+ /* IntaShield IS-100 */
+ PCI_VDEVICE(INTASHIELD, 0x0D60),
+ .driver_data = pbn_b2_1_115200,
+ }, {
+ /* IntaShield IS-200; 135a.0d80 */
+ PCI_VDEVICE(INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ /* IntaShield IS-400; 135a.0dc0 */
+ PCI_VDEVICE(INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400),
+ .driver_data = pbn_b2_4_115200,
+ }, {
+ /* IntaShield IX-100 */
+ PCI_VDEVICE(INTASHIELD, 0x4027),
+ .driver_data = pbn_oxsemi_1_15625000,
+ }, {
+ /* IntaShield IX-200 */
+ PCI_VDEVICE(INTASHIELD, 0x4028),
+ .driver_data = pbn_oxsemi_2_15625000,
+ }, {
+ /* IntaShield IX-400 */
+ PCI_VDEVICE(INTASHIELD, 0x4029),
+ .driver_data = pbn_oxsemi_4_15625000,
+ },
/* Brainboxes Devices */
/*
* Brainboxes UC-101
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x0BA2,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x0BA3,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x0BA1),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x0BA2),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x0BA3),
+ .driver_data = pbn_b2_2_115200,
+ },
/*
* Brainboxes UC-235/246
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_1_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x0AA2,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_1_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x0AA1),
+ .driver_data = pbn_b2_1_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x0AA2),
+ .driver_data = pbn_b2_1_115200,
+ },
/*
* Brainboxes UC-253/UC-734
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x0CA1,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x0CA1),
+ .driver_data = pbn_b2_2_115200,
+ },
/*
* Brainboxes UC-260/271/701/756
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
- PCI_ANY_ID, PCI_ANY_ID,
- PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
- pbn_b2_4_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
- PCI_ANY_ID, PCI_ANY_ID,
- PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
- pbn_b2_4_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x0D21),
+ .class = PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
+ .class_mask = 0xffff00,
+ .driver_data = pbn_b2_4_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x0E34),
+ .class = PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
+ .class_mask = 0xffff00,
+ .driver_data = pbn_b2_4_115200,
+ },
/*
* Brainboxes UC-268
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x0841,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_4_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x0841),
+ .driver_data = pbn_b2_4_115200,
+ },
/*
* Brainboxes UC-275/279
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x0881,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_8_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x0881),
+ .driver_data = pbn_b2_8_115200,
+ },
/*
* Brainboxes UC-302
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x08E1,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x08E2,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x08E3,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x08E1),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x08E2),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x08E3),
+ .driver_data = pbn_b2_2_115200,
+ },
/*
* Brainboxes UC-310
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x08C1,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x08C1),
+ .driver_data = pbn_b2_2_115200,
+ },
/*
* Brainboxes UC-313
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x08A1,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x08A2,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x08A3,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x08A1),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x08A2),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x08A3),
+ .driver_data = pbn_b2_2_115200,
+ },
/*
* Brainboxes UC-320/324
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x0A61,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_1_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x0A61),
+ .driver_data = pbn_b2_1_115200,
+ },
/*
* Brainboxes UC-346
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x0B01,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_4_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x0B02,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_4_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x0B01),
+ .driver_data = pbn_b2_4_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x0B02),
+ .driver_data = pbn_b2_4_115200,
+ },
/*
* Brainboxes UC-357
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x0A81,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x0A82,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x0A83,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x0A81),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x0A82),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x0A83),
+ .driver_data = pbn_b2_2_115200,
+ },
/*
* Brainboxes UC-368
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x0C41,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_4_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x0C42,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_4_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x0C43,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_4_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x0C41),
+ .driver_data = pbn_b2_4_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x0C42),
+ .driver_data = pbn_b2_4_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x0C43),
+ .driver_data = pbn_b2_4_115200,
+ },
/*
* Brainboxes UC-420
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x0921,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_4_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x0921),
+ .driver_data = pbn_b2_4_115200,
+ },
/*
* Brainboxes UC-607
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x09A1,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x09A2,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x09A3,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x09A1),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x09A2),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x09A3),
+ .driver_data = pbn_b2_2_115200,
+ },
/*
* Brainboxes UC-836
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x0D41,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_4_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x0D41),
+ .driver_data = pbn_b2_4_115200,
+ },
/*
* Brainboxes UP-189
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x0AC1,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x0AC2,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x0AC3,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x0AC1),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x0AC2),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x0AC3),
+ .driver_data = pbn_b2_2_115200,
+ },
/*
* Brainboxes UP-200
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x0B21,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x0B22,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x0B23,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x0B21),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x0B22),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x0B23),
+ .driver_data = pbn_b2_2_115200,
+ },
/*
* Brainboxes UP-869
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x0C01,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x0C02,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x0C03,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x0C01),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x0C02),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x0C03),
+ .driver_data = pbn_b2_2_115200,
+ },
/*
* Brainboxes UP-880
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x0C21,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x0C22,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x0C23,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_2_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x0C21),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x0C22),
+ .driver_data = pbn_b2_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x0C23),
+ .driver_data = pbn_b2_2_115200,
+ },
/*
* Brainboxes PX-101
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x4005,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b0_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x4019,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_2_15625000 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x4005),
+ .driver_data = pbn_b0_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x4019),
+ .driver_data = pbn_oxsemi_2_15625000,
+ },
/*
* Brainboxes PX-235/246
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x4004,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b0_1_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x4016,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_1_15625000 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x4004),
+ .driver_data = pbn_b0_1_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x4016),
+ .driver_data = pbn_oxsemi_1_15625000,
+ },
/*
* Brainboxes PX-203/PX-257
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x4006,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b0_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x4015,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_2_15625000 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x4006),
+ .driver_data = pbn_b0_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x4015),
+ .driver_data = pbn_oxsemi_2_15625000,
+ },
/*
* Brainboxes PX-260/PX-701
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x400A,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_4_15625000 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x400A),
+ .driver_data = pbn_oxsemi_4_15625000,
+ },
/*
* Brainboxes PX-275/279
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x0E41,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b2_8_115200 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x0E41),
+ .driver_data = pbn_b2_8_115200,
+ },
/*
* Brainboxes PX-310
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x400E,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_2_15625000 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x400E),
+ .driver_data = pbn_oxsemi_2_15625000,
+ },
/*
* Brainboxes PX-313
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x400C,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_2_15625000 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x400C),
+ .driver_data = pbn_oxsemi_2_15625000,
+ },
/*
* Brainboxes PX-320/324/PX-376/PX-387
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x400B,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_1_15625000 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x400B),
+ .driver_data = pbn_oxsemi_1_15625000,
+ },
/*
* Brainboxes PX-335/346
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x400F,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_4_15625000 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x400F),
+ .driver_data = pbn_oxsemi_4_15625000,
+ },
/*
* Brainboxes PX-368
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x4010,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_4_15625000 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x4010),
+ .driver_data = pbn_oxsemi_4_15625000,
+ },
/*
* Brainboxes PX-420
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x4000,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b0_4_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x4011,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_4_15625000 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x4000),
+ .driver_data = pbn_b0_4_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x4011),
+ .driver_data = pbn_oxsemi_4_15625000,
+ },
/*
* Brainboxes PX-475
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x401D,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_1_15625000 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x401D),
+ .driver_data = pbn_oxsemi_1_15625000,
+ },
/*
* Brainboxes PX-803/PX-857
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x4009,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b0_2_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x4018,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_2_15625000 },
- { PCI_VENDOR_ID_INTASHIELD, 0x401E,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_2_15625000 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x4009),
+ .driver_data = pbn_b0_2_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x4018),
+ .driver_data = pbn_oxsemi_2_15625000,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x401E),
+ .driver_data = pbn_oxsemi_2_15625000,
+ },
/*
* Brainboxes PX-820
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x4002,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b0_4_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x4013,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_4_15625000 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x4002),
+ .driver_data = pbn_b0_4_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x4013),
+ .driver_data = pbn_oxsemi_4_15625000,
+ },
/*
* Brainboxes PX-835/PX-846
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x4008,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_b0_1_115200 },
- { PCI_VENDOR_ID_INTASHIELD, 0x4017,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_1_15625000 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x4008),
+ .driver_data = pbn_b0_1_115200,
+ }, {
+ PCI_VDEVICE(INTASHIELD, 0x4017),
+ .driver_data = pbn_oxsemi_1_15625000,
+ },
/*
* Brainboxes XC-235
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x4026,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_1_15625000 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x4026),
+ .driver_data = pbn_oxsemi_1_15625000,
+ },
/*
* Brainboxes XC-475
*/
- { PCI_VENDOR_ID_INTASHIELD, 0x4021,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0,
- pbn_oxsemi_1_15625000 },
+ {
+ PCI_VDEVICE(INTASHIELD, 0x4021),
+ .driver_data = pbn_oxsemi_1_15625000,
+ },
/*
* Perle PCI-RAS cards
*/
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
- PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
- 0, 0, pbn_b2_4_921600 },
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
- PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
- 0, 0, pbn_b2_8_921600 },
+ {
+ PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9030,
+ PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4),
+ .driver_data = pbn_b2_4_921600,
+ },
+ {
+ PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9030,
+ PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8),
+ .driver_data = pbn_b2_8_921600,
+ },
/*
* Mainpine series cards: Fairly standard layout but fools
@@ -5725,375 +5737,343 @@ static const struct pci_device_id serial_pci_tbl[] = {
* unmatched communications subclasses in the PCI Express case
*/
- { /* RockForceDUO */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x0200,
- 0, 0, pbn_b0_2_115200 },
- { /* RockForceQUATRO */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x0300,
- 0, 0, pbn_b0_4_115200 },
- { /* RockForceDUO+ */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x0400,
- 0, 0, pbn_b0_2_115200 },
- { /* RockForceQUATRO+ */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x0500,
- 0, 0, pbn_b0_4_115200 },
- { /* RockForce+ */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x0600,
- 0, 0, pbn_b0_2_115200 },
- { /* RockForce+ */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x0700,
- 0, 0, pbn_b0_4_115200 },
- { /* RockForceOCTO+ */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x0800,
- 0, 0, pbn_b0_8_115200 },
- { /* RockForceDUO+ */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x0C00,
- 0, 0, pbn_b0_2_115200 },
- { /* RockForceQUARTRO+ */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x0D00,
- 0, 0, pbn_b0_4_115200 },
- { /* RockForceOCTO+ */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x1D00,
- 0, 0, pbn_b0_8_115200 },
- { /* RockForceD1 */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x2000,
- 0, 0, pbn_b0_1_115200 },
- { /* RockForceF1 */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x2100,
- 0, 0, pbn_b0_1_115200 },
- { /* RockForceD2 */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x2200,
- 0, 0, pbn_b0_2_115200 },
- { /* RockForceF2 */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x2300,
- 0, 0, pbn_b0_2_115200 },
- { /* RockForceD4 */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x2400,
- 0, 0, pbn_b0_4_115200 },
- { /* RockForceF4 */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x2500,
- 0, 0, pbn_b0_4_115200 },
- { /* RockForceD8 */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x2600,
- 0, 0, pbn_b0_8_115200 },
- { /* RockForceF8 */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x2700,
- 0, 0, pbn_b0_8_115200 },
- { /* IQ Express D1 */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x3000,
- 0, 0, pbn_b0_1_115200 },
- { /* IQ Express F1 */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x3100,
- 0, 0, pbn_b0_1_115200 },
- { /* IQ Express D2 */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x3200,
- 0, 0, pbn_b0_2_115200 },
- { /* IQ Express F2 */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x3300,
- 0, 0, pbn_b0_2_115200 },
- { /* IQ Express D4 */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x3400,
- 0, 0, pbn_b0_4_115200 },
- { /* IQ Express F4 */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x3500,
- 0, 0, pbn_b0_4_115200 },
- { /* IQ Express D8 */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x3C00,
- 0, 0, pbn_b0_8_115200 },
- { /* IQ Express F8 */
- PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
- PCI_VENDOR_ID_MAINPINE, 0x3D00,
- 0, 0, pbn_b0_8_115200 },
+ {
+ /* RockForceDUO */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x0200),
+ .driver_data = pbn_b0_2_115200,
+ }, {
+ /* RockForceQUATRO */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x0300),
+ .driver_data = pbn_b0_4_115200,
+ }, {
+ /* RockForceDUO+ */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x0400),
+ .driver_data = pbn_b0_2_115200,
+ }, {
+ /* RockForceQUATRO+ */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x0500),
+ .driver_data = pbn_b0_4_115200,
+ }, {
+ /* RockForce+ */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x0600),
+ .driver_data = pbn_b0_2_115200,
+ }, {
+ /* RockForce+ */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x0700),
+ .driver_data = pbn_b0_4_115200,
+ }, {
+ /* RockForceOCTO+ */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x0800),
+ .driver_data = pbn_b0_8_115200,
+ }, {
+ /* RockForceDUO+ */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x0C00),
+ .driver_data = pbn_b0_2_115200,
+ }, {
+ /* RockForceQUARTRO+ */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x0D00),
+ .driver_data = pbn_b0_4_115200,
+ }, {
+ /* RockForceOCTO+ */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x1D00),
+ .driver_data = pbn_b0_8_115200,
+ }, {
+ /* RockForceD1 */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x2000),
+ .driver_data = pbn_b0_1_115200,
+ }, {
+ /* RockForceF1 */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x2100),
+ .driver_data = pbn_b0_1_115200,
+ }, { /* RockForceD2 */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x2200),
+ .driver_data = pbn_b0_2_115200,
+ }, { /* RockForceF2 */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x2300),
+ .driver_data = pbn_b0_2_115200,
+ }, {
+ /* RockForceD4 */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x2400),
+ .driver_data = pbn_b0_4_115200,
+ }, {
+ /* RockForceF4 */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x2500),
+ .driver_data = pbn_b0_4_115200,
+ }, {
+ /* RockForceD8 */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x2600),
+ .driver_data = pbn_b0_8_115200,
+ }, {
+ /* RockForceF8 */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x2700),
+ .driver_data = pbn_b0_8_115200,
+ }, {
+ /* IQ Express D1 */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x3000),
+ .driver_data = pbn_b0_1_115200,
+ }, {
+ /* IQ Express F1 */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x3100),
+ .driver_data = pbn_b0_1_115200,
+ }, {
+ /* IQ Express D2 */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x3200),
+ .driver_data = pbn_b0_2_115200,
+ }, {
+ /* IQ Express F2 */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x3300),
+ .driver_data = pbn_b0_2_115200,
+ }, {
+ /* IQ Express D4 */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x3400),
+ .driver_data = pbn_b0_4_115200,
+ }, {
+ /* IQ Express F4 */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x3500),
+ .driver_data = pbn_b0_4_115200,
+ }, {
+ /* IQ Express D8 */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x3C00),
+ .driver_data = pbn_b0_8_115200,
+ }, {
+ /* IQ Express F8 */
+ PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+ PCI_VENDOR_ID_MAINPINE, 0x3D00),
+ .driver_data = pbn_b0_8_115200,
+ },
-
- /*
- * PA Semi PA6T-1682M on-chip UART
- */
- { PCI_VENDOR_ID_PASEMI, 0xa004,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_pasemi_1682M },
+ {
+ /* PA Semi PA6T-1682M on-chip UART */
+ PCI_VDEVICE(PASEMI, 0xa004),
+ .driver_data = pbn_pasemi_1682M,
+ },
/*
* National Instruments
*/
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_16_115200 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_8_115200 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_bt_4_115200 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_bt_2_115200 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_bt_4_115200 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_bt_2_115200 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_16_115200 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_8_115200 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_bt_4_115200 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_bt_2_115200 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_bt_4_115200 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_b1_bt_2_115200 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_ni8430_2 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_ni8430_2 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_ni8430_4 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_ni8430_4 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_ni8430_8 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_ni8430_8 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_ni8430_16 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_ni8430_16 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_ni8430_2 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_ni8430_2 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_ni8430_4 },
- { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_ni8430_4 },
+ {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI23216),
+ .driver_data = pbn_b1_16_115200,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI2328),
+ .driver_data = pbn_b1_8_115200,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI2324),
+ .driver_data = pbn_b1_bt_4_115200,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI2322),
+ .driver_data = pbn_b1_bt_2_115200,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI2324I),
+ .driver_data = pbn_b1_bt_4_115200,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI2322I),
+ .driver_data = pbn_b1_bt_2_115200,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8420_23216),
+ .driver_data = pbn_b1_16_115200,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8420_2328),
+ .driver_data = pbn_b1_8_115200,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8420_2324),
+ .driver_data = pbn_b1_bt_4_115200,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8420_2322),
+ .driver_data = pbn_b1_bt_2_115200,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8422_2324),
+ .driver_data = pbn_b1_bt_4_115200,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8422_2322),
+ .driver_data = pbn_b1_bt_2_115200,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8430_2322),
+ .driver_data = pbn_ni8430_2,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI8430_2322),
+ .driver_data = pbn_ni8430_2,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8430_2324),
+ .driver_data = pbn_ni8430_4,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI8430_2324),
+ .driver_data = pbn_ni8430_4,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8430_2328),
+ .driver_data = pbn_ni8430_8,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI8430_2328),
+ .driver_data = pbn_ni8430_8,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8430_23216),
+ .driver_data = pbn_ni8430_16,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI8430_23216),
+ .driver_data = pbn_ni8430_16,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8432_2322),
+ .driver_data = pbn_ni8430_2,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI8432_2322),
+ .driver_data = pbn_ni8430_2,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8432_2324),
+ .driver_data = pbn_ni8430_4,
+ }, {
+ PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI8432_2324),
+ .driver_data = pbn_ni8430_4,
+ },
/*
* MOXA
*/
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E), pbn_moxa_2 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL), pbn_moxa_2 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N), pbn_moxa_2 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A), pbn_moxa_4 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N), pbn_moxa_4 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N), pbn_moxa_2 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL), pbn_moxa_4 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N), pbn_moxa_4 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A), pbn_moxa_8 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B), pbn_moxa_8 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A), pbn_moxa_8 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I), pbn_moxa_8 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL), pbn_moxa_2 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N), pbn_moxa_2 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A), pbn_moxa_4 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N), pbn_moxa_4 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A), pbn_moxa_8 },
- { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A), pbn_moxa_8 },
+ {
+ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E),
+ .driver_data = pbn_moxa_2,
+ }, {
+ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL),
+ .driver_data = pbn_moxa_2,
+ }, {
+ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N),
+ .driver_data = pbn_moxa_2,
+ }, {
+ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A),
+ .driver_data = pbn_moxa_4,
+ }, {
+ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N),
+ .driver_data = pbn_moxa_4,
+ }, {
+ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N),
+ .driver_data = pbn_moxa_2,
+ }, {
+ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL),
+ .driver_data = pbn_moxa_4,
+ }, {
+ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N),
+ .driver_data = pbn_moxa_4,
+ }, {
+ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A),
+ .driver_data = pbn_moxa_8,
+ }, {
+ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B),
+ .driver_data = pbn_moxa_8,
+ }, {
+ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A),
+ .driver_data = pbn_moxa_8,
+ }, {
+ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I),
+ .driver_data = pbn_moxa_8,
+ }, {
+ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL),
+ .driver_data = pbn_moxa_2,
+ }, {
+ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N),
+ .driver_data = pbn_moxa_2,
+ }, {
+ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A),
+ .driver_data = pbn_moxa_4,
+ }, {
+ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N),
+ .driver_data = pbn_moxa_4,
+ }, {
+ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A),
+ .driver_data = pbn_moxa_8,
+ }, {
+ PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A),
+ .driver_data = pbn_moxa_8,
+ },
/*
* ADDI-DATA GmbH communication cards <info@addi-data.com>
*/
- { PCI_VENDOR_ID_ADDIDATA,
- PCI_DEVICE_ID_ADDIDATA_APCI7500,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0,
- 0,
- pbn_b0_4_115200 },
-
- { PCI_VENDOR_ID_ADDIDATA,
- PCI_DEVICE_ID_ADDIDATA_APCI7420,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0,
- 0,
- pbn_b0_2_115200 },
-
- { PCI_VENDOR_ID_ADDIDATA,
- PCI_DEVICE_ID_ADDIDATA_APCI7300,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0,
- 0,
- pbn_b0_1_115200 },
-
- { PCI_VENDOR_ID_AMCC,
- PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0,
- 0,
- pbn_b1_8_115200 },
-
- { PCI_VENDOR_ID_ADDIDATA,
- PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0,
- 0,
- pbn_b0_4_115200 },
-
- { PCI_VENDOR_ID_ADDIDATA,
- PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0,
- 0,
- pbn_b0_2_115200 },
-
- { PCI_VENDOR_ID_ADDIDATA,
- PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0,
- 0,
- pbn_b0_1_115200 },
-
- { PCI_VENDOR_ID_ADDIDATA,
- PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0,
- 0,
- pbn_b0_4_115200 },
-
- { PCI_VENDOR_ID_ADDIDATA,
- PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0,
- 0,
- pbn_b0_2_115200 },
-
- { PCI_VENDOR_ID_ADDIDATA,
- PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0,
- 0,
- pbn_b0_1_115200 },
-
- { PCI_VENDOR_ID_ADDIDATA,
- PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0,
- 0,
- pbn_b0_8_115200 },
-
- { PCI_VENDOR_ID_ADDIDATA,
- PCI_DEVICE_ID_ADDIDATA_APCIe7500,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0,
- 0,
- pbn_ADDIDATA_PCIe_4_3906250 },
-
- { PCI_VENDOR_ID_ADDIDATA,
- PCI_DEVICE_ID_ADDIDATA_APCIe7420,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0,
- 0,
- pbn_ADDIDATA_PCIe_2_3906250 },
-
- { PCI_VENDOR_ID_ADDIDATA,
- PCI_DEVICE_ID_ADDIDATA_APCIe7300,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0,
- 0,
- pbn_ADDIDATA_PCIe_1_3906250 },
-
- { PCI_VENDOR_ID_ADDIDATA,
- PCI_DEVICE_ID_ADDIDATA_APCIe7800,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0,
- 0,
- pbn_ADDIDATA_PCIe_8_3906250 },
-
- { PCI_VENDOR_ID_ADDIDATA,
- PCI_DEVICE_ID_ADDIDATA_CPCI7500,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0,
- 0,
- pbn_b0_4_115200 },
-
- { PCI_VENDOR_ID_ADDIDATA,
- PCI_DEVICE_ID_ADDIDATA_CPCI7500_NG,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0,
- 0,
- pbn_b0_4_115200 },
-
- { PCI_VENDOR_ID_ADDIDATA,
- PCI_DEVICE_ID_ADDIDATA_CPCI7420_NG,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0,
- 0,
- pbn_b0_2_115200 },
-
- { PCI_VENDOR_ID_ADDIDATA,
- PCI_DEVICE_ID_ADDIDATA_CPCI7300_NG,
- PCI_ANY_ID,
- PCI_ANY_ID,
- 0,
- 0,
- pbn_b0_1_115200 },
-
- { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
- PCI_VENDOR_ID_IBM, 0x0299,
- 0, 0, pbn_b0_bt_2_115200 },
+ {
+ PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7500),
+ .driver_data = pbn_b0_4_115200,
+ }, {
+ PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7420),
+ .driver_data = pbn_b0_2_115200,
+ }, {
+ PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7300),
+ .driver_data = pbn_b0_1_115200,
+ }, {
+ PCI_VDEVICE(AMCC, PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800),
+ .driver_data = pbn_b1_8_115200,
+ }, {
+ PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7500_2),
+ .driver_data = pbn_b0_4_115200,
+ }, {
+ PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7420_2),
+ .driver_data = pbn_b0_2_115200,
+ }, {
+ PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7300_2),
+ .driver_data = pbn_b0_1_115200,
+ }, {
+ PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7500_3),
+ .driver_data = pbn_b0_4_115200,
+ }, {
+ PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7420_3),
+ .driver_data = pbn_b0_2_115200,
+ }, {
+ PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7300_3),
+ .driver_data = pbn_b0_1_115200,
+ }, {
+ PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7800_3),
+ .driver_data = pbn_b0_8_115200,
+ }, {
+ PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCIe7500),
+ .driver_data = pbn_ADDIDATA_PCIe_4_3906250,
+ }, {
+ PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCIe7420),
+ .driver_data = pbn_ADDIDATA_PCIe_2_3906250,
+ }, {
+ PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCIe7300),
+ .driver_data = pbn_ADDIDATA_PCIe_1_3906250,
+ }, {
+ PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCIe7800),
+ .driver_data = pbn_ADDIDATA_PCIe_8_3906250,
+ }, {
+ PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_CPCI7500),
+ .driver_data = pbn_b0_4_115200,
+ }, {
+ PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_CPCI7500_NG),
+ .driver_data = pbn_b0_4_115200,
+ }, {
+ PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_CPCI7420_NG),
+ .driver_data = pbn_b0_2_115200,
+ }, {
+ PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_CPCI7300_NG),
+ .driver_data = pbn_b0_1_115200,
+ }, {
+ PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9835,
+ PCI_VENDOR_ID_IBM, 0x0299),
+ .driver_data = pbn_b0_bt_2_115200,
+ },
/*
* other NetMos 9835 devices are most likely handled by the
@@ -6101,157 +6081,183 @@ static const struct pci_device_id serial_pci_tbl[] = {
* before adding them here.
*/
- { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
- 0xA000, 0x1000,
- 0, 0, pbn_b0_1_115200 },
-
- /* the 9901 is a rebranded 9912 */
- { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
- 0xA000, 0x1000,
- 0, 0, pbn_b0_1_115200 },
-
- { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
- 0xA000, 0x1000,
- 0, 0, pbn_b0_1_115200 },
-
- { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
- 0xA000, 0x1000,
- 0, 0, pbn_b0_1_115200 },
-
- { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
- 0xA000, 0x1000,
- 0, 0, pbn_b0_1_115200 },
-
- { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
- 0xA000, 0x3002,
- 0, 0, pbn_NETMOS9900_2s_115200 },
-
- { PCIE_VENDOR_ID_ASIX, PCIE_DEVICE_ID_AX99100,
- 0xA000, 0x1000,
- 0, 0, pbn_b0_1_115200 },
+ {
+ PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9901,
+ 0xA000, 0x1000),
+ .driver_data = pbn_b0_1_115200,
+ }, {
+ /* the 9901 is a rebranded 9912 */
+ PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9912,
+ 0xA000, 0x1000),
+ .driver_data = pbn_b0_1_115200,
+ }, {
+ PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9922,
+ 0xA000, 0x1000),
+ .driver_data = pbn_b0_1_115200,
+ }, {
+ PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9904,
+ 0xA000, 0x1000),
+ .driver_data = pbn_b0_1_115200,
+ }, {
+ PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9900,
+ 0xA000, 0x1000),
+ .driver_data = pbn_b0_1_115200,
+ }, {
+ PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9900,
+ 0xA000, 0x3002),
+ .driver_data = pbn_NETMOS9900_2s_115200,
+ }, {
+ PCI_DEVICE_SUB(PCIE_VENDOR_ID_ASIX, PCIE_DEVICE_ID_AX99100,
+ 0xA000, 0x1000),
+ .driver_data = pbn_b0_1_115200,
+ },
/*
* Best Connectivity and Rosewill PCI Multi I/O cards
*/
- { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
- 0xA000, 0x1000,
- 0, 0, pbn_b0_1_115200 },
-
- { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
- 0xA000, 0x3002,
- 0, 0, pbn_b0_bt_2_115200 },
-
- { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
- 0xA000, 0x3004,
- 0, 0, pbn_b0_bt_4_115200 },
+ {
+ PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9865,
+ 0xA000, 0x1000),
+ .driver_data = pbn_b0_1_115200,
+ }, {
+ PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9865,
+ 0xA000, 0x3002),
+ .driver_data = pbn_b0_bt_2_115200,
+ }, {
+ PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9865,
+ 0xA000, 0x3004),
+ .driver_data = pbn_b0_bt_4_115200,
+ },
/*
* ASIX AX99100 PCIe to Multi I/O Controller
*/
- { PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
- 0xA000, 0x1000,
- 0, 0, pbn_b0_1_115200 },
+ {
+ PCI_VDEVICE_SUB(ASIX, PCI_DEVICE_ID_ASIX_AX99100,
+ 0xA000, 0x1000),
+ .driver_data = pbn_b0_1_115200,
+ },
/* Intel CE4100 */
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_ce4100_1_115200 },
+ {
+ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART),
+ .driver_data = pbn_ce4100_1_115200,
+ },
/*
* Cronyx Omega PCI
*/
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_omegapci },
+ {
+ PCI_VDEVICE(PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA),
+ .driver_data = pbn_omegapci,
+ },
/*
* Broadcom TruManage
*/
- { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
- pbn_brcm_trumanage },
+ {
+ PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE),
+ .driver_data = pbn_brcm_trumanage,
+ },
/*
* AgeStar as-prs2-009
*/
- { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0, pbn_b0_bt_2_115200 },
+ {
+ PCI_VDEVICE(AGESTAR, PCI_DEVICE_ID_AGESTAR_9375),
+ .driver_data = pbn_b0_bt_2_115200,
+ },
/*
* WCH CH353 series devices: The 2S1P is handled by parport_serial
* so not listed here.
*/
- { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_4S,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0, pbn_b0_bt_4_115200 },
+ {
+ PCI_VDEVICE(WCHCN, PCI_DEVICE_ID_WCHCN_CH353_4S),
+ .driver_data = pbn_b0_bt_4_115200,
+ }, {
+ PCI_VDEVICE(WCHCN, PCI_DEVICE_ID_WCHCN_CH353_2S1PF),
+ .driver_data = pbn_b0_bt_2_115200,
+ }, {
+ PCI_VDEVICE(WCHCN, PCI_DEVICE_ID_WCHCN_CH355_4S),
+ .driver_data = pbn_b0_bt_4_115200,
+ }, {
+ PCI_VDEVICE(WCHIC, PCI_DEVICE_ID_WCHIC_CH382_2S),
+ .driver_data = pbn_wch382_2,
+ }, {
+ PCI_VDEVICE(WCHIC, PCI_DEVICE_ID_WCHIC_CH384_4S),
+ .driver_data = pbn_wch384_4,
+ }, {
+ PCI_VDEVICE(WCHIC, PCI_DEVICE_ID_WCHIC_CH384_8S),
+ .driver_data = pbn_wch384_8,
+ },
- { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_2S1PF,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0, pbn_b0_bt_2_115200 },
-
- { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH355_4S,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0, pbn_b0_bt_4_115200 },
-
- { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH382_2S,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0, pbn_wch382_2 },
-
- { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_4S,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0, pbn_wch384_4 },
-
- { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_8S,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0, pbn_wch384_8 },
/*
* Realtek RealManage
*/
- { PCI_VENDOR_ID_REALTEK, 0x816a,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0, pbn_b0_1_115200 },
-
- { PCI_VENDOR_ID_REALTEK, 0x816b,
- PCI_ANY_ID, PCI_ANY_ID,
- 0, 0, pbn_b0_1_115200 },
+ {
+ PCI_VDEVICE(REALTEK, 0x816a),
+ .driver_data = pbn_b0_1_115200,
+ }, {
+ PCI_VDEVICE(REALTEK, 0x816b),
+ .driver_data = pbn_b0_1_115200,
+ },
/* Systembase Multi I/O cards */
- { PCI_VDEVICE(SYSTEMBASE, 0x0008), pbn_b0_8_921600 },
+ {
+ PCI_VDEVICE(SYSTEMBASE, 0x0008),
+ .driver_data = pbn_b0_8_921600,
+ },
/* Fintek PCI serial cards */
- { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
- { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
- { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
- { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
- { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
- { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
+ {
+ PCI_DEVICE(0x1c29, 0x1104),
+ .driver_data = pbn_fintek_4,
+ }, {
+ PCI_DEVICE(0x1c29, 0x1108),
+ .driver_data = pbn_fintek_8,
+ }, {
+ PCI_DEVICE(0x1c29, 0x1112),
+ .driver_data = pbn_fintek_12,
+ }, {
+ PCI_DEVICE(0x1c29, 0x1204),
+ .driver_data = pbn_fintek_F81504A,
+ }, {
+ PCI_DEVICE(0x1c29, 0x1208),
+ .driver_data = pbn_fintek_F81508A,
+ }, {
+ PCI_DEVICE(0x1c29, 0x1212),
+ .driver_data = pbn_fintek_F81512A,
+ },
/* MKS Tenta SCOM-080x serial cards */
- { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
- { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
+ {
+ PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000,
+ }, {
+ PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000,
+ },
/* Amazon PCI serial device */
- { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
+ {
+ PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200,
+ },
/*
* These entries match devices with class COMMUNICATION_SERIAL,
* COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
*/
- { PCI_ANY_ID, PCI_ANY_ID,
- PCI_ANY_ID, PCI_ANY_ID,
- PCI_CLASS_COMMUNICATION_SERIAL << 8,
- 0xffff00, pbn_default },
- { PCI_ANY_ID, PCI_ANY_ID,
- PCI_ANY_ID, PCI_ANY_ID,
- PCI_CLASS_COMMUNICATION_MODEM << 8,
- 0xffff00, pbn_default },
- { PCI_ANY_ID, PCI_ANY_ID,
- PCI_ANY_ID, PCI_ANY_ID,
- PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
- 0xffff00, pbn_default },
- { 0, }
+ {
+ PCI_DEVICE_CLASS(PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00),
+ .driver_data = pbn_default,
+ }, {
+ PCI_DEVICE_CLASS(PCI_CLASS_COMMUNICATION_MODEM << 8, 0xffff00),
+ .driver_data = pbn_default,
+ }, {
+ PCI_DEVICE_CLASS(PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00),
+ .driver_data = pbn_default,
+ },
+ { }
};
static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
base-commit: 254f49634ee16a731174d2ae34bc50bd5f45e731
prerequisite-patch-id: a31e1d7b9e6310e9c453afcd2037468686cb552c
prerequisite-patch-id: 7779c63f16ef6f7247cdb71c89e66b27e299eb74
prerequisite-patch-id: 6f920b6f8c31dc0ad1689200c37680755c20ce8b
prerequisite-patch-id: d0d54f7acecd560cdeb6ea0c0e5ae77a50695d68
prerequisite-patch-id: 1fd68e883664147052540eea19769ea9e92d0138
prerequisite-patch-id: fff07090df18a39a361bbb091a3f17223b4606b4
--
2.47.3
^ permalink raw reply related
* [PATCH v2 14/15] serial: max3100: use new UPIO_BUS as iotype
From: Hugo Villeneuve @ 2026-04-28 17:54 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: hugo, ilpo.jarvinen, linux-kernel, linux-serial, Hugo Villeneuve
In-Reply-To: <20260428-tty-upio-v2-0-01c1857cf761@dimonoff.com>
From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Now that we have a new UPIO_BUS I/O type, use it to register our serial
port. This allows the driver to work properly when using DT where
membase/iobase are not set.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
drivers/tty/serial/max3100.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/tty/serial/max3100.c b/drivers/tty/serial/max3100.c
index 475b0a6efce4bec36aa4b94ccff83934dbdf9246..17a2ff410305142798ddbbb22b46f18eadce91aa 100644
--- a/drivers/tty/serial/max3100.c
+++ b/drivers/tty/serial/max3100.c
@@ -725,6 +725,7 @@ static int max3100_probe(struct spi_device *spi)
max3100s[i]->port.ops = &max3100_ops;
max3100s[i]->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
max3100s[i]->port.line = i;
+ max3100s[i]->port.iotype = UPIO_BUS;
max3100s[i]->port.type = PORT_MAX3100;
max3100s[i]->port.dev = &spi->dev;
--
2.47.3
^ permalink raw reply related
* [PATCH v2 00/15] serial: add new I/O type for SPI and I2C bus devices
From: Hugo Villeneuve @ 2026-04-28 17:53 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: hugo, ilpo.jarvinen, linux-kernel, linux-serial, Hugo Villeneuve
Hello,
this patch series add a new I/O type for serial devices on a SPI/I2C bus,
and a few related cleanups/improvements.
These changes are based on a suggestion [1] made by Ilpo Järvinen during
past sc16is7xx driver patches review.
The first patches make use of uart_iotype_*() functions to simplify and
cleanup the UART report functions.
This cleanup sets the stage to avoid displaying irrelevant MMIO or legacy
I/O information for serial devices on I2C or SPI busses when we add the new
UPIO_BUS type.
The patch "serial: uniformize serial port I/O infos display" is more of an
RFC as an attempt to uniformize the display of I/O informations. If deemed
usefull/appropriate, it can be reworked and integrasted with previous
patches.
Tested on a imx6 board with two SC16is752 using SPI mode, and a dummy
device-tree entry for a MAX3100:
dmesg -t | grep "base_baud"
2020000.serial: ttymxc0 at MMIO 0x2020000 (irq = 197, base_baud = 5000000) is a IMX
21e8000.serial: ttymxc1 at MMIO 0x21e8000 (irq = 198, base_baud = 5000000) is a IMX
spi1.0: ttySC0 (irq = 165, base_baud = 1500000) is a SC16IS752
spi1.0: ttySC1 (irq = 165, base_baud = 1500000) is a SC16IS752
spi3.0: ttySC2 (irq = 37, base_baud = 1500000) is a SC16IS752
spi3.0: ttySC3 (irq = 37, base_baud = 1500000) is a SC16IS752
spi3.1: ttyMAX0 (irq = 0, base_baud = 0) is a MAX3100
Note that before these patches, max3100 silently failed in uart_configure_port()
because membase/iobase/mapbase were zero.
For max310x and SC16is7xx in i2c mode, tested only that driver is properly
registered by using i2c-stub.
Also tested on a custom board with a Renesas RZ/G2L cpu (sh-sci driver) to
confirm there is no regression (also with earlycon):
dmesg -t | grep "MMIO"
earlycon: scif0 at MMIO 0x000000001004b800 (options '115200n8')
1004b800.serial: ttySC0 at MMIO 0x000000001004b800 (irq = 35, base_baud = 0) is a scif
1004bc00.serial: ttySC1 at MMIO 0x000000001004bc00 (irq = 40, base_baud = 0) is a scif
Maybe some of the patches could be merged together, but for now I decided
to keep them separate to help the review process.
Thank you.
[1] https://lore.kernel.org/lkml/2936e18f-44ea-faed-9fa0-2ddefe7c3194@linux.intel.com/raw
Link: [v1] https://lore.kernel.org/all/20260423-tty-upio-v1-0-baf82d3b86d1@dimonoff.com/
Changes for v2:
- Replace snprintf with scnprintf (Ilpo)
- Fix alignment of : to ? (Ilpo)
- Move hub6 match port to 8250_hub6.c (Ilpo)
- earlycon: use uart_iotype_*()
- 8250_rsa: use uart_iotype_*()
- 8250_port: use uart_iotype_*() in serial_port_out_sync()
- simplified uart_line_info() even more and remove intermediate mmio
variable
- Split and rename patch serial: core: prevent irrelevant I/O infos display
for UPIO_BUS to serial: core: use uart_iotype_*() to simplify
uart_report_port() and moved before UPIO_BUS patch.
- Add a new patch to implement a function to uniformize the display
of I/O infos for uart_report_port(), uart_line_info() and
earlycon_print_info(). If accepted could be better integrated/merged with
the next series submission. If not, can simply be dropped.
- Add patch for uart_regiowidth_to_iotype()
---
Hugo Villeneuve (15):
serial: 8250_hub6: add hub6_match_port()
serial: core: add uart_iotype_mmio/legacy_io helper functions
serial: core: use uart_iotype_*() to simplify uart_match_port()
serial: core: use uart_iotype_*() to simplify uart_line_info()
serial: core: replace snprintf with more robust scnprintf
serial: core: fix indentation/alignment
serial: core: use uart_iotype_*() to simplify uart_report_port()
serial: earlycon: use uart_iotype_*() to simplify code
serial: 8250: use uart_iotype_*() to simplify code
serial: 8250_rsa: use uart_iotype_*() to simplify code
serial: core: add new I/O type for SPI and I2C bus devices
serial: sc16is7xx: use new UPIO_BUS as iotype
serial: max310x: use new UPIO_BUS as iotype
serial: max3100: use new UPIO_BUS as iotype
serial: uniformize serial port I/O infos display
drivers/tty/serial/8250/8250.h | 7 ++
drivers/tty/serial/8250/8250_hub6.c | 6 ++
drivers/tty/serial/8250/8250_port.c | 43 ++---------
drivers/tty/serial/8250/8250_rsa.c | 40 +++++------
drivers/tty/serial/earlycon.c | 17 ++---
drivers/tty/serial/max3100.c | 1 +
drivers/tty/serial/max310x.c | 9 +--
drivers/tty/serial/sc16is7xx.c | 9 +--
drivers/tty/serial/serial_core.c | 137 ++++++++++++++++++++++--------------
include/linux/serial_core.h | 6 ++
include/uapi/linux/serial.h | 1 +
11 files changed, 137 insertions(+), 139 deletions(-)
---
base-commit: 254f49634ee16a731174d2ae34bc50bd5f45e731
change-id: 20260428-tty-upio-93a350a4d69a
Best regards,
--
Hugo Villeneuve <hvilleneuve@dimonoff.com>
^ permalink raw reply
* [PATCH v2 05/15] serial: core: replace snprintf with more robust scnprintf
From: Hugo Villeneuve @ 2026-04-28 17:53 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: hugo, ilpo.jarvinen, linux-kernel, linux-serial, Hugo Villeneuve
In-Reply-To: <20260428-tty-upio-v2-0-01c1857cf761@dimonoff.com>
From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Use scnprintf() so we could perhaps one day get rid of snprintf() entirely.
Suggested-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
drivers/tty/serial/serial_core.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index c5ef2dd00a9c9ad57c4010c05daea34fd2053676..3c909b8a82135a6245e98a9ae6bb050fc32590cc 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -2487,11 +2487,11 @@ uart_report_port(struct uart_driver *drv, struct uart_port *port)
switch (port->iotype) {
case UPIO_PORT:
- snprintf(address, sizeof(address), "I/O 0x%lx", port->iobase);
+ scnprintf(address, sizeof(address), "I/O 0x%lx", port->iobase);
break;
case UPIO_HUB6:
- snprintf(address, sizeof(address),
- "I/O 0x%lx offset 0x%x", port->iobase, port->hub6);
+ scnprintf(address, sizeof(address),
+ "I/O 0x%lx offset 0x%x", port->iobase, port->hub6);
break;
case UPIO_MEM:
case UPIO_MEM16:
@@ -2499,8 +2499,8 @@ uart_report_port(struct uart_driver *drv, struct uart_port *port)
case UPIO_MEM32BE:
case UPIO_AU:
case UPIO_TSI:
- snprintf(address, sizeof(address),
- "MMIO 0x%llx", (unsigned long long)port->mapbase);
+ scnprintf(address, sizeof(address),
+ "MMIO 0x%llx", (unsigned long long)port->mapbase);
break;
default:
strscpy(address, "*unknown*", sizeof(address));
--
2.47.3
^ permalink raw reply related
* [PATCH v2 04/15] serial: core: use uart_iotype_*() to simplify uart_line_info()
From: Hugo Villeneuve @ 2026-04-28 17:53 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: hugo, ilpo.jarvinen, linux-kernel, linux-serial, Hugo Villeneuve
In-Reply-To: <20260428-tty-upio-v2-0-01c1857cf761@dimonoff.com>
From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Make use of new functions uart_iotype_mmio() and uart_iotype_legacy_io()
to simplify and improve code readability. This will prevent displaying
irrelevant information for future IO types (ex: UPIO_BUS), while also
addressing the (eventually) invalid check for "iotype >= UPIO_MEM".
This also allows us to remove the confusing cast to (unsigned long long)
for iobase which is defined as an unsigned long, and use %pa to display the
mapbase pointer, as it is done in earlycon_print_info().
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
On 32-bit cpu:
no changes.
On 64-bit cpu:
# cat /proc/tty/driver/sci
before
serinfo:1.0 driver revision:
0: uart:scif mmio:0x1004B800 irq:35 tx:11192 rx:37 RTS|CTS|DTR|DSR|CD
after:
serinfo:1.0 driver revision:
0: uart:scif mmio:0x000000001004b800 irq:35 tx:11339 rx:35 RTS|CTS|DTR|DSR|CD
---
drivers/tty/serial/serial_core.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index 06a774f93652d65bc8e0f1ed912aa3e5c95e2bfa..c5ef2dd00a9c9ad57c4010c05daea34fd2053676 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -2004,7 +2004,6 @@ static void uart_line_info(struct seq_file *m, struct uart_state *state)
struct uart_port *uport;
char stat_buf[32];
unsigned int status;
- int mmio;
guard(mutex)(&port->mutex);
@@ -2012,13 +2011,14 @@ static void uart_line_info(struct seq_file *m, struct uart_state *state)
if (!uport)
return;
- mmio = uport->iotype >= UPIO_MEM;
- seq_printf(m, "%u: uart:%s %s%08llX irq:%u",
- uport->line, uart_type(uport),
- mmio ? "mmio:0x" : "port:",
- mmio ? (unsigned long long)uport->mapbase
- : (unsigned long long)uport->iobase,
- uport->irq);
+ seq_printf(m, "%u: uart:%s", uport->line, uart_type(uport));
+
+ if (uart_iotype_mmio(uport->iotype))
+ seq_printf(m, " mmio:%pa", &uport->mapbase);
+ else if (uart_iotype_legacy_io(uport->iotype))
+ seq_printf(m, " port:%08lX", uport->iobase);
+
+ seq_printf(m, " irq:%u", uport->irq);
if (uport->type == PORT_UNKNOWN) {
seq_putc(m, '\n');
--
2.47.3
^ permalink raw reply related
* [PATCH v2 15/15] serial: uniformize serial port I/O infos display
From: Hugo Villeneuve @ 2026-04-28 17:54 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: hugo, ilpo.jarvinen, linux-kernel, linux-serial, Hugo Villeneuve
In-Reply-To: <20260428-tty-upio-v2-0-01c1857cf761@dimonoff.com>
From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Uniformize serial port I/O infos display from three different functions
that display mostly the same information, but with some variations, by
adding a common function.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
Maybe the width information could be dropped entirely?
---
drivers/tty/serial/earlycon.c | 13 +++-------
drivers/tty/serial/serial_core.c | 52 +++++++++++++++++++++++++++-------------
include/linux/serial_core.h | 1 +
3 files changed, 40 insertions(+), 26 deletions(-)
diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c
index e799feaa14bf1ac7c1a5677cd84490e7c486449b..ce740cdc7cebffca0b4f6be98b8bca66540af72d 100644
--- a/drivers/tty/serial/earlycon.c
+++ b/drivers/tty/serial/earlycon.c
@@ -75,19 +75,12 @@ static void __init earlycon_print_info(struct earlycon_device *device)
{
struct console *earlycon = device->con;
struct uart_port *port = &device->port;
- char address[64] = "";
+ char ioinfos[64];
- if (uart_iotype_mmio(port->iotype))
- scnprintf(address, sizeof(address), " at MMIO%s %pa",
- (port->iotype == UPIO_MEM) ? "" :
- (port->iotype == UPIO_MEM16) ? "16" :
- (port->iotype == UPIO_MEM32) ? "32" : "32be",
- &port->mapbase);
- else if (uart_iotype_legacy_io(port->iotype))
- scnprintf(address, sizeof(address), " at I/O port 0x%lx", port->iobase);
+ uart_get_ioinfos(port, ioinfos, sizeof(ioinfos));
pr_info("%s%d%s (options '%s')\n", earlycon->name, earlycon->index,
- address, device->options);
+ ioinfos, device->options);
}
static int __init parse_options(struct earlycon_device *device, char *options)
diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index 0e015477848504e37afb34c8088957083f1662c7..b9a9225d99b616a7f691a8f990fd77ab02609012 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -2002,6 +2002,7 @@ static void uart_line_info(struct seq_file *m, struct uart_state *state)
struct tty_port *port = &state->port;
enum uart_pm_state pm_state;
struct uart_port *uport;
+ char ioinfos[64];
char stat_buf[32];
unsigned int status;
@@ -2013,10 +2014,8 @@ static void uart_line_info(struct seq_file *m, struct uart_state *state)
seq_printf(m, "%u: uart:%s", uport->line, uart_type(uport));
- if (uart_iotype_mmio(uport->iotype))
- seq_printf(m, " mmio:%pa", &uport->mapbase);
- else if (uart_iotype_legacy_io(uport->iotype))
- seq_printf(m, " port:%08lX", uport->iobase);
+ uart_get_ioinfos(uport, ioinfos, sizeof(ioinfos));
+ seq_printf(m, "%s", ioinfos);
seq_printf(m, " irq:%u", uport->irq);
@@ -2480,26 +2479,47 @@ int uart_resume_port(struct uart_driver *drv, struct uart_port *uport)
}
EXPORT_SYMBOL(uart_resume_port);
+static const char *uart_get_mmio_width(struct uart_port *port)
+{
+ switch (port->iotype) {
+ case UPIO_MEM16:
+ return "16";
+ case UPIO_MEM32:
+ case UPIO_MEM32BE:
+ return "32be";
+ case UPIO_AU:
+ case UPIO_MEM:
+ default:
+ return "";
+ }
+}
+
+void uart_get_ioinfos(struct uart_port *port, char *buf, size_t size)
+{
+ buf[0] = '\0';
+
+ if (uart_iotype_mmio(port->iotype)) {
+ scnprintf(buf, size, " MMIO%s:%pa", uart_get_mmio_width(port), &port->mapbase);
+ } else if (uart_iotype_legacy_io(port->iotype)) {
+ if (port->iotype == UPIO_PORT)
+ scnprintf(buf, size, " I/O:0x%lx", port->iobase);
+ else if (port->iotype == UPIO_HUB6)
+ scnprintf(buf, size, " I/O:0x%lx, offset 0x%x", port->iobase, port->hub6);
+ }
+}
+EXPORT_SYMBOL(uart_get_ioinfos);
+
static inline void
uart_report_port(struct uart_driver *drv, struct uart_port *port)
{
- char address[64] = "";
+ char ioinfos[64];
- if (uart_iotype_mmio(port->iotype))
- scnprintf(address, sizeof(address), " at MMIO %pa", &port->mapbase);
- else if (uart_iotype_legacy_io(port->iotype)) {
- if (port->iotype == UPIO_PORT)
- scnprintf(address, sizeof(address), " at I/O 0x%lx", port->iobase);
- else if (port->iotype == UPIO_HUB6)
- scnprintf(address, sizeof(address), " at I/O 0x%lx offset 0x%x",
- port->iobase, port->hub6);
- }
+ uart_get_ioinfos(port, ioinfos, sizeof(ioinfos));
pr_info("%s%s%s%s (irq = %u, base_baud = %u) is a %s\n",
port->dev ? dev_name(port->dev) : "",
port->dev ? ": " : "",
- port->name,
- address, port->irq, port->uartclk / 16, uart_type(port));
+ port->name, ioinfos, port->irq, port->uartclk / 16, uart_type(port));
/* The magic multiplier feature is a bit obscure, so report it too. */
if (port->flags & UPF_MAGIC_MULTIPLIER)
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 626dd939c53c9f920d71aadd360ec0ea0bacce0d..1289e812b40f3d7b7a02ff1a87eaf649e71e0d2f 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -1308,6 +1308,7 @@ static inline int uart_handle_break(struct uart_port *port)
int uart_get_rs485_mode(struct uart_port *port);
+void uart_get_ioinfos(struct uart_port *port, char *buf, size_t size);
bool uart_iotype_mmio(enum uart_iotype iotype);
bool uart_iotype_legacy_io(enum uart_iotype iotype);
--
2.47.3
^ permalink raw reply related
* [PATCH v2 01/15] serial: 8250_hub6: add hub6_match_port()
From: Hugo Villeneuve @ 2026-04-28 17:53 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: hugo, ilpo.jarvinen, linux-kernel, linux-serial, Hugo Villeneuve
In-Reply-To: <20260428-tty-upio-v2-0-01c1857cf761@dimonoff.com>
From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Move the entire hub6 related match port check into its own function in
8250_hub6.c and add a stub for the case when hub6 code is not even built
into kernel.
Suggested-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
drivers/tty/serial/8250/8250.h | 7 +++++++
drivers/tty/serial/8250/8250_hub6.c | 6 ++++++
drivers/tty/serial/serial_core.c | 4 ++--
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h
index 77fe0588fd6bd5c5baac0fa03b7c466742aa9432..9d1068d0489dc4285b1d30489926bd676bcbe60e 100644
--- a/drivers/tty/serial/8250/8250.h
+++ b/drivers/tty/serial/8250/8250.h
@@ -334,6 +334,13 @@ int fintek_8250_probe(struct uart_8250_port *uart);
static inline int fintek_8250_probe(struct uart_8250_port *uart) { return 0; }
#endif
+#ifdef CONFIG_SERIAL_8250_HUB6
+bool hub6_match_port(const struct uart_port *port1, const struct uart_port *port2);
+#else
+static inline bool hub6_match_port(const struct uart_port *port1, const struct uart_port *port2)
+{ return false; }
+#endif
+
#ifdef CONFIG_ARCH_OMAP1
#include <linux/soc/ti/omap1-soc.h>
static inline int is_omap1_8250(struct uart_8250_port *pt)
diff --git a/drivers/tty/serial/8250/8250_hub6.c b/drivers/tty/serial/8250/8250_hub6.c
index 273f59b9bca555e9fb035005d3df2089c5b0a039..eae32c924e29bcaf608d66988aca461b9a53dc91 100644
--- a/drivers/tty/serial/8250/8250_hub6.c
+++ b/drivers/tty/serial/8250/8250_hub6.c
@@ -41,6 +41,12 @@ static struct platform_device hub6_device = {
},
};
+bool hub6_match_port(const struct uart_port *port1, const struct uart_port *port2)
+{
+ return port1->iobase == port2->iobase && port1->hub6 == port2->hub6;
+}
+EXPORT_SYMBOL_GPL(hub6_match_port);
+
static int __init hub6_init(void)
{
return platform_device_register(&hub6_device);
diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index 89cebdd278410a5a97f3f5ee1b9c171715145067..7354f8af4853d34e5e819c2887f287970c653b69 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -33,6 +33,7 @@
#include <linux/uaccess.h>
#include "serial_base.h"
+#include "8250/8250.h" /* For hub6_match_port() */
/*
* This is used to lock changes in serial line configuration.
@@ -3198,8 +3199,7 @@ bool uart_match_port(const struct uart_port *port1,
case UPIO_PORT:
return port1->iobase == port2->iobase;
case UPIO_HUB6:
- return port1->iobase == port2->iobase &&
- port1->hub6 == port2->hub6;
+ return hub6_match_port(port1, port2);
case UPIO_MEM:
case UPIO_MEM16:
case UPIO_MEM32:
--
2.47.3
^ permalink raw reply related
* [PATCH v2 03/15] serial: core: use uart_iotype_*() to simplify uart_match_port()
From: Hugo Villeneuve @ 2026-04-28 17:53 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: hugo, ilpo.jarvinen, linux-kernel, linux-serial, Hugo Villeneuve
In-Reply-To: <20260428-tty-upio-v2-0-01c1857cf761@dimonoff.com>
From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Make use of new functions uart_iotype_mmio() and uart_iotype_legacy_io()
to simplify and improve code readability.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
drivers/tty/serial/serial_core.c | 16 ++++------------
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index c177054f9515e1cb5a1e557c0dac096cb1cbd8cf..06a774f93652d65bc8e0f1ed912aa3e5c95e2bfa 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -3222,22 +3222,14 @@ bool uart_match_port(const struct uart_port *port1,
{
if (port1->iotype != port2->iotype)
return false;
-
- switch (port1->iotype) {
- case UPIO_PORT:
+ else if (port1->iotype == UPIO_PORT)
return port1->iobase == port2->iobase;
- case UPIO_HUB6:
+ else if (port1->iotype == UPIO_HUB6)
return hub6_match_port(port1, port2);
- case UPIO_MEM:
- case UPIO_MEM16:
- case UPIO_MEM32:
- case UPIO_MEM32BE:
- case UPIO_AU:
- case UPIO_TSI:
+ else if (uart_iotype_mmio(port1->iotype))
return port1->mapbase == port2->mapbase;
- default:
+ else
return false;
- }
}
EXPORT_SYMBOL(uart_match_port);
--
2.47.3
^ permalink raw reply related
* [PATCH v2 02/15] serial: core: add uart_iotype_mmio/legacy_io helper functions
From: Hugo Villeneuve @ 2026-04-28 17:53 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: hugo, ilpo.jarvinen, linux-kernel, linux-serial, Hugo Villeneuve
In-Reply-To: <20260428-tty-upio-v2-0-01c1857cf761@dimonoff.com>
From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
To help simplify code that check on the io type mode of the port.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
Will also be used by future commit that add UPIO_BUS.
---
drivers/tty/serial/serial_core.c | 28 ++++++++++++++++++++++++++++
include/linux/serial_core.h | 4 ++++
2 files changed, 32 insertions(+)
diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index 7354f8af4853d34e5e819c2887f287970c653b69..c177054f9515e1cb5a1e557c0dac096cb1cbd8cf 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -1967,6 +1967,34 @@ static const char *uart_type(struct uart_port *port)
return str;
}
+bool uart_iotype_mmio(enum uart_iotype iotype)
+{
+ switch (iotype) {
+ case UPIO_MEM:
+ case UPIO_MEM32:
+ case UPIO_AU:
+ case UPIO_TSI:
+ case UPIO_MEM32BE:
+ case UPIO_MEM16:
+ return true;
+ default:
+ return false;
+ }
+}
+EXPORT_SYMBOL_GPL(uart_iotype_mmio);
+
+bool uart_iotype_legacy_io(enum uart_iotype iotype)
+{
+ switch (iotype) {
+ case UPIO_PORT:
+ case UPIO_HUB6:
+ return true;
+ default:
+ return false;
+ }
+}
+EXPORT_SYMBOL_GPL(uart_iotype_legacy_io);
+
#ifdef CONFIG_PROC_FS
static void uart_line_info(struct seq_file *m, struct uart_state *state)
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 666430b4789977ae19641442b369eb1c773233f4..fc3f5ebe389658c197ffc105ce4ac11cacef59bb 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -1306,4 +1306,8 @@ static inline int uart_handle_break(struct uart_port *port)
!((cflag) & CLOCAL))
int uart_get_rs485_mode(struct uart_port *port);
+
+bool uart_iotype_mmio(enum uart_iotype iotype);
+bool uart_iotype_legacy_io(enum uart_iotype iotype);
+
#endif /* LINUX_SERIAL_CORE_H */
--
2.47.3
^ permalink raw reply related
* [PATCH v2 06/15] serial: core: fix indentation/alignment
From: Hugo Villeneuve @ 2026-04-28 17:53 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: hugo, ilpo.jarvinen, linux-kernel, linux-serial, Hugo Villeneuve
In-Reply-To: <20260428-tty-upio-v2-0-01c1857cf761@dimonoff.com>
From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Fixes the following checkpatch warnings:
CHECK: Alignment should match open parenthesis
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
Without this, the next patch will have a checkpatch warning.
---
drivers/tty/serial/serial_core.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index 3c909b8a82135a6245e98a9ae6bb050fc32590cc..e9986f9221f946c9075a8eea7ac28d2ad818f095 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -2508,10 +2508,10 @@ uart_report_port(struct uart_driver *drv, struct uart_port *port)
}
pr_info("%s%s%s at %s (irq = %u, base_baud = %u) is a %s\n",
- port->dev ? dev_name(port->dev) : "",
- port->dev ? ": " : "",
- port->name,
- address, port->irq, port->uartclk / 16, uart_type(port));
+ port->dev ? dev_name(port->dev) : "",
+ port->dev ? ": " : "",
+ port->name,
+ address, port->irq, port->uartclk / 16, uart_type(port));
/* The magic multiplier feature is a bit obscure, so report it too. */
if (port->flags & UPF_MAGIC_MULTIPLIER)
--
2.47.3
^ permalink raw reply related
* [PATCH v2 09/15] serial: 8250: use uart_iotype_*() to simplify code
From: Hugo Villeneuve @ 2026-04-28 17:53 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: hugo, ilpo.jarvinen, linux-kernel, linux-serial, Hugo Villeneuve
In-Reply-To: <20260428-tty-upio-v2-0-01c1857cf761@dimonoff.com>
From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Make use of new functions uart_iotype_mmio() and uart_iotype_legacy_io()
to simplify and improve code readability.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
drivers/tty/serial/8250/8250_port.c | 43 ++++++-------------------------------
1 file changed, 7 insertions(+), 36 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
index af78cc02f38e719573becd0aea226f7790555a3e..20b7de120b1bab596de22d09fdeff8361afd8b17 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -472,16 +472,10 @@ static void set_io_from_upio(struct uart_port *p)
static void
serial_port_out_sync(struct uart_port *p, int offset, int value)
{
- switch (p->iotype) {
- case UPIO_MEM:
- case UPIO_MEM16:
- case UPIO_MEM32:
- case UPIO_MEM32BE:
- case UPIO_AU:
+ if (uart_iotype_mmio(p->iotype)) {
p->serial_out(p, offset, value);
p->serial_in(p, UART_LCR); /* safe, no side-effects */
- break;
- default:
+ } else {
p->serial_out(p, offset, value);
}
}
@@ -2863,13 +2857,7 @@ static int serial8250_request_std_resource(struct uart_8250_port *up)
unsigned int size = serial8250_port_size(up);
struct uart_port *port = &up->port;
- switch (port->iotype) {
- case UPIO_AU:
- case UPIO_TSI:
- case UPIO_MEM32:
- case UPIO_MEM32BE:
- case UPIO_MEM16:
- case UPIO_MEM:
+ if (uart_iotype_mmio(port->iotype)) {
if (!port->mapbase)
return -EINVAL;
@@ -2883,14 +2871,9 @@ static int serial8250_request_std_resource(struct uart_8250_port *up)
return -ENOMEM;
}
}
- return 0;
- case UPIO_HUB6:
- case UPIO_PORT:
+ } else if (uart_iotype_legacy_io(port->iotype)) {
if (!request_region(port->iobase, size, "serial"))
return -EBUSY;
- return 0;
- case UPIO_UNKNOWN:
- break;
}
return 0;
@@ -2901,15 +2884,9 @@ static void serial8250_release_std_resource(struct uart_8250_port *up)
unsigned int size = serial8250_port_size(up);
struct uart_port *port = &up->port;
- switch (port->iotype) {
- case UPIO_AU:
- case UPIO_TSI:
- case UPIO_MEM32:
- case UPIO_MEM32BE:
- case UPIO_MEM16:
- case UPIO_MEM:
+ if (uart_iotype_mmio(port->iotype)) {
if (!port->mapbase)
- break;
+ return;
if (port->flags & UPF_IOREMAP) {
iounmap(port->membase);
@@ -2917,14 +2894,8 @@ static void serial8250_release_std_resource(struct uart_8250_port *up)
}
release_mem_region(port->mapbase, size);
- break;
-
- case UPIO_HUB6:
- case UPIO_PORT:
+ } else if (uart_iotype_legacy_io(port->iotype)) {
release_region(port->iobase, size);
- break;
- case UPIO_UNKNOWN:
- break;
}
}
--
2.47.3
^ permalink raw reply related
* [PATCH v2 07/15] serial: core: use uart_iotype_*() to simplify uart_report_port()
From: Hugo Villeneuve @ 2026-04-28 17:53 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: hugo, ilpo.jarvinen, linux-kernel, linux-serial, Hugo Villeneuve
In-Reply-To: <20260428-tty-upio-v2-0-01c1857cf761@dimonoff.com>
From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Make use of new functions uart_iotype_mmio() and uart_iotype_legacy_io()
to simplify and improve code readability. It will also prevent displaying
irrelevant I/O information for future IO types (ex: UPIO_BUS). Use %pa to
display the mapbase pointer, as it is done in earlycon_print_info().
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
On 32-bit cpu:
no changes.
On 64-bit cpu:
before:
1004b800.serial: ttySC0 at MMIO 0x1004b800 (irq = 35, base_baud = 0) is a scif
1004bc00.serial: ttySC1 at MMIO 0x1004bc00 (irq = 40, base_baud = 0) is a scif
after:
1004b800.serial: ttySC0 at MMIO 0x000000001004b800 (irq = 35, base_baud = 0) is a scif
1004bc00.serial: ttySC1 at MMIO 0x000000001004bc00 (irq = 40, base_baud = 0) is a scif
---
drivers/tty/serial/serial_core.c | 32 ++++++++++----------------------
1 file changed, 10 insertions(+), 22 deletions(-)
diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index e9986f9221f946c9075a8eea7ac28d2ad818f095..d0d4dba41fb9ee43403391d9d599abc1d64b48ec 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -2483,31 +2483,19 @@ EXPORT_SYMBOL(uart_resume_port);
static inline void
uart_report_port(struct uart_driver *drv, struct uart_port *port)
{
- char address[64];
+ char address[64] = "";
- switch (port->iotype) {
- case UPIO_PORT:
- scnprintf(address, sizeof(address), "I/O 0x%lx", port->iobase);
- break;
- case UPIO_HUB6:
- scnprintf(address, sizeof(address),
- "I/O 0x%lx offset 0x%x", port->iobase, port->hub6);
- break;
- case UPIO_MEM:
- case UPIO_MEM16:
- case UPIO_MEM32:
- case UPIO_MEM32BE:
- case UPIO_AU:
- case UPIO_TSI:
- scnprintf(address, sizeof(address),
- "MMIO 0x%llx", (unsigned long long)port->mapbase);
- break;
- default:
- strscpy(address, "*unknown*", sizeof(address));
- break;
+ if (uart_iotype_mmio(port->iotype))
+ scnprintf(address, sizeof(address), " at MMIO %pa", &port->mapbase);
+ else if (uart_iotype_legacy_io(port->iotype)) {
+ if (port->iotype == UPIO_PORT)
+ scnprintf(address, sizeof(address), " at I/O 0x%lx", port->iobase);
+ else if (port->iotype == UPIO_HUB6)
+ scnprintf(address, sizeof(address), " at I/O 0x%lx offset 0x%x",
+ port->iobase, port->hub6);
}
- pr_info("%s%s%s at %s (irq = %u, base_baud = %u) is a %s\n",
+ pr_info("%s%s%s%s (irq = %u, base_baud = %u) is a %s\n",
port->dev ? dev_name(port->dev) : "",
port->dev ? ": " : "",
port->name,
--
2.47.3
^ permalink raw reply related
* [PATCH v2 08/15] serial: earlycon: use uart_iotype_*() to simplify code
From: Hugo Villeneuve @ 2026-04-28 17:53 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: hugo, ilpo.jarvinen, linux-kernel, linux-serial, Hugo Villeneuve
In-Reply-To: <20260428-tty-upio-v2-0-01c1857cf761@dimonoff.com>
From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Make use of new functions uart_iotype_mmio() and uart_iotype_legacy_io()
to simplify and improve code readability.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
Using uart_iotype_mmio() now includes the case for UPIO_TSI and UPIO_AU,
which fell before this patch in the else clause.
UPIO_TSI is no longer used by any driver, so not an issue.
UPIO_AU, if this is even possible for earlycon, falls into the "MMIO" category
in uart_line_info() and uart_report_port()...
---
drivers/tty/serial/earlycon.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c
index ab9af37f6cda35ea2e3ea966fdac8ba5c4475cb2..e799feaa14bf1ac7c1a5677cd84490e7c486449b 100644
--- a/drivers/tty/serial/earlycon.c
+++ b/drivers/tty/serial/earlycon.c
@@ -75,19 +75,19 @@ static void __init earlycon_print_info(struct earlycon_device *device)
{
struct console *earlycon = device->con;
struct uart_port *port = &device->port;
+ char address[64] = "";
- if (port->iotype == UPIO_MEM || port->iotype == UPIO_MEM16 ||
- port->iotype == UPIO_MEM32 || port->iotype == UPIO_MEM32BE)
- pr_info("%s%d at MMIO%s %pa (options '%s')\n",
- earlycon->name, earlycon->index,
- (port->iotype == UPIO_MEM) ? "" :
- (port->iotype == UPIO_MEM16) ? "16" :
- (port->iotype == UPIO_MEM32) ? "32" : "32be",
- &port->mapbase, device->options);
- else
- pr_info("%s%d at I/O port 0x%lx (options '%s')\n",
- earlycon->name, earlycon->index,
- port->iobase, device->options);
+ if (uart_iotype_mmio(port->iotype))
+ scnprintf(address, sizeof(address), " at MMIO%s %pa",
+ (port->iotype == UPIO_MEM) ? "" :
+ (port->iotype == UPIO_MEM16) ? "16" :
+ (port->iotype == UPIO_MEM32) ? "32" : "32be",
+ &port->mapbase);
+ else if (uart_iotype_legacy_io(port->iotype))
+ scnprintf(address, sizeof(address), " at I/O port 0x%lx", port->iobase);
+
+ pr_info("%s%d%s (options '%s')\n", earlycon->name, earlycon->index,
+ address, device->options);
}
static int __init parse_options(struct earlycon_device *device, char *options)
--
2.47.3
^ permalink raw reply related
* [PATCH v2 10/15] serial: 8250_rsa: use uart_iotype_*() to simplify code
From: Hugo Villeneuve @ 2026-04-28 17:53 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: hugo, ilpo.jarvinen, linux-kernel, linux-serial, Hugo Villeneuve
In-Reply-To: <20260428-tty-upio-v2-0-01c1857cf761@dimonoff.com>
From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Make use of new functions uart_iotype_mmio() and uart_iotype_legacy_io()
to simplify and improve code readability, as well as avoid some variables
init if the iotype is not valid.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
drivers/tty/serial/8250/8250_rsa.c | 40 ++++++++++++++++++--------------------
1 file changed, 19 insertions(+), 21 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_rsa.c b/drivers/tty/serial/8250/8250_rsa.c
index fff9395948e33be6b08355bace70275b7515b608..010ba5af81a08e737e0198d06d150bbe470e6688 100644
--- a/drivers/tty/serial/8250/8250_rsa.c
+++ b/drivers/tty/serial/8250/8250_rsa.c
@@ -19,35 +19,33 @@ static const struct uart_ops *core_port_base_ops;
static int rsa8250_request_resource(struct uart_8250_port *up)
{
struct uart_port *port = &up->port;
- unsigned long start = UART_RSA_BASE << port->regshift;
- unsigned int size = 8 << port->regshift;
+ unsigned long start;
+ unsigned int size;
- switch (port->iotype) {
- case UPIO_HUB6:
- case UPIO_PORT:
- start += port->iobase;
- if (!request_region(start, size, "serial-rsa"))
- return -EBUSY;
- return 0;
- default:
+ if (!uart_iotype_legacy_io(port->iotype))
return -EINVAL;
- }
+
+ start = UART_RSA_BASE << port->regshift;
+ start += port->iobase;
+ size = 8 << port->regshift;
+
+ if (!request_region(start, size, "serial-rsa"))
+ return -EBUSY;
+ return 0;
}
static void rsa8250_release_resource(struct uart_8250_port *up)
{
struct uart_port *port = &up->port;
- unsigned long offset = UART_RSA_BASE << port->regshift;
- unsigned int size = 8 << port->regshift;
+ unsigned long offset;
+ unsigned int size;
- switch (port->iotype) {
- case UPIO_HUB6:
- case UPIO_PORT:
- release_region(port->iobase + offset, size);
- break;
- default:
- break;
- }
+ if (!uart_iotype_legacy_io(port->iotype))
+ return;
+
+ offset = UART_RSA_BASE << port->regshift;
+ size = 8 << port->regshift;
+ release_region(port->iobase + offset, size);
}
static void univ8250_config_port(struct uart_port *port, int flags)
--
2.47.3
^ permalink raw reply related
* [PATCH v2 11/15] serial: core: add new I/O type for SPI and I2C bus devices
From: Hugo Villeneuve @ 2026-04-28 17:53 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: hugo, ilpo.jarvinen, linux-kernel, linux-serial, Hugo Villeneuve
In-Reply-To: <20260428-tty-upio-v2-0-01c1857cf761@dimonoff.com>
From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
I2C/SPI serial drivers don't use the following struct uart_port variables:
port->membase
port->mapbase
port->iobase
However, they are forced to set membase to a non-zero value so that
uart_configure_port() will succeed because of the following check:
/* If there isn't a port here, don't do anything further. */
if (!port->iobase && !port->mapbase && !port->membase)
return;
Add a new I/O type for SPI and I2C bus devices to remove the need to
implement the kind of above-mentioned ambiguous workarounds to make them
work. Now that UART report functions are using uart_iotype_*() functions,
no more irrelevant I/O information are being printed for UPIO_BUS iotypes.
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
With this change, uart_match_port() will always return true for UPIO_BUS
types, and this function is not used by any of the SPI/I2C drivers.
---
drivers/tty/serial/serial_core.c | 11 ++++++-----
include/linux/serial_core.h | 1 +
include/uapi/linux/serial.h | 1 +
3 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index d0d4dba41fb9ee43403391d9d599abc1d64b48ec..0e015477848504e37afb34c8088957083f1662c7 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -2516,11 +2516,10 @@ uart_configure_port(struct uart_driver *drv, struct uart_state *state,
{
unsigned int flags;
- /*
- * If there isn't a port here, don't do anything further.
- */
- if (!port->iobase && !port->mapbase && !port->membase)
- return;
+ /* If there isn't a port here, don't do anything further. */
+ if (uart_iotype_mmio(port->iotype) || uart_iotype_legacy_io(port->iotype))
+ if (!port->iobase && !port->mapbase && !port->membase)
+ return;
/*
* Now do the auto configuration stuff. Note that config_port
@@ -3216,6 +3215,8 @@ bool uart_match_port(const struct uart_port *port1,
return hub6_match_port(port1, port2);
else if (uart_iotype_mmio(port1->iotype))
return port1->mapbase == port2->mapbase;
+ else if (port1->iotype == UPIO_BUS)
+ return true;
else
return false;
}
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index fc3f5ebe389658c197ffc105ce4ac11cacef59bb..626dd939c53c9f920d71aadd360ec0ea0bacce0d 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -437,6 +437,7 @@ enum uart_iotype {
UPIO_TSI = SERIAL_IO_TSI, /* Tsi108/109 type IO */
UPIO_MEM32BE = SERIAL_IO_MEM32BE, /* 32b big endian */
UPIO_MEM16 = SERIAL_IO_MEM16, /* 16b little endian */
+ UPIO_BUS = SERIAL_IO_BUS, /* Serial bus I/O access (ex: SPI, I2C) */
};
struct uart_port {
diff --git a/include/uapi/linux/serial.h b/include/uapi/linux/serial.h
index de9b4733607e6b61b08ff7089ff90070168ff4a2..e6f61538fc2837a264d27942afaaf3f12e743445 100644
--- a/include/uapi/linux/serial.h
+++ b/include/uapi/linux/serial.h
@@ -72,6 +72,7 @@ struct serial_struct {
#define SERIAL_IO_TSI 5
#define SERIAL_IO_MEM32BE 6
#define SERIAL_IO_MEM16 7
+#define SERIAL_IO_BUS 8
#define UART_CLEAR_FIFO 0x01
#define UART_USE_FIFO 0x02
--
2.47.3
^ permalink raw reply related
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