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From: Cathy Zhang <cathy.zhang@intel.com>
To: linux-sgx@vger.kernel.org, x86@kernel.org
Cc: jarkko@kernel.org, reinette.chatre@intel.com,
	dave.hansen@intel.com, ashok.raj@intel.com,
	cathy.zhang@intel.com, chao.p.peng@linux.intel.com,
	yang.zhong@intel.com
Subject: [PATCH v5 8/9] x86/cpu: Call ENCLS[EUPDATESVN] procedure in microcode update
Date: Fri, 20 May 2022 18:39:03 +0800	[thread overview]
Message-ID: <20220520103904.1216-9-cathy.zhang@intel.com> (raw)
In-Reply-To: <20220520103904.1216-1-cathy.zhang@intel.com>

EUPDATESVN is the SGX instruction which allows enclave attestation
to include information about updated microcode without a reboot.

Microcode updates which affect SGX require two phases:

1. Do the main microcode update
2. Make the new CPUSVN available for enclave attestation via
   EUPDATESVN.

Before a EUPDATESVN can succeed, all enclave pages (EPC) must be
marked as unused in the SGX metadata (EPCM). This operation destroys
all preexisting SGX enclave data and metadata. This is by design and
mitigates the impact of vulnerabilities that may have compromised
enclaves or the SGX hardware itself prior to the update.

Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>

---
Changes since v4:
 - Remove #include <asm/sgx.h> from microcode.h which is not needed
   in this file. (Borislav Petkov)

Changes since v3:
 - Rename update_cpusvn_intel() as sgx_update_cpusvn_intel().
   (Dave Hansen)
 - Refine the comments when sgx_update_cpusvn_intel is called by
   microcode_check(). (Borislav Petkov, Dave Hansen)
 - Define both the 'static inline' stub *and* the declaration for
   sgx_update_cpusvn_intel() in sgx.h. (Dave Hansen)

Changes since v1:
 - Remove the sysfs file svnupdate. (Thomas Gleixner, Dave Hansen)
 - Let late microcode load path call ENCLS[EUPDATESVN] procedure
   directly. (Borislav Petkov)
 - Redefine update_cpusvn_intel() to return void instead of int.
---
 arch/x86/include/asm/sgx.h     |  6 ++++++
 arch/x86/kernel/cpu/common.c   | 10 ++++++++++
 arch/x86/kernel/cpu/sgx/main.c | 12 ++++++++++++
 3 files changed, 28 insertions(+)

diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h
index 74bcb6841a4b..1321670a6338 100644
--- a/arch/x86/include/asm/sgx.h
+++ b/arch/x86/include/asm/sgx.h
@@ -409,4 +409,10 @@ int sgx_virt_einit(void __user *sigstruct, void __user *token,
 int sgx_set_attribute(unsigned long *allowed_attributes,
 		      unsigned int attribute_fd);
 
+#ifdef CONFIG_X86_SGX
+extern void sgx_update_cpusvn_intel(void);
+#else
+static inline void sgx_update_cpusvn_intel(void) {}
+#endif
+
 #endif /* _ASM_X86_SGX_H */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index e342ae4db3c4..a50e0e183139 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -59,6 +59,7 @@
 #include <asm/cpu_device_id.h>
 #include <asm/uv/uv.h>
 #include <asm/sigframe.h>
+#include <asm/sgx.h>
 #include <asm/traps.h>
 
 #include "cpu.h"
@@ -2224,6 +2225,15 @@ void microcode_check(void)
 
 	perf_check_microcode();
 
+	/*
+	 * SGX attestation incorporates the microcode versions of all processors
+	 * on the system and is affected by microcode updates. So, update SGX
+	 * attestation metric (called CPUSVN) to ensure enclaves attest to the
+	 * new version after microcode update.
+	 */
+	if (IS_ENABLED(CONFIG_X86_SGX) && (cpuid_eax(SGX_CPUID) & SGX_CPUID_EUPDATESVN))
+		sgx_update_cpusvn_intel();
+
 	/* Reload CPUID max function as it might've changed. */
 	info.cpuid_level = cpuid_eax(0);
 
diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c
index 43dd2b34e040..0f541d01e561 100644
--- a/arch/x86/kernel/cpu/sgx/main.c
+++ b/arch/x86/kernel/cpu/sgx/main.c
@@ -1403,3 +1403,15 @@ static int sgx_updatesvn(void)
 
 	return ret;
 }
+
+void sgx_update_cpusvn_intel(void)
+{
+	sgx_lock_epc();
+	if (sgx_zap_pages())
+		goto out;
+
+	sgx_updatesvn();
+
+out:
+	sgx_unlock_epc();
+}
-- 
2.17.1


  parent reply	other threads:[~2022-05-20 10:41 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-20 10:38 [PATCH v5 0/9] Support microcode updates affecting SGX Cathy Zhang
2022-05-20 10:38 ` [PATCH v5 1/9] x86/sgx: Introduce mechanism to prevent new initializations of EPC pages Cathy Zhang
2022-05-20 19:05   ` Jarkko Sakkinen
2022-05-20 10:38 ` [PATCH v5 2/9] x86/sgx: Save enclave pointer for VA page Cathy Zhang
2022-05-20 19:07   ` Jarkko Sakkinen
2022-05-20 10:38 ` [PATCH v5 3/9] x86/sgx: Keep record for SGX VA and Guest page type Cathy Zhang
2022-05-20 19:11   ` Jarkko Sakkinen
2022-05-23  0:06     ` Zhang, Cathy
2022-05-23  6:09       ` Zhang, Cathy
2022-05-23 19:19         ` Jarkko Sakkinen
2022-05-20 10:38 ` [PATCH v5 4/9] x86/sgx: Save the size of each EPC section Cathy Zhang
2022-05-20 10:39 ` [PATCH v5 5/9] x86/sgx: Forced EPC page zapping for EUPDATESVN Cathy Zhang
2022-05-20 10:39 ` [PATCH v5 6/9] x86/sgx: Define error codes for ENCLS[EUPDATESVN] Cathy Zhang
2022-05-20 10:39 ` [PATCH v5 7/9] x86/sgx: Implement ENCLS[EUPDATESVN] Cathy Zhang
2022-05-20 10:39 ` Cathy Zhang [this message]
2022-05-20 10:39 ` [PATCH v5 9/9] x86/sgx: Call ENCLS[EUPDATESVN] during SGX initialization Cathy Zhang
2022-05-24 19:15 ` [PATCH v5 0/9] Support microcode updates affecting SGX Thomas Gleixner
2022-05-24 19:26   ` Borislav Petkov

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