From: Artem Bityutskiy <dedekind1@gmail.com>
To: Bastian Hecht <hechtb@googlemail.com>
Cc: Magnus Damm <magnus.damm@gmail.com>,
linux-mtd@lists.infradead.org,
Laurent Pichart <laurent.pinchart@ideasonboard.com>,
linux-sh@vger.kernel.org
Subject: Re: [PATCH v3 1/7] mtd: sh_flctl: Expand FLCMNCR register bit field
Date: Fri, 09 Mar 2012 12:48:51 +0000 [thread overview]
Message-ID: <1331297331.29445.19.camel@sauron.fi.intel.com> (raw)
In-Reply-To: <1330595321-2728-1-git-send-email-hechtb@gmail.com>
On Thu, 2012-03-01 at 10:48 +0100, Bastian Hecht wrote:
> Add support for a new hardware generation. The meaning of some bits
> of the FLCMNCR register changed, so some new defines are added
> parallel to the existing ones to keep backward compatibility.
>
> The defines allow to choose an appropriate clocking scheme.
>
> Signed-off-by: Bastian Hecht <hechtb@gmail.com>
Pushed the patch-set to l2-mtd.git, thanks!
--
Best Regards,
Artem Bityutskiy
prev parent reply other threads:[~2012-03-09 12:48 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-01 9:48 [PATCH v3 1/7] mtd: sh_flctl: Expand FLCMNCR register bit field Bastian Hecht
2012-03-01 9:48 ` [PATCH v3 2/7] mtd: sh_flctl: Reorder empty_fifo() calls Bastian Hecht
2012-03-01 9:48 ` [PATCH v3 3/7] mtd: sh_flctl: Expand the READID command to 8 bytes Bastian Hecht
2012-03-01 9:48 ` [PATCH v3 4/7] mtd: sh_flctl: Implement NAND_CMD_RNDOUT command Bastian Hecht
2012-03-01 9:48 ` [PATCH v3 5/7] mtd: sh_flctl: Use cached register value for FLCMNCR Bastian Hecht
2012-03-01 9:48 ` [PATCH v3 6/7] mtd: sh_flctl: Add FLHOLDCR register Bastian Hecht
2012-03-01 9:48 ` [PATCH v3 7/7] ARM: mach-shmobile: mackerel: Add the flash controller flctl Bastian Hecht
2012-03-01 15:19 ` [PATCH v3 1/7] mtd: sh_flctl: Expand FLCMNCR register bit field Laurent Pinchart
2012-03-09 12:48 ` Artem Bityutskiy [this message]
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