[GIT PULL 000/130] Renesas ARM based SoC pinmux and GPIO update for

[GIT PULL 000/130] Renesas ARM based SoC pinmux and GPIO update for

[Simon Horman]

Hi Olof, Hi Arnd,

Please note that this pull-request is based on renesas-fixes-for-v3.10
in order to avoid a messy conflict.

The following changes since commit 5600a8485603b240790005b9b58de4c4f6ada69d:

  ARM: shmobile: sh73a0: Update CMT clockevent rating to 80 (2013-06-04 14:37:53 +0900)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-pinmux-for-v3.11

for you to fetch changes up to 5fcf4a3c3a5bc08bf72a50ef1332501a3c1b96bb:

  ARM: shmobile: marzen: Use RCAR_GP_PIN macro (2013-06-05 17:18:24 +0900)

----------------------------------------------------------------
Renesas ARM based SoC pinmux and GPIO update for v3.11

SH-PFC:
* Entries for INTC external IRQs
* Remove dependency on GPIOLIB
* PFC support for r8a7790 SoC
* Pinmux support for r8a7778 SoC
* Increase pin group and function coverage for sh7372, r8a7740,
  r8a7778, r8a7779 and r8a7790 SoCs
* Use pinctrl mapping on mackerel, ap4evb, armadillo800eva,
  bonito, bockw, lager boards
* Use RCAR_GP_PIN macro in marzen board
* Remove unused GPIOs for sh7372, sh73a0, r8a7740 and r8a7790 SoCs
* Add bias (pull-up/down) pinconf support for r8a7740 SoC
* Add VCCQ support for sh73a0

GPIO car:
* Add RCAR_GP_PIN macro
* Add support for IRQ_TYPE_EDGE_BOTH
* Make the platform data gpio_base field signed

The GPIO changes have been included as the RCAR_GP_PIN and
IRQ_TYPE_EDGE_BOTH changes are depended on by SH-PFC changes.

----------------------------------------------------------------
Bastian Hecht (3):
      sh-pfc: Add entries for INTC external IRQs
      sh-pfc: r8a7740: Add SCIFA1 data group
      ARM: shmobile: armadillo800eva: Convert SCIFA1 to pinctrl

Guennadi Liakhovetski (3):
      pinctrl: sh-pfc: fix r8a7790 Function Select register tables
      pinctrl: sh-pfc: fix a typo in pfc-r8a7790
      pinctrl: r8a7790: add pinmux data for MMCIF and SDHI interfaces

Koji Matsuoka (1):
      sh-pfc: Initial r8a7790 PFC support

Kuninori Morimoto (15):
      gpio-rcar: R-Car GPIO IRQ share interrupt
      ARM: shmobile: add GPIO IRQ macro
      ARM: shmobile: r8a7778: Register PFC device
      sh-pfc: Add r8a7778 pinmux support
      sh-pfc: r8a7779: use RCAR_GP_PIN() on _GP_GPIO() macro
      sh-pfc: r8a7778: add common PFC macro helper
      sh-pfc: r8a7778: add SDHI support
      sh-pfc: r8a7778: tidyup SDHI naming suffixes and sort it alphabetically
      ARM: shmobile: r8a7778: add GPIO support
      sh-pfc: r8a7778: fixup IRQ1A settings
      sh-pfc: r8a7778: add I2C pin groups
      sh-pfc: r8a7778: add HSPI pin groups
      sh-pfc: r8a7778: add MMCIF pin groups
      ARM: shmobile: kzm9g: tidyup FSI pinctrl
      ARM: shmobile: bockw: add pinctrl support

Laurent Pinchart (98):
      gpio-rcar: Make the platform data gpio_base field signed
      gpio-rcar: Add RCAR_GP_PIN macro
      sh-pfc: Remove dependency on GPIOLIB
      sh-pfc: r8a7790: Add ETH pin groups and functions
      sh-pfc: r8a7790: Add INTC pin groups and functions
      sh-pfc: r8a7790: Add SCIF, SCIFA and SCIFB pin groups and functions
      sh-pfc: r8a7790: Remove GPIO data
      sh-pfc: r8a7790: Remove function GPIOs
      sh-pfc: r8a7790: Don't use GPIO enum entries
      sh-pfc: r8a7779: Replace hardcoded pin numbers with RCAR_GP_PIN macro
      sh-pfc: sh7372: Add BSC pin groups and functions
      sh-pfc: sh7372: Add CEU pin groups and functions
      sh-pfc: sh7372: Add FLCTL pin groups and functions
      sh-pfc: sh7372: Add FSI pin groups and functions
      sh-pfc: sh7372: Add HDMI pin groups and functions
      sh-pfc: sh7372: Add INTC pin groups and functions
      sh-pfc: sh7372: Add KEYSC pin groups and functions
      sh-pfc: sh7372: Add LCDC pin groups and functions
      sh-pfc: sh7372: Add SCIF pin groups and functions
      sh-pfc: sh7372: Add USB pin groups and functions
      ARM: shmobile: mackerel: Register pinctrl mapping for the ADXL34X
      ARM: shmobile: mackerel: Register pinctrl mapping for CEU
      ARM: shmobile: mackerel: Register pinctrl mapping for FLCTL
      ARM: shmobile: mackerel: Register pinctrl mapping for FSI
      ARM: shmobile: mackerel: Register pinctrl mapping for HDMI
      ARM: shmobile: mackerel: Register pinctrl mapping for LCD
      ARM: shmobile: mackerel: Register pinctrl mapping for SCIF
      ARM: shmobile: mackerel: Register IRQ pinctrl mapping for SDHI0
      ARM: shmobile: mackerel: Register pinctrl mapping for SMSC911x
      ARM: shmobile: mackerel: Register pinctrl mapping for ST1232
      ARM: shmobile: mackerel: Register pinctrl mapping for TCA6416
      ARM: shmobile: mackerel: Register pinctrl mapping for USBHS
      ARM: shmobile: ap4evb: Register pinctrl mapping for CEU
      ARM: shmobile: ap4evb: Register pinctrl mapping for FSI
      ARM: shmobile: ap4evb: Register pinctrl mapping for HDMI
      ARM: shmobile: ap4evb: Register pinctrl mapping for KEYSC
      ARM: shmobile: ap4evb: Register pinctrl mapping for LCD
      ARM: shmobile: ap4evb: Register pinctrl mapping for SCIF
      ARM: shmobile: ap4evb: Register pinctrl mapping for SMSC911x
      ARM: shmobile: ap4evb: Simplify tsc2007 pen state read function
      ARM: shmobile: ap4evb: Register pinctrl mapping for TSC2007
      ARM: shmobile: ap4evb: Register pinctrl mapping for USBHS
      sh-pfc: sh7372: Replace GPIO_PORTx enum with GPIO port numbers
      sh-pfc: sh7372: Remove function GPIOs
      ARM: shmobile: sh7372: Remove all GPIOs
      sh-pfc: sh7372: Add bias (pull-up/down) pinconf support
      sh-pfc: r8a7740: Add SCIF pin groups and functions
      sh-pfc: r8a7740: Declare missing INTC function
      sh-pfc: r8a7740: Add BSC pin groups and functions
      sh-pfc: r8a7740: Add GETHER pin groups and functions
      sh-pfc: r8a7740: Add CEU pin groups and functions
      sh-pfc: r8a7740: Add FSI pin groups and functions
      sh-pfc: r8a7740: Add HDMI pin groups and functions
      sh-pfc: r8a7740: Hardcode the LCDC0 output
      ARM: shmobile: armadillo800eva: Register pinctrl mapping for INTC
      ARM: shmobile: armadillo800eva: Register pinctrl mapping for GETHER
      ARM: shmobile: armadillo800eva: Register pinctrl mapping for CEU0
      ARM: shmobile: armadillo800eva: Register pinctrl mapping for FSI
      ARM: shmobile: armadillo800eva: Register pinctrl mapping for HDMI
      ARM: shmobile: armadillo800eva: Don't configure LCDC routing manually
      ARM: shmobile: armadillo800eva: Replace GPIO_PORTx with GPIO port numbers
      ARM: shmobile: bonito: Remove empty core devices array
      ARM: shmobile: bonito: Register pinctrl mapping for SCIF
      ARM: shmobile: bonito: Register pinctrl mapping for INTC
      ARM: shmobile: bonito: Register pinctrl mapping for BSC
      ARM: shmobile: bonito: Don't configure LCDC routing manually
      sh-pfc: r8a7740: Remove SCIF function GPIOS
      sh-pfc: r8a7740: Remove INTC function GPIOS
      sh-pfc: r8a7740: Remove BSC function GPIOS
      sh-pfc: r8a7740: Remove GETHER function GPIOS
      sh-pfc: r8a7740: Remove CEU function GPIOS
      sh-pfc: r8a7740: Remove FSI function GPIOS
      sh-pfc: r8a7740: Remove HDMI function GPIOS
      ARM: shmobile: r8a7740: Remove SCIF function GPIOs
      ARM: shmobile: r8a7740: Remove INTC function GPIOs
      ARM: shmobile: r8a7740: Remove BSC function GPIOs
      ARM: shmobile: r8a7740: Remove GETHER function GPIOs
      ARM: shmobile: r8a7740: Remove CEU function GPIOs
      ARM: shmobile: r8a7740: Remove FSI function GPIOs
      ARM: shmobile: r8a7740: Remove HDMI function GPIOs
      sh-pfc: r8a7740: Remove function GPIOs
      sh-pfc: r8a7740: Replace GPIO_PORTx enum with GPIO port numbers
      ARM: shmobile: r8a7740: Remove all GPIOs
      sh-pfc: r8a7740: Add bias (pull-up/down) pinconf support
      sh-pfc: r8a7778: Fix outdated GPIO_FN comments
      ARM: shmobile: r8a7790: Register GPIO devices
      ARM: shmobile: r8a7790: Remove all GPIOs
      sh-pfc: Add support for SoC-specific initialization
      sh-pfc: sh73a0: Add VCCQ MC0 regulator
      ARM: shmobile: kzm9g: Remove the VCCQ MC0 function GPIO
      ARM: shmobile: kzm9g-reference: Remove the VCCQ MC0 function GPIO
      sh-pfc: sh73a0: Add TPU pin groups and functions
      sh-pfc: r8a7740: Add TPU pin groups and functions
      sh-pfc: r8a7790: Add TPU pin groups and functions
      sh-pfc: sh73a0: Remove function GPIOs
      Revert "ARM: shmobile: Disallow PINCTRL without GPIOLIB"
      ARM: shmobile: lager: Initialize pinmux
      ARM: shmobile: marzen: Use RCAR_GP_PIN macro

Magnus Damm (2):
      ARM: shmobile: r8a7779 pinmux platform device cleanup
      ARM: shmobile: r8a7740 pinmux platform device cleanup

Phil Edworthy (1):
      pinctrl: sh-pfc: r8a7779: Fix missing MOD_SEL2 entry

Sergei Shtylyov (3):
      sh-pfc: r8a7778: add USB pin groups
      sh-pfc: r8a7778: add Ether pin groups
      sh-pfc: r8a7779: add Ether pin groups

Simon Horman (2):
      gpio-rcar: Add support for IRQ_TYPE_EDGE_BOTH
      ARM: shmobile: r8a7790: Configure R-Car GPIO for IRQ_TYPE_EDGE_BOTH

Vladimir Barinov (2):
      sh-pfc: r8a7779: add VIN pin groups
      sh-pfc: r8a7778: add VIN pin groups

 arch/arm/Kconfig                               |    2 +-
 arch/arm/mach-shmobile/Kconfig                 |    1 +
 arch/arm/mach-shmobile/board-ap4evb.c          |  132 +-
 arch/arm/mach-shmobile/board-armadillo800eva.c |  116 +-
 arch/arm/mach-shmobile/board-bockw.c           |   13 +
 arch/arm/mach-shmobile/board-bonito.c          |   47 +-
 arch/arm/mach-shmobile/board-kzm9g-reference.c |    1 -
 arch/arm/mach-shmobile/board-kzm9g.c           |   11 +-
 arch/arm/mach-shmobile/board-lager.c           |   15 +
 arch/arm/mach-shmobile/board-mackerel.c        |  171 +-
 arch/arm/mach-shmobile/board-marzen.c          |    7 +-
 arch/arm/mach-shmobile/include/mach/irqs.h     |    5 +
 arch/arm/mach-shmobile/include/mach/r8a7740.h  |  488 ---
 arch/arm/mach-shmobile/include/mach/r8a7778.h  |    1 +
 arch/arm/mach-shmobile/include/mach/sh7372.h   |  391 ---
 arch/arm/mach-shmobile/setup-r8a7740.c         |   24 +-
 arch/arm/mach-shmobile/setup-r8a7778.c         |   47 +
 arch/arm/mach-shmobile/setup-r8a7779.c         |   17 +-
 arch/arm/mach-shmobile/setup-r8a7790.c         |   36 +-
 drivers/gpio/gpio-rcar.c                       |   28 +-
 drivers/pinctrl/sh-pfc/Kconfig                 |   13 +-
 drivers/pinctrl/sh-pfc/Makefile                |    2 +
 drivers/pinctrl/sh-pfc/core.c                  |   22 +-
 drivers/pinctrl/sh-pfc/core.h                  |    4 +
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c           | 1923 ++++++++----
 drivers/pinctrl/sh-pfc/pfc-r8a7778.c           | 2783 +++++++++++++++++
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c           |  493 ++-
 drivers/pinctrl/sh-pfc/pfc-r8a7790.c           | 3835 ++++++++++++++++++++++++
 drivers/pinctrl/sh-pfc/pfc-sh7372.c            | 1652 +++++++---
 drivers/pinctrl/sh-pfc/pfc-sh73a0.c            |  742 +++--
 drivers/pinctrl/sh-pfc/sh_pfc.h                |    4 +-
 include/linux/platform_data/gpio-rcar.h        |    5 +-
 32 files changed, 10304 insertions(+), 2727 deletions(-)
 create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a7778.c
 create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a7790.c

-- 
1.8.2.1

[PATCH 001/130] gpio-rcar: R-Car GPIO IRQ share interrupt

[Simon Horman]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

R-Car H1 or Gen2 GPIO interrupts are assigned per each GPIO domain,
but, Gen1 E1/M1 GPIO interrupts are shared for all GPIO domain.
gpio-rcar driver needs IRQF_SHARED flags for these.
This patch was tested on Bock-W board

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/gpio/gpio-rcar.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index b4ca450..0f3d647 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -333,7 +333,7 @@ static int gpio_rcar_probe(struct platform_device *pdev)
 	}
 
 	if (devm_request_irq(&pdev->dev, irq->start,
-			     gpio_rcar_irq_handler, 0, name, p)) {
+			     gpio_rcar_irq_handler, IRQF_SHARED, name, p)) {
 		dev_err(&pdev->dev, "failed to request IRQ\n");
 		ret = -ENOENT;
 		goto err1;
-- 
1.8.2.1

[PATCH 002/130] gpio-rcar: Make the platform data gpio_base field signed

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

The gpio_base field is used to specify the desired GPIO base for the
GPIO controller. The GPIO core can automatically allocate a GPIO number
range when the base is set to -1. To make this possible, make the field
signed.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 include/linux/platform_data/gpio-rcar.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h
index b253f77..aba7079 100644
--- a/include/linux/platform_data/gpio-rcar.h
+++ b/include/linux/platform_data/gpio-rcar.h
@@ -17,7 +17,7 @@
 #define __GPIO_RCAR_H__
 
 struct gpio_rcar_config {
-	unsigned int gpio_base;
+	int gpio_base;
 	unsigned int irq_base;
 	unsigned int number_of_pins;
 	const char *pctl_name;
-- 
1.8.2.1

[PATCH 003/130] gpio-rcar: Add support for IRQ_TYPE_EDGE_BOTH

[Simon Horman]

As hardware support for this feature is not universal for all SoCs a flag,
has_both_edge_trigger, has been added to the platform data of the driver to
allow this feature to be enabled.

The motivation for this is to allow use of the gpio-keys driver on the
lager board which is based on the r8a7790 SoC. The V2 of this patch has been
fully exercised using that driver on that board.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/gpio/gpio-rcar.c                | 26 +++++++++++++++++++++-----
 include/linux/platform_data/gpio-rcar.h |  1 +
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 0f3d647..d173d56 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -49,6 +49,7 @@ struct gpio_rcar_priv {
 #define POSNEG 0x20
 #define EDGLEVEL 0x24
 #define FILONOFF 0x28
+#define BOTHEDGE 0x4c
 
 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
 {
@@ -91,7 +92,8 @@ static void gpio_rcar_irq_enable(struct irq_data *d)
 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
 						  unsigned int hwirq,
 						  bool active_high_rising_edge,
-						  bool level_trigger)
+						  bool level_trigger,
+						  bool both)
 {
 	unsigned long flags;
 
@@ -108,6 +110,10 @@ static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
 	/* Configure edge or level trigger in EDGLEVEL */
 	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
 
+	/* Select one edge or both edges in BOTHEDGE */
+	if (p->config.has_both_edge_trigger)
+		gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
+
 	/* Select "Interrupt Input Mode" in IOINTSEL */
 	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
 
@@ -127,16 +133,26 @@ static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
 
 	switch (type & IRQ_TYPE_SENSE_MASK) {
 	case IRQ_TYPE_LEVEL_HIGH:
-		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true);
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
+						      false);
 		break;
 	case IRQ_TYPE_LEVEL_LOW:
-		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true);
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
+						      false);
 		break;
 	case IRQ_TYPE_EDGE_RISING:
-		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false);
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
+						      false);
 		break;
 	case IRQ_TYPE_EDGE_FALLING:
-		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false);
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
+						      false);
+		break;
+	case IRQ_TYPE_EDGE_BOTH:
+		if (!p->config.has_both_edge_trigger)
+			return -EINVAL;
+		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
+						      true);
 		break;
 	default:
 		return -EINVAL;
diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h
index aba7079..6c0027a 100644
--- a/include/linux/platform_data/gpio-rcar.h
+++ b/include/linux/platform_data/gpio-rcar.h
@@ -21,6 +21,7 @@ struct gpio_rcar_config {
 	unsigned int irq_base;
 	unsigned int number_of_pins;
 	const char *pctl_name;
+	unsigned has_both_edge_trigger:1;
 };
 
 #endif /* __GPIO_RCAR_H__ */
-- 
1.8.2.1

[PATCH 004/130] gpio-rcar: Add RCAR_GP_PIN macro

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Pins are numbered in the R-Car family documentation using a bank number
and a pin number in the bank. As the Linux pin number space is linear,
we need to flatten this by multiplying the bank number by 32 and adding
the pin number. The resulting number bear no directly visible
relationship  to the documentation, making it error-prone.

Add a RCAR_GP_PIN macro to convert from the documentation pin number
space to the linear Linux space.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[horms+renesas@verge.net.au: non-trivial rebase on top of
 "sh-pfc: r8a7779: Don't group USB OVC and PENC pins"]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 include/linux/platform_data/gpio-rcar.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h
index 6c0027a..2d8d694 100644
--- a/include/linux/platform_data/gpio-rcar.h
+++ b/include/linux/platform_data/gpio-rcar.h
@@ -24,4 +24,6 @@ struct gpio_rcar_config {
 	unsigned has_both_edge_trigger:1;
 };
 
+#define RCAR_GP_PIN(bank, pin)		(((bank) * 32) + (pin))
+
 #endif /* __GPIO_RCAR_H__ */
-- 
1.8.2.1

[PATCH 005/130] ARM: shmobile: add GPIO IRQ macro

[Simon Horman]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

R-Car series gpio_rcar driver can control GPIO IRQ today.
It needs base IRQ number for gpio_rcar_config :: .irq_base
This patch adds macro for GPIO IRQ.
This patch was tested on Bock-W board

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/irqs.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index b2074e2..d241bfd 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -16,4 +16,9 @@
 #define IRQPIN_BASE		2000
 #define irq_pin(nr)		((nr) + IRQPIN_BASE)
 
+/* GPIO IRQ */
+#define _GPIO_IRQ_BASE		2500
+#define GPIO_IRQ_BASE(x)	(_GPIO_IRQ_BASE + (32 * x))
+#define GPIO_IRQ(x, y)		(_GPIO_IRQ_BASE + (32 * x) + y)
+
 #endif /* __ASM_MACH_IRQS_H */
-- 
1.8.2.1

[PATCH 006/130] ARM: shmobile: r8a7778: Register PFC device

[Simon Horman]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/Kconfig                |  1 +
 arch/arm/mach-shmobile/include/mach/r8a7778.h |  1 +
 arch/arm/mach-shmobile/setup-r8a7778.c        | 13 +++++++++++++
 3 files changed, 15 insertions(+)

diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 1a517e2..06da4d3 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -37,6 +37,7 @@ config ARCH_R8A7740
 
 config ARCH_R8A7778
 	bool "R-Car M1 (R8A77780)"
+	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select CPU_V7
 	select SH_CLK_CPG
 	select ARM_GIC
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
index 951149e..68053fc 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -28,5 +28,6 @@ extern void r8a7778_init_irq(void);
 extern void r8a7778_init_irq_dt(void);
 extern void r8a7778_clock_init(void);
 extern void r8a7778_init_irq_extpin(int irlm);
+extern void r8a7778_pinmux_init(void);
 
 #endif /* __ASM_R8A7778_H__ */
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 30b4a33..0ca5701 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -94,6 +94,19 @@ static struct resource ether_resources[] = {
 		&sh_tmu##idx##_platform_data,		\
 		sizeof(sh_tmu##idx##_platform_data))
 
+/* PFC */
+static struct resource pfc_resources[] = {
+	DEFINE_RES_MEM(0xfffc0000, 0x118),
+};
+
+void __init r8a7778_pinmux_init(void)
+{
+	platform_device_register_simple(
+		"pfc-r8a7778", -1,
+		pfc_resources,
+		ARRAY_SIZE(pfc_resources));
+}
+
 void __init r8a7778_add_standard_devices(void)
 {
 	int i;
-- 
1.8.2.1

[PATCH 008/130] sh-pfc: Add entries for INTC external IRQs

[Simon Horman]

From: Bastian Hecht <hechtb@gmail.com>

We add all necessary entries to support the external IRQs from the INTC.

Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 174 +++++++++++++++++++++++++++++++++++
 1 file changed, 174 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index bbd87d2..d95040c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -30,6 +30,22 @@
 	PORT_10(fn, pfx##20, sfx),					\
 	PORT_1(fn, pfx##210, sfx),	PORT_1(fn, pfx##211, sfx)
 
+#define IRQC_PIN_MUX(irq, pin)						\
+static const unsigned int intc_irq##irq##_pins[] = {			\
+	pin,								\
+};									\
+static const unsigned int intc_irq##irq##_mux[] = {			\
+	IRQ##irq##_MARK,						\
+}
+
+#define IRQC_PINS_MUX(irq, idx, pin)					\
+static const unsigned int intc_irq##irq##_##idx##_pins[] = {		\
+	pin,								\
+};									\
+static const unsigned int intc_irq##irq##_##idx##_mux[] = {		\
+	IRQ##irq##_PORT##pin##_MARK,					\
+}
+
 enum {
 	PINMUX_RESERVED = 0,
 
@@ -1658,6 +1674,59 @@ static struct sh_pfc_pin pinmux_pins[] = {
 	GPIO_PORT_ALL(),
 };
 
+/* - INTC ------------------------------------------------------------------- */
+IRQC_PINS_MUX(0, 0, 2);
+IRQC_PINS_MUX(0, 1, 13);
+IRQC_PIN_MUX(1, 20);
+IRQC_PINS_MUX(2, 0, 11);
+IRQC_PINS_MUX(2, 1, 12);
+IRQC_PINS_MUX(3, 0, 10);
+IRQC_PINS_MUX(3, 1, 14);
+IRQC_PINS_MUX(4, 0, 15);
+IRQC_PINS_MUX(4, 1, 172);
+IRQC_PINS_MUX(5, 0, 0);
+IRQC_PINS_MUX(5, 1, 1);
+IRQC_PINS_MUX(6, 0, 121);
+IRQC_PINS_MUX(6, 1, 173);
+IRQC_PINS_MUX(7, 0, 120);
+IRQC_PINS_MUX(7, 1, 209);
+IRQC_PIN_MUX(8, 119);
+IRQC_PINS_MUX(9, 0, 118);
+IRQC_PINS_MUX(9, 1, 210);
+IRQC_PIN_MUX(10, 19);
+IRQC_PIN_MUX(11, 104);
+IRQC_PINS_MUX(12, 0, 42);
+IRQC_PINS_MUX(12, 1, 97);
+IRQC_PINS_MUX(13, 0, 64);
+IRQC_PINS_MUX(13, 1, 98);
+IRQC_PINS_MUX(14, 0, 63);
+IRQC_PINS_MUX(14, 1, 99);
+IRQC_PINS_MUX(15, 0, 62);
+IRQC_PINS_MUX(15, 1, 100);
+IRQC_PINS_MUX(16, 0, 68);
+IRQC_PINS_MUX(16, 1, 211);
+IRQC_PIN_MUX(17, 69);
+IRQC_PIN_MUX(18, 70);
+IRQC_PIN_MUX(19, 71);
+IRQC_PIN_MUX(20, 67);
+IRQC_PIN_MUX(21, 202);
+IRQC_PIN_MUX(22, 95);
+IRQC_PIN_MUX(23, 96);
+IRQC_PIN_MUX(24, 180);
+IRQC_PIN_MUX(25, 38);
+IRQC_PINS_MUX(26, 0, 58);
+IRQC_PINS_MUX(26, 1, 81);
+IRQC_PINS_MUX(27, 0, 57);
+IRQC_PINS_MUX(27, 1, 168);
+IRQC_PINS_MUX(28, 0, 56);
+IRQC_PINS_MUX(28, 1, 169);
+IRQC_PINS_MUX(29, 0, 50);
+IRQC_PINS_MUX(29, 1, 170);
+IRQC_PINS_MUX(30, 0, 49);
+IRQC_PINS_MUX(30, 1, 171);
+IRQC_PINS_MUX(31, 0, 41);
+IRQC_PINS_MUX(31, 1, 167);
+
 /* - LCD0 ------------------------------------------------------------------- */
 static const unsigned int lcd0_data8_pins[] = {
 	/* D[0:7] */
@@ -2054,6 +2123,57 @@ static const unsigned int sdhi2_wp_1_mux[] = {
 };
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SH_PFC_PIN_GROUP(intc_irq0_0),
+	SH_PFC_PIN_GROUP(intc_irq0_1),
+	SH_PFC_PIN_GROUP(intc_irq1),
+	SH_PFC_PIN_GROUP(intc_irq2_0),
+	SH_PFC_PIN_GROUP(intc_irq2_1),
+	SH_PFC_PIN_GROUP(intc_irq3_0),
+	SH_PFC_PIN_GROUP(intc_irq3_1),
+	SH_PFC_PIN_GROUP(intc_irq4_0),
+	SH_PFC_PIN_GROUP(intc_irq4_1),
+	SH_PFC_PIN_GROUP(intc_irq5_0),
+	SH_PFC_PIN_GROUP(intc_irq5_1),
+	SH_PFC_PIN_GROUP(intc_irq6_0),
+	SH_PFC_PIN_GROUP(intc_irq6_1),
+	SH_PFC_PIN_GROUP(intc_irq7_0),
+	SH_PFC_PIN_GROUP(intc_irq7_1),
+	SH_PFC_PIN_GROUP(intc_irq8),
+	SH_PFC_PIN_GROUP(intc_irq9_0),
+	SH_PFC_PIN_GROUP(intc_irq9_1),
+	SH_PFC_PIN_GROUP(intc_irq10),
+	SH_PFC_PIN_GROUP(intc_irq11),
+	SH_PFC_PIN_GROUP(intc_irq12_0),
+	SH_PFC_PIN_GROUP(intc_irq12_1),
+	SH_PFC_PIN_GROUP(intc_irq13_0),
+	SH_PFC_PIN_GROUP(intc_irq13_1),
+	SH_PFC_PIN_GROUP(intc_irq14_0),
+	SH_PFC_PIN_GROUP(intc_irq14_1),
+	SH_PFC_PIN_GROUP(intc_irq15_0),
+	SH_PFC_PIN_GROUP(intc_irq15_1),
+	SH_PFC_PIN_GROUP(intc_irq16_0),
+	SH_PFC_PIN_GROUP(intc_irq16_1),
+	SH_PFC_PIN_GROUP(intc_irq17),
+	SH_PFC_PIN_GROUP(intc_irq18),
+	SH_PFC_PIN_GROUP(intc_irq19),
+	SH_PFC_PIN_GROUP(intc_irq20),
+	SH_PFC_PIN_GROUP(intc_irq21),
+	SH_PFC_PIN_GROUP(intc_irq22),
+	SH_PFC_PIN_GROUP(intc_irq23),
+	SH_PFC_PIN_GROUP(intc_irq24),
+	SH_PFC_PIN_GROUP(intc_irq25),
+	SH_PFC_PIN_GROUP(intc_irq26_0),
+	SH_PFC_PIN_GROUP(intc_irq26_1),
+	SH_PFC_PIN_GROUP(intc_irq27_0),
+	SH_PFC_PIN_GROUP(intc_irq27_1),
+	SH_PFC_PIN_GROUP(intc_irq28_0),
+	SH_PFC_PIN_GROUP(intc_irq28_1),
+	SH_PFC_PIN_GROUP(intc_irq29_0),
+	SH_PFC_PIN_GROUP(intc_irq29_1),
+	SH_PFC_PIN_GROUP(intc_irq30_0),
+	SH_PFC_PIN_GROUP(intc_irq30_1),
+	SH_PFC_PIN_GROUP(intc_irq31_0),
+	SH_PFC_PIN_GROUP(intc_irq31_1),
 	SH_PFC_PIN_GROUP(lcd0_data8),
 	SH_PFC_PIN_GROUP(lcd0_data9),
 	SH_PFC_PIN_GROUP(lcd0_data12),
@@ -2103,6 +2223,60 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(sdhi2_wp_1),
 };
 
+static const char * const intc_groups[] = {
+	"intc_irq0_0",
+	"intc_irq0_1",
+	"intc_irq1",
+	"intc_irq2_0",
+	"intc_irq2_1",
+	"intc_irq3_0",
+	"intc_irq3_1",
+	"intc_irq4_0",
+	"intc_irq4_1",
+	"intc_irq5_0",
+	"intc_irq5_1",
+	"intc_irq6_0",
+	"intc_irq6_1",
+	"intc_irq7_0",
+	"intc_irq7_1",
+	"intc_irq8",
+	"intc_irq9_0",
+	"intc_irq9_1",
+	"intc_irq10",
+	"intc_irq11",
+	"intc_irq12_0",
+	"intc_irq12_1",
+	"intc_irq13_0",
+	"intc_irq13_1",
+	"intc_irq14_0",
+	"intc_irq14_1",
+	"intc_irq15_0",
+	"intc_irq15_1",
+	"intc_irq16_0",
+	"intc_irq16_1",
+	"intc_irq17",
+	"intc_irq18",
+	"intc_irq19",
+	"intc_irq20",
+	"intc_irq21",
+	"intc_irq22",
+	"intc_irq23",
+	"intc_irq24",
+	"intc_irq25",
+	"intc_irq26_0",
+	"intc_irq26_1",
+	"intc_irq27_0",
+	"intc_irq27_1",
+	"intc_irq28_0",
+	"intc_irq28_1",
+	"intc_irq29_0",
+	"intc_irq29_1",
+	"intc_irq30_0",
+	"intc_irq30_1",
+	"intc_irq31_0",
+	"intc_irq31_1",
+};
+
 static const char * const lcd0_groups[] = {
 	"lcd0_data8",
 	"lcd0_data9",
-- 
1.8.2.1

[PATCH 009/130] sh-pfc: Remove dependency on GPIOLIB

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Make GPIO support optional for platforms that don't support GPIOLIB.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/Kconfig  | 2 --
 drivers/pinctrl/sh-pfc/core.h   | 1 +
 drivers/pinctrl/sh-pfc/sh_pfc.h | 2 +-
 3 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 9f0217b..a0b6bd0 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -5,8 +5,6 @@
 if ARCH_SHMOBILE || SUPERH
 
 config PINCTRL_SH_PFC
-	# XXX move off the gpio dependency
-	depends on GPIOLIB
 	select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
 	select PINMUX
 	select PINCONF
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index ee4a4d6..6ec746f 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -11,6 +11,7 @@
 #define __SH_PFC_CORE_H__
 
 #include <linux/compiler.h>
+#include <linux/spinlock.h>
 #include <linux/types.h>
 
 #include "sh_pfc.h"
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 3b785fc..b170761 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -11,8 +11,8 @@
 #ifndef __SH_PFC_H
 #define __SH_PFC_H
 
+#include <linux/bug.h>
 #include <linux/stringify.h>
-#include <asm-generic/gpio.h>
 
 typedef unsigned short pinmux_enum_t;
 
-- 
1.8.2.1

[PATCH 010/130] sh-pfc: r8a7790: Add ETH pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 58 ++++++++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 42b0c55..3774242 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -20,7 +20,10 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
+
 #include <linux/kernel.h>
+#include <linux/platform_data/gpio-rcar.h>
+
 #include <mach/r8a7790.h>
 
 #include "core.h"
@@ -1820,6 +1823,57 @@ static struct sh_pfc_pin pinmux_pins[] = {
 	PINMUX_GPIO_GP_ALL(),
 };
 
+/* - ETH -------------------------------------------------------------------- */
+static const unsigned int eth_link_pins[] = {
+	/* LINK */
+	RCAR_GP_PIN(2, 22),
+};
+static const unsigned int eth_link_mux[] = {
+	ETH_LINK_MARK,
+};
+static const unsigned int eth_magic_pins[] = {
+	/* MAGIC */
+	RCAR_GP_PIN(2, 27),
+};
+static const unsigned int eth_magic_mux[] = {
+	ETH_MAGIC_MARK,
+};
+static const unsigned int eth_mdio_pins[] = {
+	/* MDC, MDIO */
+	RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
+};
+static const unsigned int eth_mdio_mux[] = {
+	ETH_MDC_MARK, ETH_MDIO_MARK,
+};
+static const unsigned int eth_rmii_pins[] = {
+	/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
+	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
+	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
+	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
+};
+static const unsigned int eth_rmii_mux[] = {
+	ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
+	ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SH_PFC_PIN_GROUP(eth_link),
+	SH_PFC_PIN_GROUP(eth_magic),
+	SH_PFC_PIN_GROUP(eth_mdio),
+	SH_PFC_PIN_GROUP(eth_rmii),
+};
+
+static const char * const eth_groups[] = {
+	"eth_link",
+	"eth_magic",
+	"eth_mdio",
+	"eth_rmii",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(eth),
+};
+
 #define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
 
 static const struct pinmux_func pinmux_func_gpios[] = {
@@ -3226,6 +3280,10 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = {
 
 	.pins = pinmux_pins,
 	.nr_pins = ARRAY_SIZE(pinmux_pins),
+	.groups = pinmux_groups,
+	.nr_groups = ARRAY_SIZE(pinmux_groups),
+	.functions = pinmux_functions,
+	.nr_functions = ARRAY_SIZE(pinmux_functions),
 
 	.func_gpios	= pinmux_func_gpios,
 	.nr_func_gpios	= ARRAY_SIZE(pinmux_func_gpios),
-- 
1.8.2.1

[PATCH 011/130] sh-pfc: r8a7790: Add INTC pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 40 ++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 3774242..a92b204 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -1855,12 +1855,45 @@ static const unsigned int eth_rmii_mux[] = {
 	ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
 	ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
 };
+/* - INTC ------------------------------------------------------------------- */
+static const unsigned int intc_irq0_pins[] = {
+	/* IRQ */
+	RCAR_GP_PIN(1, 25),
+};
+static const unsigned int intc_irq0_mux[] = {
+	IRQ0_MARK,
+};
+static const unsigned int intc_irq1_pins[] = {
+	/* IRQ */
+	RCAR_GP_PIN(1, 27),
+};
+static const unsigned int intc_irq1_mux[] = {
+	IRQ1_MARK,
+};
+static const unsigned int intc_irq2_pins[] = {
+	/* IRQ */
+	RCAR_GP_PIN(1, 29),
+};
+static const unsigned int intc_irq2_mux[] = {
+	IRQ2_MARK,
+};
+static const unsigned int intc_irq3_pins[] = {
+	/* IRQ */
+	RCAR_GP_PIN(1, 23),
+};
+static const unsigned int intc_irq3_mux[] = {
+	IRQ3_MARK,
+};
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(eth_link),
 	SH_PFC_PIN_GROUP(eth_magic),
 	SH_PFC_PIN_GROUP(eth_mdio),
 	SH_PFC_PIN_GROUP(eth_rmii),
+	SH_PFC_PIN_GROUP(intc_irq0),
+	SH_PFC_PIN_GROUP(intc_irq1),
+	SH_PFC_PIN_GROUP(intc_irq2),
+	SH_PFC_PIN_GROUP(intc_irq3),
 };
 
 static const char * const eth_groups[] = {
@@ -1870,8 +1903,15 @@ static const char * const eth_groups[] = {
 	"eth_rmii",
 };
 
+static const char * const intc_groups[] = {
+	"intc_irq0",
+	"intc_irq1",
+	"intc_irq2",
+	"intc_irq3",
+};
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(eth),
+	SH_PFC_FUNCTION(intc),
 };
 
 #define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-- 
1.8.2.1

[PATCH 012/130] sh-pfc: r8a7790: Add SCIF, SCIFA and SCIFB pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 617 +++++++++++++++++++++++++++++++++++
 1 file changed, 617 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index a92b204..54c1e10 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -1884,6 +1884,462 @@ static const unsigned int intc_irq3_pins[] = {
 static const unsigned int intc_irq3_mux[] = {
 	IRQ3_MARK,
 };
+/* - SCIF0 ----------------------------------------------------------------- */
+static const unsigned int scif0_data_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
+};
+static const unsigned int scif0_data_mux[] = {
+	RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(4, 27),
+};
+static const unsigned int scif0_clk_mux[] = {
+	SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+	RTS0_N_TANS_MARK, CTS0_N_MARK,
+};
+static const unsigned int scif0_data_b_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int scif0_data_b_mux[] = {
+	RX0_B_MARK, TX0_B_MARK,
+};
+/* - SCIF1 ----------------------------------------------------------------- */
+static const unsigned int scif1_data_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
+};
+static const unsigned int scif1_data_mux[] = {
+	RX1_MARK, TX1_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(4, 20),
+};
+static const unsigned int scif1_clk_mux[] = {
+	SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+	RTS1_N_TANS_MARK, CTS1_N_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+static const unsigned int scif1_data_b_mux[] = {
+	RX1_B_MARK, TX1_B_MARK,
+};
+static const unsigned int scif1_data_c_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int scif1_data_c_mux[] = {
+	RX1_C_MARK, TX1_C_MARK,
+};
+static const unsigned int scif1_data_d_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+};
+static const unsigned int scif1_data_d_mux[] = {
+	RX1_D_MARK, TX1_D_MARK,
+};
+static const unsigned int scif1_clk_d_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(3, 17),
+};
+static const unsigned int scif1_clk_d_mux[] = {
+	SCK1_D_MARK,
+};
+static const unsigned int scif1_data_e_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+};
+static const unsigned int scif1_data_e_mux[] = {
+	RX1_E_MARK, TX1_E_MARK,
+};
+static const unsigned int scif1_clk_e_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(2, 20),
+};
+static const unsigned int scif1_clk_e_mux[] = {
+	SCK1_E_MARK,
+};
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
+};
+static const unsigned int scifa0_data_mux[] = {
+	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(4, 27),
+};
+static const unsigned int scifa0_clk_mux[] = {
+	SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+	SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
+};
+static const unsigned int scifa0_data_b_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
+};
+static const unsigned int scifa0_data_b_mux[] = {
+	SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
+};
+static const unsigned int scifa0_clk_b_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(1, 19),
+};
+static const unsigned int scifa0_clk_b_mux[] = {
+	SCIFA0_SCK_B_MARK,
+};
+static const unsigned int scifa0_ctrl_b_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
+};
+static const unsigned int scifa0_ctrl_b_mux[] = {
+	SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
+};
+static const unsigned int scifa1_data_mux[] = {
+	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(4, 20),
+};
+static const unsigned int scifa1_clk_mux[] = {
+	SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+	SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
+};
+static const unsigned int scifa1_data_b_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
+};
+static const unsigned int scifa1_data_b_mux[] = {
+	SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
+};
+static const unsigned int scifa1_clk_b_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(0, 23),
+};
+static const unsigned int scifa1_clk_b_mux[] = {
+	SCIFA1_SCK_B_MARK,
+};
+static const unsigned int scifa1_ctrl_b_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
+};
+static const unsigned int scifa1_ctrl_b_mux[] = {
+	SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
+};
+static const unsigned int scifa1_data_c_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+};
+static const unsigned int scifa1_data_c_mux[] = {
+	SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
+};
+static const unsigned int scifa1_clk_c_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(0, 8),
+};
+static const unsigned int scifa1_clk_c_mux[] = {
+	SCIFA1_SCK_C_MARK,
+};
+static const unsigned int scifa1_ctrl_c_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
+};
+static const unsigned int scifa1_ctrl_c_mux[] = {
+	SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
+};
+static const unsigned int scifa1_data_d_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+};
+static const unsigned int scifa1_data_d_mux[] = {
+	SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
+};
+static const unsigned int scifa1_clk_d_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(2, 10),
+};
+static const unsigned int scifa1_clk_d_mux[] = {
+	SCIFA1_SCK_D_MARK,
+};
+static const unsigned int scifa1_ctrl_d_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int scifa1_ctrl_d_mux[] = {
+	SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int scifa2_data_mux[] = {
+	SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
+};
+static const unsigned int scifa2_clk_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(5, 4),
+};
+static const unsigned int scifa2_clk_mux[] = {
+	SCIFA2_SCK_MARK,
+};
+static const unsigned int scifa2_ctrl_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
+};
+static const unsigned int scifa2_ctrl_mux[] = {
+	SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
+};
+static const unsigned int scifa2_data_b_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
+};
+static const unsigned int scifa2_data_b_mux[] = {
+	SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
+};
+static const unsigned int scifa2_data_c_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
+};
+static const unsigned int scifa2_data_c_mux[] = {
+	SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
+};
+static const unsigned int scifa2_clk_c_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(5, 29),
+};
+static const unsigned int scifa2_clk_c_mux[] = {
+	SCIFA2_SCK_C_MARK,
+};
+/* - SCIFB0 ----------------------------------------------------------------- */
+static const unsigned int scifb0_data_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
+};
+static const unsigned int scifb0_data_mux[] = {
+	SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
+};
+static const unsigned int scifb0_clk_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(4, 8),
+};
+static const unsigned int scifb0_clk_mux[] = {
+	SCIFB0_SCK_MARK,
+};
+static const unsigned int scifb0_ctrl_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
+};
+static const unsigned int scifb0_ctrl_mux[] = {
+	SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
+};
+static const unsigned int scifb0_data_b_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+static const unsigned int scifb0_data_b_mux[] = {
+	SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
+};
+static const unsigned int scifb0_clk_b_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(3, 9),
+};
+static const unsigned int scifb0_clk_b_mux[] = {
+	SCIFB0_SCK_B_MARK,
+};
+static const unsigned int scifb0_ctrl_b_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
+};
+static const unsigned int scifb0_ctrl_b_mux[] = {
+	SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
+};
+static const unsigned int scifb0_data_c_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int scifb0_data_c_mux[] = {
+	SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
+};
+/* - SCIFB1 ----------------------------------------------------------------- */
+static const unsigned int scifb1_data_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
+};
+static const unsigned int scifb1_data_mux[] = {
+	SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
+};
+static const unsigned int scifb1_clk_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(4, 14),
+};
+static const unsigned int scifb1_clk_mux[] = {
+	SCIFB1_SCK_MARK,
+};
+static const unsigned int scifb1_ctrl_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
+};
+static const unsigned int scifb1_ctrl_mux[] = {
+	SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
+};
+static const unsigned int scifb1_data_b_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+};
+static const unsigned int scifb1_data_b_mux[] = {
+	SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
+};
+static const unsigned int scifb1_clk_b_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(3, 1),
+};
+static const unsigned int scifb1_clk_b_mux[] = {
+	SCIFB1_SCK_B_MARK,
+};
+static const unsigned int scifb1_ctrl_b_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
+};
+static const unsigned int scifb1_ctrl_b_mux[] = {
+	SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
+};
+static const unsigned int scifb1_data_c_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+static const unsigned int scifb1_data_c_mux[] = {
+	SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
+};
+static const unsigned int scifb1_data_d_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int scifb1_data_d_mux[] = {
+	SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
+};
+static const unsigned int scifb1_data_e_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+};
+static const unsigned int scifb1_data_e_mux[] = {
+	SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
+};
+static const unsigned int scifb1_clk_e_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(3, 17),
+};
+static const unsigned int scifb1_clk_e_mux[] = {
+	SCIFB1_SCK_E_MARK,
+};
+static const unsigned int scifb1_data_f_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int scifb1_data_f_mux[] = {
+	SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
+};
+static const unsigned int scifb1_data_g_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+};
+static const unsigned int scifb1_data_g_mux[] = {
+	SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
+};
+static const unsigned int scifb1_clk_g_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(2, 20),
+};
+static const unsigned int scifb1_clk_g_mux[] = {
+	SCIFB1_SCK_G_MARK,
+};
+/* - SCIFB2 ----------------------------------------------------------------- */
+static const unsigned int scifb2_data_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
+};
+static const unsigned int scifb2_data_mux[] = {
+	SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
+};
+static const unsigned int scifb2_clk_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(4, 21),
+};
+static const unsigned int scifb2_clk_mux[] = {
+	SCIFB2_SCK_MARK,
+};
+static const unsigned int scifb2_ctrl_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
+};
+static const unsigned int scifb2_ctrl_mux[] = {
+	SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
+};
+static const unsigned int scifb2_data_b_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
+};
+static const unsigned int scifb2_data_b_mux[] = {
+	SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
+};
+static const unsigned int scifb2_clk_b_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(0, 31),
+};
+static const unsigned int scifb2_clk_b_mux[] = {
+	SCIFB2_SCK_B_MARK,
+};
+static const unsigned int scifb2_ctrl_b_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
+};
+static const unsigned int scifb2_ctrl_b_mux[] = {
+	SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
+};
+static const unsigned int scifb2_data_c_pins[] = {
+	/* RXD, TXD */
+	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
+};
+static const unsigned int scifb2_data_c_mux[] = {
+	SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
+};
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(eth_link),
@@ -1894,6 +2350,70 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(intc_irq1),
 	SH_PFC_PIN_GROUP(intc_irq2),
 	SH_PFC_PIN_GROUP(intc_irq3),
+	SH_PFC_PIN_GROUP(scif0_data),
+	SH_PFC_PIN_GROUP(scif0_clk),
+	SH_PFC_PIN_GROUP(scif0_ctrl),
+	SH_PFC_PIN_GROUP(scif0_data_b),
+	SH_PFC_PIN_GROUP(scif1_data),
+	SH_PFC_PIN_GROUP(scif1_clk),
+	SH_PFC_PIN_GROUP(scif1_ctrl),
+	SH_PFC_PIN_GROUP(scif1_data_b),
+	SH_PFC_PIN_GROUP(scif1_data_c),
+	SH_PFC_PIN_GROUP(scif1_data_d),
+	SH_PFC_PIN_GROUP(scif1_clk_d),
+	SH_PFC_PIN_GROUP(scif1_data_e),
+	SH_PFC_PIN_GROUP(scif1_clk_e),
+	SH_PFC_PIN_GROUP(scifa0_data),
+	SH_PFC_PIN_GROUP(scifa0_clk),
+	SH_PFC_PIN_GROUP(scifa0_ctrl),
+	SH_PFC_PIN_GROUP(scifa0_data_b),
+	SH_PFC_PIN_GROUP(scifa0_clk_b),
+	SH_PFC_PIN_GROUP(scifa0_ctrl_b),
+	SH_PFC_PIN_GROUP(scifa1_data),
+	SH_PFC_PIN_GROUP(scifa1_clk),
+	SH_PFC_PIN_GROUP(scifa1_ctrl),
+	SH_PFC_PIN_GROUP(scifa1_data_b),
+	SH_PFC_PIN_GROUP(scifa1_clk_b),
+	SH_PFC_PIN_GROUP(scifa1_ctrl_b),
+	SH_PFC_PIN_GROUP(scifa1_data_c),
+	SH_PFC_PIN_GROUP(scifa1_clk_c),
+	SH_PFC_PIN_GROUP(scifa1_ctrl_c),
+	SH_PFC_PIN_GROUP(scifa1_data_d),
+	SH_PFC_PIN_GROUP(scifa1_clk_d),
+	SH_PFC_PIN_GROUP(scifa1_ctrl_d),
+	SH_PFC_PIN_GROUP(scifa2_data),
+	SH_PFC_PIN_GROUP(scifa2_clk),
+	SH_PFC_PIN_GROUP(scifa2_ctrl),
+	SH_PFC_PIN_GROUP(scifa2_data_b),
+	SH_PFC_PIN_GROUP(scifa2_data_c),
+	SH_PFC_PIN_GROUP(scifa2_clk_c),
+	SH_PFC_PIN_GROUP(scifb0_data),
+	SH_PFC_PIN_GROUP(scifb0_clk),
+	SH_PFC_PIN_GROUP(scifb0_ctrl),
+	SH_PFC_PIN_GROUP(scifb0_data_b),
+	SH_PFC_PIN_GROUP(scifb0_clk_b),
+	SH_PFC_PIN_GROUP(scifb0_ctrl_b),
+	SH_PFC_PIN_GROUP(scifb0_data_c),
+	SH_PFC_PIN_GROUP(scifb1_data),
+	SH_PFC_PIN_GROUP(scifb1_clk),
+	SH_PFC_PIN_GROUP(scifb1_ctrl),
+	SH_PFC_PIN_GROUP(scifb1_data_b),
+	SH_PFC_PIN_GROUP(scifb1_clk_b),
+	SH_PFC_PIN_GROUP(scifb1_ctrl_b),
+	SH_PFC_PIN_GROUP(scifb1_data_c),
+	SH_PFC_PIN_GROUP(scifb1_data_d),
+	SH_PFC_PIN_GROUP(scifb1_data_e),
+	SH_PFC_PIN_GROUP(scifb1_clk_e),
+	SH_PFC_PIN_GROUP(scifb1_data_f),
+	SH_PFC_PIN_GROUP(scifb1_data_g),
+	SH_PFC_PIN_GROUP(scifb1_clk_g),
+	SH_PFC_PIN_GROUP(scifb2_data),
+	SH_PFC_PIN_GROUP(scifb2_clk),
+	SH_PFC_PIN_GROUP(scifb2_ctrl),
+	SH_PFC_PIN_GROUP(scifb2_data_b),
+	SH_PFC_PIN_GROUP(scifb2_clk_b),
+	SH_PFC_PIN_GROUP(scifb2_ctrl_b),
+	SH_PFC_PIN_GROUP(scifb2_data_c),
 };
 
 static const char * const eth_groups[] = {
@@ -1909,9 +2429,106 @@ static const char * const intc_groups[] = {
 	"intc_irq2",
 	"intc_irq3",
 };
+
+static const char * const scif0_groups[] = {
+	"scif0_data",
+	"scif0_clk",
+	"scif0_ctrl",
+	"scif0_data_b",
+};
+
+static const char * const scif1_groups[] = {
+	"scif1_data",
+	"scif1_clk",
+	"scif1_ctrl",
+	"scif1_data_b",
+	"scif1_data_c",
+	"scif1_data_d",
+	"scif1_clk_d",
+	"scif1_data_e",
+	"scif1_clk_e",
+};
+
+static const char * const scifa0_groups[] = {
+	"scifa0_data",
+	"scifa0_clk",
+	"scifa0_ctrl",
+	"scifa0_data_b",
+	"scifa0_clk_b",
+	"scifa0_ctrl_b",
+};
+
+static const char * const scifa1_groups[] = {
+	"scifa1_data",
+	"scifa1_clk",
+	"scifa1_ctrl",
+	"scifa1_data_b",
+	"scifa1_clk_b",
+	"scifa1_ctrl_b",
+	"scifa1_data_c",
+	"scifa1_clk_c",
+	"scifa1_ctrl_c",
+	"scifa1_data_d",
+	"scifa1_clk_d",
+	"scifa1_ctrl_d",
+};
+
+static const char * const scifa2_groups[] = {
+	"scifa2_data",
+	"scifa2_clk",
+	"scifa2_ctrl",
+	"scifa2_data_b",
+	"scifa2_data_c",
+	"scifa2_clk_c",
+};
+
+static const char * const scifb0_groups[] = {
+	"scifb0_data",
+	"scifb0_clk",
+	"scifb0_ctrl",
+	"scifb0_data_b",
+	"scifb0_clk_b",
+	"scifb0_ctrl_b",
+	"scifb0_data_c",
+};
+
+static const char * const scifb1_groups[] = {
+	"scifb1_data",
+	"scifb1_clk",
+	"scifb1_ctrl",
+	"scifb1_data_b",
+	"scifb1_clk_b",
+	"scifb1_ctrl_b",
+	"scifb1_data_c",
+	"scifb1_data_d",
+	"scifb1_data_e",
+	"scifb1_clk_e",
+	"scifb1_data_f",
+	"scifb1_data_g",
+	"scifb1_clk_g",
+};
+
+static const char * const scifb2_groups[] = {
+	"scifb2_data",
+	"scifb2_clk",
+	"scifb2_ctrl",
+	"scifb2_data_b",
+	"scifb2_clk_b",
+	"scifb2_ctrl_b",
+	"scifb2_data_c",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(eth),
 	SH_PFC_FUNCTION(intc),
+	SH_PFC_FUNCTION(scif0),
+	SH_PFC_FUNCTION(scif1),
+	SH_PFC_FUNCTION(scifa0),
+	SH_PFC_FUNCTION(scifa1),
+	SH_PFC_FUNCTION(scifa2),
+	SH_PFC_FUNCTION(scifb0),
+	SH_PFC_FUNCTION(scifb1),
+	SH_PFC_FUNCTION(scifb2),
 };
 
 #define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-- 
1.8.2.1

[PATCH 013/130] sh-pfc: r8a7790: Remove GPIO data

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

GPIOs are now handled by a separate driver, remove GPIO data from the
SoC information structure.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 133 +----------------------------------
 1 file changed, 1 insertion(+), 132 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 54c1e10..7716a1e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -52,32 +52,12 @@
 	CPU_32_PORT(fn, pfx##_5_, sfx)				\
 
 #define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN,	\
-				       GP##pfx##_IN, GP##pfx##_OUT)
-
-#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
-#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
+#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN)
 
 #define GP_ALL(str)	CPU_ALL_PORT(_PORT_ALL, GP, str)
 #define PINMUX_GPIO_GP_ALL()	CPU_ALL_PORT(_GP_GPIO, , unused)
 #define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_GP_DATA, , unused)
 
-
-#define PORT_10_REV(fn, pfx, sfx)				\
-	PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx),	\
-	PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx),	\
-	PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx),	\
-	PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx),	\
-	PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
-
-#define CPU_32_PORT_REV(fn, pfx, sfx)					\
-	PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx),		\
-	PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx),	\
-	PORT_10_REV(fn, pfx, sfx)
-
-#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
-#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
-
 #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
 #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
 							  FN_##ipsr, FN_##fn)
@@ -89,14 +69,6 @@ enum {
 	GP_ALL(DATA),
 	PINMUX_DATA_END,
 
-	PINMUX_INPUT_BEGIN,
-	GP_ALL(IN),
-	PINMUX_INPUT_END,
-
-	PINMUX_OUTPUT_BEGIN,
-	GP_ALL(OUT),
-	PINMUX_OUTPUT_END,
-
 	PINMUX_FUNCTION_BEGIN,
 	GP_ALL(FN),
 
@@ -3824,106 +3796,6 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
 		/* SEL_I2C1 [2] */
 		FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
 	},
-	{ PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
-	{ PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
-		0, 0,
-		0, 0,
-		GP_1_29_IN, GP_1_29_OUT,
-		GP_1_28_IN, GP_1_28_OUT,
-		GP_1_27_IN, GP_1_27_OUT,
-		GP_1_26_IN, GP_1_26_OUT,
-		GP_1_25_IN, GP_1_25_OUT,
-		GP_1_24_IN, GP_1_24_OUT,
-		GP_1_23_IN, GP_1_23_OUT,
-		GP_1_22_IN, GP_1_22_OUT,
-		GP_1_21_IN, GP_1_21_OUT,
-		GP_1_20_IN, GP_1_20_OUT,
-		GP_1_19_IN, GP_1_19_OUT,
-		GP_1_18_IN, GP_1_18_OUT,
-		GP_1_17_IN, GP_1_17_OUT,
-		GP_1_16_IN, GP_1_16_OUT,
-		GP_1_15_IN, GP_1_15_OUT,
-		GP_1_14_IN, GP_1_14_OUT,
-		GP_1_13_IN, GP_1_13_OUT,
-		GP_1_12_IN, GP_1_12_OUT,
-		GP_1_11_IN, GP_1_11_OUT,
-		GP_1_10_IN, GP_1_10_OUT,
-		GP_1_9_IN, GP_1_9_OUT,
-		GP_1_8_IN, GP_1_8_OUT,
-		GP_1_7_IN, GP_1_7_OUT,
-		GP_1_6_IN, GP_1_6_OUT,
-		GP_1_5_IN, GP_1_5_OUT,
-		GP_1_4_IN, GP_1_4_OUT,
-		GP_1_3_IN, GP_1_3_OUT,
-		GP_1_2_IN, GP_1_2_OUT,
-		GP_1_1_IN, GP_1_1_OUT,
-		GP_1_0_IN, GP_1_0_OUT, }
-	},
-	{ PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) {
-		0, 0,
-		0, 0,
-		GP_2_29_IN, GP_2_29_OUT,
-		GP_2_28_IN, GP_2_28_OUT,
-		GP_2_27_IN, GP_2_27_OUT,
-		GP_2_26_IN, GP_2_26_OUT,
-		GP_2_25_IN, GP_2_25_OUT,
-		GP_2_24_IN, GP_2_24_OUT,
-		GP_2_23_IN, GP_2_23_OUT,
-		GP_2_22_IN, GP_2_22_OUT,
-		GP_2_21_IN, GP_2_21_OUT,
-		GP_2_20_IN, GP_2_20_OUT,
-		GP_2_19_IN, GP_2_19_OUT,
-		GP_2_18_IN, GP_2_18_OUT,
-		GP_2_17_IN, GP_2_17_OUT,
-		GP_2_16_IN, GP_2_16_OUT,
-		GP_2_15_IN, GP_2_15_OUT,
-		GP_2_14_IN, GP_2_14_OUT,
-		GP_2_13_IN, GP_2_13_OUT,
-		GP_2_12_IN, GP_2_12_OUT,
-		GP_2_11_IN, GP_2_11_OUT,
-		GP_2_10_IN, GP_2_10_OUT,
-		GP_2_9_IN, GP_2_9_OUT,
-		GP_2_8_IN, GP_2_8_OUT,
-		GP_2_7_IN, GP_2_7_OUT,
-		GP_2_6_IN, GP_2_6_OUT,
-		GP_2_5_IN, GP_2_5_OUT,
-		GP_2_4_IN, GP_2_4_OUT,
-		GP_2_3_IN, GP_2_3_OUT,
-		GP_2_2_IN, GP_2_2_OUT,
-		GP_2_1_IN, GP_2_1_OUT,
-		GP_2_0_IN, GP_2_0_OUT, }
-	},
-	{ PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
-	{ PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
-	{ PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
-	{ },
-};
-
-static const struct pinmux_data_reg pinmux_data_regs[] = {
-	{ PINMUX_DATA_REG("INDT0", 0xE605000C, 32) { GP_INDT(0) } },
-	{ PINMUX_DATA_REG("INDT1", 0xE605100C, 32) {
-		0, 0, GP_1_29_DATA, GP_1_28_DATA,
-		GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA,
-		GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
-		GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
-		GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
-		GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
-		GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
-		GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
-	},
-	{ PINMUX_DATA_REG("INDT2", 0xE605200C, 32) {
-		0, 0, GP_2_29_DATA, GP_2_28_DATA,
-		GP_2_27_DATA, GP_2_26_DATA, GP_2_25_DATA, GP_2_24_DATA,
-		GP_2_23_DATA, GP_2_22_DATA, GP_2_21_DATA, GP_2_20_DATA,
-		GP_2_19_DATA, GP_2_18_DATA, GP_2_17_DATA, GP_2_16_DATA,
-		GP_2_15_DATA, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA,
-		GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA,
-		GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA,
-		GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA }
-	},
-	{ PINMUX_DATA_REG("INDT3", 0xE605300C, 32) { GP_INDT(3) } },
-	{ PINMUX_DATA_REG("INDT4", 0xE605400C, 32) { GP_INDT(4) } },
-	{ PINMUX_DATA_REG("INDT5", 0xE605500C, 32) { GP_INDT(5) } },
 	{ },
 };
 
@@ -3931,8 +3803,6 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = {
 	.name = "r8a77900_pfc",
 	.unlock_reg = 0xe6060000, /* PMMR */
 
-	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
 	.pins = pinmux_pins,
@@ -3946,7 +3816,6 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = {
 	.nr_func_gpios	= ARRAY_SIZE(pinmux_func_gpios),
 
 	.cfg_regs = pinmux_config_regs,
-	.data_regs = pinmux_data_regs,
 
 	.gpio_data = pinmux_data,
 	.gpio_data_size = ARRAY_SIZE(pinmux_data),
-- 
1.8.2.1

[PATCH 014/130] sh-pfc: r8a7790: Remove function GPIOs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

No r8a7770 platform use the function GPIOs API. Remove it.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[horms+renesas@verge.net.au: fixed typo in changelog: r8a7779 -> r8a7770]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 350 -----------------------------------
 1 file changed, 350 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 7716a1e..51219e1 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -2503,353 +2503,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(scifb2),
 };
 
-#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC_VBUS),
-	GPIO_FN(USB2_PWEN), GPIO_FN(USB2_OVC), GPIO_FN(AVS1), GPIO_FN(AVS2),
-	GPIO_FN(DU_DOTCLKIN0), GPIO_FN(DU_DOTCLKIN2),
-
-	/*IPSR0*/
-	GPIO_FN(D1), GPIO_FN(MSIOF3_SYNC_B), GPIO_FN(VI3_DATA1),
-	GPIO_FN(VI0_G5), GPIO_FN(VI0_G5_B), GPIO_FN(D2), GPIO_FN(MSIOF3_RXD_B),
-	GPIO_FN(VI3_DATA2), GPIO_FN(VI0_G6), GPIO_FN(VI0_G6_B), GPIO_FN(D3),
-	GPIO_FN(MSIOF3_TXD_B), GPIO_FN(VI3_DATA3), GPIO_FN(VI0_G7),
-	GPIO_FN(VI0_G7_B), GPIO_FN(D4), GPIO_FN(SCIFB1_RXD_F),
-	GPIO_FN(SCIFB0_RXD_C), GPIO_FN(VI3_DATA4), GPIO_FN(VI0_R0),
-	GPIO_FN(VI0_R0_B), GPIO_FN(RX0_B), GPIO_FN(D5), GPIO_FN(SCIFB1_TXD_F),
-	GPIO_FN(SCIFB0_TXD_C), GPIO_FN(VI3_DATA5), GPIO_FN(VI0_R1),
-	GPIO_FN(VI0_R1_B), GPIO_FN(TX0_B), GPIO_FN(D6), GPIO_FN(SCL2_C),
-	GPIO_FN(VI3_DATA6), GPIO_FN(VI0_R2), GPIO_FN(VI0_R2_B),
-	GPIO_FN(SCL2_CIS_C), GPIO_FN(D7), GPIO_FN(AD_DI_B), GPIO_FN(SDA2_C),
-	GPIO_FN(VI3_DATA7), GPIO_FN(VI0_R3), GPIO_FN(VI0_R3_B),
-	GPIO_FN(SDA2_CIS_C), GPIO_FN(D8), GPIO_FN(SCIFA1_SCK_C),
-	GPIO_FN(AVB_TXD0), GPIO_FN(MII_TXD0), GPIO_FN(VI0_G0),
-	GPIO_FN(VI0_G0_B), GPIO_FN(VI2_DATA0_VI2_B0),
-
-	/*IPSR1*/
-	GPIO_FN(D9), GPIO_FN(SCIFA1_RXD_C), GPIO_FN(AVB_TXD1),
-	GPIO_FN(MII_TXD1), GPIO_FN(VI0_G1), GPIO_FN(VI0_G1_B),
-	GPIO_FN(VI2_DATA1_VI2_B1), GPIO_FN(D10), GPIO_FN(SCIFA1_TXD_C),
-	GPIO_FN(AVB_TXD2), GPIO_FN(MII_TXD2), GPIO_FN(VI0_G2),
-	GPIO_FN(VI0_G2_B), GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(D11),
-	GPIO_FN(SCIFA1_CTS_N_C), GPIO_FN(AVB_TXD3), GPIO_FN(MII_TXD3),
-	GPIO_FN(VI0_G3), GPIO_FN(VI0_G3_B), GPIO_FN(VI2_DATA3_VI2_B3),
-	GPIO_FN(D12), GPIO_FN(SCIFA1_RTS_N_C), GPIO_FN(AVB_TXD4),
-	GPIO_FN(VI0_HSYNC_N), GPIO_FN(VI0_HSYNC_N_B), GPIO_FN(VI2_DATA4_VI2_B4),
-	GPIO_FN(D13), GPIO_FN(AVB_TXD5), GPIO_FN(VI0_VSYNC_N),
-	GPIO_FN(VI0_VSYNC_N_B), GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(D14),
-	GPIO_FN(SCIFB1_RXD_C), GPIO_FN(AVB_TXD6), GPIO_FN(RX1_B),
-	GPIO_FN(VI0_CLKENB), GPIO_FN(VI0_CLKENB_B), GPIO_FN(VI2_DATA6_VI2_B6),
-	GPIO_FN(D15), GPIO_FN(SCIFB1_TXD_C), GPIO_FN(AVB_TXD7), GPIO_FN(TX1_B),
-	GPIO_FN(VI0_FIELD), GPIO_FN(VI0_FIELD_B), GPIO_FN(VI2_DATA7_VI2_B7),
-	GPIO_FN(A0), GPIO_FN(PWM3), GPIO_FN(A1), GPIO_FN(PWM4),
-
-	/*IPSR2*/
-	GPIO_FN(A2), GPIO_FN(PWM5), GPIO_FN(MSIOF1_SS1_B), GPIO_FN(A3),
-	GPIO_FN(PWM6), GPIO_FN(MSIOF1_SS2_B), GPIO_FN(A4),
-	GPIO_FN(MSIOF1_TXD_B), GPIO_FN(TPU0TO0), GPIO_FN(A5),
-	GPIO_FN(SCIFA1_TXD_B), GPIO_FN(TPU0TO1), GPIO_FN(A6),
-	GPIO_FN(SCIFA1_RTS_N_B), GPIO_FN(TPU0TO2), GPIO_FN(A7),
-	GPIO_FN(SCIFA1_SCK_B), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(TPU0TO3),
-	GPIO_FN(A8), GPIO_FN(SCIFA1_RXD_B), GPIO_FN(SSI_SCK5_B),
-	GPIO_FN(VI0_R4), GPIO_FN(VI0_R4_B), GPIO_FN(SCIFB2_RXD_C),
-	GPIO_FN(VI2_DATA0_VI2_B0_B), GPIO_FN(A9), GPIO_FN(SCIFA1_CTS_N_B),
-	GPIO_FN(SSI_WS5_B), GPIO_FN(VI0_R5), GPIO_FN(VI0_R5_B),
-	GPIO_FN(SCIFB2_TXD_C), GPIO_FN(VI2_DATA1_VI2_B1_B), GPIO_FN(A10),
-	GPIO_FN(SSI_SDATA5_B), GPIO_FN(MSIOF2_SYNC), GPIO_FN(VI0_R6),
-	GPIO_FN(VI0_R6_B), GPIO_FN(VI2_DATA2_VI2_B2_B),
-
-	/*IPSR3*/
-	GPIO_FN(A11), GPIO_FN(SCIFB2_CTS_N_B), GPIO_FN(MSIOF2_SCK),
-	GPIO_FN(VI1_R0), GPIO_FN(VI1_R0_B), GPIO_FN(VI2_G0),
-	GPIO_FN(VI2_DATA3_VI2_B3_B), GPIO_FN(A12), GPIO_FN(SCIFB2_RXD_B),
-	GPIO_FN(MSIOF2_TXD), GPIO_FN(VI1_R1), GPIO_FN(VI1_R1_B),
-	GPIO_FN(VI2_G1), GPIO_FN(VI2_DATA4_VI2_B4_B), GPIO_FN(A13),
-	GPIO_FN(SCIFB2_RTS_N_B), GPIO_FN(EX_WAIT2), GPIO_FN(MSIOF2_RXD),
-	GPIO_FN(VI1_R2), GPIO_FN(VI1_R2_B), GPIO_FN(VI2_G2),
-	GPIO_FN(VI2_DATA5_VI2_B5_B), GPIO_FN(A14), GPIO_FN(SCIFB2_TXD_B),
-	GPIO_FN(ATACS11_N), GPIO_FN(MSIOF2_SS1), GPIO_FN(A15),
-	GPIO_FN(SCIFB2_SCK_B), GPIO_FN(ATARD1_N), GPIO_FN(MSIOF2_SS2),
-	GPIO_FN(A16), GPIO_FN(ATAWR1_N), GPIO_FN(A17), GPIO_FN(AD_DO_B),
-	GPIO_FN(ATADIR1_N), GPIO_FN(A18), GPIO_FN(AD_CLK_B), GPIO_FN(ATAG1_N),
-	GPIO_FN(A19), GPIO_FN(AD_NCS_N_B), GPIO_FN(ATACS01_N),
-	GPIO_FN(EX_WAIT0_B), GPIO_FN(A20), GPIO_FN(SPCLK), GPIO_FN(VI1_R3),
-	GPIO_FN(VI1_R3_B), GPIO_FN(VI2_G4),
-
-	/*IPSR4*/
-	GPIO_FN(A21), GPIO_FN(MOSI_IO0), GPIO_FN(VI1_R4), GPIO_FN(VI1_R4_B),
-	GPIO_FN(VI2_G5), GPIO_FN(A22), GPIO_FN(MISO_IO1), GPIO_FN(VI1_R5),
-	GPIO_FN(VI1_R5_B), GPIO_FN(VI2_G6), GPIO_FN(A23), GPIO_FN(IO2),
-	GPIO_FN(VI1_G7), GPIO_FN(VI1_G7_B), GPIO_FN(VI2_G7), GPIO_FN(A24),
-	GPIO_FN(IO3), GPIO_FN(VI1_R7), GPIO_FN(VI1_R7_B), GPIO_FN(VI2_CLKENB),
-	GPIO_FN(VI2_CLKENB_B), GPIO_FN(A25), GPIO_FN(SSL), GPIO_FN(VI1_G6),
-	GPIO_FN(VI1_G6_B), GPIO_FN(VI2_FIELD), GPIO_FN(VI2_FIELD_B),
-	GPIO_FN(CS0_N), GPIO_FN(VI1_R6), GPIO_FN(VI1_R6_B), GPIO_FN(VI2_G3),
-	GPIO_FN(MSIOF0_SS2_B), GPIO_FN(CS1_N_A26), GPIO_FN(SPEEDIN),
-	GPIO_FN(VI0_R7), GPIO_FN(VI0_R7_B), GPIO_FN(VI2_CLK),
-	GPIO_FN(VI2_CLK_B), GPIO_FN(EX_CS0_N), GPIO_FN(HRX1_B),
-	GPIO_FN(VI1_G5), GPIO_FN(VI1_G5_B), GPIO_FN(VI2_R0), GPIO_FN(HTX0_B),
-	GPIO_FN(MSIOF0_SS1_B), GPIO_FN(EX_CS1_N), GPIO_FN(GPS_CLK),
-	GPIO_FN(HCTS1_N_B), GPIO_FN(VI1_FIELD), GPIO_FN(VI1_FIELD_B),
-	GPIO_FN(VI2_R1), GPIO_FN(EX_CS2_N), GPIO_FN(GPS_SIGN),
-	GPIO_FN(HRTS1_N_B), GPIO_FN(VI3_CLKENB), GPIO_FN(VI1_G0),
-	GPIO_FN(VI1_G0_B), GPIO_FN(VI2_R2),
-
-	/*IPSR5*/
-	GPIO_FN(EX_CS3_N), GPIO_FN(GPS_MAG), GPIO_FN(VI3_FIELD),
-	GPIO_FN(VI1_G1), GPIO_FN(VI1_G1_B), GPIO_FN(VI2_R3), GPIO_FN(EX_CS4_N),
-	GPIO_FN(MSIOF1_SCK_B), GPIO_FN(VI3_HSYNC_N), GPIO_FN(VI2_HSYNC_N),
-	GPIO_FN(SCL1), GPIO_FN(VI2_HSYNC_N_B), GPIO_FN(INTC_EN0_N),
-	GPIO_FN(SCL1_CIS), GPIO_FN(EX_CS5_N), GPIO_FN(CAN0_RX),
-	GPIO_FN(MSIOF1_RXD_B), GPIO_FN(VI3_VSYNC_N), GPIO_FN(VI1_G2),
-	GPIO_FN(VI1_G2_B), GPIO_FN(VI2_R4), GPIO_FN(SDA1), GPIO_FN(INTC_EN1_N),
-	GPIO_FN(SDA1_CIS), GPIO_FN(BS_N), GPIO_FN(IETX), GPIO_FN(HTX1_B),
-	GPIO_FN(CAN1_TX), GPIO_FN(DRACK0), GPIO_FN(IETX_C), GPIO_FN(RD_N),
-	GPIO_FN(CAN0_TX), GPIO_FN(SCIFA0_SCK_B), GPIO_FN(RD_WR_N),
-	GPIO_FN(VI1_G3), GPIO_FN(VI1_G3_B), GPIO_FN(VI2_R5),
-	GPIO_FN(SCIFA0_RXD_B), GPIO_FN(INTC_IRQ4_N), GPIO_FN(WE0_N),
-	GPIO_FN(IECLK), GPIO_FN(CAN_CLK), GPIO_FN(VI2_VSYNC_N),
-	GPIO_FN(SCIFA0_TXD_B), GPIO_FN(VI2_VSYNC_N_B), GPIO_FN(WE1_N),
-	GPIO_FN(IERX), GPIO_FN(CAN1_RX), GPIO_FN(VI1_G4), GPIO_FN(VI1_G4_B),
-	GPIO_FN(VI2_R6), GPIO_FN(SCIFA0_CTS_N_B), GPIO_FN(IERX_C),
-	GPIO_FN(EX_WAIT0), GPIO_FN(IRQ3), GPIO_FN(INTC_IRQ3_N),
-	GPIO_FN(VI3_CLK), GPIO_FN(SCIFA0_RTS_N_B), GPIO_FN(HRX0_B),
-	GPIO_FN(MSIOF0_SCK_B), GPIO_FN(DREQ0_N), GPIO_FN(VI1_HSYNC_N),
-	GPIO_FN(VI1_HSYNC_N_B), GPIO_FN(VI2_R7), GPIO_FN(SSI_SCK78_C),
-	GPIO_FN(SSI_WS78_B),
-
-	/*IPSR6*/
-	GPIO_FN(DACK0), GPIO_FN(IRQ0), GPIO_FN(INTC_IRQ0_N),
-	GPIO_FN(SSI_SCK6_B), GPIO_FN(VI1_VSYNC_N), GPIO_FN(VI1_VSYNC_N_B),
-	GPIO_FN(SSI_WS78_C), GPIO_FN(DREQ1_N), GPIO_FN(VI1_CLKENB),
-	GPIO_FN(VI1_CLKENB_B), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SSI_SCK78_B),
-	GPIO_FN(DACK1), GPIO_FN(IRQ1), GPIO_FN(INTC_IRQ1_N), GPIO_FN(SSI_WS6_B),
-	GPIO_FN(SSI_SDATA8_C), GPIO_FN(DREQ2_N), GPIO_FN(HSCK1_B),
-	GPIO_FN(HCTS0_N_B), GPIO_FN(MSIOF0_TXD_B), GPIO_FN(DACK2),
-	GPIO_FN(IRQ2), GPIO_FN(INTC_IRQ2_N), GPIO_FN(SSI_SDATA6_B),
-	GPIO_FN(HRTS0_N_B), GPIO_FN(MSIOF0_RXD_B), GPIO_FN(ETH_CRS_DV),
-	GPIO_FN(RMII_CRS_DV), GPIO_FN(STP_ISCLK_0_B), GPIO_FN(TS_SDEN0_D),
-	GPIO_FN(GLO_Q0_C), GPIO_FN(SCL2_E), GPIO_FN(SCL2_CIS_E),
-	GPIO_FN(ETH_RX_ER), GPIO_FN(RMII_RX_ER), GPIO_FN(STP_ISD_0_B),
-	GPIO_FN(TS_SPSYNC0_D), GPIO_FN(GLO_Q1_C), GPIO_FN(SDA2_E),
-	GPIO_FN(SDA2_CIS_E), GPIO_FN(ETH_RXD0), GPIO_FN(RMII_RXD0),
-	GPIO_FN(STP_ISEN_0_B), GPIO_FN(TS_SDAT0_D), GPIO_FN(GLO_I0_C),
-	GPIO_FN(SCIFB1_SCK_G), GPIO_FN(SCK1_E), GPIO_FN(ETH_RXD1),
-	GPIO_FN(RMII_RXD1), GPIO_FN(HRX0_E), GPIO_FN(STP_ISSYNC_0_B),
-	GPIO_FN(TS_SCK0_D), GPIO_FN(GLO_I1_C), GPIO_FN(SCIFB1_RXD_G),
-	GPIO_FN(RX1_E), GPIO_FN(ETH_LINK), GPIO_FN(RMII_LINK), GPIO_FN(HTX0_E),
-	GPIO_FN(STP_IVCXO27_0_B), GPIO_FN(SCIFB1_TXD_G), GPIO_FN(TX1_E),
-	GPIO_FN(ETH_REF_CLK), GPIO_FN(RMII_REF_CLK), GPIO_FN(HCTS0_N_E),
-	GPIO_FN(STP_IVCXO27_1_B), GPIO_FN(HRX0_F),
-
-	/*IPSR7*/
-	GPIO_FN(ETH_MDIO), GPIO_FN(RMII_MDIO), GPIO_FN(HRTS0_N_E),
-	GPIO_FN(SIM0_D_C), GPIO_FN(HCTS0_N_F), GPIO_FN(ETH_TXD1),
-	GPIO_FN(RMII_TXD1), GPIO_FN(HTX0_F), GPIO_FN(BPFCLK_G),
-	GPIO_FN(RDS_CLK_F), GPIO_FN(ETH_TX_EN), GPIO_FN(RMII_TX_EN),
-	GPIO_FN(SIM0_CLK_C), GPIO_FN(HRTS0_N_F), GPIO_FN(ETH_MAGIC),
-	GPIO_FN(RMII_MAGIC), GPIO_FN(SIM0_RST_C), GPIO_FN(ETH_TXD0),
-	GPIO_FN(RMII_TXD0), GPIO_FN(STP_ISCLK_1_B), GPIO_FN(TS_SDEN1_C),
-	GPIO_FN(GLO_SCLK_C), GPIO_FN(ETH_MDC), GPIO_FN(RMII_MDC),
-	GPIO_FN(STP_ISD_1_B), GPIO_FN(TS_SPSYNC1_C), GPIO_FN(GLO_SDATA_C),
-	GPIO_FN(PWM0), GPIO_FN(SCIFA2_SCK_C), GPIO_FN(STP_ISEN_1_B),
-	GPIO_FN(TS_SDAT1_C), GPIO_FN(GLO_SS_C), GPIO_FN(PWM1),
-	GPIO_FN(SCIFA2_TXD_C), GPIO_FN(STP_ISSYNC_1_B), GPIO_FN(TS_SCK1_C),
-	GPIO_FN(GLO_RFON_C), GPIO_FN(PCMOE_N), GPIO_FN(PWM2), GPIO_FN(PWMFSW0),
-	GPIO_FN(SCIFA2_RXD_C), GPIO_FN(PCMWE_N), GPIO_FN(IECLK_C),
-	GPIO_FN(DU1_DOTCLKIN), GPIO_FN(AUDIO_CLKC), GPIO_FN(AUDIO_CLKOUT_C),
-	GPIO_FN(VI0_CLK), GPIO_FN(ATACS00_N), GPIO_FN(AVB_RXD1),
-	GPIO_FN(MII_RXD1), GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(ATACS10_N),
-	GPIO_FN(AVB_RXD2), GPIO_FN(MII_RXD2),
-
-	/*IPSR8*/
-	GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(ATARD0_N), GPIO_FN(AVB_RXD3),
-	GPIO_FN(MII_RXD3), GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(ATAWR0_N),
-	GPIO_FN(AVB_RXD4), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(ATADIR0_N),
-	GPIO_FN(AVB_RXD5), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(ATAG0_N),
-	GPIO_FN(AVB_RXD6), GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(EX_WAIT1),
-	GPIO_FN(AVB_RXD7), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(AVB_RX_ER),
-	GPIO_FN(MII_RX_ER), GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(AVB_RX_CLK),
-	GPIO_FN(MII_RX_CLK), GPIO_FN(VI1_CLK), GPIO_FN(AVB_RX_DV),
-	GPIO_FN(MII_RX_DV), GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SCIFA1_SCK_D),
-	GPIO_FN(AVB_CRS), GPIO_FN(MII_CRS), GPIO_FN(VI1_DATA1_VI1_B1),
-	GPIO_FN(SCIFA1_RXD_D), GPIO_FN(AVB_MDC), GPIO_FN(MII_MDC),
-	GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SCIFA1_TXD_D), GPIO_FN(AVB_MDIO),
-	GPIO_FN(MII_MDIO), GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SCIFA1_CTS_N_D),
-	GPIO_FN(AVB_GTX_CLK), GPIO_FN(VI1_DATA4_VI1_B4),
-	GPIO_FN(SCIFA1_RTS_N_D), GPIO_FN(AVB_MAGIC), GPIO_FN(MII_MAGIC),
-	GPIO_FN(VI1_DATA5_VI1_B5), GPIO_FN(AVB_PHY_INT),
-	GPIO_FN(VI1_DATA6_VI1_B6), GPIO_FN(AVB_GTXREFCLK),
-	GPIO_FN(SD0_CLK), GPIO_FN(VI1_DATA0_VI1_B0_B), GPIO_FN(SD0_CMD),
-	GPIO_FN(SCIFB1_SCK_B), GPIO_FN(VI1_DATA1_VI1_B1_B),
-
-	/*IPSR9*/
-	GPIO_FN(SD0_DAT0), GPIO_FN(SCIFB1_RXD_B), GPIO_FN(VI1_DATA2_VI1_B2_B),
-	GPIO_FN(SD0_DAT1), GPIO_FN(SCIFB1_TXD_B), GPIO_FN(VI1_DATA3_VI1_B3_B),
-	GPIO_FN(SD0_DAT2), GPIO_FN(SCIFB1_CTS_N_B), GPIO_FN(VI1_DATA4_VI1_B4_B),
-	GPIO_FN(SD0_DAT3), GPIO_FN(SCIFB1_RTS_N_B), GPIO_FN(VI1_DATA5_VI1_B5_B),
-	GPIO_FN(SD0_CD), GPIO_FN(MMC0_D6), GPIO_FN(TS_SDEN0_B),
-	GPIO_FN(USB0_EXTP), GPIO_FN(GLO_SCLK), GPIO_FN(VI1_DATA6_VI1_B6_B),
-	GPIO_FN(SCL1_B), GPIO_FN(SCL1_CIS_B), GPIO_FN(VI2_DATA6_VI2_B6_B),
-	GPIO_FN(SD0_WP), GPIO_FN(MMC0_D7), GPIO_FN(TS_SPSYNC0_B),
-	GPIO_FN(USB0_IDIN), GPIO_FN(GLO_SDATA), GPIO_FN(VI1_DATA7_VI1_B7_B),
-	GPIO_FN(SDA1_B), GPIO_FN(SDA1_CIS_B), GPIO_FN(VI2_DATA7_VI2_B7_B),
-	GPIO_FN(SD1_CLK), GPIO_FN(AVB_TX_EN), GPIO_FN(MII_TX_EN),
-	GPIO_FN(SD1_CMD), GPIO_FN(AVB_TX_ER), GPIO_FN(MII_TX_ER),
-	GPIO_FN(SCIFB0_SCK_B), GPIO_FN(SD1_DAT0), GPIO_FN(AVB_TX_CLK),
-	GPIO_FN(MII_TX_CLK), GPIO_FN(SCIFB0_RXD_B), GPIO_FN(SD1_DAT1),
-	GPIO_FN(AVB_LINK), GPIO_FN(MII_LINK), GPIO_FN(SCIFB0_TXD_B),
-	GPIO_FN(SD1_DAT2), GPIO_FN(AVB_COL), GPIO_FN(MII_COL),
-	GPIO_FN(SCIFB0_CTS_N_B), GPIO_FN(SD1_DAT3), GPIO_FN(AVB_RXD0),
-	GPIO_FN(MII_RXD0), GPIO_FN(SCIFB0_RTS_N_B), GPIO_FN(SD1_CD),
-	GPIO_FN(MMC1_D6), GPIO_FN(TS_SDEN1), GPIO_FN(USB1_EXTP),
-	GPIO_FN(GLO_SS), GPIO_FN(VI0_CLK_B), GPIO_FN(SCL2_D),
-	GPIO_FN(SCL2_CIS_D), GPIO_FN(SIM0_CLK_B), GPIO_FN(VI3_CLK_B),
-
-	/*IPSR10*/
-	GPIO_FN(SD1_WP), GPIO_FN(MMC1_D7), GPIO_FN(TS_SPSYNC1),
-	GPIO_FN(USB1_IDIN), GPIO_FN(GLO_RFON), GPIO_FN(VI1_CLK_B),
-	GPIO_FN(SDA2_D), GPIO_FN(SDA2_CIS_D), GPIO_FN(SIM0_D_B),
-	GPIO_FN(SD2_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(SIM0_CLK),
-	GPIO_FN(VI0_DATA0_VI0_B0_B), GPIO_FN(TS_SDEN0_C), GPIO_FN(GLO_SCLK_B),
-	GPIO_FN(VI3_DATA0_B), GPIO_FN(SD2_CMD), GPIO_FN(MMC0_CMD),
-	GPIO_FN(SIM0_D), GPIO_FN(VI0_DATA1_VI0_B1_B), GPIO_FN(SCIFB1_SCK_E),
-	GPIO_FN(SCK1_D), GPIO_FN(TS_SPSYNC0_C), GPIO_FN(GLO_SDATA_B),
-	GPIO_FN(VI3_DATA1_B), GPIO_FN(SD2_DAT0), GPIO_FN(MMC0_D0),
-	GPIO_FN(FMCLK_B), GPIO_FN(VI0_DATA2_VI0_B2_B), GPIO_FN(SCIFB1_RXD_E),
-	GPIO_FN(RX1_D), GPIO_FN(TS_SDAT0_C), GPIO_FN(GLO_SS_B),
-	GPIO_FN(VI3_DATA2_B), GPIO_FN(SD2_DAT1), GPIO_FN(MMC0_D1),
-	GPIO_FN(FMIN_B), GPIO_FN(RDS_DATA), GPIO_FN(VI0_DATA3_VI0_B3_B),
-	GPIO_FN(SCIFB1_TXD_E), GPIO_FN(TX1_D), GPIO_FN(TS_SCK0_C),
-	GPIO_FN(GLO_RFON_B), GPIO_FN(VI3_DATA3_B), GPIO_FN(SD2_DAT2),
-	GPIO_FN(MMC0_D2), GPIO_FN(BPFCLK_B), GPIO_FN(RDS_CLK),
-	GPIO_FN(VI0_DATA4_VI0_B4_B), GPIO_FN(HRX0_D), GPIO_FN(TS_SDEN1_B),
-	GPIO_FN(GLO_Q0_B), GPIO_FN(VI3_DATA4_B), GPIO_FN(SD2_DAT3),
-	GPIO_FN(MMC0_D3), GPIO_FN(SIM0_RST), GPIO_FN(VI0_DATA5_VI0_B5_B),
-	GPIO_FN(HTX0_D), GPIO_FN(TS_SPSYNC1_B), GPIO_FN(GLO_Q1_B),
-	GPIO_FN(VI3_DATA5_B), GPIO_FN(SD2_CD), GPIO_FN(MMC0_D4),
-	GPIO_FN(TS_SDAT0_B), GPIO_FN(USB2_EXTP), GPIO_FN(GLO_I0),
-	GPIO_FN(VI0_DATA6_VI0_B6_B), GPIO_FN(HCTS0_N_D), GPIO_FN(TS_SDAT1_B),
-	GPIO_FN(GLO_I0_B), GPIO_FN(VI3_DATA6_B),
-
-	/*IPSR11*/
-	GPIO_FN(SD2_WP), GPIO_FN(MMC0_D5), GPIO_FN(TS_SCK0_B),
-	GPIO_FN(USB2_IDIN), GPIO_FN(GLO_I1), GPIO_FN(VI0_DATA7_VI0_B7_B),
-	GPIO_FN(HRTS0_N_D), GPIO_FN(TS_SCK1_B), GPIO_FN(GLO_I1_B),
-	GPIO_FN(VI3_DATA7_B), GPIO_FN(SD3_CLK), GPIO_FN(MMC1_CLK),
-	GPIO_FN(SD3_CMD), GPIO_FN(MMC1_CMD), GPIO_FN(MTS_N), GPIO_FN(SD3_DAT0),
-	GPIO_FN(MMC1_D0), GPIO_FN(STM_N), GPIO_FN(SD3_DAT1), GPIO_FN(MMC1_D1),
-	GPIO_FN(MDATA), GPIO_FN(SD3_DAT2), GPIO_FN(MMC1_D2), GPIO_FN(SDATA),
-	GPIO_FN(SD3_DAT3), GPIO_FN(MMC1_D3), GPIO_FN(SCKZ), GPIO_FN(SD3_CD),
-	GPIO_FN(MMC1_D4), GPIO_FN(TS_SDAT1), GPIO_FN(VSP), GPIO_FN(GLO_Q0),
-	GPIO_FN(SIM0_RST_B), GPIO_FN(SD3_WP), GPIO_FN(MMC1_D5),
-	GPIO_FN(TS_SCK1), GPIO_FN(GLO_Q1), GPIO_FN(FMIN_C), GPIO_FN(RDS_DATA_B),
-	GPIO_FN(FMIN_E), GPIO_FN(RDS_DATA_D), GPIO_FN(FMIN_F),
-	GPIO_FN(RDS_DATA_E), GPIO_FN(MLB_CLK), GPIO_FN(SCL2_B),
-	GPIO_FN(SCL2_CIS_B), GPIO_FN(MLB_SIG), GPIO_FN(SCIFB1_RXD_D),
-	GPIO_FN(RX1_C), GPIO_FN(SDA2_B), GPIO_FN(SDA2_CIS_B), GPIO_FN(MLB_DAT),
-	GPIO_FN(SPV_EVEN), GPIO_FN(SCIFB1_TXD_D), GPIO_FN(TX1_C),
-	GPIO_FN(BPFCLK_C), GPIO_FN(RDS_CLK_B), GPIO_FN(SSI_SCK0129),
-	GPIO_FN(CAN_CLK_B), GPIO_FN(MOUT0),
-
-	/*IPSR12*/
-	GPIO_FN(SSI_WS0129), GPIO_FN(CAN0_TX_B), GPIO_FN(MOUT1),
-	GPIO_FN(SSI_SDATA0), GPIO_FN(CAN0_RX_B), GPIO_FN(MOUT2),
-	GPIO_FN(SSI_SDATA1), GPIO_FN(CAN1_TX_B), GPIO_FN(MOUT5),
-	GPIO_FN(SSI_SDATA2), GPIO_FN(CAN1_RX_B), GPIO_FN(SSI_SCK1),
-	GPIO_FN(MOUT6), GPIO_FN(SSI_SCK34), GPIO_FN(STP_OPWM_0),
-	GPIO_FN(SCIFB0_SCK), GPIO_FN(MSIOF1_SCK), GPIO_FN(CAN_DEBUG_HW_TRIGGER),
-	GPIO_FN(SSI_WS34), GPIO_FN(STP_IVCXO27_0), GPIO_FN(SCIFB0_RXD),
-	GPIO_FN(MSIOF1_SYNC), GPIO_FN(CAN_STEP0), GPIO_FN(SSI_SDATA3),
-	GPIO_FN(STP_ISCLK_0), GPIO_FN(SCIFB0_TXD), GPIO_FN(MSIOF1_SS1),
-	GPIO_FN(CAN_TXCLK), GPIO_FN(SSI_SCK4), GPIO_FN(STP_ISD_0),
-	GPIO_FN(SCIFB0_CTS_N), GPIO_FN(MSIOF1_SS2), GPIO_FN(SSI_SCK5_C),
-	GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(SSI_WS4), GPIO_FN(STP_ISEN_0),
-	GPIO_FN(SCIFB0_RTS_N), GPIO_FN(MSIOF1_TXD), GPIO_FN(SSI_WS5_C),
-	GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(SSI_SDATA4), GPIO_FN(STP_ISSYNC_0),
-	GPIO_FN(MSIOF1_RXD), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(SSI_SCK5),
-	GPIO_FN(SCIFB1_SCK), GPIO_FN(IERX_B), GPIO_FN(DU2_EXHSYNC_DU2_HSYNC),
-	GPIO_FN(QSTH_QHS), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(SSI_WS5),
-	GPIO_FN(SCIFB1_RXD), GPIO_FN(IECLK_B), GPIO_FN(DU2_EXVSYNC_DU2_VSYNC),
-	GPIO_FN(QSTB_QHE), GPIO_FN(CAN_DEBUGOUT4),
-
-	/*IPSR13*/
-	GPIO_FN(SSI_SDATA5), GPIO_FN(SCIFB1_TXD), GPIO_FN(IETX_B),
-	GPIO_FN(DU2_DR2), GPIO_FN(LCDOUT2), GPIO_FN(CAN_DEBUGOUT5),
-	GPIO_FN(SSI_SCK6), GPIO_FN(SCIFB1_CTS_N), GPIO_FN(BPFCLK_D),
-	GPIO_FN(RDS_CLK_C), GPIO_FN(DU2_DR3), GPIO_FN(LCDOUT3),
-	GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(BPFCLK_F), GPIO_FN(RDS_CLK_E),
-	GPIO_FN(SSI_WS6), GPIO_FN(SCIFB1_RTS_N), GPIO_FN(CAN0_TX_D),
-	GPIO_FN(DU2_DR4), GPIO_FN(LCDOUT4), GPIO_FN(CAN_DEBUGOUT7),
-	GPIO_FN(SSI_SDATA6), GPIO_FN(FMIN_D), GPIO_FN(RDS_DATA_C),
-	GPIO_FN(DU2_DR5), GPIO_FN(LCDOUT5), GPIO_FN(CAN_DEBUGOUT8),
-	GPIO_FN(SSI_SCK78), GPIO_FN(STP_IVCXO27_1), GPIO_FN(SCK1),
-	GPIO_FN(SCIFA1_SCK), GPIO_FN(DU2_DR6), GPIO_FN(LCDOUT6),
-	GPIO_FN(CAN_DEBUGOUT9), GPIO_FN(SSI_WS78), GPIO_FN(STP_ISCLK_1),
-	GPIO_FN(SCIFB2_SCK), GPIO_FN(SCIFA2_CTS_N), GPIO_FN(DU2_DR7),
-	GPIO_FN(LCDOUT7), GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SSI_SDATA7),
-	GPIO_FN(STP_ISD_1), GPIO_FN(SCIFB2_RXD), GPIO_FN(SCIFA2_RTS_N),
-	GPIO_FN(TCLK2), GPIO_FN(QSTVA_QVS), GPIO_FN(CAN_DEBUGOUT11),
-	GPIO_FN(BPFCLK_E), GPIO_FN(RDS_CLK_D), GPIO_FN(SSI_SDATA7_B),
-	GPIO_FN(FMIN_G), GPIO_FN(RDS_DATA_F), GPIO_FN(SSI_SDATA8),
-	GPIO_FN(STP_ISEN_1), GPIO_FN(SCIFB2_TXD), GPIO_FN(CAN0_TX_C),
-	GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SDATA8_B), GPIO_FN(SSI_SDATA9),
-	GPIO_FN(STP_ISSYNC_1), GPIO_FN(SCIFB2_CTS_N), GPIO_FN(SSI_WS1),
-	GPIO_FN(SSI_SDATA5_C), GPIO_FN(CAN_DEBUGOUT13), GPIO_FN(AUDIO_CLKA),
-	GPIO_FN(SCIFB2_RTS_N), GPIO_FN(CAN_DEBUGOUT14),
-
-	/*IPSR14*/
-	GPIO_FN(AUDIO_CLKB), GPIO_FN(SCIF_CLK), GPIO_FN(CAN0_RX_D),
-	GPIO_FN(DVC_MUTE), GPIO_FN(CAN0_RX_C), GPIO_FN(CAN_DEBUGOUT15),
-	GPIO_FN(REMOCON), GPIO_FN(SCIFA0_SCK), GPIO_FN(HSCK1), GPIO_FN(SCK0),
-	GPIO_FN(MSIOF3_SS2), GPIO_FN(DU2_DG2), GPIO_FN(LCDOUT10),
-	GPIO_FN(SDA1_C), GPIO_FN(SDA1_CIS_C), GPIO_FN(SCIFA0_RXD),
-	GPIO_FN(HRX1), GPIO_FN(RX0), GPIO_FN(DU2_DR0), GPIO_FN(LCDOUT0),
-	GPIO_FN(SCIFA0_TXD), GPIO_FN(HTX1), GPIO_FN(TX0), GPIO_FN(DU2_DR1),
-	GPIO_FN(LCDOUT1), GPIO_FN(SCIFA0_CTS_N), GPIO_FN(HCTS1_N),
-	GPIO_FN(CTS0_N), GPIO_FN(MSIOF3_SYNC), GPIO_FN(DU2_DG3),
-	GPIO_FN(LCDOUT11), GPIO_FN(PWM0_B), GPIO_FN(SCL1_C),
-	GPIO_FN(SCL1_CIS_C), GPIO_FN(SCIFA0_RTS_N), GPIO_FN(HRTS1_N),
-	GPIO_FN(RTS0_N_TANS), GPIO_FN(MSIOF3_SS1), GPIO_FN(DU2_DG0),
-	GPIO_FN(LCDOUT8), GPIO_FN(PWM1_B), GPIO_FN(SCIFA1_RXD), GPIO_FN(AD_DI),
-	GPIO_FN(RX1), GPIO_FN(DU2_EXODDF_DU2_ODDF_DISP_CDE), GPIO_FN(QCPV_QDE),
-	GPIO_FN(SCIFA1_TXD), GPIO_FN(AD_DO), GPIO_FN(TX1), GPIO_FN(DU2_DG1),
-	GPIO_FN(LCDOUT9), GPIO_FN(SCIFA1_CTS_N), GPIO_FN(AD_CLK),
-	GPIO_FN(CTS1_N), GPIO_FN(MSIOF3_RXD), GPIO_FN(DU0_DOTCLKOUT),
-	GPIO_FN(QCLK), GPIO_FN(SCIFA1_RTS_N), GPIO_FN(AD_NCS_N),
-	GPIO_FN(RTS1_N_TANS), GPIO_FN(MSIOF3_TXD), GPIO_FN(DU1_DOTCLKOUT),
-	GPIO_FN(QSTVB_QVE), GPIO_FN(HRTS0_N_C),
-
-	/*IPSR15*/
-	GPIO_FN(SCIFA2_SCK), GPIO_FN(FMCLK), GPIO_FN(MSIOF3_SCK),
-	GPIO_FN(DU2_DG7), GPIO_FN(LCDOUT15), GPIO_FN(SCIF_CLK_B),
-	GPIO_FN(SCIFA2_RXD), GPIO_FN(FMIN), GPIO_FN(DU2_DB0),
-	GPIO_FN(LCDOUT16), GPIO_FN(SCL2), GPIO_FN(SCL2_CIS),
-	GPIO_FN(SCIFA2_TXD), GPIO_FN(BPFCLK), GPIO_FN(DU2_DB1),
-	GPIO_FN(LCDOUT17), GPIO_FN(SDA2), GPIO_FN(SDA2_CIS), GPIO_FN(HSCK0),
-	GPIO_FN(TS_SDEN0), GPIO_FN(DU2_DG4), GPIO_FN(LCDOUT12),
-	GPIO_FN(HCTS0_N_C), GPIO_FN(HRX0), GPIO_FN(DU2_DB2), GPIO_FN(LCDOUT18),
-	GPIO_FN(HTX0), GPIO_FN(DU2_DB3), GPIO_FN(LCDOUT19), GPIO_FN(HCTS0_N),
-	GPIO_FN(SSI_SCK9), GPIO_FN(DU2_DB4), GPIO_FN(LCDOUT20),
-	GPIO_FN(HRTS0_N), GPIO_FN(SSI_WS9), GPIO_FN(DU2_DB5),
-	GPIO_FN(LCDOUT21), GPIO_FN(MSIOF0_SCK), GPIO_FN(TS_SDAT0),
-	GPIO_FN(ADICLK), GPIO_FN(DU2_DB6), GPIO_FN(LCDOUT22),
-	GPIO_FN(MSIOF0_SYNC), GPIO_FN(TS_SCK0), GPIO_FN(SSI_SCK2),
-	GPIO_FN(ADIDATA), GPIO_FN(DU2_DB7), GPIO_FN(LCDOUT23),
-	GPIO_FN(SCIFA2_RXD_B), GPIO_FN(MSIOF0_SS1), GPIO_FN(ADICHS0),
-	GPIO_FN(DU2_DG5), GPIO_FN(LCDOUT13), GPIO_FN(MSIOF0_TXD),
-	GPIO_FN(ADICHS1), GPIO_FN(DU2_DG6), GPIO_FN(LCDOUT14),
-
-	/*IPSR16*/
-	GPIO_FN(MSIOF0_SS2), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(ADICHS2),
-	GPIO_FN(DU2_DISP), GPIO_FN(QPOLA), GPIO_FN(HTX0_C),
-	GPIO_FN(SCIFA2_TXD_B), GPIO_FN(MSIOF0_RXD), GPIO_FN(TS_SPSYNC0),
-	GPIO_FN(SSI_WS2), GPIO_FN(ADICS_SAMP), GPIO_FN(DU2_CDE),
-	GPIO_FN(QPOLB), GPIO_FN(HRX0_C), GPIO_FN(USB1_PWEN),
-	GPIO_FN(AUDIO_CLKOUT_D), GPIO_FN(USB1_OVC), GPIO_FN(TCLK1_B),
-};
-
 static struct pinmux_cfg_reg pinmux_config_regs[] = {
 	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
 		GP_0_31_FN, FN_IP3_17_15,
@@ -3812,9 +3465,6 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = {
 	.functions = pinmux_functions,
 	.nr_functions = ARRAY_SIZE(pinmux_functions),
 
-	.func_gpios	= pinmux_func_gpios,
-	.nr_func_gpios	= ARRAY_SIZE(pinmux_func_gpios),
-
 	.cfg_regs = pinmux_config_regs,
 
 	.gpio_data = pinmux_data,
-- 
1.8.2.1

[PATCH 015/130] sh-pfc: r8a7790: Don't use GPIO enum entries

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Refactor the GPIO macro magic to use GPIO numbers directly instead of
the GPIO_GP_x_y enum entries. This will allow removing the GPIO enum
entries from the mach/r8a7790.h header.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 90 ++++++++++++++++++++++++------------
 1 file changed, 60 insertions(+), 30 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 51219e1..1656915 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -24,39 +24,69 @@
 #include <linux/kernel.h>
 #include <linux/platform_data/gpio-rcar.h>
 
-#include <mach/r8a7790.h>
-
 #include "core.h"
 #include "sh_pfc.h"
 
-#define CPU_32_PORT(fn, pfx, sfx)				\
-	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
-	PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx),	\
-	PORT_1(fn, pfx##31, sfx)
-
-#define CPU_32_PORT1(fn, pfx, sfx)				\
-	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
-	PORT_10(fn, pfx##2, sfx)
-
-#define CPU_32_PORT2(fn, pfx, sfx)				\
-	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
-	PORT_10(fn, pfx##2, sfx)
-
-/* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */
-#define CPU_ALL_PORT(fn, pfx, sfx)				\
-	CPU_32_PORT(fn, pfx##_0_, sfx),				\
-	CPU_32_PORT1(fn, pfx##_1_, sfx),			\
-	CPU_32_PORT2(fn, pfx##_2_, sfx),			\
-	CPU_32_PORT(fn, pfx##_3_, sfx),				\
-	CPU_32_PORT(fn, pfx##_4_, sfx),				\
-	CPU_32_PORT(fn, pfx##_5_, sfx)				\
-
-#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN)
-
-#define GP_ALL(str)	CPU_ALL_PORT(_PORT_ALL, GP, str)
-#define PINMUX_GPIO_GP_ALL()	CPU_ALL_PORT(_GP_GPIO, , unused)
-#define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_GP_DATA, , unused)
+#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
+
+#define PORT_GP_32(bank, fn, sfx)					\
+	PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),	\
+	PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),	\
+	PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),	\
+	PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),	\
+	PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),	\
+	PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),	\
+	PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),	\
+	PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),	\
+	PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),	\
+	PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),	\
+	PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),	\
+	PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),	\
+	PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),	\
+	PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx),	\
+	PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx),	\
+	PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
+
+#define PORT_GP_32_REV(bank, fn, sfx)					\
+	PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),	\
+	PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),	\
+	PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),	\
+	PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),	\
+	PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),	\
+	PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),	\
+	PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),	\
+	PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),	\
+	PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),	\
+	PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),	\
+	PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),	\
+	PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),	\
+	PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),	\
+	PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),	\
+	PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),	\
+	PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)
+
+#define CPU_ALL_PORT(fn, sfx)						\
+	PORT_GP_32(0, fn, sfx),						\
+	PORT_GP_32(1, fn, sfx),						\
+	PORT_GP_32(2, fn, sfx),						\
+	PORT_GP_32(3, fn, sfx),						\
+	PORT_GP_32(4, fn, sfx),						\
+	PORT_GP_32(5, fn, sfx)
+
+#define _GP_PORT_ALL(bank, pin, name, sfx)	name##_##sfx
+
+#define _GP_GPIO(bank, pin, _name, sfx)					\
+	[(bank * 32) + pin] = {						\
+		.name = __stringify(_name),				\
+		.enum_id = _name##_DATA,				\
+	}
+
+#define _GP_DATA(bank, pin, name, sfx)					\
+	PINMUX_DATA(name##_DATA, name##_FN)
+
+#define GP_ALL(str)		CPU_ALL_PORT(_GP_PORT_ALL, str)
+#define PINMUX_GPIO_GP_ALL()	CPU_ALL_PORT(_GP_GPIO, unused)
+#define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_GP_DATA, unused)
 
 #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
 #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
-- 
1.8.2.1

[PATCH 016/130] sh-pfc: Add r8a7778 pinmux support

[Simon Horman]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
---
 drivers/pinctrl/sh-pfc/Kconfig       |    5 +
 drivers/pinctrl/sh-pfc/Makefile      |    1 +
 drivers/pinctrl/sh-pfc/core.c        |    3 +
 drivers/pinctrl/sh-pfc/core.h        |    1 +
 drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 2369 ++++++++++++++++++++++++++++++++++
 5 files changed, 2379 insertions(+)
 create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a7778.c

diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index a0b6bd0..32161c4 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -30,6 +30,11 @@ config PINCTRL_PFC_R8A7740
 	depends on ARCH_R8A7740
 	select PINCTRL_SH_PFC
 
+config PINCTRL_PFC_R8A7778
+	def_bool y
+	depends on ARCH_R8A7778
+	select PINCTRL_SH_PFC
+
 config PINCTRL_PFC_R8A7779
 	def_bool y
 	depends on ARCH_R8A7779
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 1cbf5b1..5e0c222 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -5,6 +5,7 @@ endif
 obj-$(CONFIG_PINCTRL_SH_PFC)	+= sh-pfc.o
 obj-$(CONFIG_PINCTRL_PFC_R8A73A4)	+= pfc-r8a73a4.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7740)	+= pfc-r8a7740.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7778)	+= pfc-r8a7778.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7779)	+= pfc-r8a7779.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7790)	+= pfc-r8a7790.o
 obj-$(CONFIG_PINCTRL_PFC_SH7203)	+= pfc-sh7203.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index db0d6f7..4540ce3 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -424,6 +424,9 @@ static const struct platform_device_id sh_pfc_id_table[] = {
 #ifdef CONFIG_PINCTRL_PFC_R8A7740
 	{ "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
 #endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7778
+	{ "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
+#endif
 #ifdef CONFIG_PINCTRL_PFC_R8A7779
 	{ "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
 #endif
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 6ec746f..e847afb 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -57,6 +57,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
 
 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
 extern const struct sh_pfc_soc_info sh7203_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
new file mode 100644
index 0000000..ddbd27b
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -0,0 +1,2369 @@
+/*
+ * r8a7778 processor support - PFC hardware block
+ *
+ * Copyright (C) 2013  Renesas Solutions Corp.
+ * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * based on
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/platform_data/gpio-rcar.h>
+#include <linux/kernel.h>
+#include "sh_pfc.h"
+
+#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
+
+#define PORT_GP_32(bank, fn, sfx)					\
+	PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),	\
+	PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),	\
+	PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),	\
+	PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),	\
+	PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),	\
+	PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),	\
+	PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),	\
+	PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),	\
+	PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),	\
+	PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),	\
+	PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),	\
+	PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),	\
+	PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),	\
+	PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx),	\
+	PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx),	\
+	PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
+
+#define PORT_GP_27(bank, fn, sfx)					\
+	PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),	\
+	PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),	\
+	PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),	\
+	PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),	\
+	PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),	\
+	PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),	\
+	PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),	\
+	PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),	\
+	PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),	\
+	PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),	\
+	PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),	\
+	PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),	\
+	PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),	\
+	PORT_GP_1(bank, 26, fn, sfx)
+
+#define CPU_ALL_PORT(fn, sfx)		\
+	PORT_GP_32(0, fn, sfx),		\
+	PORT_GP_32(1, fn, sfx),		\
+	PORT_GP_32(2, fn, sfx),		\
+	PORT_GP_32(3, fn, sfx),		\
+	PORT_GP_27(4, fn, sfx)
+
+#define _GP_PORT_ALL(bank, pin, name, sfx)	name##_##sfx
+
+#define _GP_GPIO(bank, pin, _name, sfx)		\
+	[RCAR_GP_PIN(bank, pin)] = {		\
+		.name = __stringify(_name),	\
+		.enum_id = _name##_DATA,	\
+	}
+
+#define _GP_DATA(bank, pin, name, sfx)		\
+	PINMUX_DATA(name##_DATA, name##_FN)
+
+#define GP_ALL(str)		CPU_ALL_PORT(_GP_PORT_ALL, str)
+#define PINMUX_GPIO_GP_ALL()	CPU_ALL_PORT(_GP_GPIO, unused)
+#define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_GP_DATA, unused)
+
+#define PINMUX_IPSR_NOGP(ispr, fn)	PINMUX_DATA(fn##_MARK, FN_##fn)
+#define PINMUX_IPSR_DATA(ipsr, fn)	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
+#define PINMUX_IPSR_MSEL(ipsr, fn, ms)	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
+#define PINMUX_IPSR_NOGM(ispr, fn, ms)	PINMUX_DATA(fn##_MARK, FN_##fn,            FN_##ms)
+
+enum {
+	PINMUX_RESERVED = 0,
+
+	PINMUX_DATA_BEGIN,
+	GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */
+	PINMUX_DATA_END,
+
+	PINMUX_FUNCTION_BEGIN,
+	GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */
+
+	/* GPSR0 */
+	FN_IP0_1_0,	FN_PENC0,	FN_PENC1,	FN_IP0_4_2,
+	FN_IP0_7_5,	FN_IP0_11_8,	FN_IP0_14_12,	FN_A1,
+	FN_A2,		FN_A3,		FN_IP0_15,	FN_IP0_16,
+	FN_IP0_17,	FN_IP0_18,	FN_IP0_19,	FN_IP0_20,
+	FN_IP0_21,	FN_IP0_22,	FN_IP0_23,	FN_IP0_24,
+	FN_IP0_25,	FN_IP0_26,	FN_IP0_27,	FN_IP0_28,
+	FN_IP0_29,	FN_IP0_30,	FN_IP1_0,	FN_IP1_1,
+	FN_IP1_4_2,	FN_IP1_7_5,	FN_IP1_10_8,	FN_IP1_14_11,
+
+	/* GPSR1 */
+	FN_IP1_23_21,	FN_WE0,		FN_IP1_24,	FN_IP1_27_25,
+	FN_IP1_29_28,	FN_IP2_2_0,	FN_IP2_5_3,	FN_IP2_8_6,
+	FN_IP2_11_9,	FN_IP2_13_12,	FN_IP2_16_14,	FN_IP2_17,
+	FN_IP2_30,	FN_IP2_31,	FN_IP3_1_0,	FN_IP3_4_2,
+	FN_IP3_7_5,	FN_IP3_9_8,	FN_IP3_12_10,	FN_IP3_15_13,
+	FN_IP3_18_16,	FN_IP3_20_19,	FN_IP3_23_21,	FN_IP3_26_24,
+	FN_IP3_27,	FN_IP3_28,	FN_IP3_29,	FN_IP3_30,
+	FN_IP3_31,	FN_IP4_0,	FN_IP4_3_1,	FN_IP4_6_4,
+
+	/* GPSR2 */
+	FN_IP4_7,	FN_IP4_8,	FN_IP4_10_9,	FN_IP4_12_11,
+	FN_IP4_14_13,	FN_IP4_16_15,	FN_IP4_20_17,	FN_IP4_24_21,
+	FN_IP4_26_25,	FN_IP4_28_27,	FN_IP4_30_29,	FN_IP5_1_0,
+	FN_IP5_3_2,	FN_IP5_5_4,	FN_IP5_6,	FN_IP5_7,
+	FN_IP5_9_8,	FN_IP5_11_10,	FN_IP5_12,	FN_IP5_14_13,
+	FN_IP5_17_15,	FN_IP5_20_18,	FN_AUDIO_CLKA,	FN_AUDIO_CLKB,
+	FN_IP5_22_21,	FN_IP5_25_23,	FN_IP5_28_26,	FN_IP5_30_29,
+	FN_IP6_1_0,	FN_IP6_4_2,	FN_IP6_6_5,	FN_IP6_7,
+
+	/* GPSR3 */
+	FN_IP6_8,	FN_IP6_9,	FN_SSI_SCK34,	FN_IP6_10,
+	FN_IP6_12_11,	FN_IP6_13,	FN_IP6_15_14,	FN_IP6_16,
+	FN_IP6_18_17,	FN_IP6_20_19,	FN_IP6_21,	FN_IP6_23_22,
+	FN_IP6_25_24,	FN_IP6_27_26,	FN_IP6_29_28,	FN_IP6_31_30,
+	FN_IP7_1_0,	FN_IP7_3_2,	FN_IP7_5_4,	FN_IP7_8_6,
+	FN_IP7_11_9,	FN_IP7_14_12,	FN_IP7_17_15,	FN_IP7_20_18,
+	FN_IP7_21,	FN_IP7_24_22,	FN_IP7_28_25,	FN_IP7_31_29,
+	FN_IP8_2_0,	FN_IP8_5_3,	FN_IP8_8_6,	FN_IP8_10_9,
+
+	/* GPSR4 */
+	FN_IP8_13_11,	FN_IP8_15_14,	FN_IP8_18_16,	FN_IP8_21_19,
+	FN_IP8_23_22,	FN_IP8_26_24,	FN_IP8_29_27,	FN_IP9_2_0,
+	FN_IP9_5_3,	FN_IP9_8_6,	FN_IP9_11_9,	FN_IP9_14_12,
+	FN_IP9_17_15,	FN_IP9_20_18,	FN_IP9_23_21,	FN_IP9_26_24,
+	FN_IP9_29_27,	FN_IP10_2_0,	FN_IP10_5_3,	FN_IP10_8_6,
+	FN_IP10_12_9,	FN_IP10_15_13,	FN_IP10_18_16,	FN_IP10_21_19,
+	FN_IP10_24_22,	FN_AVS1,	FN_AVS2,
+
+	/* IPSR0 */
+	FN_PRESETOUT,	FN_PWM1,	FN_AUDATA0,	FN_ARM_TRACEDATA_0,
+	FN_GPSCLK_C,	FN_USB_OVC0,	FN_TX2_E,	FN_SDA2_B,
+	FN_AUDATA1,	FN_ARM_TRACEDATA_1,		FN_GPSIN_C,
+	FN_USB_OVC1,	FN_RX2_E,	FN_SCL2_B,	FN_SD1_DAT2_A,
+	FN_MMC_D2,	FN_BS,		FN_ATADIR0_A,	FN_SDSELF_A,
+	FN_PWM4_B,	FN_SD1_DAT3_A,	FN_MMC_D3,	FN_A0,
+	FN_ATAG0_A,	FN_REMOCON_B,	FN_A4,		FN_A5,
+	FN_A6,		FN_A7,		FN_A8,		FN_A9,
+	FN_A10,		FN_A11,		FN_A12,		FN_A13,
+	FN_A14,		FN_A15,		FN_A16,		FN_A17,
+	FN_A18,		FN_A19,
+
+	/* IPSR1 */
+	FN_A20,		FN_HSPI_CS1_B,	FN_A21,		FN_HSPI_CLK1_B,
+	FN_A22,		FN_HRTS0_B,	FN_RX2_B,	FN_DREQ2_A,
+	FN_A23,		FN_HTX0_B,	FN_TX2_B,	FN_DACK2_A,
+	FN_TS_SDEN0_A,	FN_SD1_CD_A,	FN_MMC_D6,	FN_A24,
+	FN_DREQ1_A,	FN_HRX0_B,	FN_TS_SPSYNC0_A,
+	FN_SD1_WP_A,	FN_MMC_D7,	FN_A25,	FN_DACK1_A,
+	FN_HCTS0_B,	FN_RX3_C,	FN_TS_SDAT0_A,	FN_CLKOUT,
+	FN_HSPI_TX1_B,	FN_PWM0_B,	FN_CS0,		FN_HSPI_RX1_B,
+	FN_SSI_SCK1_B,	FN_ATAG0_B,	FN_CS1_A26,	FN_SDA2_A,
+	FN_SCK2_B,	FN_MMC_D5,	FN_ATADIR0_B,	FN_RD_WR,
+	FN_WE1,		FN_ATAWR0_B,	FN_SSI_WS1_B,	FN_EX_CS0,
+	FN_SCL2_A,	FN_TX3_C,	FN_TS_SCK0_A,	FN_EX_CS1,
+	FN_MMC_D4,
+
+	/* IPSR2 */
+	FN_SD1_CLK_A,	FN_MMC_CLK,	FN_ATACS00,	FN_EX_CS2,
+	FN_SD1_CMD_A,	FN_MMC_CMD,	FN_ATACS10,	FN_EX_CS3,
+	FN_SD1_DAT0_A,	FN_MMC_D0,	FN_ATARD0,	FN_EX_CS4,
+	FN_EX_WAIT1_A,	FN_SD1_DAT1_A,	FN_MMC_D1,	FN_ATAWR0_A,
+	FN_EX_CS5,	FN_EX_WAIT2_A,	FN_DREQ0_A,	FN_RX3_A,
+	FN_DACK0,	FN_TX3_A,	FN_DRACK0,	FN_EX_WAIT0,
+	FN_PWM0_C,	FN_D0,		FN_D1,		FN_D2,
+	FN_D3,		FN_D4,		FN_D5,		FN_D6,
+	FN_D7,		FN_D8,		FN_D9,		FN_D10,
+	FN_D11,		FN_RD_WR_B,	FN_IRQ0,	FN_MLB_CLK,
+	FN_IRQ1_A,
+
+	/* IPSR3 */
+	FN_MLB_SIG,	FN_RX5_B,	FN_SDA3_A,	FN_IRQ2_A,
+	FN_MLB_DAT,	FN_TX5_B,	FN_SCL3_A,	FN_IRQ3_A,
+	FN_SDSELF_B,	FN_SD1_CMD_B,	FN_SCIF_CLK,	FN_AUDIO_CLKOUT_B,
+	FN_CAN_CLK_B,	FN_SDA3_B,	FN_SD1_CLK_B,	FN_HTX0_A,
+	FN_TX0_A,	FN_SD1_DAT0_B,	FN_HRX0_A,	FN_RX0_A,
+	FN_SD1_DAT1_B,	FN_HSCK0,	FN_SCK0,	FN_SCL3_B,
+	FN_SD1_DAT2_B,	FN_HCTS0_A,	FN_CTS0,	FN_SD1_DAT3_B,
+	FN_HRTS0_A,	FN_RTS0,	FN_SSI_SCK4,	FN_DU0_DR0,
+	FN_LCDOUT0,	FN_AUDATA2,	FN_ARM_TRACEDATA_2,
+	FN_SDA3_C,	FN_ADICHS1,	FN_TS_SDEN0_B,	FN_SSI_WS4,
+	FN_DU0_DR1,	FN_LCDOUT1,	FN_AUDATA3,	FN_ARM_TRACEDATA_3,
+	FN_SCL3_C,	FN_ADICHS2,	FN_TS_SPSYNC0_B,
+	FN_DU0_DR2,	FN_LCDOUT2,	FN_DU0_DR3,	FN_LCDOUT3,
+	FN_DU0_DR4,	FN_LCDOUT4,	FN_DU0_DR5,	FN_LCDOUT5,
+	FN_DU0_DR6,	FN_LCDOUT6,
+
+	/* IPSR4 */
+	FN_DU0_DR7,	FN_LCDOUT7,	FN_DU0_DG0,	FN_LCDOUT8,
+	FN_AUDATA4,	FN_ARM_TRACEDATA_4,		FN_TX1_D,
+	FN_CAN0_TX_A,	FN_ADICHS0,	FN_DU0_DG1,	FN_LCDOUT9,
+	FN_AUDATA5,	FN_ARM_TRACEDATA_5,		FN_RX1_D,
+	FN_CAN0_RX_A,	FN_ADIDATA,	FN_DU0_DG2,	FN_LCDOUT10,
+	FN_DU0_DG3,	FN_LCDOUT11,	FN_DU0_DG4,	FN_LCDOUT12,
+	FN_RX0_B,	FN_DU0_DG5,	FN_LCDOUT13,	FN_TX0_B,
+	FN_DU0_DG6,	FN_LCDOUT14,	FN_RX4_A,	FN_DU0_DG7,
+	FN_LCDOUT15,	FN_TX4_A,	FN_SSI_SCK2_B,	FN_VI0_R0_B,
+	FN_DU0_DB0,	FN_LCDOUT16,	FN_AUDATA6,	FN_ARM_TRACEDATA_6,
+	FN_GPSCLK_A,	FN_PWM0_A,	FN_ADICLK,	FN_TS_SDAT0_B,
+	FN_AUDIO_CLKC,	FN_VI0_R1_B,	FN_DU0_DB1,	FN_LCDOUT17,
+	FN_AUDATA7,	FN_ARM_TRACEDATA_7,		FN_GPSIN_A,
+	FN_ADICS_SAMP,	FN_TS_SCK0_B,	FN_VI0_R2_B,	FN_DU0_DB2,
+	FN_LCDOUT18,	FN_VI0_R3_B,	FN_DU0_DB3,	FN_LCDOUT19,
+	FN_VI0_R4_B,	FN_DU0_DB4,	FN_LCDOUT20,
+
+	/* IPSR5 */
+	FN_VI0_R5_B,	FN_DU0_DB5,	FN_LCDOUT21,	FN_VI1_DATA10_B,
+	FN_DU0_DB6,	FN_LCDOUT22,	FN_VI1_DATA11_B,
+	FN_DU0_DB7,	FN_LCDOUT23,	FN_DU0_DOTCLKIN,
+	FN_QSTVA_QVS,	FN_DU0_DOTCLKO_UT0,		FN_QCLK,
+	FN_DU0_DOTCLKO_UT1,		FN_QSTVB_QVE,	FN_AUDIO_CLKOUT_A,
+	FN_REMOCON_C,	FN_SSI_WS2_B,	FN_DU0_EXHSYNC_DU0_HSYNC,
+	FN_QSTH_QHS,	FN_DU0_EXVSYNC_DU0_VSYNC,	FN_QSTB_QHE,
+	FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,
+	FN_QCPV_QDE,	FN_FMCLK_D,	FN_SSI_SCK1_A,	FN_DU0_DISP,
+	FN_QPOLA,	FN_AUDCK,	FN_ARM_TRACECLK,
+	FN_BPFCLK_D,	FN_SSI_WS1_A,	FN_DU0_CDE,	FN_QPOLB,
+	FN_AUDSYNC,	FN_ARM_TRACECTL,		FN_FMIN_D,
+	FN_SD1_CD_B,	FN_SSI_SCK78,	FN_HSPI_RX0_B,	FN_TX1_B,
+	FN_SD1_WP_B,	FN_SSI_WS78,	FN_HSPI_CLK0_B,	FN_RX1_B,
+	FN_CAN_CLK_D,	FN_SSI_SDATA8,	FN_SSI_SCK2_A,	FN_HSPI_CS0_B,
+	FN_TX2_A,	FN_CAN0_TX_B,	FN_SSI_SDATA7,	FN_HSPI_TX0_B,
+	FN_RX2_A,	FN_CAN0_RX_B,
+
+	/* IPSR6 */
+	FN_SSI_SCK6,	FN_HSPI_RX2_A,	FN_FMCLK_B,	FN_CAN1_TX_B,
+	FN_SSI_WS6,	FN_HSPI_CLK2_A,	FN_BPFCLK_B,	FN_CAN1_RX_B,
+	FN_SSI_SDATA6,	FN_HSPI_TX2_A,	FN_FMIN_B,	FN_SSI_SCK5,
+	FN_RX4_C,	FN_SSI_WS5,	FN_TX4_C,	FN_SSI_SDATA5,
+	FN_RX0_D,	FN_SSI_WS34,	FN_ARM_TRACEDATA_8,
+	FN_SSI_SDATA4,	FN_SSI_WS2_A,	FN_ARM_TRACEDATA_9,
+	FN_SSI_SDATA3,	FN_ARM_TRACEDATA_10,
+	FN_SSI_SCK012,	FN_ARM_TRACEDATA_11,
+	FN_TX0_D,	FN_SSI_WS012,	FN_ARM_TRACEDATA_12,
+	FN_SSI_SDATA2,	FN_HSPI_CS2_A,	FN_ARM_TRACEDATA_13,
+	FN_SDA1_A,	FN_SSI_SDATA1,	FN_ARM_TRACEDATA_14,
+	FN_SCL1_A,	FN_SCK2_A,	FN_SSI_SDATA0,
+	FN_ARM_TRACEDATA_15,
+	FN_SD0_CLK,	FN_SUB_TDO,	FN_SD0_CMD,	FN_SUB_TRST,
+	FN_SD0_DAT0,	FN_SUB_TMS,	FN_SD0_DAT1,	FN_SUB_TCK,
+	FN_SD0_DAT2,	FN_SUB_TDI,
+
+	/* IPSR7 */
+	FN_SD0_DAT3,	FN_IRQ1_B,	FN_SD0_CD,	FN_TX5_A,
+	FN_SD0_WP,	FN_RX5_A,	FN_VI1_CLKENB,	FN_HSPI_CLK0_A,
+	FN_HTX1_A,	FN_RTS1_C,	FN_VI1_FIELD,	FN_HSPI_CS0_A,
+	FN_HRX1_A,	FN_SCK1_C,	FN_VI1_HSYNC,	FN_HSPI_RX0_A,
+	FN_HRTS1_A,	FN_FMCLK_A,	FN_RX1_C,	FN_VI1_VSYNC,
+	FN_HSPI_TX0,	FN_HCTS1_A,	FN_BPFCLK_A,	FN_TX1_C,
+	FN_TCLK0,	FN_HSCK1_A,	FN_FMIN_A,	FN_IRQ2_C,
+	FN_CTS1_C,	FN_SPEEDIN,	FN_VI0_CLK,	FN_CAN_CLK_A,
+	FN_VI0_CLKENB,	FN_SD2_DAT2_B,	FN_VI1_DATA0,	FN_DU1_DG6,
+	FN_HSPI_RX1_A,	FN_RX4_B,	FN_VI0_FIELD,	FN_SD2_DAT3_B,
+	FN_VI0_R3_C,	FN_VI1_DATA1,	FN_DU1_DG7,	FN_HSPI_CLK1_A,
+	FN_TX4_B,	FN_VI0_HSYNC,	FN_SD2_CD_B,	FN_VI1_DATA2,
+	FN_DU1_DR2,	FN_HSPI_CS1_A,	FN_RX3_B,
+
+	/* IPSR8 */
+	FN_VI0_VSYNC,	FN_SD2_WP_B,	FN_VI1_DATA3,	FN_DU1_DR3,
+	FN_HSPI_TX1_A,	FN_TX3_B,	FN_VI0_DATA0_VI0_B0,
+	FN_DU1_DG2,	FN_IRQ2_B,	FN_RX3_D,	FN_VI0_DATA1_VI0_B1,
+	FN_DU1_DG3,	FN_IRQ3_B,	FN_TX3_D,	FN_VI0_DATA2_VI0_B2,
+	FN_DU1_DG4,	FN_RX0_C,	FN_VI0_DATA3_VI0_B3,
+	FN_DU1_DG5,	FN_TX1_A,	FN_TX0_C,	FN_VI0_DATA4_VI0_B4,
+	FN_DU1_DB2,	FN_RX1_A,	FN_VI0_DATA5_VI0_B5,
+	FN_DU1_DB3,	FN_SCK1_A,	FN_PWM4,	FN_HSCK1_B,
+	FN_VI0_DATA6_VI0_G0,		FN_DU1_DB4,	FN_CTS1_A,
+	FN_PWM5,	FN_VI0_DATA7_VI0_G1,		FN_DU1_DB5,
+	FN_RTS1_A,	FN_VI0_G2,	FN_SD2_CLK_B,	FN_VI1_DATA4,
+	FN_DU1_DR4,	FN_HTX1_B,	FN_VI0_G3,	FN_SD2_CMD_B,
+	FN_VI1_DATA5,	FN_DU1_DR5,	FN_HRX1_B,
+
+	/* IPSR9 */
+	FN_VI0_G4,	FN_SD2_DAT0_B,	FN_VI1_DATA6,	FN_DU1_DR6,
+	FN_HRTS1_B,	FN_VI0_G5,	FN_SD2_DAT1_B,	FN_VI1_DATA7,
+	FN_DU1_DR7,	FN_HCTS1_B,	FN_VI0_R0_A,	FN_VI1_CLK,
+	FN_ETH_REF_CLK,	FN_DU1_DOTCLKIN,		FN_VI0_R1_A,
+	FN_VI1_DATA8,	FN_DU1_DB6,	FN_ETH_TXD0,	FN_PWM2,
+	FN_TCLK1,	FN_VI0_R2_A,	FN_VI1_DATA9,	FN_DU1_DB7,
+	FN_ETH_TXD1,	FN_PWM3,	FN_VI0_R3_A,	FN_ETH_CRS_DV,
+	FN_IECLK,	FN_SCK2_C,	FN_VI0_R4_A,	FN_ETH_TX_EN,
+	FN_IETX,	FN_TX2_C,	FN_VI0_R5_A,	FN_ETH_RX_ER,
+	FN_FMCLK_C,	FN_IERX,	FN_RX2_C,	FN_VI1_DATA10_A,
+	FN_DU1_DOTCLKOUT,		FN_ETH_RXD0,	FN_BPFCLK_C,
+	FN_TX2_D,	FN_SDA2_C,	FN_VI1_DATA11_A,
+	FN_DU1_EXHSYNC_DU1_HSYNC,	FN_ETH_RXD1,	FN_FMIN_C,
+	FN_RX2_D,	FN_SCL2_C,
+
+	/* IPSR10 */
+	FN_SD2_CLK_A,	FN_DU1_EXVSYNC_DU1_VSYNC,	FN_ATARD1,
+	FN_ETH_MDC,	FN_SDA1_B,	FN_SD2_CMD_A,
+	FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,		FN_ATAWR1,
+	FN_ETH_MDIO,	FN_SCL1_B,	FN_SD2_DAT0_A,	FN_DU1_DISP,
+	FN_ATACS01,	FN_DREQ1_B,	FN_ETH_LINK,	FN_CAN1_RX_A,
+	FN_SD2_DAT1_A,	FN_DU1_CDE,	FN_ATACS11,	FN_DACK1_B,
+	FN_ETH_MAGIC,	FN_CAN1_TX_A,	FN_PWM6,	FN_SD2_DAT2_A,
+	FN_VI1_DATA12,	FN_DREQ2_B,	FN_ATADIR1,	FN_HSPI_CLK2_B,
+	FN_GPSCLK_B,	FN_SD2_DAT3_A,	FN_VI1_DATA13,	FN_DACK2_B,
+	FN_ATAG1,	FN_HSPI_CS2_B,	FN_GPSIN_B,	FN_SD2_CD_A,
+	FN_VI1_DATA14,	FN_EX_WAIT1_B,	FN_DREQ0_B,	FN_HSPI_RX2_B,
+	FN_REMOCON_A,	FN_SD2_WP_A,	FN_VI1_DATA15,	FN_EX_WAIT2_B,
+	FN_DACK0_B,	FN_HSPI_TX2_B,	FN_CAN_CLK_C,
+
+	/* SEL */
+	FN_SEL_SCIF5_A,	FN_SEL_SCIF5_B,
+	FN_SEL_SCIF4_A,	FN_SEL_SCIF4_B,	FN_SEL_SCIF4_C,
+	FN_SEL_SCIF3_A,	FN_SEL_SCIF3_B,	FN_SEL_SCIF3_C,	FN_SEL_SCIF3_D,
+	FN_SEL_SCIF2_A,	FN_SEL_SCIF2_B,	FN_SEL_SCIF2_C,	FN_SEL_SCIF2_D,	FN_SEL_SCIF2_E,
+	FN_SEL_SCIF1_A,	FN_SEL_SCIF1_B,	FN_SEL_SCIF1_C,	FN_SEL_SCIF1_D,
+	FN_SEL_SCIF0_A,	FN_SEL_SCIF0_B,	FN_SEL_SCIF0_C,	FN_SEL_SCIF0_D,
+	FN_SEL_SSI2_A,	FN_SEL_SSI2_B,
+	FN_SEL_SSI1_A,	FN_SEL_SSI1_B,
+	FN_SEL_VI1_A,	FN_SEL_VI1_B,
+	FN_SEL_VI0_A,	FN_SEL_VI0_B,	FN_SEL_VI0_C,	FN_SEL_VI0_D,
+	FN_SEL_SD2_A,	FN_SEL_SD2_B,
+	FN_SEL_SD1_A,	FN_SEL_SD1_B,
+	FN_SEL_IRQ3_A,	FN_SEL_IRQ3_B,
+	FN_SEL_IRQ2_A,	FN_SEL_IRQ2_B,	FN_SEL_IRQ2_C,
+	FN_SEL_IRQ1_A,	FN_SEL_IRQ1_B,
+	FN_SEL_DREQ2_A,	FN_SEL_DREQ2_B,
+	FN_SEL_DREQ1_A,	FN_SEL_DREQ1_B,
+	FN_SEL_DREQ0_A,	FN_SEL_DREQ0_B,
+	FN_SEL_WAIT2_A,	FN_SEL_WAIT2_B,
+	FN_SEL_WAIT1_A,	FN_SEL_WAIT1_B,
+	FN_SEL_CAN1_A,	FN_SEL_CAN1_B,
+	FN_SEL_CAN0_A,	FN_SEL_CAN0_B,
+	FN_SEL_CANCLK_A,	FN_SEL_CANCLK_B,
+	FN_SEL_CANCLK_C,	FN_SEL_CANCLK_D,
+	FN_SEL_HSCIF1_A,	FN_SEL_HSCIF1_B,
+	FN_SEL_HSCIF0_A,	FN_SEL_HSCIF0_B,
+	FN_SEL_REMOCON_A,	FN_SEL_REMOCON_B,	FN_SEL_REMOCON_C,
+	FN_SEL_FM_A,	FN_SEL_FM_B,	FN_SEL_FM_C,	FN_SEL_FM_D,
+	FN_SEL_GPS_A,	FN_SEL_GPS_B,	FN_SEL_GPS_C,
+	FN_SEL_TSIF0_A,	FN_SEL_TSIF0_B,
+	FN_SEL_HSPI2_A,	FN_SEL_HSPI2_B,
+	FN_SEL_HSPI1_A,	FN_SEL_HSPI1_B,
+	FN_SEL_HSPI0_A,	FN_SEL_HSPI0_B,
+	FN_SEL_I2C3_A,	FN_SEL_I2C3_B,	FN_SEL_I2C3_C,
+	FN_SEL_I2C2_A,	FN_SEL_I2C2_B,	FN_SEL_I2C2_C,
+	FN_SEL_I2C1_A,	FN_SEL_I2C1_B,
+	PINMUX_FUNCTION_END,
+
+	PINMUX_MARK_BEGIN,
+
+	/* GPSR0 */
+	PENC0_MARK,	PENC1_MARK,	A1_MARK,	A2_MARK,	A3_MARK,
+
+	/* GPSR1 */
+	WE0_MARK,
+
+	/* GPSR2 */
+	AUDIO_CLKA_MARK,
+	AUDIO_CLKB_MARK,
+
+	/* GPSR3 */
+	SSI_SCK34_MARK,
+
+	/* GPSR4 */
+	AVS1_MARK,
+	AVS2_MARK,
+
+	VI0_R0_C_MARK,  /* see GPIO_FN_VI0_R0_A */
+	VI0_R1_C_MARK,  /* see GPIO_FN_VI0_R1_A */
+	VI0_R2_C_MARK,  /* see GPIO_FN_VI0_R2_A */
+	/* VI0_R3_C_MARK,  see GPIO_FN_VI0_R3_A */
+	VI0_R4_C_MARK,  /* see GPIO_FN_VI0_R4_A */
+	VI0_R5_C_MARK,  /* see GPIO_FN_VI0_R5_A */
+
+	VI0_R0_D_MARK,  /* see GPIO_FN_VI0_R0_B */
+	VI0_R1_D_MARK,  /* see GPIO_FN_VI0_R1_B */
+	VI0_R2_D_MARK,  /* see GPIO_FN_VI0_R2_B */
+	VI0_R3_D_MARK,  /* see GPIO_FN_VI0_R3_B */
+	VI0_R4_D_MARK,  /* see GPIO_FN_VI0_R4_B */
+	VI0_R5_D_MARK,  /* see GPIO_FN_VI0_R5_B */
+
+	/* IPSR0 */
+	PRESETOUT_MARK,	PWM1_MARK,	AUDATA0_MARK,
+	ARM_TRACEDATA_0_MARK,		GPSCLK_C_MARK,	USB_OVC0_MARK,
+	TX2_E_MARK,	SDA2_B_MARK,	AUDATA1_MARK,	ARM_TRACEDATA_1_MARK,
+	GPSIN_C_MARK,	USB_OVC1_MARK,	RX2_E_MARK,	SCL2_B_MARK,
+	SD1_DAT2_A_MARK,		MMC_D2_MARK,	BS_MARK,
+	ATADIR0_A_MARK,	SDSELF_A_MARK,	PWM4_B_MARK,	SD1_DAT3_A_MARK,
+	MMC_D3_MARK,	A0_MARK,	ATAG0_A_MARK,	REMOCON_B_MARK,
+	A4_MARK,	A5_MARK,	A6_MARK,	A7_MARK,
+	A8_MARK,	A9_MARK,	A10_MARK,	A11_MARK,
+	A12_MARK,	A13_MARK,	A14_MARK,	A15_MARK,
+	A16_MARK,	A17_MARK,	A18_MARK,	A19_MARK,
+
+	/* IPSR1 */
+	A20_MARK,	HSPI_CS1_B_MARK,		A21_MARK,
+	HSPI_CLK1_B_MARK,		A22_MARK,	HRTS0_B_MARK,
+	RX2_B_MARK,	DREQ2_A_MARK,	A23_MARK,	HTX0_B_MARK,
+	TX2_B_MARK,	DACK2_A_MARK,	TS_SDEN0_A_MARK,
+	SD1_CD_A_MARK,	MMC_D6_MARK,	A24_MARK,	DREQ1_A_MARK,
+	HRX0_B_MARK,	TS_SPSYNC0_A_MARK,		SD1_WP_A_MARK,
+	MMC_D7_MARK,	A25_MARK,	DACK1_A_MARK,	HCTS0_B_MARK,
+	RX3_C_MARK,	TS_SDAT0_A_MARK,		CLKOUT_MARK,
+	HSPI_TX1_B_MARK,		PWM0_B_MARK,	CS0_MARK,
+	HSPI_RX1_B_MARK,		SSI_SCK1_B_MARK,
+	ATAG0_B_MARK,	CS1_A26_MARK,	SDA2_A_MARK,	SCK2_B_MARK,
+	MMC_D5_MARK,	ATADIR0_B_MARK,	RD_WR_MARK,	WE1_MARK,
+	ATAWR0_B_MARK,	SSI_WS1_B_MARK,	EX_CS0_MARK,	SCL2_A_MARK,
+	TX3_C_MARK,	TS_SCK0_A_MARK,	EX_CS1_MARK,	MMC_D4_MARK,
+
+	/* IPSR2 */
+	SD1_CLK_A_MARK,	MMC_CLK_MARK,	ATACS00_MARK,	EX_CS2_MARK,
+	SD1_CMD_A_MARK,	MMC_CMD_MARK,	ATACS10_MARK,	EX_CS3_MARK,
+	SD1_DAT0_A_MARK,		MMC_D0_MARK,	ATARD0_MARK,
+	EX_CS4_MARK,	EX_WAIT1_A_MARK,		SD1_DAT1_A_MARK,
+	MMC_D1_MARK,	ATAWR0_A_MARK,	EX_CS5_MARK,	EX_WAIT2_A_MARK,
+	DREQ0_A_MARK,	RX3_A_MARK,	DACK0_MARK,	TX3_A_MARK,
+	DRACK0_MARK,	EX_WAIT0_MARK,	PWM0_C_MARK,	D0_MARK,
+	D1_MARK,	D2_MARK,	D3_MARK,	D4_MARK,
+	D5_MARK,	D6_MARK,	D7_MARK,	D8_MARK,
+	D9_MARK,	D10_MARK,	D11_MARK,	RD_WR_B_MARK,
+	IRQ0_MARK,	MLB_CLK_MARK,	IRQ1_A_MARK,
+
+	/* IPSR3 */
+	MLB_SIG_MARK,	RX5_B_MARK,	SDA3_A_MARK,	IRQ2_A_MARK,
+	MLB_DAT_MARK,	TX5_B_MARK,	SCL3_A_MARK,	IRQ3_A_MARK,
+	SDSELF_B_MARK,	SD1_CMD_B_MARK,	SCIF_CLK_MARK,	AUDIO_CLKOUT_B_MARK,
+	CAN_CLK_B_MARK,	SDA3_B_MARK,	SD1_CLK_B_MARK,	HTX0_A_MARK,
+	TX0_A_MARK,	SD1_DAT0_B_MARK,		HRX0_A_MARK,
+	RX0_A_MARK,	SD1_DAT1_B_MARK,		HSCK0_MARK,
+	SCK0_MARK,	SCL3_B_MARK,	SD1_DAT2_B_MARK,
+	HCTS0_A_MARK,	CTS0_MARK,	SD1_DAT3_B_MARK,
+	HRTS0_A_MARK,	RTS0_MARK,	SSI_SCK4_MARK,
+	DU0_DR0_MARK,	LCDOUT0_MARK,	AUDATA2_MARK,	ARM_TRACEDATA_2_MARK,
+	SDA3_C_MARK,	ADICHS1_MARK,	TS_SDEN0_B_MARK,
+	SSI_WS4_MARK,	DU0_DR1_MARK,	LCDOUT1_MARK,	AUDATA3_MARK,
+	ARM_TRACEDATA_3_MARK,		SCL3_C_MARK,	ADICHS2_MARK,
+	TS_SPSYNC0_B_MARK,		DU0_DR2_MARK,	LCDOUT2_MARK,
+	DU0_DR3_MARK,	LCDOUT3_MARK,	DU0_DR4_MARK,	LCDOUT4_MARK,
+	DU0_DR5_MARK,	LCDOUT5_MARK,	DU0_DR6_MARK,	LCDOUT6_MARK,
+
+	/* IPSR4 */
+	DU0_DR7_MARK,	LCDOUT7_MARK,	DU0_DG0_MARK,	LCDOUT8_MARK,
+	AUDATA4_MARK,	ARM_TRACEDATA_4_MARK,
+	TX1_D_MARK,	CAN0_TX_A_MARK,	ADICHS0_MARK,	DU0_DG1_MARK,
+	LCDOUT9_MARK,	AUDATA5_MARK,	ARM_TRACEDATA_5_MARK,
+	RX1_D_MARK,	CAN0_RX_A_MARK,	ADIDATA_MARK,	DU0_DG2_MARK,
+	LCDOUT10_MARK,	DU0_DG3_MARK,	LCDOUT11_MARK,	DU0_DG4_MARK,
+	LCDOUT12_MARK,	RX0_B_MARK,	DU0_DG5_MARK,	LCDOUT13_MARK,
+	TX0_B_MARK,	DU0_DG6_MARK,	LCDOUT14_MARK,	RX4_A_MARK,
+	DU0_DG7_MARK,	LCDOUT15_MARK,	TX4_A_MARK,	SSI_SCK2_B_MARK,
+	VI0_R0_B_MARK,	DU0_DB0_MARK,	LCDOUT16_MARK,	AUDATA6_MARK,
+	ARM_TRACEDATA_6_MARK,		GPSCLK_A_MARK,	PWM0_A_MARK,
+	ADICLK_MARK,	TS_SDAT0_B_MARK,		AUDIO_CLKC_MARK,
+	VI0_R1_B_MARK,	DU0_DB1_MARK,	LCDOUT17_MARK,	AUDATA7_MARK,
+	ARM_TRACEDATA_7_MARK,		GPSIN_A_MARK,	ADICS_SAMP_MARK,
+	TS_SCK0_B_MARK,	VI0_R2_B_MARK,	DU0_DB2_MARK,	LCDOUT18_MARK,
+	VI0_R3_B_MARK,	DU0_DB3_MARK,	LCDOUT19_MARK,	VI0_R4_B_MARK,
+	DU0_DB4_MARK,	LCDOUT20_MARK,
+
+	/* IPSR5 */
+	VI0_R5_B_MARK,	DU0_DB5_MARK,	LCDOUT21_MARK,	VI1_DATA10_B_MARK,
+	DU0_DB6_MARK,	LCDOUT22_MARK,	VI1_DATA11_B_MARK,
+	DU0_DB7_MARK,	LCDOUT23_MARK,	DU0_DOTCLKIN_MARK,
+	QSTVA_QVS_MARK,	DU0_DOTCLKO_UT0_MARK,
+	QCLK_MARK,	DU0_DOTCLKO_UT1_MARK,		QSTVB_QVE_MARK,
+	AUDIO_CLKOUT_A_MARK,		REMOCON_C_MARK,	SSI_WS2_B_MARK,
+	DU0_EXHSYNC_DU0_HSYNC_MARK,	QSTH_QHS_MARK,
+	DU0_EXVSYNC_DU0_VSYNC_MARK,	QSTB_QHE_MARK,
+	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
+	QCPV_QDE_MARK,	FMCLK_D_MARK,	SSI_SCK1_A_MARK,
+	DU0_DISP_MARK,	QPOLA_MARK,	AUDCK_MARK,	ARM_TRACECLK_MARK,
+	BPFCLK_D_MARK,	SSI_WS1_A_MARK,	DU0_CDE_MARK,	QPOLB_MARK,
+	AUDSYNC_MARK,	ARM_TRACECTL_MARK,		FMIN_D_MARK,
+	SD1_CD_B_MARK,	SSI_SCK78_MARK,	HSPI_RX0_B_MARK,
+	TX1_B_MARK,	SD1_WP_B_MARK,	SSI_WS78_MARK,	HSPI_CLK0_B_MARK,
+	RX1_B_MARK,	CAN_CLK_D_MARK,	SSI_SDATA8_MARK,
+	SSI_SCK2_A_MARK,		HSPI_CS0_B_MARK,
+	TX2_A_MARK,	CAN0_TX_B_MARK,	SSI_SDATA7_MARK,
+	HSPI_TX0_B_MARK,		RX2_A_MARK,	CAN0_RX_B_MARK,
+
+	/* IPSR6 */
+	SSI_SCK6_MARK,	HSPI_RX2_A_MARK,		FMCLK_B_MARK,
+	CAN1_TX_B_MARK,	SSI_WS6_MARK,	HSPI_CLK2_A_MARK,
+	BPFCLK_B_MARK,	CAN1_RX_B_MARK,	SSI_SDATA6_MARK,
+	HSPI_TX2_A_MARK,		FMIN_B_MARK,	SSI_SCK5_MARK,
+	RX4_C_MARK,	SSI_WS5_MARK,	TX4_C_MARK,	SSI_SDATA5_MARK,
+	RX0_D_MARK,	SSI_WS34_MARK,	ARM_TRACEDATA_8_MARK,
+	SSI_SDATA4_MARK,		SSI_WS2_A_MARK,	ARM_TRACEDATA_9_MARK,
+	SSI_SDATA3_MARK,		ARM_TRACEDATA_10_MARK,
+	SSI_SCK012_MARK,		ARM_TRACEDATA_11_MARK,
+	TX0_D_MARK,	SSI_WS012_MARK,	ARM_TRACEDATA_12_MARK,
+	SSI_SDATA2_MARK,		HSPI_CS2_A_MARK,
+	ARM_TRACEDATA_13_MARK,		SDA1_A_MARK,	SSI_SDATA1_MARK,
+	ARM_TRACEDATA_14_MARK,		SCL1_A_MARK,	SCK2_A_MARK,
+	SSI_SDATA0_MARK,		ARM_TRACEDATA_15_MARK,
+	SD0_CLK_MARK,	SUB_TDO_MARK,	SD0_CMD_MARK,	SUB_TRST_MARK,
+	SD0_DAT0_MARK,	SUB_TMS_MARK,	SD0_DAT1_MARK,	SUB_TCK_MARK,
+	SD0_DAT2_MARK,	SUB_TDI_MARK,
+
+	/* IPSR7 */
+	SD0_DAT3_MARK,	IRQ1_B_MARK,	SD0_CD_MARK,	TX5_A_MARK,
+	SD0_WP_MARK,	RX5_A_MARK,	VI1_CLKENB_MARK,
+	HSPI_CLK0_A_MARK,	HTX1_A_MARK,	RTS1_C_MARK,	VI1_FIELD_MARK,
+	HSPI_CS0_A_MARK,	HRX1_A_MARK,	SCK1_C_MARK,	VI1_HSYNC_MARK,
+	HSPI_RX0_A_MARK,	HRTS1_A_MARK,	FMCLK_A_MARK,	RX1_C_MARK,
+	VI1_VSYNC_MARK,	HSPI_TX0_MARK,	HCTS1_A_MARK,	BPFCLK_A_MARK,
+	TX1_C_MARK,	TCLK0_MARK,	HSCK1_A_MARK,	FMIN_A_MARK,
+	IRQ2_C_MARK,	CTS1_C_MARK,	SPEEDIN_MARK,	VI0_CLK_MARK,
+	CAN_CLK_A_MARK,	VI0_CLKENB_MARK,		SD2_DAT2_B_MARK,
+	VI1_DATA0_MARK,	DU1_DG6_MARK,	HSPI_RX1_A_MARK,
+	RX4_B_MARK,	VI0_FIELD_MARK,	SD2_DAT3_B_MARK,
+	VI0_R3_C_MARK,	VI1_DATA1_MARK,	DU1_DG7_MARK,	HSPI_CLK1_A_MARK,
+	TX4_B_MARK,	VI0_HSYNC_MARK,	SD2_CD_B_MARK,	VI1_DATA2_MARK,
+	DU1_DR2_MARK,	HSPI_CS1_A_MARK,		RX3_B_MARK,
+
+	/* IPSR8 */
+	VI0_VSYNC_MARK,	SD2_WP_B_MARK,	VI1_DATA3_MARK,	DU1_DR3_MARK,
+	HSPI_TX1_A_MARK,		TX3_B_MARK,	VI0_DATA0_VI0_B0_MARK,
+	DU1_DG2_MARK,	IRQ2_B_MARK,	RX3_D_MARK,	VI0_DATA1_VI0_B1_MARK,
+	DU1_DG3_MARK,	IRQ3_B_MARK,	TX3_D_MARK,	VI0_DATA2_VI0_B2_MARK,
+	DU1_DG4_MARK,	RX0_C_MARK,	VI0_DATA3_VI0_B3_MARK,
+	DU1_DG5_MARK,	TX1_A_MARK,	TX0_C_MARK,	VI0_DATA4_VI0_B4_MARK,
+	DU1_DB2_MARK,	RX1_A_MARK,	VI0_DATA5_VI0_B5_MARK,
+	DU1_DB3_MARK,	SCK1_A_MARK,	PWM4_MARK,	HSCK1_B_MARK,
+	VI0_DATA6_VI0_G0_MARK,		DU1_DB4_MARK,	CTS1_A_MARK,
+	PWM5_MARK,	VI0_DATA7_VI0_G1_MARK,		DU1_DB5_MARK,
+	RTS1_A_MARK,	VI0_G2_MARK,	SD2_CLK_B_MARK,	VI1_DATA4_MARK,
+	DU1_DR4_MARK,	HTX1_B_MARK,	VI0_G3_MARK,	SD2_CMD_B_MARK,
+	VI1_DATA5_MARK,	DU1_DR5_MARK,	HRX1_B_MARK,
+
+	/* IPSR9 */
+	VI0_G4_MARK,	SD2_DAT0_B_MARK,		VI1_DATA6_MARK,
+	DU1_DR6_MARK,	HRTS1_B_MARK,	VI0_G5_MARK,	SD2_DAT1_B_MARK,
+	VI1_DATA7_MARK,	DU1_DR7_MARK,	HCTS1_B_MARK,	VI0_R0_A_MARK,
+	VI1_CLK_MARK,	ETH_REF_CLK_MARK,		DU1_DOTCLKIN_MARK,
+	VI0_R1_A_MARK,	VI1_DATA8_MARK,	DU1_DB6_MARK,	ETH_TXD0_MARK,
+	PWM2_MARK,	TCLK1_MARK,	VI0_R2_A_MARK,	VI1_DATA9_MARK,
+	DU1_DB7_MARK,	ETH_TXD1_MARK,	PWM3_MARK,	VI0_R3_A_MARK,
+	ETH_CRS_DV_MARK,		IECLK_MARK,	SCK2_C_MARK,
+	VI0_R4_A_MARK,			ETH_TX_EN_MARK,	IETX_MARK,
+	TX2_C_MARK,	VI0_R5_A_MARK,	ETH_RX_ER_MARK,	FMCLK_C_MARK,
+	IERX_MARK,	RX2_C_MARK,	VI1_DATA10_A_MARK,
+	DU1_DOTCLKOUT_MARK,		ETH_RXD0_MARK,
+	BPFCLK_C_MARK,	TX2_D_MARK,	SDA2_C_MARK,	VI1_DATA11_A_MARK,
+	DU1_EXHSYNC_DU1_HSYNC_MARK,	ETH_RXD1_MARK,	FMIN_C_MARK,
+	RX2_D_MARK,	SCL2_C_MARK,
+
+	/* IPSR10 */
+	SD2_CLK_A_MARK,	DU1_EXVSYNC_DU1_VSYNC_MARK,	ATARD1_MARK,
+	ETH_MDC_MARK,	SDA1_B_MARK,	SD2_CMD_A_MARK,
+	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,		ATAWR1_MARK,
+	ETH_MDIO_MARK,	SCL1_B_MARK,	SD2_DAT0_A_MARK,
+	DU1_DISP_MARK,	ATACS01_MARK,	DREQ1_B_MARK,	ETH_LINK_MARK,
+	CAN1_RX_A_MARK,	SD2_DAT1_A_MARK,		DU1_CDE_MARK,
+	ATACS11_MARK,	DACK1_B_MARK,	ETH_MAGIC_MARK,	CAN1_TX_A_MARK,
+	PWM6_MARK,	SD2_DAT2_A_MARK,		VI1_DATA12_MARK,
+	DREQ2_B_MARK,	ATADIR1_MARK,	HSPI_CLK2_B_MARK,
+	GPSCLK_B_MARK,	SD2_DAT3_A_MARK,		VI1_DATA13_MARK,
+	DACK2_B_MARK,	ATAG1_MARK,	HSPI_CS2_B_MARK,
+	GPSIN_B_MARK,	SD2_CD_A_MARK,	VI1_DATA14_MARK,
+	EX_WAIT1_B_MARK,		DREQ0_B_MARK,	HSPI_RX2_B_MARK,
+	REMOCON_A_MARK,	SD2_WP_A_MARK,	VI1_DATA15_MARK,
+	EX_WAIT2_B_MARK,		DACK0_B_MARK,
+	HSPI_TX2_B_MARK,		CAN_CLK_C_MARK,
+
+	PINMUX_MARK_END,
+};
+
+static const pinmux_enum_t pinmux_data[] = {
+	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+	PINMUX_DATA(PENC0_MARK,		FN_PENC0),
+	PINMUX_DATA(PENC1_MARK,		FN_PENC1),
+	PINMUX_DATA(A1_MARK,		FN_A1),
+	PINMUX_DATA(A2_MARK,		FN_A2),
+	PINMUX_DATA(A3_MARK,		FN_A3),
+	PINMUX_DATA(WE0_MARK,		FN_WE0),
+	PINMUX_DATA(AUDIO_CLKA_MARK,	FN_AUDIO_CLKA),
+	PINMUX_DATA(AUDIO_CLKB_MARK,	FN_AUDIO_CLKB),
+	PINMUX_DATA(SSI_SCK34_MARK,	FN_SSI_SCK34),
+	PINMUX_DATA(AVS1_MARK,		FN_AVS1),
+	PINMUX_DATA(AVS2_MARK,		FN_AVS2),
+
+	/* IPSR0 */
+	PINMUX_IPSR_DATA(IP0_1_0,	PRESETOUT),
+	PINMUX_IPSR_DATA(IP0_1_0,	PWM1),
+
+	PINMUX_IPSR_DATA(IP0_4_2,	AUDATA0),
+	PINMUX_IPSR_DATA(IP0_4_2,	ARM_TRACEDATA_0),
+	PINMUX_IPSR_MSEL(IP0_4_2,	GPSCLK_C,	SEL_GPS_C),
+	PINMUX_IPSR_DATA(IP0_4_2,	USB_OVC0),
+	PINMUX_IPSR_DATA(IP0_4_2,	TX2_E),
+	PINMUX_IPSR_MSEL(IP0_4_2,	SDA2_B,		SEL_I2C2_B),
+
+	PINMUX_IPSR_DATA(IP0_7_5,	AUDATA1),
+	PINMUX_IPSR_DATA(IP0_7_5,	ARM_TRACEDATA_1),
+	PINMUX_IPSR_MSEL(IP0_7_5,	GPSIN_C,	SEL_GPS_C),
+	PINMUX_IPSR_DATA(IP0_7_5,	USB_OVC1),
+	PINMUX_IPSR_MSEL(IP0_7_5,	RX2_E,		SEL_SCIF2_E),
+	PINMUX_IPSR_MSEL(IP0_7_5,	SCL2_B,		SEL_I2C2_B),
+
+	PINMUX_IPSR_MSEL(IP0_11_8,	SD1_DAT2_A,	SEL_SD1_A),
+	PINMUX_IPSR_DATA(IP0_11_8,	MMC_D2),
+	PINMUX_IPSR_DATA(IP0_11_8,	BS),
+	PINMUX_IPSR_DATA(IP0_11_8,	ATADIR0_A),
+	PINMUX_IPSR_DATA(IP0_11_8,	SDSELF_A),
+	PINMUX_IPSR_DATA(IP0_11_8,	PWM4_B),
+
+	PINMUX_IPSR_MSEL(IP0_14_12,	SD1_DAT3_A,	SEL_SD1_A),
+	PINMUX_IPSR_DATA(IP0_14_12,	MMC_D3),
+	PINMUX_IPSR_DATA(IP0_14_12,	A0),
+	PINMUX_IPSR_DATA(IP0_14_12,	ATAG0_A),
+	PINMUX_IPSR_MSEL(IP0_14_12,	REMOCON_B,	SEL_REMOCON_B),
+
+	PINMUX_IPSR_DATA(IP0_15,	A4),
+	PINMUX_IPSR_DATA(IP0_16,	A5),
+	PINMUX_IPSR_DATA(IP0_17,	A6),
+	PINMUX_IPSR_DATA(IP0_18,	A7),
+	PINMUX_IPSR_DATA(IP0_19,	A8),
+	PINMUX_IPSR_DATA(IP0_20,	A9),
+	PINMUX_IPSR_DATA(IP0_21,	A10),
+	PINMUX_IPSR_DATA(IP0_22,	A11),
+	PINMUX_IPSR_DATA(IP0_23,	A12),
+	PINMUX_IPSR_DATA(IP0_24,	A13),
+	PINMUX_IPSR_DATA(IP0_25,	A14),
+	PINMUX_IPSR_DATA(IP0_26,	A15),
+	PINMUX_IPSR_DATA(IP0_27,	A16),
+	PINMUX_IPSR_DATA(IP0_28,	A17),
+	PINMUX_IPSR_DATA(IP0_29,	A18),
+	PINMUX_IPSR_DATA(IP0_30,	A19),
+
+	/* IPSR1 */
+	PINMUX_IPSR_DATA(IP1_0,		A20),
+	PINMUX_IPSR_MSEL(IP1_0,		HSPI_CS1_B,	SEL_HSPI1_B),
+
+	PINMUX_IPSR_DATA(IP1_1,		A21),
+	PINMUX_IPSR_MSEL(IP1_1,		HSPI_CLK1_B,	SEL_HSPI1_B),
+
+	PINMUX_IPSR_DATA(IP1_4_2,	A22),
+	PINMUX_IPSR_MSEL(IP1_4_2,	HRTS0_B,	SEL_HSCIF0_B),
+	PINMUX_IPSR_MSEL(IP1_4_2,	RX2_B,		SEL_SCIF2_B),
+	PINMUX_IPSR_MSEL(IP1_4_2,	DREQ2_A,	SEL_DREQ2_A),
+
+	PINMUX_IPSR_DATA(IP1_7_5,	A23),
+	PINMUX_IPSR_DATA(IP1_7_5,	HTX0_B),
+	PINMUX_IPSR_DATA(IP1_7_5,	TX2_B),
+	PINMUX_IPSR_DATA(IP1_7_5,	DACK2_A),
+	PINMUX_IPSR_MSEL(IP1_7_5,	TS_SDEN0_A,	SEL_TSIF0_A),
+
+	PINMUX_IPSR_MSEL(IP1_10_8,	SD1_CD_A,	SEL_SD1_A),
+	PINMUX_IPSR_DATA(IP1_10_8,	MMC_D6),
+	PINMUX_IPSR_DATA(IP1_10_8,	A24),
+	PINMUX_IPSR_MSEL(IP1_10_8,	DREQ1_A,	SEL_DREQ1_A),
+	PINMUX_IPSR_MSEL(IP1_10_8,	HRX0_B,		SEL_HSCIF0_B),
+	PINMUX_IPSR_MSEL(IP1_10_8,	TS_SPSYNC0_A,	SEL_TSIF0_A),
+
+	PINMUX_IPSR_MSEL(IP1_14_11,	SD1_WP_A,	SEL_SD1_A),
+	PINMUX_IPSR_DATA(IP1_14_11,	MMC_D7),
+	PINMUX_IPSR_DATA(IP1_14_11,	A25),
+	PINMUX_IPSR_DATA(IP1_14_11,	DACK1_A),
+	PINMUX_IPSR_MSEL(IP1_14_11,	HCTS0_B,	SEL_HSCIF0_B),
+	PINMUX_IPSR_MSEL(IP1_14_11,	RX3_C,		SEL_SCIF3_C),
+	PINMUX_IPSR_MSEL(IP1_14_11,	TS_SDAT0_A,	SEL_TSIF0_A),
+
+	PINMUX_IPSR_NOGP(IP1_16_15,	CLKOUT),
+	PINMUX_IPSR_NOGP(IP1_16_15,	HSPI_TX1_B),
+	PINMUX_IPSR_NOGP(IP1_16_15,	PWM0_B),
+
+	PINMUX_IPSR_NOGP(IP1_17,	CS0),
+	PINMUX_IPSR_NOGM(IP1_17,	HSPI_RX1_B,	SEL_HSPI1_B),
+
+	PINMUX_IPSR_NOGM(IP1_20_18,	SSI_SCK1_B,	SEL_SSI1_B),
+	PINMUX_IPSR_NOGP(IP1_20_18,	ATAG0_B),
+	PINMUX_IPSR_NOGP(IP1_20_18,	CS1_A26),
+	PINMUX_IPSR_NOGM(IP1_20_18,	SDA2_A,		SEL_I2C2_A),
+	PINMUX_IPSR_NOGM(IP1_20_18,	SCK2_B,		SEL_SCIF2_B),
+
+	PINMUX_IPSR_DATA(IP1_23_21,	MMC_D5),
+	PINMUX_IPSR_DATA(IP1_23_21,	ATADIR0_B),
+	PINMUX_IPSR_DATA(IP1_23_21,	RD_WR),
+
+	PINMUX_IPSR_DATA(IP1_24,	WE1),
+	PINMUX_IPSR_DATA(IP1_24,	ATAWR0_B),
+
+	PINMUX_IPSR_MSEL(IP1_27_25,	SSI_WS1_B,	SEL_SSI1_B),
+	PINMUX_IPSR_DATA(IP1_27_25,	EX_CS0),
+	PINMUX_IPSR_MSEL(IP1_27_25,	SCL2_A,		SEL_I2C2_A),
+	PINMUX_IPSR_DATA(IP1_27_25,	TX3_C),
+	PINMUX_IPSR_MSEL(IP1_27_25,	TS_SCK0_A,	SEL_TSIF0_A),
+
+	PINMUX_IPSR_DATA(IP1_29_28,	EX_CS1),
+	PINMUX_IPSR_DATA(IP1_29_28,	MMC_D4),
+
+	/* IPSR2 */
+	PINMUX_IPSR_DATA(IP2_2_0,	SD1_CLK_A),
+	PINMUX_IPSR_DATA(IP2_2_0,	MMC_CLK),
+	PINMUX_IPSR_DATA(IP2_2_0,	ATACS00),
+	PINMUX_IPSR_DATA(IP2_2_0,	EX_CS2),
+
+	PINMUX_IPSR_MSEL(IP2_5_3,	SD1_CMD_A,	SEL_SD1_A),
+	PINMUX_IPSR_DATA(IP2_5_3,	MMC_CMD),
+	PINMUX_IPSR_DATA(IP2_5_3,	ATACS10),
+	PINMUX_IPSR_DATA(IP2_5_3,	EX_CS3),
+
+	PINMUX_IPSR_MSEL(IP2_8_6,	SD1_DAT0_A,	SEL_SD1_A),
+	PINMUX_IPSR_DATA(IP2_8_6,	MMC_D0),
+	PINMUX_IPSR_DATA(IP2_8_6,	ATARD0),
+	PINMUX_IPSR_DATA(IP2_8_6,	EX_CS4),
+	PINMUX_IPSR_MSEL(IP2_8_6,	EX_WAIT1_A,	SEL_WAIT1_A),
+
+	PINMUX_IPSR_MSEL(IP2_11_9,	SD1_DAT1_A,	SEL_SD1_A),
+	PINMUX_IPSR_DATA(IP2_11_9,	MMC_D1),
+	PINMUX_IPSR_DATA(IP2_11_9,	ATAWR0_A),
+	PINMUX_IPSR_DATA(IP2_11_9,	EX_CS5),
+	PINMUX_IPSR_MSEL(IP2_11_9,	EX_WAIT2_A,	SEL_WAIT2_A),
+
+	PINMUX_IPSR_MSEL(IP2_13_12,	DREQ0_A,	SEL_DREQ0_A),
+	PINMUX_IPSR_MSEL(IP2_13_12,	RX3_A,		SEL_SCIF3_A),
+
+	PINMUX_IPSR_DATA(IP2_16_14,	DACK0),
+	PINMUX_IPSR_DATA(IP2_16_14,	TX3_A),
+	PINMUX_IPSR_DATA(IP2_16_14,	DRACK0),
+
+	PINMUX_IPSR_DATA(IP2_17,	EX_WAIT0),
+	PINMUX_IPSR_DATA(IP2_17,	PWM0_C),
+
+	PINMUX_IPSR_NOGP(IP2_18,	D0),
+	PINMUX_IPSR_NOGP(IP2_19,	D1),
+	PINMUX_IPSR_NOGP(IP2_20,	D2),
+	PINMUX_IPSR_NOGP(IP2_21,	D3),
+	PINMUX_IPSR_NOGP(IP2_22,	D4),
+	PINMUX_IPSR_NOGP(IP2_23,	D5),
+	PINMUX_IPSR_NOGP(IP2_24,	D6),
+	PINMUX_IPSR_NOGP(IP2_25,	D7),
+	PINMUX_IPSR_NOGP(IP2_26,	D8),
+	PINMUX_IPSR_NOGP(IP2_27,	D9),
+	PINMUX_IPSR_NOGP(IP2_28,	D10),
+	PINMUX_IPSR_NOGP(IP2_29,	D11),
+
+	PINMUX_IPSR_DATA(IP2_30,	RD_WR_B),
+	PINMUX_IPSR_DATA(IP2_30,	IRQ0),
+
+	PINMUX_IPSR_DATA(IP2_31,	MLB_CLK),
+	PINMUX_IPSR_MSEL(IP2_31,	IRQ1_A,		SEL_IRQ1_A),
+
+	/* IPSR3 */
+	PINMUX_IPSR_DATA(IP3_1_0,	MLB_SIG),
+	PINMUX_IPSR_MSEL(IP3_1_0,	RX5_B,		SEL_SCIF5_B),
+	PINMUX_IPSR_MSEL(IP3_1_0,	SDA3_A,		SEL_I2C3_A),
+	PINMUX_IPSR_MSEL(IP3_1_0,	IRQ2_A,		SEL_IRQ2_A),
+
+	PINMUX_IPSR_DATA(IP3_4_2,	MLB_DAT),
+	PINMUX_IPSR_DATA(IP3_4_2,	TX5_B),
+	PINMUX_IPSR_MSEL(IP3_4_2,	SCL3_A,		SEL_I2C3_A),
+	PINMUX_IPSR_MSEL(IP3_4_2,	IRQ3_A,		SEL_IRQ3_A),
+	PINMUX_IPSR_DATA(IP3_4_2,	SDSELF_B),
+
+	PINMUX_IPSR_MSEL(IP3_7_5,	SD1_CMD_B,	SEL_SD1_B),
+	PINMUX_IPSR_DATA(IP3_7_5,	SCIF_CLK),
+	PINMUX_IPSR_DATA(IP3_7_5,	AUDIO_CLKOUT_B),
+	PINMUX_IPSR_MSEL(IP3_7_5,	CAN_CLK_B,	SEL_CANCLK_B),
+	PINMUX_IPSR_MSEL(IP3_7_5,	SDA3_B,		SEL_I2C3_B),
+
+	PINMUX_IPSR_DATA(IP3_9_8,	SD1_CLK_B),
+	PINMUX_IPSR_DATA(IP3_9_8,	HTX0_A),
+	PINMUX_IPSR_DATA(IP3_9_8,	TX0_A),
+
+	PINMUX_IPSR_MSEL(IP3_12_10,	SD1_DAT0_B,	SEL_SD1_B),
+	PINMUX_IPSR_MSEL(IP3_12_10,	HRX0_A,		SEL_HSCIF0_A),
+	PINMUX_IPSR_MSEL(IP3_12_10,	RX0_A,		SEL_SCIF0_A),
+
+	PINMUX_IPSR_MSEL(IP3_15_13,	SD1_DAT1_B,	SEL_SD1_B),
+	PINMUX_IPSR_MSEL(IP3_15_13,	HSCK0,		SEL_HSCIF0_A),
+	PINMUX_IPSR_DATA(IP3_15_13,	SCK0),
+	PINMUX_IPSR_MSEL(IP3_15_13,	SCL3_B,		SEL_I2C3_B),
+
+	PINMUX_IPSR_MSEL(IP3_18_16,	SD1_DAT2_B,	SEL_SD1_B),
+	PINMUX_IPSR_MSEL(IP3_18_16,	HCTS0_A,	SEL_HSCIF0_A),
+	PINMUX_IPSR_DATA(IP3_18_16,	CTS0),
+
+	PINMUX_IPSR_MSEL(IP3_20_19,	SD1_DAT3_B,	SEL_SD1_B),
+	PINMUX_IPSR_MSEL(IP3_20_19,	HRTS0_A,	SEL_HSCIF0_A),
+	PINMUX_IPSR_DATA(IP3_20_19,	RTS0),
+
+	PINMUX_IPSR_DATA(IP3_23_21,	SSI_SCK4),
+	PINMUX_IPSR_DATA(IP3_23_21,	DU0_DR0),
+	PINMUX_IPSR_DATA(IP3_23_21,	LCDOUT0),
+	PINMUX_IPSR_DATA(IP3_23_21,	AUDATA2),
+	PINMUX_IPSR_DATA(IP3_23_21,	ARM_TRACEDATA_2),
+	PINMUX_IPSR_MSEL(IP3_23_21,	SDA3_C,		SEL_I2C3_C),
+	PINMUX_IPSR_DATA(IP3_23_21,	ADICHS1),
+	PINMUX_IPSR_MSEL(IP3_23_21,	TS_SDEN0_B,	SEL_TSIF0_B),
+
+	PINMUX_IPSR_DATA(IP3_26_24,	SSI_WS4),
+	PINMUX_IPSR_DATA(IP3_26_24,	DU0_DR1),
+	PINMUX_IPSR_DATA(IP3_26_24,	LCDOUT1),
+	PINMUX_IPSR_DATA(IP3_26_24,	AUDATA3),
+	PINMUX_IPSR_DATA(IP3_26_24,	ARM_TRACEDATA_3),
+	PINMUX_IPSR_MSEL(IP3_26_24,	SCL3_C,		SEL_I2C3_C),
+	PINMUX_IPSR_DATA(IP3_26_24,	ADICHS2),
+	PINMUX_IPSR_MSEL(IP3_26_24,	TS_SPSYNC0_B,	SEL_TSIF0_B),
+
+	PINMUX_IPSR_DATA(IP3_27,	DU0_DR2),
+	PINMUX_IPSR_DATA(IP3_27,	LCDOUT2),
+
+	PINMUX_IPSR_DATA(IP3_28,	DU0_DR3),
+	PINMUX_IPSR_DATA(IP3_28,	LCDOUT3),
+
+	PINMUX_IPSR_DATA(IP3_29,	DU0_DR4),
+	PINMUX_IPSR_DATA(IP3_29,	LCDOUT4),
+
+	PINMUX_IPSR_DATA(IP3_30,	DU0_DR5),
+	PINMUX_IPSR_DATA(IP3_30,	LCDOUT5),
+
+	PINMUX_IPSR_DATA(IP3_31,	DU0_DR6),
+	PINMUX_IPSR_DATA(IP3_31,	LCDOUT6),
+
+	/* IPSR4 */
+	PINMUX_IPSR_DATA(IP4_0,		DU0_DR7),
+	PINMUX_IPSR_DATA(IP4_0,		LCDOUT7),
+
+	PINMUX_IPSR_DATA(IP4_3_1,	DU0_DG0),
+	PINMUX_IPSR_DATA(IP4_3_1,	LCDOUT8),
+	PINMUX_IPSR_DATA(IP4_3_1,	AUDATA4),
+	PINMUX_IPSR_DATA(IP4_3_1,	ARM_TRACEDATA_4),
+	PINMUX_IPSR_DATA(IP4_3_1,	TX1_D),
+	PINMUX_IPSR_DATA(IP4_3_1,	CAN0_TX_A),
+	PINMUX_IPSR_DATA(IP4_3_1,	ADICHS0),
+
+	PINMUX_IPSR_DATA(IP4_6_4,	DU0_DG1),
+	PINMUX_IPSR_DATA(IP4_6_4,	LCDOUT9),
+	PINMUX_IPSR_DATA(IP4_6_4,	AUDATA5),
+	PINMUX_IPSR_DATA(IP4_6_4,	ARM_TRACEDATA_5),
+	PINMUX_IPSR_MSEL(IP4_6_4,	RX1_D,		SEL_SCIF1_D),
+	PINMUX_IPSR_MSEL(IP4_6_4,	CAN0_RX_A,	SEL_CAN0_A),
+	PINMUX_IPSR_DATA(IP4_6_4,	ADIDATA),
+
+	PINMUX_IPSR_DATA(IP4_7,		DU0_DG2),
+	PINMUX_IPSR_DATA(IP4_7,		LCDOUT10),
+
+	PINMUX_IPSR_DATA(IP4_8,		DU0_DG3),
+	PINMUX_IPSR_DATA(IP4_8,		LCDOUT11),
+
+	PINMUX_IPSR_DATA(IP4_10_9,	DU0_DG4),
+	PINMUX_IPSR_DATA(IP4_10_9,	LCDOUT12),
+	PINMUX_IPSR_MSEL(IP4_10_9,	RX0_B,		SEL_SCIF0_B),
+
+	PINMUX_IPSR_DATA(IP4_12_11,	DU0_DG5),
+	PINMUX_IPSR_DATA(IP4_12_11,	LCDOUT13),
+	PINMUX_IPSR_DATA(IP4_12_11,	TX0_B),
+
+	PINMUX_IPSR_DATA(IP4_14_13,	DU0_DG6),
+	PINMUX_IPSR_DATA(IP4_14_13,	LCDOUT14),
+	PINMUX_IPSR_MSEL(IP4_14_13,	RX4_A,		SEL_SCIF4_A),
+
+	PINMUX_IPSR_DATA(IP4_16_15,	DU0_DG7),
+	PINMUX_IPSR_DATA(IP4_16_15,	LCDOUT15),
+	PINMUX_IPSR_DATA(IP4_16_15,	TX4_A),
+
+	PINMUX_IPSR_MSEL(IP4_20_17,	SSI_SCK2_B,	SEL_SSI2_B),
+	PINMUX_DATA(VI0_R0_B_MARK,	FN_IP4_20_17,	FN_VI0_R0_B,	FN_SEL_VI0_B), /* see sel_vi0 */
+	PINMUX_DATA(VI0_R0_D_MARK,	FN_IP4_20_17,	FN_VI0_R0_B,	FN_SEL_VI0_D), /* see sel_vi0 */
+	PINMUX_IPSR_DATA(IP4_20_17,	DU0_DB0),
+	PINMUX_IPSR_DATA(IP4_20_17,	LCDOUT16),
+	PINMUX_IPSR_DATA(IP4_20_17,	AUDATA6),
+	PINMUX_IPSR_DATA(IP4_20_17,	ARM_TRACEDATA_6),
+	PINMUX_IPSR_MSEL(IP4_20_17,	GPSCLK_A,	SEL_GPS_A),
+	PINMUX_IPSR_DATA(IP4_20_17,	PWM0_A),
+	PINMUX_IPSR_DATA(IP4_20_17,	ADICLK),
+	PINMUX_IPSR_MSEL(IP4_20_17,	TS_SDAT0_B,	SEL_TSIF0_B),
+
+	PINMUX_IPSR_DATA(IP4_24_21,	AUDIO_CLKC),
+	PINMUX_DATA(VI0_R1_B_MARK,	FN_IP4_24_21,	FN_VI0_R1_B,	FN_SEL_VI0_B), /* see sel_vi0 */
+	PINMUX_DATA(VI0_R1_D_MARK,	FN_IP4_24_21,	FN_VI0_R1_B,	FN_SEL_VI0_D), /* see sel_vi0 */
+	PINMUX_IPSR_DATA(IP4_24_21,	DU0_DB1),
+	PINMUX_IPSR_DATA(IP4_24_21,	LCDOUT17),
+	PINMUX_IPSR_DATA(IP4_24_21,	AUDATA7),
+	PINMUX_IPSR_DATA(IP4_24_21,	ARM_TRACEDATA_7),
+	PINMUX_IPSR_MSEL(IP4_24_21,	GPSIN_A,	SEL_GPS_A),
+	PINMUX_IPSR_DATA(IP4_24_21,	ADICS_SAMP),
+	PINMUX_IPSR_MSEL(IP4_24_21,	TS_SCK0_B,	SEL_TSIF0_B),
+
+	PINMUX_DATA(VI0_R2_B_MARK,	FN_IP4_26_25,	FN_VI0_R2_B,	FN_SEL_VI0_B), /* see sel_vi0 */
+	PINMUX_DATA(VI0_R2_D_MARK,	FN_IP4_26_25,	FN_VI0_R2_B,	FN_SEL_VI0_D), /* see sel_vi0 */
+	PINMUX_IPSR_DATA(IP4_26_25,	DU0_DB2),
+	PINMUX_IPSR_DATA(IP4_26_25,	LCDOUT18),
+
+	PINMUX_IPSR_MSEL(IP4_28_27,	VI0_R3_B,	SEL_VI0_B),
+	PINMUX_IPSR_DATA(IP4_28_27,	DU0_DB3),
+	PINMUX_IPSR_DATA(IP4_28_27,	LCDOUT19),
+
+	PINMUX_DATA(VI0_R4_B_MARK,	FN_IP4_30_29,	FN_VI0_R4_B,	FN_SEL_VI0_B), /* see sel_vi0 */
+	PINMUX_DATA(VI0_R4_D_MARK,	FN_IP4_30_29,	FN_VI0_R4_B,	FN_SEL_VI0_D), /* see sel_vi0 */
+	PINMUX_IPSR_DATA(IP4_30_29,	DU0_DB4),
+	PINMUX_IPSR_DATA(IP4_30_29,	LCDOUT20),
+
+	/* IPSR5 */
+	PINMUX_DATA(VI0_R5_B_MARK,	FN_IP5_1_0,	FN_VI0_R5_B,	FN_SEL_VI0_B), /* see sel_vi0 */
+	PINMUX_DATA(VI0_R5_D_MARK,	FN_IP5_1_0,	FN_VI0_R5_B,	FN_SEL_VI0_D), /* see sel_vi0 */
+	PINMUX_IPSR_DATA(IP5_1_0,	DU0_DB5),
+	PINMUX_IPSR_DATA(IP5_1_0,	LCDOUT21),
+
+	PINMUX_IPSR_MSEL(IP5_3_2,	VI1_DATA10_B,	SEL_VI1_B),
+	PINMUX_IPSR_DATA(IP5_3_2,	DU0_DB6),
+	PINMUX_IPSR_DATA(IP5_3_2,	LCDOUT22),
+
+	PINMUX_IPSR_MSEL(IP5_5_4,	VI1_DATA11_B,	SEL_VI1_B),
+	PINMUX_IPSR_DATA(IP5_5_4,	DU0_DB7),
+	PINMUX_IPSR_DATA(IP5_5_4,	LCDOUT23),
+
+	PINMUX_IPSR_DATA(IP5_6,		DU0_DOTCLKIN),
+	PINMUX_IPSR_DATA(IP5_6,		QSTVA_QVS),
+
+	PINMUX_IPSR_DATA(IP5_7,		DU0_DOTCLKO_UT0),
+	PINMUX_IPSR_DATA(IP5_7,		QCLK),
+
+	PINMUX_IPSR_DATA(IP5_9_8,	DU0_DOTCLKO_UT1),
+	PINMUX_IPSR_DATA(IP5_9_8,	QSTVB_QVE),
+	PINMUX_IPSR_DATA(IP5_9_8,	AUDIO_CLKOUT_A),
+	PINMUX_IPSR_MSEL(IP5_9_8,	REMOCON_C,	SEL_REMOCON_C),
+
+	PINMUX_IPSR_MSEL(IP5_11_10,	SSI_WS2_B,	SEL_SSI2_B),
+	PINMUX_IPSR_DATA(IP5_11_10,	DU0_EXHSYNC_DU0_HSYNC),
+	PINMUX_IPSR_DATA(IP5_11_10,	QSTH_QHS),
+
+	PINMUX_IPSR_DATA(IP5_12,	DU0_EXVSYNC_DU0_VSYNC),
+	PINMUX_IPSR_DATA(IP5_12,	QSTB_QHE),
+
+	PINMUX_IPSR_DATA(IP5_14_13,	DU0_EXODDF_DU0_ODDF_DISP_CDE),
+	PINMUX_IPSR_DATA(IP5_14_13,	QCPV_QDE),
+	PINMUX_IPSR_MSEL(IP5_14_13,	FMCLK_D,	SEL_FM_D),
+
+	PINMUX_IPSR_MSEL(IP5_17_15,	SSI_SCK1_A,	SEL_SSI1_A),
+	PINMUX_IPSR_DATA(IP5_17_15,	DU0_DISP),
+	PINMUX_IPSR_DATA(IP5_17_15,	QPOLA),
+	PINMUX_IPSR_DATA(IP5_17_15,	AUDCK),
+	PINMUX_IPSR_DATA(IP5_17_15,	ARM_TRACECLK),
+	PINMUX_IPSR_DATA(IP5_17_15,	BPFCLK_D),
+
+	PINMUX_IPSR_MSEL(IP5_20_18,	SSI_WS1_A,	SEL_SSI1_A),
+	PINMUX_IPSR_DATA(IP5_20_18,	DU0_CDE),
+	PINMUX_IPSR_DATA(IP5_20_18,	QPOLB),
+	PINMUX_IPSR_DATA(IP5_20_18,	AUDSYNC),
+	PINMUX_IPSR_DATA(IP5_20_18,	ARM_TRACECTL),
+	PINMUX_IPSR_MSEL(IP5_20_18,	FMIN_D,		SEL_FM_D),
+
+	PINMUX_IPSR_MSEL(IP5_22_21,	SD1_CD_B,	SEL_SD1_B),
+	PINMUX_IPSR_DATA(IP5_22_21,	SSI_SCK78),
+	PINMUX_IPSR_MSEL(IP5_22_21,	HSPI_RX0_B,	SEL_HSPI0_B),
+	PINMUX_IPSR_DATA(IP5_22_21,	TX1_B),
+
+	PINMUX_IPSR_MSEL(IP5_25_23,	SD1_WP_B,	SEL_SD1_B),
+	PINMUX_IPSR_DATA(IP5_25_23,	SSI_WS78),
+	PINMUX_IPSR_MSEL(IP5_25_23,	HSPI_CLK0_B,	SEL_HSPI0_B),
+	PINMUX_IPSR_MSEL(IP5_25_23,	RX1_B,		SEL_SCIF1_B),
+	PINMUX_IPSR_MSEL(IP5_25_23,	CAN_CLK_D,	SEL_CANCLK_D),
+
+	PINMUX_IPSR_DATA(IP5_28_26,	SSI_SDATA8),
+	PINMUX_IPSR_MSEL(IP5_28_26,	SSI_SCK2_A,	SEL_SSI2_A),
+	PINMUX_IPSR_MSEL(IP5_28_26,	HSPI_CS0_B,	SEL_HSPI0_B),
+	PINMUX_IPSR_DATA(IP5_28_26,	TX2_A),
+	PINMUX_IPSR_DATA(IP5_28_26,	CAN0_TX_B),
+
+	PINMUX_IPSR_DATA(IP5_30_29,	SSI_SDATA7),
+	PINMUX_IPSR_DATA(IP5_30_29,	HSPI_TX0_B),
+	PINMUX_IPSR_MSEL(IP5_30_29,	RX2_A,		SEL_SCIF2_A),
+	PINMUX_IPSR_MSEL(IP5_30_29,	CAN0_RX_B,	SEL_CAN0_B),
+
+	/* IPSR6 */
+	PINMUX_IPSR_DATA(IP6_1_0,	SSI_SCK6),
+	PINMUX_IPSR_MSEL(IP6_1_0,	HSPI_RX2_A,	SEL_HSPI2_A),
+	PINMUX_IPSR_MSEL(IP6_1_0,	FMCLK_B,	SEL_FM_B),
+	PINMUX_IPSR_DATA(IP6_1_0,	CAN1_TX_B),
+
+	PINMUX_IPSR_DATA(IP6_4_2,	SSI_WS6),
+	PINMUX_IPSR_MSEL(IP6_4_2,	HSPI_CLK2_A,	SEL_HSPI2_A),
+	PINMUX_IPSR_DATA(IP6_4_2,	BPFCLK_B),
+	PINMUX_IPSR_MSEL(IP6_4_2,	CAN1_RX_B,	SEL_CAN1_B),
+
+	PINMUX_IPSR_DATA(IP6_6_5,	SSI_SDATA6),
+	PINMUX_IPSR_DATA(IP6_6_5,	HSPI_TX2_A),
+	PINMUX_IPSR_MSEL(IP6_6_5,	FMIN_B,		SEL_FM_B),
+
+	PINMUX_IPSR_DATA(IP6_7,		SSI_SCK5),
+	PINMUX_IPSR_MSEL(IP6_7,		RX4_C,		SEL_SCIF4_C),
+
+	PINMUX_IPSR_DATA(IP6_8,		SSI_WS5),
+	PINMUX_IPSR_DATA(IP6_8,		TX4_C),
+
+	PINMUX_IPSR_DATA(IP6_9,		SSI_SDATA5),
+	PINMUX_IPSR_MSEL(IP6_9,		RX0_D,		SEL_SCIF0_D),
+
+	PINMUX_IPSR_DATA(IP6_10,	SSI_WS34),
+	PINMUX_IPSR_DATA(IP6_10,	ARM_TRACEDATA_8),
+
+	PINMUX_IPSR_DATA(IP6_12_11,	SSI_SDATA4),
+	PINMUX_IPSR_MSEL(IP6_12_11,	SSI_WS2_A,	SEL_SSI2_A),
+	PINMUX_IPSR_DATA(IP6_12_11,	ARM_TRACEDATA_9),
+
+	PINMUX_IPSR_DATA(IP6_13,	SSI_SDATA3),
+	PINMUX_IPSR_DATA(IP6_13,	ARM_TRACEDATA_10),
+
+	PINMUX_IPSR_DATA(IP6_15_14,	SSI_SCK012),
+	PINMUX_IPSR_DATA(IP6_15_14,	ARM_TRACEDATA_11),
+	PINMUX_IPSR_DATA(IP6_15_14,	TX0_D),
+
+	PINMUX_IPSR_DATA(IP6_16,	SSI_WS012),
+	PINMUX_IPSR_DATA(IP6_16,	ARM_TRACEDATA_12),
+
+	PINMUX_IPSR_DATA(IP6_18_17,	SSI_SDATA2),
+	PINMUX_IPSR_MSEL(IP6_18_17,	HSPI_CS2_A,	SEL_HSPI2_A),
+	PINMUX_IPSR_DATA(IP6_18_17,	ARM_TRACEDATA_13),
+	PINMUX_IPSR_MSEL(IP6_18_17,	SDA1_A,		SEL_I2C1_A),
+
+	PINMUX_IPSR_DATA(IP6_20_19,	SSI_SDATA1),
+	PINMUX_IPSR_DATA(IP6_20_19,	ARM_TRACEDATA_14),
+	PINMUX_IPSR_MSEL(IP6_20_19,	SCL1_A,		SEL_I2C1_A),
+	PINMUX_IPSR_MSEL(IP6_20_19,	SCK2_A,		SEL_SCIF2_A),
+
+	PINMUX_IPSR_DATA(IP6_21,	SSI_SDATA0),
+	PINMUX_IPSR_DATA(IP6_21,	ARM_TRACEDATA_15),
+
+	PINMUX_IPSR_DATA(IP6_23_22,	SD0_CLK),
+	PINMUX_IPSR_DATA(IP6_23_22,	SUB_TDO),
+
+	PINMUX_IPSR_DATA(IP6_25_24,	SD0_CMD),
+	PINMUX_IPSR_DATA(IP6_25_24,	SUB_TRST),
+
+	PINMUX_IPSR_DATA(IP6_27_26,	SD0_DAT0),
+	PINMUX_IPSR_DATA(IP6_27_26,	SUB_TMS),
+
+	PINMUX_IPSR_DATA(IP6_29_28,	SD0_DAT1),
+	PINMUX_IPSR_DATA(IP6_29_28,	SUB_TCK),
+
+	PINMUX_IPSR_DATA(IP6_31_30,	SD0_DAT2),
+	PINMUX_IPSR_DATA(IP6_31_30,	SUB_TDI),
+
+	/* IPSR7 */
+	PINMUX_IPSR_DATA(IP7_1_0,	SD0_DAT3),
+	PINMUX_IPSR_MSEL(IP7_1_0,	IRQ1_B,		SEL_IRQ1_B),
+
+	PINMUX_IPSR_DATA(IP7_3_2,	SD0_CD),
+	PINMUX_IPSR_DATA(IP7_3_2,	TX5_A),
+
+	PINMUX_IPSR_DATA(IP7_5_4,	SD0_WP),
+	PINMUX_IPSR_MSEL(IP7_5_4,	RX5_A,		SEL_SCIF5_A),
+
+	PINMUX_IPSR_DATA(IP7_8_6,	VI1_CLKENB),
+	PINMUX_IPSR_MSEL(IP7_8_6,	HSPI_CLK0_A,	SEL_HSPI0_A),
+	PINMUX_IPSR_DATA(IP7_8_6,	HTX1_A),
+	PINMUX_IPSR_MSEL(IP7_8_6,	RTS1_C,		SEL_SCIF1_C),
+
+	PINMUX_IPSR_DATA(IP7_11_9,	VI1_FIELD),
+	PINMUX_IPSR_MSEL(IP7_11_9,	HSPI_CS0_A,	SEL_HSPI0_A),
+	PINMUX_IPSR_MSEL(IP7_11_9,	HRX1_A,		SEL_HSCIF1_A),
+	PINMUX_IPSR_MSEL(IP7_11_9,	SCK1_C,		SEL_SCIF1_C),
+
+	PINMUX_IPSR_DATA(IP7_14_12,	VI1_HSYNC),
+	PINMUX_IPSR_MSEL(IP7_14_12,	HSPI_RX0_A,	SEL_HSPI0_A),
+	PINMUX_IPSR_MSEL(IP7_14_12,	HRTS1_A,	SEL_HSCIF1_A),
+	PINMUX_IPSR_MSEL(IP7_14_12,	FMCLK_A,	SEL_FM_A),
+	PINMUX_IPSR_MSEL(IP7_14_12,	RX1_C,		SEL_SCIF1_C),
+
+	PINMUX_IPSR_DATA(IP7_17_15,	VI1_VSYNC),
+	PINMUX_IPSR_DATA(IP7_17_15,	HSPI_TX0),
+	PINMUX_IPSR_MSEL(IP7_17_15,	HCTS1_A,	SEL_HSCIF1_A),
+	PINMUX_IPSR_DATA(IP7_17_15,	BPFCLK_A),
+	PINMUX_IPSR_DATA(IP7_17_15,	TX1_C),
+
+	PINMUX_IPSR_DATA(IP7_20_18,	TCLK0),
+	PINMUX_IPSR_MSEL(IP7_20_18,	HSCK1_A,	SEL_HSCIF1_A),
+	PINMUX_IPSR_MSEL(IP7_20_18,	FMIN_A,		SEL_FM_A),
+	PINMUX_IPSR_MSEL(IP7_20_18,	IRQ2_C,		SEL_IRQ2_C),
+	PINMUX_IPSR_MSEL(IP7_20_18,	CTS1_C,		SEL_SCIF1_C),
+	PINMUX_IPSR_DATA(IP7_20_18,	SPEEDIN),
+
+	PINMUX_IPSR_DATA(IP7_21,	VI0_CLK),
+	PINMUX_IPSR_MSEL(IP7_21,	CAN_CLK_A,	SEL_CANCLK_A),
+
+	PINMUX_IPSR_DATA(IP7_24_22,	VI0_CLKENB),
+	PINMUX_IPSR_MSEL(IP7_24_22,	SD2_DAT2_B,	SEL_SD2_B),
+	PINMUX_IPSR_DATA(IP7_24_22,	VI1_DATA0),
+	PINMUX_IPSR_DATA(IP7_24_22,	DU1_DG6),
+	PINMUX_IPSR_MSEL(IP7_24_22,	HSPI_RX1_A,	SEL_HSPI1_A),
+	PINMUX_IPSR_MSEL(IP7_24_22,	RX4_B,		SEL_SCIF4_B),
+
+	PINMUX_IPSR_DATA(IP7_28_25,	VI0_FIELD),
+	PINMUX_IPSR_MSEL(IP7_28_25,	SD2_DAT3_B,	SEL_SD2_B),
+	PINMUX_DATA(VI0_R3_C_MARK,	FN_IP7_28_25,	FN_VI0_R3_C,	FN_SEL_VI0_C), /* see sel_vi0 */
+	PINMUX_DATA(VI0_R3_D_MARK,	FN_IP7_28_25,	FN_VI0_R3_C,	FN_SEL_VI0_D), /* see sel_vi0 */
+	PINMUX_IPSR_DATA(IP7_28_25,	VI1_DATA1),
+	PINMUX_IPSR_DATA(IP7_28_25,	DU1_DG7),
+	PINMUX_IPSR_MSEL(IP7_28_25,	HSPI_CLK1_A,	SEL_HSPI1_A),
+	PINMUX_IPSR_DATA(IP7_28_25,	TX4_B),
+
+	PINMUX_IPSR_DATA(IP7_31_29,	VI0_HSYNC),
+	PINMUX_IPSR_MSEL(IP7_31_29,	SD2_CD_B,	SEL_SD2_B),
+	PINMUX_IPSR_DATA(IP7_31_29,	VI1_DATA2),
+	PINMUX_IPSR_DATA(IP7_31_29,	DU1_DR2),
+	PINMUX_IPSR_MSEL(IP7_31_29,	HSPI_CS1_A,	SEL_HSPI1_A),
+	PINMUX_IPSR_MSEL(IP7_31_29,	RX3_B,		SEL_SCIF3_B),
+
+	/* IPSR8 */
+	PINMUX_IPSR_DATA(IP8_2_0,	VI0_VSYNC),
+	PINMUX_IPSR_MSEL(IP8_2_0,	SD2_WP_B,	SEL_SD2_B),
+	PINMUX_IPSR_DATA(IP8_2_0,	VI1_DATA3),
+	PINMUX_IPSR_DATA(IP8_2_0,	DU1_DR3),
+	PINMUX_IPSR_DATA(IP8_2_0,	HSPI_TX1_A),
+	PINMUX_IPSR_DATA(IP8_2_0,	TX3_B),
+
+	PINMUX_IPSR_DATA(IP8_5_3,	VI0_DATA0_VI0_B0),
+	PINMUX_IPSR_DATA(IP8_5_3,	DU1_DG2),
+	PINMUX_IPSR_MSEL(IP8_5_3,	IRQ2_B,		SEL_IRQ2_B),
+	PINMUX_IPSR_MSEL(IP8_5_3,	RX3_D,		SEL_SCIF3_D),
+
+	PINMUX_IPSR_DATA(IP8_8_6,	VI0_DATA1_VI0_B1),
+	PINMUX_IPSR_DATA(IP8_8_6,	DU1_DG3),
+	PINMUX_IPSR_MSEL(IP8_8_6,	IRQ3_B,		SEL_IRQ3_B),
+	PINMUX_IPSR_DATA(IP8_8_6,	TX3_D),
+
+	PINMUX_IPSR_DATA(IP8_10_9,	VI0_DATA2_VI0_B2),
+	PINMUX_IPSR_DATA(IP8_10_9,	DU1_DG4),
+	PINMUX_IPSR_MSEL(IP8_10_9,	RX0_C,		SEL_SCIF0_C),
+
+	PINMUX_IPSR_DATA(IP8_13_11,	VI0_DATA3_VI0_B3),
+	PINMUX_IPSR_DATA(IP8_13_11,	DU1_DG5),
+	PINMUX_IPSR_DATA(IP8_13_11,	TX1_A),
+	PINMUX_IPSR_DATA(IP8_13_11,	TX0_C),
+
+	PINMUX_IPSR_DATA(IP8_15_14,	VI0_DATA4_VI0_B4),
+	PINMUX_IPSR_DATA(IP8_15_14,	DU1_DB2),
+	PINMUX_IPSR_MSEL(IP8_15_14,	RX1_A,		SEL_SCIF1_A),
+
+	PINMUX_IPSR_DATA(IP8_18_16,	VI0_DATA5_VI0_B5),
+	PINMUX_IPSR_DATA(IP8_18_16,	DU1_DB3),
+	PINMUX_IPSR_MSEL(IP8_18_16,	SCK1_A,		SEL_SCIF1_A),
+	PINMUX_IPSR_DATA(IP8_18_16,	PWM4),
+	PINMUX_IPSR_MSEL(IP8_18_16,	HSCK1_B,	SEL_HSCIF1_B),
+
+	PINMUX_IPSR_DATA(IP8_21_19,	VI0_DATA6_VI0_G0),
+	PINMUX_IPSR_DATA(IP8_21_19,	DU1_DB4),
+	PINMUX_IPSR_MSEL(IP8_21_19,	CTS1_A,		SEL_SCIF1_A),
+	PINMUX_IPSR_DATA(IP8_21_19,	PWM5),
+
+	PINMUX_IPSR_DATA(IP8_23_22,	VI0_DATA7_VI0_G1),
+	PINMUX_IPSR_DATA(IP8_23_22,	DU1_DB5),
+	PINMUX_IPSR_MSEL(IP8_23_22,	RTS1_A,		SEL_SCIF1_A),
+
+	PINMUX_IPSR_DATA(IP8_26_24,	VI0_G2),
+	PINMUX_IPSR_DATA(IP8_26_24,	SD2_CLK_B),
+	PINMUX_IPSR_DATA(IP8_26_24,	VI1_DATA4),
+	PINMUX_IPSR_DATA(IP8_26_24,	DU1_DR4),
+	PINMUX_IPSR_DATA(IP8_26_24,	HTX1_B),
+
+	PINMUX_IPSR_DATA(IP8_29_27,	VI0_G3),
+	PINMUX_IPSR_MSEL(IP8_29_27,	SD2_CMD_B,	SEL_SD2_B),
+	PINMUX_IPSR_DATA(IP8_29_27,	VI1_DATA5),
+	PINMUX_IPSR_DATA(IP8_29_27,	DU1_DR5),
+	PINMUX_IPSR_MSEL(IP8_29_27,	HRX1_B,		SEL_HSCIF1_B),
+
+	/* IPSR9 */
+	PINMUX_IPSR_DATA(IP9_2_0,	VI0_G4),
+	PINMUX_IPSR_MSEL(IP9_2_0,	SD2_DAT0_B,	SEL_SD2_B),
+	PINMUX_IPSR_DATA(IP9_2_0,	VI1_DATA6),
+	PINMUX_IPSR_DATA(IP9_2_0,	DU1_DR6),
+	PINMUX_IPSR_MSEL(IP9_2_0,	HRTS1_B,	SEL_HSCIF1_B),
+
+	PINMUX_IPSR_DATA(IP9_5_3,	VI0_G5),
+	PINMUX_IPSR_MSEL(IP9_5_3,	SD2_DAT1_B,	SEL_SD2_B),
+	PINMUX_IPSR_DATA(IP9_5_3,	VI1_DATA7),
+	PINMUX_IPSR_DATA(IP9_5_3,	DU1_DR7),
+	PINMUX_IPSR_MSEL(IP9_5_3,	HCTS1_B,	SEL_HSCIF1_B),
+
+	PINMUX_DATA(VI0_R0_A_MARK,	FN_IP9_8_6,	FN_VI0_R0_A,	FN_SEL_VI0_A), /* see sel_vi0 */
+	PINMUX_DATA(VI0_R0_C_MARK,	FN_IP9_8_6,	FN_VI0_R0_A,	FN_SEL_VI0_C), /* see sel_vi0 */
+	PINMUX_IPSR_DATA(IP9_8_6,	VI1_CLK),
+	PINMUX_IPSR_DATA(IP9_8_6,	ETH_REF_CLK),
+	PINMUX_IPSR_DATA(IP9_8_6,	DU1_DOTCLKIN),
+
+	PINMUX_DATA(VI0_R1_A_MARK,	FN_IP9_11_9,	FN_VI0_R1_A,	FN_SEL_VI0_A), /* see sel_vi0 */
+	PINMUX_DATA(VI0_R1_C_MARK,	FN_IP9_11_9,	FN_VI0_R1_A,	FN_SEL_VI0_C), /* see sel_vi0 */
+	PINMUX_IPSR_DATA(IP9_11_9,	VI1_DATA8),
+	PINMUX_IPSR_DATA(IP9_11_9,	DU1_DB6),
+	PINMUX_IPSR_DATA(IP9_11_9,	ETH_TXD0),
+	PINMUX_IPSR_DATA(IP9_11_9,	PWM2),
+	PINMUX_IPSR_DATA(IP9_11_9,	TCLK1),
+
+	PINMUX_DATA(VI0_R2_A_MARK,	FN_IP9_14_12,	FN_VI0_R2_A,	FN_SEL_VI0_A), /* see sel_vi0 */
+	PINMUX_DATA(VI0_R2_C_MARK,	FN_IP9_14_12,	FN_VI0_R2_A,	FN_SEL_VI0_C), /* see sel_vi0 */
+	PINMUX_IPSR_DATA(IP9_14_12,	VI1_DATA9),
+	PINMUX_IPSR_DATA(IP9_14_12,	DU1_DB7),
+	PINMUX_IPSR_DATA(IP9_14_12,	ETH_TXD1),
+	PINMUX_IPSR_DATA(IP9_14_12,	PWM3),
+
+	PINMUX_IPSR_MSEL(IP9_17_15,	VI0_R3_A,	SEL_VI0_A),
+	PINMUX_IPSR_DATA(IP9_17_15,	ETH_CRS_DV),
+	PINMUX_IPSR_DATA(IP9_17_15,	IECLK),
+	PINMUX_IPSR_MSEL(IP9_17_15,	SCK2_C,		SEL_SCIF2_C),
+
+	PINMUX_DATA(VI0_R4_A_MARK,	FN_IP9_20_18,	FN_VI0_R4_A,	FN_SEL_VI0_A), /* see sel_vi0 */
+	PINMUX_DATA(VI0_R3_C_MARK,	FN_IP9_20_18,	FN_VI0_R4_A,	FN_SEL_VI0_C), /* see sel_vi0 */
+	PINMUX_IPSR_DATA(IP9_20_18,	ETH_TX_EN),
+	PINMUX_IPSR_DATA(IP9_20_18,	IETX),
+	PINMUX_IPSR_DATA(IP9_20_18,	TX2_C),
+
+	PINMUX_DATA(VI0_R5_A_MARK,	FN_IP9_23_21,	FN_VI0_R5_A,	FN_SEL_VI0_A), /* see sel_vi0 */
+	PINMUX_DATA(VI0_R5_C_MARK,	FN_IP9_23_21,	FN_VI0_R5_A,	FN_SEL_VI0_C), /* see sel_vi0 */
+	PINMUX_IPSR_DATA(IP9_23_21,	ETH_RX_ER),
+	PINMUX_IPSR_MSEL(IP9_23_21,	FMCLK_C,	SEL_FM_C),
+	PINMUX_IPSR_DATA(IP9_23_21,	IERX),
+	PINMUX_IPSR_MSEL(IP9_23_21,	RX2_C,		SEL_SCIF2_C),
+
+	PINMUX_IPSR_MSEL(IP9_26_24,	VI1_DATA10_A,	SEL_VI1_A),
+	PINMUX_IPSR_DATA(IP9_26_24,	DU1_DOTCLKOUT),
+	PINMUX_IPSR_DATA(IP9_26_24,	ETH_RXD0),
+	PINMUX_IPSR_DATA(IP9_26_24,	BPFCLK_C),
+	PINMUX_IPSR_DATA(IP9_26_24,	TX2_D),
+	PINMUX_IPSR_MSEL(IP9_26_24,	SDA2_C,		SEL_I2C2_C),
+
+	PINMUX_IPSR_MSEL(IP9_29_27,	VI1_DATA11_A,	SEL_VI1_A),
+	PINMUX_IPSR_DATA(IP9_29_27,	DU1_EXHSYNC_DU1_HSYNC),
+	PINMUX_IPSR_DATA(IP9_29_27,	ETH_RXD1),
+	PINMUX_IPSR_MSEL(IP9_29_27,	FMIN_C,		SEL_FM_C),
+	PINMUX_IPSR_MSEL(IP9_29_27,	RX2_D,		SEL_SCIF2_D),
+	PINMUX_IPSR_MSEL(IP9_29_27,	SCL2_C,		SEL_I2C2_C),
+
+	/* IPSR10 */
+	PINMUX_IPSR_DATA(IP10_2_0,	SD2_CLK_A),
+	PINMUX_IPSR_DATA(IP10_2_0,	DU1_EXVSYNC_DU1_VSYNC),
+	PINMUX_IPSR_DATA(IP10_2_0,	ATARD1),
+	PINMUX_IPSR_DATA(IP10_2_0,	ETH_MDC),
+	PINMUX_IPSR_MSEL(IP10_2_0,	SDA1_B,		SEL_I2C1_B),
+
+	PINMUX_IPSR_MSEL(IP10_5_3,	SD2_CMD_A,	SEL_SD2_A),
+	PINMUX_IPSR_DATA(IP10_5_3,	DU1_EXODDF_DU1_ODDF_DISP_CDE),
+	PINMUX_IPSR_DATA(IP10_5_3,	ATAWR1),
+	PINMUX_IPSR_DATA(IP10_5_3,	ETH_MDIO),
+	PINMUX_IPSR_MSEL(IP10_5_3,	SCL1_B,		SEL_I2C1_B),
+
+	PINMUX_IPSR_MSEL(IP10_8_6,	SD2_DAT0_A,	SEL_SD2_A),
+	PINMUX_IPSR_DATA(IP10_8_6,	DU1_DISP),
+	PINMUX_IPSR_DATA(IP10_8_6,	ATACS01),
+	PINMUX_IPSR_MSEL(IP10_8_6,	DREQ1_B,	SEL_DREQ1_B),
+	PINMUX_IPSR_DATA(IP10_8_6,	ETH_LINK),
+	PINMUX_IPSR_MSEL(IP10_8_6,	CAN1_RX_A,	SEL_CAN1_A),
+
+	PINMUX_IPSR_MSEL(IP10_12_9,	SD2_DAT1_A,	SEL_SD2_A),
+	PINMUX_IPSR_DATA(IP10_12_9,	DU1_CDE),
+	PINMUX_IPSR_DATA(IP10_12_9,	ATACS11),
+	PINMUX_IPSR_DATA(IP10_12_9,	DACK1_B),
+	PINMUX_IPSR_DATA(IP10_12_9,	ETH_MAGIC),
+	PINMUX_IPSR_DATA(IP10_12_9,	CAN1_TX_A),
+	PINMUX_IPSR_DATA(IP10_12_9,	PWM6),
+
+	PINMUX_IPSR_MSEL(IP10_15_13,	SD2_DAT2_A,	SEL_SD2_A),
+	PINMUX_IPSR_DATA(IP10_15_13,	VI1_DATA12),
+	PINMUX_IPSR_MSEL(IP10_15_13,	DREQ2_B,	SEL_DREQ2_B),
+	PINMUX_IPSR_DATA(IP10_15_13,	ATADIR1),
+	PINMUX_IPSR_MSEL(IP10_15_13,	HSPI_CLK2_B,	SEL_HSPI2_B),
+	PINMUX_IPSR_MSEL(IP10_15_13,	GPSCLK_B,	SEL_GPS_B),
+
+	PINMUX_IPSR_MSEL(IP10_18_16,	SD2_DAT3_A,	SEL_SD2_A),
+	PINMUX_IPSR_DATA(IP10_18_16,	VI1_DATA13),
+	PINMUX_IPSR_DATA(IP10_18_16,	DACK2_B),
+	PINMUX_IPSR_DATA(IP10_18_16,	ATAG1),
+	PINMUX_IPSR_MSEL(IP10_18_16,	HSPI_CS2_B,	SEL_HSPI2_B),
+	PINMUX_IPSR_MSEL(IP10_18_16,	GPSIN_B,	SEL_GPS_B),
+
+	PINMUX_IPSR_MSEL(IP10_21_19,	SD2_CD_A,	SEL_SD2_A),
+	PINMUX_IPSR_DATA(IP10_21_19,	VI1_DATA14),
+	PINMUX_IPSR_MSEL(IP10_21_19,	EX_WAIT1_B,	SEL_WAIT1_B),
+	PINMUX_IPSR_MSEL(IP10_21_19,	DREQ0_B,	SEL_DREQ0_B),
+	PINMUX_IPSR_MSEL(IP10_21_19,	HSPI_RX2_B,	SEL_HSPI2_B),
+	PINMUX_IPSR_MSEL(IP10_21_19,	REMOCON_A,	SEL_REMOCON_A),
+
+	PINMUX_IPSR_MSEL(IP10_24_22,	SD2_WP_A,	SEL_SD2_A),
+	PINMUX_IPSR_DATA(IP10_24_22,	VI1_DATA15),
+	PINMUX_IPSR_MSEL(IP10_24_22,	EX_WAIT2_B,	SEL_WAIT2_B),
+	PINMUX_IPSR_DATA(IP10_24_22,	DACK0_B),
+	PINMUX_IPSR_DATA(IP10_24_22,	HSPI_TX2_B),
+	PINMUX_IPSR_MSEL(IP10_24_22,	CAN_CLK_C,	SEL_CANCLK_C),
+};
+
+static struct sh_pfc_pin pinmux_pins[] = {
+	PINMUX_GPIO_GP_ALL(),
+};
+
+/* Pin numbers for pins without a corresponding GPIO port number are computed
+ * from the row and column numbers with a 1000 offset to avoid collisions with
+ * GPIO port numbers.
+ */
+#define PIN_NUMBER(row, col)		(1000+((row)-1)*25+(col)-1)
+
+/* - SCIF macro ------------------------------------------------------------- */
+#define SCIF_PFC_PIN(name, args...)					\
+	static const unsigned int name ##_pins[] = { args }
+#define SCIF_PFC_DAT(name, tx, rx)					\
+	static const unsigned int name ##_mux[]  = { tx##_MARK, rx##_MARK, }
+#define SCIF_PFC_CTR(name, cts, rts)					\
+	static const unsigned int name ##_mux[]  = { cts##_MARK, rts##_MARK, }
+#define SCIF_PFC_CLK(name, sck)					\
+	static const unsigned int name ##_mux[]  = { sck##_MARK, }
+
+/* - HSCIF0 ----------------------------------------------------------------- */
+SCIF_PFC_PIN(hscif0_data_a,	RCAR_GP_PIN(1, 17),	RCAR_GP_PIN(1, 18));
+SCIF_PFC_DAT(hscif0_data_a,	HTX0_A,			HRX0_A);
+SCIF_PFC_PIN(hscif0_data_b,	RCAR_GP_PIN(0, 29),	RCAR_GP_PIN(0, 30));
+SCIF_PFC_DAT(hscif0_data_b,	HTX0_B,			HRX0_B);
+SCIF_PFC_PIN(hscif0_ctrl_a,	RCAR_GP_PIN(1, 20),	RCAR_GP_PIN(1, 21));
+SCIF_PFC_CTR(hscif0_ctrl_a,	HCTS0_A,		HRTS0_A);
+SCIF_PFC_PIN(hscif0_ctrl_b,	RCAR_GP_PIN(0, 31),	RCAR_GP_PIN(0, 28));
+SCIF_PFC_CTR(hscif0_ctrl_b,	HCTS0_B,		HRTS0_B);
+SCIF_PFC_PIN(hscif0_clk,	RCAR_GP_PIN(1, 19));
+SCIF_PFC_CLK(hscif0_clk,	HSCK0);
+
+/* - HSCIF1 ----------------------------------------------------------------- */
+SCIF_PFC_PIN(hscif1_data_a,	RCAR_GP_PIN(3, 19),	RCAR_GP_PIN(3, 20));
+SCIF_PFC_DAT(hscif1_data_a,	HTX1_A,			HRX1_A);
+SCIF_PFC_PIN(hscif1_data_b,	RCAR_GP_PIN(4, 5),	RCAR_GP_PIN(4, 6));
+SCIF_PFC_DAT(hscif1_data_b,	HTX1_B,			HRX1_B);
+SCIF_PFC_PIN(hscif1_ctrl_a,	RCAR_GP_PIN(3, 22),	RCAR_GP_PIN(3, 21));
+SCIF_PFC_CTR(hscif1_ctrl_a,	HCTS1_A,		HRTS1_A);
+SCIF_PFC_PIN(hscif1_ctrl_b,	RCAR_GP_PIN(4, 8),	RCAR_GP_PIN(4, 7));
+SCIF_PFC_CTR(hscif1_ctrl_b,	HCTS1_B,		HRTS1_B);
+SCIF_PFC_PIN(hscif1_clk_a,	RCAR_GP_PIN(3, 23));
+SCIF_PFC_CLK(hscif1_clk_a,	HSCK1_A);
+SCIF_PFC_PIN(hscif1_clk_b,	RCAR_GP_PIN(4, 2));
+SCIF_PFC_CLK(hscif1_clk_b,	HSCK1_B);
+
+/* - SCIF CLOCK ------------------------------------------------------------- */
+SCIF_PFC_PIN(scif_clk,		RCAR_GP_PIN(1, 16));
+SCIF_PFC_CLK(scif_clk,		SCIF_CLK);
+
+/* - SCIF0 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif0_data_a,	RCAR_GP_PIN(1, 17),	RCAR_GP_PIN(1, 18));
+SCIF_PFC_DAT(scif0_data_a,	TX0_A,			RX0_A);
+SCIF_PFC_PIN(scif0_data_b,	RCAR_GP_PIN(2, 3),	RCAR_GP_PIN(2, 2));
+SCIF_PFC_DAT(scif0_data_b,	TX0_B,			RX0_B);
+SCIF_PFC_PIN(scif0_data_c,	RCAR_GP_PIN(4, 0),	RCAR_GP_PIN(3, 31));
+SCIF_PFC_DAT(scif0_data_c,	TX0_C,			RX0_C);
+SCIF_PFC_PIN(scif0_data_d,	RCAR_GP_PIN(3, 6),	RCAR_GP_PIN(3, 1));
+SCIF_PFC_DAT(scif0_data_d,	TX0_D,			RX0_D);
+SCIF_PFC_PIN(scif0_ctrl,	RCAR_GP_PIN(1, 20),	RCAR_GP_PIN(1, 21));
+SCIF_PFC_CTR(scif0_ctrl,	CTS0,			RTS0);
+SCIF_PFC_PIN(scif0_clk,		RCAR_GP_PIN(1, 19));
+SCIF_PFC_CLK(scif0_clk,		SCK0);
+
+/* - SCIF1 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif1_data_a,	RCAR_GP_PIN(4, 0),	RCAR_GP_PIN(4, 1));
+SCIF_PFC_DAT(scif1_data_a,	TX1_A,			RX1_A);
+SCIF_PFC_PIN(scif1_data_b,	RCAR_GP_PIN(2, 24),	RCAR_GP_PIN(2, 25));
+SCIF_PFC_DAT(scif1_data_b,	TX1_B,			RX1_B);
+SCIF_PFC_PIN(scif1_data_c,	RCAR_GP_PIN(3, 22),	RCAR_GP_PIN(3, 21));
+SCIF_PFC_DAT(scif1_data_c,	TX1_C,			RX1_C);
+SCIF_PFC_PIN(scif1_data_d,	RCAR_GP_PIN(1, 30),	RCAR_GP_PIN(1, 31));
+SCIF_PFC_DAT(scif1_data_d,	TX1_D,			RX1_D);
+SCIF_PFC_PIN(scif1_ctrl_a,	RCAR_GP_PIN(4, 3),	RCAR_GP_PIN(4, 4));
+SCIF_PFC_CTR(scif1_ctrl_a,	CTS1_A,			RTS1_A);
+SCIF_PFC_PIN(scif1_ctrl_c,	RCAR_GP_PIN(3, 23),	RCAR_GP_PIN(3, 19));
+SCIF_PFC_CTR(scif1_ctrl_c,	CTS1_C,			RTS1_C);
+SCIF_PFC_PIN(scif1_clk_a,	RCAR_GP_PIN(4, 2));
+SCIF_PFC_CLK(scif1_clk_a,	SCK1_A);
+SCIF_PFC_PIN(scif1_clk_c,	RCAR_GP_PIN(3, 20));
+SCIF_PFC_CLK(scif1_clk_c,	SCK1_C);
+
+/* - SCIF2 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif2_data_a,	RCAR_GP_PIN(2, 26),	RCAR_GP_PIN(2, 27));
+SCIF_PFC_DAT(scif2_data_a,	TX2_A,			RX2_A);
+SCIF_PFC_PIN(scif2_data_b,	RCAR_GP_PIN(0, 29),	RCAR_GP_PIN(0, 28));
+SCIF_PFC_DAT(scif2_data_b,	TX2_B,			RX2_B);
+SCIF_PFC_PIN(scif2_data_c,	RCAR_GP_PIN(4, 13),	RCAR_GP_PIN(4, 14));
+SCIF_PFC_DAT(scif2_data_c,	TX2_C,			RX2_C);
+SCIF_PFC_PIN(scif2_data_d,	RCAR_GP_PIN(4, 15),	RCAR_GP_PIN(4, 16));
+SCIF_PFC_DAT(scif2_data_d,	TX2_D,			RX2_D);
+SCIF_PFC_PIN(scif2_data_e,	RCAR_GP_PIN(0, 3),	RCAR_GP_PIN(0, 4));
+SCIF_PFC_DAT(scif2_data_e,	TX2_E,			RX2_E);
+SCIF_PFC_PIN(scif2_clk_a,	RCAR_GP_PIN(3, 9));
+SCIF_PFC_CLK(scif2_clk_a,	SCK2_A);
+SCIF_PFC_PIN(scif2_clk_b,	PIN_NUMBER(3, 20));
+SCIF_PFC_CLK(scif2_clk_b,	SCK2_B);
+SCIF_PFC_PIN(scif2_clk_c,	RCAR_GP_PIN(4, 12));
+SCIF_PFC_CLK(scif2_clk_c,	SCK2_C);
+
+/* - SCIF3 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif3_data_a,	RCAR_GP_PIN(1, 10),	RCAR_GP_PIN(1, 9));
+SCIF_PFC_DAT(scif3_data_a,	TX3_A,			RX3_A);
+SCIF_PFC_PIN(scif3_data_b,	RCAR_GP_PIN(3, 28),	RCAR_GP_PIN(3, 27));
+SCIF_PFC_DAT(scif3_data_b,	TX3_B,			RX3_B);
+SCIF_PFC_PIN(scif3_data_c,	RCAR_GP_PIN(1, 3),	RCAR_GP_PIN(0, 31));
+SCIF_PFC_DAT(scif3_data_c,	TX3_C,			RX3_C);
+SCIF_PFC_PIN(scif3_data_d,	RCAR_GP_PIN(3, 30),	RCAR_GP_PIN(3, 29));
+SCIF_PFC_DAT(scif3_data_d,	TX3_D,			RX3_D);
+
+/* - SCIF4 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif4_data_a,	RCAR_GP_PIN(2, 5),	RCAR_GP_PIN(2, 4));
+SCIF_PFC_DAT(scif4_data_a,	TX4_A,			RX4_A);
+SCIF_PFC_PIN(scif4_data_b,	RCAR_GP_PIN(3, 26),	RCAR_GP_PIN(3, 25));
+SCIF_PFC_DAT(scif4_data_b,	TX4_B,			RX4_B);
+SCIF_PFC_PIN(scif4_data_c,	RCAR_GP_PIN(3, 0),	RCAR_GP_PIN(2, 31));
+SCIF_PFC_DAT(scif4_data_c,	TX4_C,			RX4_C);
+
+/* - SCIF5 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif5_data_a,	RCAR_GP_PIN(3, 17),	RCAR_GP_PIN(3, 18));
+SCIF_PFC_DAT(scif5_data_a,	TX5_A,			RX5_A);
+SCIF_PFC_PIN(scif5_data_b,	RCAR_GP_PIN(1, 15),	RCAR_GP_PIN(1, 14));
+SCIF_PFC_DAT(scif5_data_b,	TX5_B,			RX5_B);
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SH_PFC_PIN_GROUP(hscif0_data_a),
+	SH_PFC_PIN_GROUP(hscif0_data_b),
+	SH_PFC_PIN_GROUP(hscif0_ctrl_a),
+	SH_PFC_PIN_GROUP(hscif0_ctrl_b),
+	SH_PFC_PIN_GROUP(hscif0_clk),
+	SH_PFC_PIN_GROUP(hscif1_data_a),
+	SH_PFC_PIN_GROUP(hscif1_data_b),
+	SH_PFC_PIN_GROUP(hscif1_ctrl_a),
+	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
+	SH_PFC_PIN_GROUP(hscif1_clk_a),
+	SH_PFC_PIN_GROUP(hscif1_clk_b),
+	SH_PFC_PIN_GROUP(scif_clk),
+	SH_PFC_PIN_GROUP(scif0_data_a),
+	SH_PFC_PIN_GROUP(scif0_data_b),
+	SH_PFC_PIN_GROUP(scif0_data_c),
+	SH_PFC_PIN_GROUP(scif0_data_d),
+	SH_PFC_PIN_GROUP(scif0_ctrl),
+	SH_PFC_PIN_GROUP(scif0_clk),
+	SH_PFC_PIN_GROUP(scif1_data_a),
+	SH_PFC_PIN_GROUP(scif1_data_b),
+	SH_PFC_PIN_GROUP(scif1_data_c),
+	SH_PFC_PIN_GROUP(scif1_data_d),
+	SH_PFC_PIN_GROUP(scif1_ctrl_a),
+	SH_PFC_PIN_GROUP(scif1_ctrl_c),
+	SH_PFC_PIN_GROUP(scif1_clk_a),
+	SH_PFC_PIN_GROUP(scif1_clk_c),
+	SH_PFC_PIN_GROUP(scif2_data_a),
+	SH_PFC_PIN_GROUP(scif2_data_b),
+	SH_PFC_PIN_GROUP(scif2_data_c),
+	SH_PFC_PIN_GROUP(scif2_data_d),
+	SH_PFC_PIN_GROUP(scif2_data_e),
+	SH_PFC_PIN_GROUP(scif2_clk_a),
+	SH_PFC_PIN_GROUP(scif2_clk_b),
+	SH_PFC_PIN_GROUP(scif2_clk_c),
+	SH_PFC_PIN_GROUP(scif3_data_a),
+	SH_PFC_PIN_GROUP(scif3_data_b),
+	SH_PFC_PIN_GROUP(scif3_data_c),
+	SH_PFC_PIN_GROUP(scif3_data_d),
+	SH_PFC_PIN_GROUP(scif4_data_a),
+	SH_PFC_PIN_GROUP(scif4_data_b),
+	SH_PFC_PIN_GROUP(scif4_data_c),
+	SH_PFC_PIN_GROUP(scif5_data_a),
+	SH_PFC_PIN_GROUP(scif5_data_b),
+};
+
+static const char * const hscif0_groups[] = {
+	"hscif0_data_a",
+	"hscif0_data_b",
+	"hscif0_ctrl_a",
+	"hscif0_ctrl_b",
+	"hscif0_clk",
+};
+
+static const char * const hscif1_groups[] = {
+	"hscif1_data_a",
+	"hscif1_data_b",
+	"hscif1_ctrl_a",
+	"hscif1_ctrl_b",
+	"hscif1_clk_a",
+	"hscif1_clk_b",
+};
+
+static const char * const scif_clk_groups[] = {
+	"scif_clk",
+};
+
+static const char * const scif0_groups[] = {
+	"scif0_data_a",
+	"scif0_data_b",
+	"scif0_data_c",
+	"scif0_data_d",
+	"scif0_ctrl",
+	"scif0_clk",
+};
+
+static const char * const scif1_groups[] = {
+	"scif1_data_a",
+	"scif1_data_b",
+	"scif1_data_c",
+	"scif1_data_d",
+	"scif1_ctrl_a",
+	"scif1_ctrl_c",
+	"scif1_clk_a",
+	"scif1_clk_c",
+};
+
+static const char * const scif2_groups[] = {
+	"scif2_data_a",
+	"scif2_data_b",
+	"scif2_data_c",
+	"scif2_data_d",
+	"scif2_data_e",
+	"scif2_clk_a",
+	"scif2_clk_b",
+	"scif2_clk_c",
+};
+
+static const char * const scif3_groups[] = {
+	"scif3_data_a",
+	"scif3_data_b",
+	"scif3_data_c",
+	"scif3_data_d",
+};
+
+static const char * const scif4_groups[] = {
+	"scif4_data_a",
+	"scif4_data_b",
+	"scif4_data_c",
+};
+
+static const char * const scif5_groups[] = {
+	"scif5_data_a",
+	"scif5_data_b",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(hscif0),
+	SH_PFC_FUNCTION(hscif1),
+	SH_PFC_FUNCTION(scif_clk),
+	SH_PFC_FUNCTION(scif0),
+	SH_PFC_FUNCTION(scif1),
+	SH_PFC_FUNCTION(scif2),
+	SH_PFC_FUNCTION(scif3),
+	SH_PFC_FUNCTION(scif4),
+	SH_PFC_FUNCTION(scif5),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+	{ PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
+		GP_0_31_FN,	FN_IP1_14_11,
+		GP_0_30_FN,	FN_IP1_10_8,
+		GP_0_29_FN,	FN_IP1_7_5,
+		GP_0_28_FN,	FN_IP1_4_2,
+		GP_0_27_FN,	FN_IP1_1,
+		GP_0_26_FN,	FN_IP1_0,
+		GP_0_25_FN,	FN_IP0_30,
+		GP_0_24_FN,	FN_IP0_29,
+		GP_0_23_FN,	FN_IP0_28,
+		GP_0_22_FN,	FN_IP0_27,
+		GP_0_21_FN,	FN_IP0_26,
+		GP_0_20_FN,	FN_IP0_25,
+		GP_0_19_FN,	FN_IP0_24,
+		GP_0_18_FN,	FN_IP0_23,
+		GP_0_17_FN,	FN_IP0_22,
+		GP_0_16_FN,	FN_IP0_21,
+		GP_0_15_FN,	FN_IP0_20,
+		GP_0_14_FN,	FN_IP0_19,
+		GP_0_13_FN,	FN_IP0_18,
+		GP_0_12_FN,	FN_IP0_17,
+		GP_0_11_FN,	FN_IP0_16,
+		GP_0_10_FN,	FN_IP0_15,
+		GP_0_9_FN,	FN_A3,
+		GP_0_8_FN,	FN_A2,
+		GP_0_7_FN,	FN_A1,
+		GP_0_6_FN,	FN_IP0_14_12,
+		GP_0_5_FN,	FN_IP0_11_8,
+		GP_0_4_FN,	FN_IP0_7_5,
+		GP_0_3_FN,	FN_IP0_4_2,
+		GP_0_2_FN,	FN_PENC1,
+		GP_0_1_FN,	FN_PENC0,
+		GP_0_0_FN,	FN_IP0_1_0 }
+	},
+	{ PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
+		GP_1_31_FN,	FN_IP4_6_4,
+		GP_1_30_FN,	FN_IP4_3_1,
+		GP_1_29_FN,	FN_IP4_0,
+		GP_1_28_FN,	FN_IP3_31,
+		GP_1_27_FN,	FN_IP3_30,
+		GP_1_26_FN,	FN_IP3_29,
+		GP_1_25_FN,	FN_IP3_28,
+		GP_1_24_FN,	FN_IP3_27,
+		GP_1_23_FN,	FN_IP3_26_24,
+		GP_1_22_FN,	FN_IP3_23_21,
+		GP_1_21_FN,	FN_IP3_20_19,
+		GP_1_20_FN,	FN_IP3_18_16,
+		GP_1_19_FN,	FN_IP3_15_13,
+		GP_1_18_FN,	FN_IP3_12_10,
+		GP_1_17_FN,	FN_IP3_9_8,
+		GP_1_16_FN,	FN_IP3_7_5,
+		GP_1_15_FN,	FN_IP3_4_2,
+		GP_1_14_FN,	FN_IP3_1_0,
+		GP_1_13_FN,	FN_IP2_31,
+		GP_1_12_FN,	FN_IP2_30,
+		GP_1_11_FN,	FN_IP2_17,
+		GP_1_10_FN,	FN_IP2_16_14,
+		GP_1_9_FN,	FN_IP2_13_12,
+		GP_1_8_FN,	FN_IP2_11_9,
+		GP_1_7_FN,	FN_IP2_8_6,
+		GP_1_6_FN,	FN_IP2_5_3,
+		GP_1_5_FN,	FN_IP2_2_0,
+		GP_1_4_FN,	FN_IP1_29_28,
+		GP_1_3_FN,	FN_IP1_27_25,
+		GP_1_2_FN,	FN_IP1_24,
+		GP_1_1_FN,	FN_WE0,
+		GP_1_0_FN,	FN_IP1_23_21 }
+	},
+	{ PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
+		GP_2_31_FN,	FN_IP6_7,
+		GP_2_30_FN,	FN_IP6_6_5,
+		GP_2_29_FN,	FN_IP6_4_2,
+		GP_2_28_FN,	FN_IP6_1_0,
+		GP_2_27_FN,	FN_IP5_30_29,
+		GP_2_26_FN,	FN_IP5_28_26,
+		GP_2_25_FN,	FN_IP5_25_23,
+		GP_2_24_FN,	FN_IP5_22_21,
+		GP_2_23_FN,	FN_AUDIO_CLKB,
+		GP_2_22_FN,	FN_AUDIO_CLKA,
+		GP_2_21_FN,	FN_IP5_20_18,
+		GP_2_20_FN,	FN_IP5_17_15,
+		GP_2_19_FN,	FN_IP5_14_13,
+		GP_2_18_FN,	FN_IP5_12,
+		GP_2_17_FN,	FN_IP5_11_10,
+		GP_2_16_FN,	FN_IP5_9_8,
+		GP_2_15_FN,	FN_IP5_7,
+		GP_2_14_FN,	FN_IP5_6,
+		GP_2_13_FN,	FN_IP5_5_4,
+		GP_2_12_FN,	FN_IP5_3_2,
+		GP_2_11_FN,	FN_IP5_1_0,
+		GP_2_10_FN,	FN_IP4_30_29,
+		GP_2_9_FN,	FN_IP4_28_27,
+		GP_2_8_FN,	FN_IP4_26_25,
+		GP_2_7_FN,	FN_IP4_24_21,
+		GP_2_6_FN,	FN_IP4_20_17,
+		GP_2_5_FN,	FN_IP4_16_15,
+		GP_2_4_FN,	FN_IP4_14_13,
+		GP_2_3_FN,	FN_IP4_12_11,
+		GP_2_2_FN,	FN_IP4_10_9,
+		GP_2_1_FN,	FN_IP4_8,
+		GP_2_0_FN,	FN_IP4_7 }
+	},
+	{ PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
+		GP_3_31_FN,	FN_IP8_10_9,
+		GP_3_30_FN,	FN_IP8_8_6,
+		GP_3_29_FN,	FN_IP8_5_3,
+		GP_3_28_FN,	FN_IP8_2_0,
+		GP_3_27_FN,	FN_IP7_31_29,
+		GP_3_26_FN,	FN_IP7_28_25,
+		GP_3_25_FN,	FN_IP7_24_22,
+		GP_3_24_FN,	FN_IP7_21,
+		GP_3_23_FN,	FN_IP7_20_18,
+		GP_3_22_FN,	FN_IP7_17_15,
+		GP_3_21_FN,	FN_IP7_14_12,
+		GP_3_20_FN,	FN_IP7_11_9,
+		GP_3_19_FN,	FN_IP7_8_6,
+		GP_3_18_FN,	FN_IP7_5_4,
+		GP_3_17_FN,	FN_IP7_3_2,
+		GP_3_16_FN,	FN_IP7_1_0,
+		GP_3_15_FN,	FN_IP6_31_30,
+		GP_3_14_FN,	FN_IP6_29_28,
+		GP_3_13_FN,	FN_IP6_27_26,
+		GP_3_12_FN,	FN_IP6_25_24,
+		GP_3_11_FN,	FN_IP6_23_22,
+		GP_3_10_FN,	FN_IP6_21,
+		GP_3_9_FN,	FN_IP6_20_19,
+		GP_3_8_FN,	FN_IP6_18_17,
+		GP_3_7_FN,	FN_IP6_16,
+		GP_3_6_FN,	FN_IP6_15_14,
+		GP_3_5_FN,	FN_IP6_13,
+		GP_3_4_FN,	FN_IP6_12_11,
+		GP_3_3_FN,	FN_IP6_10,
+		GP_3_2_FN,	FN_SSI_SCK34,
+		GP_3_1_FN,	FN_IP6_9,
+		GP_3_0_FN,	FN_IP6_8 }
+	},
+	{ PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_4_26_FN,	FN_AVS2,
+		GP_4_25_FN,	FN_AVS1,
+		GP_4_24_FN,	FN_IP10_24_22,
+		GP_4_23_FN,	FN_IP10_21_19,
+		GP_4_22_FN,	FN_IP10_18_16,
+		GP_4_21_FN,	FN_IP10_15_13,
+		GP_4_20_FN,	FN_IP10_12_9,
+		GP_4_19_FN,	FN_IP10_8_6,
+		GP_4_18_FN,	FN_IP10_5_3,
+		GP_4_17_FN,	FN_IP10_2_0,
+		GP_4_16_FN,	FN_IP9_29_27,
+		GP_4_15_FN,	FN_IP9_26_24,
+		GP_4_14_FN,	FN_IP9_23_21,
+		GP_4_13_FN,	FN_IP9_20_18,
+		GP_4_12_FN,	FN_IP9_17_15,
+		GP_4_11_FN,	FN_IP9_14_12,
+		GP_4_10_FN,	FN_IP9_11_9,
+		GP_4_9_FN,	FN_IP9_8_6,
+		GP_4_8_FN,	FN_IP9_5_3,
+		GP_4_7_FN,	FN_IP9_2_0,
+		GP_4_6_FN,	FN_IP8_29_27,
+		GP_4_5_FN,	FN_IP8_26_24,
+		GP_4_4_FN,	FN_IP8_23_22,
+		GP_4_3_FN,	FN_IP8_21_19,
+		GP_4_2_FN,	FN_IP8_18_16,
+		GP_4_1_FN,	FN_IP8_15_14,
+		GP_4_0_FN,	FN_IP8_13_11 }
+	},
+
+	{ PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
+			     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			     1, 1, 1, 1, 1, 1, 3, 4, 3, 3, 2) {
+		/* IP0_31 [1] */
+		0,	0,
+		/* IP0_30 [1] */
+		FN_A19,	0,
+		/* IP0_29 [1] */
+		FN_A18,	0,
+		/* IP0_28 [1] */
+		FN_A17,	0,
+		/* IP0_27 [1] */
+		FN_A16,	0,
+		/* IP0_26 [1] */
+		FN_A15,	0,
+		/* IP0_25 [1] */
+		FN_A14,	0,
+		/* IP0_24 [1] */
+		FN_A13,	0,
+		/* IP0_23 [1] */
+		FN_A12,	0,
+		/* IP0_22 [1] */
+		FN_A11,	0,
+		/* IP0_21 [1] */
+		FN_A10,	0,
+		/* IP0_20 [1] */
+		FN_A9,	0,
+		/* IP0_19 [1] */
+		FN_A8,	0,
+		/* IP0_18 [1] */
+		FN_A7,	0,
+		/* IP0_17 [1] */
+		FN_A6,	0,
+		/* IP0_16 [1] */
+		FN_A5,	0,
+		/* IP0_15 [1] */
+		FN_A4,	0,
+		/* IP0_14_12 [3] */
+		FN_SD1_DAT3_A,	FN_MMC_D3,	0,		FN_A0,
+		FN_ATAG0_A,	0,		FN_REMOCON_B,	0,
+		/* IP0_11_8 [4] */
+		FN_SD1_DAT2_A,	FN_MMC_D2,	0,		FN_BS,
+		FN_ATADIR0_A,	0,		FN_SDSELF_B,	0,
+		FN_PWM4_B,	0,		0,		0,
+		0,		0,		0,		0,
+		/* IP0_7_5 [3] */
+		FN_AUDATA1,	FN_ARM_TRACEDATA_1,	FN_GPSIN_C,	FN_USB_OVC1,
+		FN_RX2_E,	FN_SCL2_B,		0,		0,
+		/* IP0_4_2 [3] */
+		FN_AUDATA0,	FN_ARM_TRACEDATA_0,	FN_GPSCLK_C,	FN_USB_OVC0,
+		FN_TX2_E,	FN_SDA2_B,		0,		0,
+		/* IP0_1_0 [2] */
+		FN_PRESETOUT,	0,	FN_PWM1,	0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
+			     1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3, 3, 1, 1) {
+		/* IP1_31 [1] */
+		0,	0,
+		/* IP1_30 [1] */
+		0,	0,
+		/* IP1_29_28 [2] */
+		FN_EX_CS1,	FN_MMC_D4,	0,	0,
+		/* IP1_27_25 [3] */
+		FN_SSI_WS1_B,	FN_EX_CS0,	FN_SCL2_A,	FN_TX3_C,
+		FN_TS_SCK0_A,	0,		0,		0,
+		/* IP1_24 [1] */
+		FN_WE1,		FN_ATAWR0_B,
+		/* IP1_23_21 [3] */
+		FN_MMC_D5,	FN_ATADIR0_B,	0,		FN_RD_WR,
+		0,		0,		0,		0,
+		/* IP1_20_18 [3] */
+		FN_SSI_SCK1_B,	FN_ATAG0_B,	FN_CS1_A26,	FN_SDA2_A,
+		FN_SCK2_B,	0,		0,		0,
+		/* IP1_17 [1] */
+		FN_CS0,		FN_HSPI_RX1_B,
+		/* IP1_16_15 [2] */
+		FN_CLKOUT,	FN_HSPI_TX1_B,	FN_PWM0_B,	0,
+		/* IP1_14_11 [4] */
+		FN_SD1_WP_A,	FN_MMC_D7,	0,		FN_A25,
+		FN_DACK1_A,	0,		FN_HCTS0_B,	FN_RX3_C,
+		FN_TS_SDAT0_A,	0,		0,		0,
+		0,		0,		0,		0,
+		/* IP1_10_8 [3] */
+		FN_SD1_CLK_B,	FN_MMC_D6,	0,		FN_A24,
+		FN_DREQ1_A,	0,		FN_HRX0_B,	FN_TS_SPSYNC0_A,
+		/* IP1_7_5 [3] */
+		FN_A23,		FN_HTX0_B,	FN_TX2_B,	FN_DACK2_A,
+		FN_TS_SDEN0_A,	0,		0,		0,
+		/* IP1_4_2 [3] */
+		FN_A22,		FN_HRTS0_B,	FN_RX2_B,	FN_DREQ2_A,
+		0,		0,		0,		0,
+		/* IP1_1 [1] */
+		FN_A21,		FN_HSPI_CLK1_B,
+		/* IP1_0 [1] */
+		FN_A20,		FN_HSPI_CS1_B,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
+			     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			     1, 1, 1, 1, 3, 2, 3, 3, 3, 3) {
+		/* IP2_31 [1] */
+		FN_MLB_CLK,	FN_IRQ3_A,
+		/* IP2_30 [1] */
+		FN_RD_WR_B,	FN_IRQ0,
+		/* IP2_29 [1] */
+		FN_D11,		0,
+		/* IP2_28 [1] */
+		FN_D10,		0,
+		/* IP2_27 [1] */
+		FN_D9,		0,
+		/* IP2_26 [1] */
+		FN_D8,		0,
+		/* IP2_25 [1] */
+		FN_D7,		0,
+		/* IP2_24 [1] */
+		FN_D6,		0,
+		/* IP2_23 [1] */
+		FN_D5,		0,
+		/* IP2_22 [1] */
+		FN_D4,		0,
+		/* IP2_21 [1] */
+		FN_D3,		0,
+		/* IP2_20 [1] */
+		FN_D2,		0,
+		/* IP2_19 [1] */
+		FN_D1,		0,
+		/* IP2_18 [1] */
+		FN_D0,		0,
+		/* IP2_17 [1] */
+		FN_EX_WAIT0,	FN_PWM0_C,
+		/* IP2_16_14 [3] */
+		FN_DACK0,	0,	0,	FN_TX3_A,
+		FN_DRACK0,	0,	0,	0,
+		/* IP2_13_12 [2] */
+		FN_DREQ0_A,	0,	0,	FN_RX3_A,
+		/* IP2_11_9 [3] */
+		FN_SD1_DAT1_A,	FN_MMC_D1,	0,	FN_ATAWR0_A,
+		FN_EX_CS5,	FN_EX_WAIT2_A,	0,	0,
+		/* IP2_8_6 [3] */
+		FN_SD1_DAT0_A,	FN_MMC_D0,	0,	FN_ATARD0,
+		FN_EX_CS4,	FN_EX_WAIT1_A,	0,	0,
+		/* IP2_5_3 [3] */
+		FN_SD1_CMD_A,	FN_MMC_CMD,	0,	FN_ATACS10,
+		FN_EX_CS3,	0,		0,	0,
+		/* IP2_2_0 [3] */
+		FN_SD1_CLK_A,	FN_MMC_CLK,	0,	FN_ATACS00,
+		FN_EX_CS2,	0,		0,	0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
+			     1, 1, 1, 1, 1, 3, 3, 2,
+			     3, 3, 3, 2, 3, 3, 2) {
+		/* IP3_31 [1] */
+		FN_DU0_DR6,	FN_LCDOUT6,
+		/* IP3_30 [1] */
+		FN_DU0_DR5,	FN_LCDOUT5,
+		/* IP3_29 [1] */
+		FN_DU0_DR4,	FN_LCDOUT4,
+		/* IP3_28 [1] */
+		FN_DU0_DR3,	FN_LCDOUT3,
+		/* IP3_27 [1] */
+		FN_DU0_DR2,	FN_LCDOUT2,
+		/* IP3_26_24 [3] */
+		FN_SSI_WS4,		FN_DU0_DR1,	FN_LCDOUT1,	FN_AUDATA3,
+		FN_ARM_TRACEDATA_3,	FN_SCL3_C,	FN_ADICHS2,	FN_TS_SPSYNC0_B,
+		/* IP3_23_21 [3] */
+		FN_SSI_SCK4,		FN_DU0_DR0,	FN_LCDOUT0,	FN_AUDATA2,
+		FN_ARM_TRACEDATA_2,	FN_SDA3_C,	FN_ADICHS1,	FN_TS_SDEN0_B,
+		/* IP3_20_19 [2] */
+		FN_SD1_DAT3_B,	FN_HRTS0_A,	FN_RTS0,	0,
+		/* IP3_18_16 [3] */
+		FN_SD1_DAT2_B,	FN_HCTS0_A,	FN_CTS0,	0,
+		0,		0,		0,		0,
+		/* IP3_15_13 [3] */
+		FN_SD1_DAT1_B,	FN_HSCK0,	FN_SCK0,	FN_SCL3_B,
+		0,		0,		0,		0,
+		/* IP3_12_10 [3] */
+		FN_SD1_DAT0_B,	FN_HRX0_A,	FN_RX0_A,	0,
+		0,		0,		0,		0,
+		/* IP3_9_8 [2] */
+		FN_SD1_CLK_B,	FN_HTX0_A,	FN_TX0_A,	0,
+		/* IP3_7_5 [3] */
+		FN_SD1_CMD_B,	FN_SCIF_CLK,	FN_AUDIO_CLKOUT_B,	FN_CAN_CLK_B,
+		FN_SDA3_B,	0,		0,			0,
+		/* IP3_4_2 [3] */
+		FN_MLB_DAT,	FN_TX5_B,	FN_SCL3_A,	FN_IRQ3_A,
+		FN_SDSELF_B,	0,		0,		0,
+		/* IP3_1_0 [2] */
+		FN_MLB_SIG,	FN_RX5_B,	FN_SDA3_A,	FN_IRQ2_A,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
+			     1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1, 3, 3, 1) {
+		/* IP4_31 [1] */
+		0,	0,
+		/* IP4_30_29 [2] */
+		FN_VI0_R4_B,	FN_DU0_DB4,	FN_LCDOUT20,	0,
+		/* IP4_28_27 [2] */
+		FN_VI0_R3_B,	FN_DU0_DB3,	FN_LCDOUT19,	0,
+		/* IP4_26_25 [2] */
+		FN_VI0_R2_B,	FN_DU0_DB2,	FN_LCDOUT18,	0,
+		/* IP4_24_21 [4] */
+		FN_AUDIO_CLKC,	FN_VI0_R1_B,		FN_DU0_DB1,	FN_LCDOUT17,
+		FN_AUDATA7,	FN_ARM_TRACEDATA_7,	FN_GPSIN_A,	0,
+		FN_ADICS_SAMP,	FN_TS_SCK0_B,		0,		0,
+		0,		0,			0,		0,
+		/* IP4_20_17 [4] */
+		FN_SSI_SCK2_B,	FN_VI0_R0_B,		FN_DU0_DB0,	FN_LCDOUT16,
+		FN_AUDATA6,	FN_ARM_TRACEDATA_6,	FN_GPSCLK_A,	FN_PWM0_A,
+		FN_ADICLK,	FN_TS_SDAT0_B,		0,		0,
+		0,		0,			0,		0,
+		/* IP4_16_15 [2] */
+		FN_DU0_DG7,	FN_LCDOUT15,	FN_TX4_A,	0,
+		/* IP4_14_13 [2] */
+		FN_DU0_DG6,	FN_LCDOUT14,	FN_RX4_A,	0,
+		/* IP4_12_11 [2] */
+		FN_DU0_DG5,	FN_LCDOUT13,	FN_TX0_B,	0,
+		/* IP4_10_9 [2] */
+		FN_DU0_DG4,	FN_LCDOUT12,	FN_RX0_B,	0,
+		/* IP4_8 [1] */
+		FN_DU0_DG3,	FN_LCDOUT11,
+		/* IP4_7 [1] */
+		FN_DU0_DG2,	FN_LCDOUT10,
+		/* IP4_6_4 [3] */
+		FN_DU0_DG1,	FN_LCDOUT9,	FN_AUDATA5,	FN_ARM_TRACEDATA_5,
+		FN_RX1_D,	FN_CAN0_RX_A,	FN_ADIDATA,	0,
+		/* IP4_3_1 [3] */
+		FN_DU0_DG0,	FN_LCDOUT8,	FN_AUDATA4,	FN_ARM_TRACEDATA_4,
+		FN_TX1_D,	FN_CAN0_TX_A,	FN_ADICHS0,	0,
+		/* IP4_0 [1] */
+		FN_DU0_DR7,	FN_LCDOUT7,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
+			     1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1, 1, 2, 2, 2) {
+
+		/* IP5_31 [1] */
+		0, 0,
+		/* IP5_30_29 [2] */
+		FN_SSI_SDATA7,	FN_HSPI_TX0_B,	FN_RX2_A,	FN_CAN0_RX_B,
+		/* IP5_28_26 [3] */
+		FN_SSI_SDATA8,	FN_SSI_SCK2_A,	FN_HSPI_CS0_B,	FN_TX2_A,
+		FN_CAN0_TX_B,	0,		0,		0,
+		/* IP5_25_23 [3] */
+		FN_SD1_WP_B,	FN_SSI_WS78,	FN_HSPI_CLK0_B,	FN_RX1_B,
+		FN_CAN_CLK_D,	0,		0,		0,
+		/* IP5_22_21 [2] */
+		FN_SD1_CD_B,	FN_SSI_SCK78,	FN_HSPI_RX0_B,	FN_TX1_B,
+		/* IP5_20_18 [3] */
+		FN_SSI_WS1_A,		FN_DU0_CDE,	FN_QPOLB,	FN_AUDSYNC,
+		FN_ARM_TRACECTL,	FN_FMIN_D,	0,		0,
+		/* IP5_17_15 [3] */
+		FN_SSI_SCK1_A,		FN_DU0_DISP,	FN_QPOLA,	FN_AUDCK,
+		FN_ARM_TRACECLK,	FN_BPFCLK_D,	0,		0,
+		/* IP5_14_13 [2] */
+		FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,	FN_QCPV_QDE,
+		FN_FMCLK_D,				0,
+		/* IP5_12 [1] */
+		FN_DU0_EXVSYNC_DU0_VSYNC,	FN_QSTB_QHE,
+		/* IP5_11_10 [2] */
+		FN_SSI_WS2_B,	FN_DU0_EXHSYNC_DU0_HSYNC,
+		FN_QSTH_QHS,	0,
+		/* IP5_9_8 [2] */
+		FN_DU0_DOTCLKO_UT1,	FN_QSTVB_QVE,
+		FN_AUDIO_CLKOUT_A,	FN_REMOCON_C,
+		/* IP5_7 [1] */
+		FN_DU0_DOTCLKO_UT0,	FN_QCLK,
+		/* IP5_6 [1] */
+		FN_DU0_DOTCLKIN,	FN_QSTVA_QVS,
+		/* IP5_5_4 [2] */
+		FN_VI1_DATA11_B,	FN_DU0_DB7,	FN_LCDOUT23,	0,
+		/* IP5_3_2 [2] */
+		FN_VI1_DATA10_B,	FN_DU0_DB6,	FN_LCDOUT22,	0,
+		/* IP5_1_0 [2] */
+		FN_VI0_R5_B,		FN_DU0_DB5,	FN_LCDOUT21,	0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
+			     2, 2, 2, 2, 2, 1, 2, 2, 1, 2,
+			     1, 2, 1, 1, 1, 1, 2, 3, 2) {
+		/* IP6_31_30 [2] */
+		FN_SD0_DAT2,	0,	FN_SUB_TDI,	0,
+		/* IP6_29_28 [2] */
+		FN_SD0_DAT1,	0,	FN_SUB_TCK,	0,
+		/* IP6_27_26 [2] */
+		FN_SD0_DAT0,	0,	FN_SUB_TMS,	0,
+		/* IP6_25_24 [2] */
+		FN_SD0_CMD,	0,	FN_SUB_TRST,	0,
+		/* IP6_23_22 [2] */
+		FN_SD0_CLK,	0,	FN_SUB_TDO,	0,
+		/* IP6_21 [1] */
+		FN_SSI_SDATA0,		FN_ARM_TRACEDATA_15,
+		/* IP6_20_19 [2] */
+		FN_SSI_SDATA1,		FN_ARM_TRACEDATA_14,
+		FN_SCL1_A,		FN_SCK2_A,
+		/* IP6_18_17 [2] */
+		FN_SSI_SDATA2,		FN_HSPI_CS2_A,
+		FN_ARM_TRACEDATA_13,	FN_SDA1_A,
+		/* IP6_16 [1] */
+		FN_SSI_WS012,		FN_ARM_TRACEDATA_12,
+		/* IP6_15_14 [2] */
+		FN_SSI_SCK012,		FN_ARM_TRACEDATA_11,
+		FN_TX0_D,		0,
+		/* IP6_13 [1] */
+		FN_SSI_SDATA3,		FN_ARM_TRACEDATA_10,
+		/* IP6_12_11 [2] */
+		FN_SSI_SDATA4,		FN_SSI_WS2_A,
+		FN_ARM_TRACEDATA_9,	0,
+		/* IP6_10 [1] */
+		FN_SSI_WS34,		FN_ARM_TRACEDATA_8,
+		/* IP6_9 [1] */
+		FN_SSI_SDATA5,		FN_RX0_D,
+		/* IP6_8 [1] */
+		FN_SSI_WS5,		FN_TX4_C,
+		/* IP6_7 [1] */
+		FN_SSI_SCK5,		FN_RX4_C,
+		/* IP6_6_5 [2] */
+		FN_SSI_SDATA6,		FN_HSPI_TX2_A,
+		FN_FMIN_B,		0,
+		/* IP6_4_2 [3] */
+		FN_SSI_WS6,		FN_HSPI_CLK2_A,
+		FN_BPFCLK_B,		FN_CAN1_RX_B,
+		0,	0,	0,	0,
+		/* IP6_1_0 [2] */
+		FN_SSI_SCK6,		FN_HSPI_RX2_A,
+		FN_FMCLK_B,		FN_CAN1_TX_B,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
+			     3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2) {
+
+		/* IP7_31_29 [3] */
+		FN_VI0_HSYNC,	FN_SD2_CD_B,	FN_VI1_DATA2,	FN_DU1_DR2,
+		0,		FN_HSPI_CS1_A,	FN_RX3_B,	0,
+		/* IP7_28_25 [4] */
+		FN_VI0_FIELD,	FN_SD2_DAT3_B,	FN_VI0_R3_C,	FN_VI1_DATA1,
+		FN_DU1_DG7,	0,		FN_HSPI_CLK1_A,	FN_TX4_B,
+		0,	0,	0,	0,
+		0,	0,	0,	0,
+		/* IP7_24_22 [3] */
+		FN_VI0_CLKENB,	FN_SD2_DAT2_B,	FN_VI1_DATA0,	FN_DU1_DG6,
+		0,		FN_HSPI_RX1_A,	FN_RX4_B,	0,
+		/* IP7_21 [1] */
+		FN_VI0_CLK,	FN_CAN_CLK_A,
+		/* IP7_20_18 [3] */
+		FN_TCLK0,	FN_HSCK1_A,	FN_FMIN_A,	0,
+		FN_IRQ2_C,	FN_CTS1_C,	FN_SPEEDIN,	0,
+		/* IP7_17_15 [3] */
+		FN_VI1_VSYNC,	FN_HSPI_TX0,	FN_HCTS1_A,	FN_BPFCLK_A,
+		0,		FN_TX1_C,	0,		0,
+		/* IP7_14_12 [3] */
+		FN_VI1_HSYNC,	FN_HSPI_RX0_A,	FN_HRTS1_A,	FN_FMCLK_A,
+		0,		FN_RX1_C,	0,		0,
+		/* IP7_11_9 [3] */
+		FN_VI1_FIELD,	FN_HSPI_CS0_A,	FN_HRX1_A,	0,
+		FN_SCK1_C,	0,		0,		0,
+		/* IP7_8_6 [3] */
+		FN_VI1_CLKENB,	FN_HSPI_CLK0_A,	FN_HTX1_A,	0,
+		FN_RTS1_C,	0,		0,		0,
+		/* IP7_5_4 [2] */
+		FN_SD0_WP,	0,		FN_RX5_A,	0,
+		/* IP7_3_2 [2] */
+		FN_SD0_CD,	0,		FN_TX5_A,	0,
+		/* IP7_1_0 [2] */
+		FN_SD0_DAT3,	0,		FN_IRQ1_B,	0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
+			     1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3) {
+		/* IP8_31 [1] */
+		0, 0,
+		/* IP8_30 [1] */
+		0, 0,
+		/* IP8_29_27 [3] */
+		FN_VI0_G3,	FN_SD2_CMD_B,	FN_VI1_DATA5,	FN_DU1_DR5,
+		0,		FN_HRX1_B,	0,		0,
+		/* IP8_26_24 [3] */
+		FN_VI0_G2,	FN_SD2_CLK_B,	FN_VI1_DATA4,	FN_DU1_DR4,
+		0,		FN_HTX1_B,	0,		0,
+		/* IP8_23_22 [2] */
+		FN_VI0_DATA7_VI0_G1,	FN_DU1_DB5,
+		FN_RTS1_A,		0,
+		/* IP8_21_19 [3] */
+		FN_VI0_DATA6_VI0_G0,	FN_DU1_DB4,
+		FN_CTS1_A,		FN_PWM5,
+		0,	0,	0,	0,
+		/* IP8_18_16 [3] */
+		FN_VI0_DATA5_VI0_B5,	FN_DU1_DB3,	FN_SCK1_A,	FN_PWM4,
+		0,			FN_HSCK1_B,	0,		0,
+		/* IP8_15_14 [2] */
+		FN_VI0_DATA4_VI0_B4,	FN_DU1_DB2,	FN_RX1_A,	0,
+		/* IP8_13_11 [3] */
+		FN_VI0_DATA3_VI0_B3,	FN_DU1_DG5,	FN_TX1_A,	FN_TX0_C,
+		0,			 0,		0,		0,
+		/* IP8_10_9 [2] */
+		FN_VI0_DATA2_VI0_B2,	FN_DU1_DG4,	FN_RX0_C,	0,
+		/* IP8_8_6 [3] */
+		FN_VI0_DATA1_VI0_B1,	FN_DU1_DG3,	FN_IRQ3_B,	FN_TX3_D,
+		0,			 0,		0,		0,
+		/* IP8_5_3 [3] */
+		FN_VI0_DATA0_VI0_B0,	FN_DU1_DG2,	FN_IRQ2_B,	FN_RX3_D,
+		0,			 0,		0,		0,
+		/* IP8_2_0 [3] */
+		FN_VI0_VSYNC,		FN_SD2_WP_B,	FN_VI1_DATA3,	FN_DU1_DR3,
+		0,			FN_HSPI_TX1_A,	FN_TX3_B,	0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
+			     1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+		/* IP9_31 [1] */
+		0, 0,
+		/* IP9_30 [1] */
+		0, 0,
+		/* IP9_29_27 [3] */
+		FN_VI1_DATA11_A,	FN_DU1_EXHSYNC_DU1_HSYNC,
+		FN_ETH_RXD1,		FN_FMIN_C,
+		0,			FN_RX2_D,
+		FN_SCL2_C,		0,
+		/* IP9_26_24 [3] */
+		FN_VI1_DATA10_A,	FN_DU1_DOTCLKOUT,
+		FN_ETH_RXD0,		FN_BPFCLK_C,
+		0,			FN_TX2_D,
+		FN_SDA2_C,		0,
+		/* IP9_23_21 [3] */
+		FN_VI0_R5_A,	0,		FN_ETH_RX_ER,	FN_FMCLK_C,
+		FN_IERX,	FN_RX2_C,	0,		0,
+		/* IP9_20_18 [3] */
+		FN_VI0_R4_A,	FN_ETH_TX_EN,	0,		0,
+		FN_IETX,	FN_TX2_C,	0,		0,
+		/* IP9_17_15 [3] */
+		FN_VI0_R3_A,	FN_ETH_CRS_DV,	0,		FN_IECLK,
+		FN_SCK2_C,	0,		0,		0,
+		/* IP9_14_12 [3] */
+		FN_VI0_R2_A,	FN_VI1_DATA9,	FN_DU1_DB7,	FN_ETH_TXD1,
+		0,		FN_PWM3,	0,		0,
+		/* IP9_11_9 [3] */
+		FN_VI0_R1_A,	FN_VI1_DATA8,	FN_DU1_DB6,	FN_ETH_TXD0,
+		0,		FN_PWM2,	FN_TCLK1,	0,
+		/* IP9_8_6 [3] */
+		FN_VI0_R0_A,	FN_VI1_CLK,	FN_ETH_REF_CLK,	FN_DU1_DOTCLKIN,
+		0,		0,		0,		0,
+		/* IP9_5_3 [3] */
+		FN_VI0_G5,	FN_SD2_DAT1_B,	FN_VI1_DATA7,	FN_DU1_DR7,
+		0,		FN_HCTS1_B,	0,		0,
+		/* IP9_2_0 [3] */
+		FN_VI0_G4,	FN_SD2_DAT0_B,	FN_VI1_DATA6,	FN_DU1_DR6,
+		0,		FN_HRTS1_B,	0,		0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
+			     1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4, 3, 3, 3) {
+
+		/* IP10_31 [1] */
+		0, 0,
+		/* IP10_30 [1] */
+		0, 0,
+		/* IP10_29 [1] */
+		0, 0,
+		/* IP10_28 [1] */
+		0, 0,
+		/* IP10_27 [1] */
+		0, 0,
+		/* IP10_26 [1] */
+		0, 0,
+		/* IP10_25 [1] */
+		0, 0,
+		/* IP10_24_22 [3] */
+		FN_SD2_WP_A,	FN_VI1_DATA15,	FN_EX_WAIT2_B,	FN_DACK0_B,
+		FN_HSPI_TX2_B,	FN_CAN_CLK_C,	0,		0,
+		/* IP10_21_19 [3] */
+		FN_SD2_CD_A,	FN_VI1_DATA14,	FN_EX_WAIT1_B,	FN_DREQ0_B,
+		FN_HSPI_RX2_B,	FN_REMOCON_A,	0,		0,
+		/* IP10_18_16 [3] */
+		FN_SD2_DAT3_A,	FN_VI1_DATA13,	FN_DACK2_B,	FN_ATAG1,
+		FN_HSPI_CS2_B,	FN_GPSIN_B,	0,		0,
+		/* IP10_15_13 [3] */
+		FN_SD2_DAT2_A,	FN_VI1_DATA12,	FN_DREQ2_B,	FN_ATADIR1,
+		FN_HSPI_CLK2_B,	FN_GPSCLK_B,	0,		0,
+		/* IP10_12_9 [4] */
+		FN_SD2_DAT1_A,	FN_DU1_CDE,	FN_ATACS11,	FN_DACK1_B,
+		FN_ETH_MAGIC,	FN_CAN1_TX_A,	0,		FN_PWM6,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IP10_8_6 [3] */
+		FN_SD2_DAT0_A,	FN_DU1_DISP,	FN_ATACS01,	FN_DREQ1_B,
+		FN_ETH_LINK,	FN_CAN1_RX_A,	0,		0,
+		/* IP10_5_3 [3] */
+		FN_SD2_CMD_A,	FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
+		FN_ATAWR1,	FN_ETH_MDIO,
+		FN_SCL1_B,	0,
+		0,		0,
+		/* IP10_2_0 [3] */
+		FN_SD2_CLK_A,	FN_DU1_EXVSYNC_DU1_VSYNC,
+		FN_ATARD1,	FN_ETH_MDC,
+		FN_SDA1_B,	0,
+		0,		0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
+			     1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
+			     1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
+
+		/* SEL 31  [1] */
+		0, 0,
+		/* SEL_30 (SCIF5) [1] */
+		FN_SEL_SCIF5_A,		FN_SEL_SCIF5_B,
+		/* SEL_29_28 (SCIF4) [2] */
+		FN_SEL_SCIF4_A,		FN_SEL_SCIF4_B,
+		FN_SEL_SCIF4_C,		0,
+		/* SEL_27_26 (SCIF3) [2] */
+		FN_SEL_SCIF3_A,		FN_SEL_SCIF3_B,
+		FN_SEL_SCIF3_C,		FN_SEL_SCIF3_D,
+		/* SEL_25_23 (SCIF2) [3] */
+		FN_SEL_SCIF2_A,		FN_SEL_SCIF2_B,
+		FN_SEL_SCIF2_C,		FN_SEL_SCIF2_D,
+		FN_SEL_SCIF2_E,		0,
+		0,			0,
+		/* SEL_22_21 (SCIF1) [2] */
+		FN_SEL_SCIF1_A,		FN_SEL_SCIF1_B,
+		FN_SEL_SCIF1_C,		FN_SEL_SCIF1_D,
+		/* SEL_20_19 (SCIF0) [2] */
+		FN_SEL_SCIF0_A,		FN_SEL_SCIF0_B,
+		FN_SEL_SCIF0_C,		FN_SEL_SCIF0_D,
+		/* SEL_18 [1] */
+		0, 0,
+		/* SEL_17 (SSI2) [1] */
+		FN_SEL_SSI2_A,		FN_SEL_SSI2_B,
+		/* SEL_16 (SSI1) [1] */
+		FN_SEL_SSI1_A,		FN_SEL_SSI1_B,
+		/* SEL_15 (VI1) [1] */
+		FN_SEL_VI1_A,		FN_SEL_VI1_B,
+		/* SEL_14_13 (VI0) [2] */
+		FN_SEL_VI0_A,		FN_SEL_VI0_B,
+		FN_SEL_VI0_C,		FN_SEL_VI0_D,
+		/* SEL_12 [1] */
+		0, 0,
+		/* SEL_11 (SD2) [1] */
+		FN_SEL_SD2_A,		FN_SEL_SD2_B,
+		/* SEL_10 (SD1) [1] */
+		FN_SEL_SD1_A,		FN_SEL_SD1_B,
+		/* SEL_9 (IRQ3) [1] */
+		FN_SEL_IRQ3_A,		FN_SEL_IRQ3_B,
+		/* SEL_8_7 (IRQ2) [2] */
+		FN_SEL_IRQ2_A,		FN_SEL_IRQ2_B,
+		FN_SEL_IRQ2_C,		0,
+		/* SEL_6 (IRQ1) [1] */
+		FN_SEL_IRQ1_A,		FN_SEL_IRQ1_B,
+		/* SEL_5 [1] */
+		0, 0,
+		/* SEL_4 (DREQ2) [1] */
+		FN_SEL_DREQ2_A,		FN_SEL_DREQ2_B,
+		/* SEL_3 (DREQ1) [1] */
+		FN_SEL_DREQ1_A,		FN_SEL_DREQ1_B,
+		/* SEL_2 (DREQ0) [1] */
+		FN_SEL_DREQ0_A,		FN_SEL_DREQ0_B,
+		/* SEL_1 (WAIT2) [1] */
+		FN_SEL_WAIT2_A,		FN_SEL_WAIT2_B,
+		/* SEL_0 (WAIT1) [1] */
+		FN_SEL_WAIT1_A,		FN_SEL_WAIT1_B,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
+			     1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1,
+			     1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1) {
+
+		/* SEL_31 [1] */
+		0, 0,
+		/* SEL_30 [1] */
+		0, 0,
+		/* SEL_29 [1] */
+		0, 0,
+		/* SEL_28 [1] */
+		0, 0,
+		/* SEL_27 (CAN1) [1] */
+		FN_SEL_CAN1_A,		FN_SEL_CAN1_B,
+		/* SEL_26 (CAN0) [1] */
+		FN_SEL_CAN0_A,		FN_SEL_CAN0_B,
+		/* SEL_25_24 (CANCLK) [2] */
+		FN_SEL_CANCLK_A,	FN_SEL_CANCLK_B,
+		FN_SEL_CANCLK_C,	FN_SEL_CANCLK_D,
+		/* SEL_23 (HSCIF1) [1] */
+		FN_SEL_HSCIF1_A,	FN_SEL_HSCIF1_B,
+		/* SEL_22 (HSCIF0) [1] */
+		FN_SEL_HSCIF0_A,	FN_SEL_HSCIF0_B,
+		/* SEL_21 [1] */
+		0, 0,
+		/* SEL_20 [1] */
+		0, 0,
+		/* SEL_19 [1] */
+		0, 0,
+		/* SEL_18 [1] */
+		0, 0,
+		/* SEL_17 [1] */
+		0, 0,
+		/* SEL_16 [1] */
+		0, 0,
+		/* SEL_15 [1] */
+		0, 0,
+		/* SEL_14_13 (REMOCON) [2] */
+		FN_SEL_REMOCON_A,	FN_SEL_REMOCON_B,
+		FN_SEL_REMOCON_C,	0,
+		/* SEL_12_11 (FM) [2] */
+		FN_SEL_FM_A,		FN_SEL_FM_B,
+		FN_SEL_FM_C,		FN_SEL_FM_D,
+		/* SEL_10_9 (GPS) [2] */
+		FN_SEL_GPS_A,		FN_SEL_GPS_B,
+		FN_SEL_GPS_C,		0,
+		/* SEL_8 (TSIF0) [1] */
+		FN_SEL_TSIF0_A,		FN_SEL_TSIF0_B,
+		/* SEL_7 (HSPI2) [1] */
+		FN_SEL_HSPI2_A,		FN_SEL_HSPI2_B,
+		/* SEL_6 (HSPI1) [1] */
+		FN_SEL_HSPI1_A,		FN_SEL_HSPI1_B,
+		/* SEL_5 (HSPI0) [1] */
+		FN_SEL_HSPI0_A,		FN_SEL_HSPI0_B,
+		/* SEL_4_3 (I2C3) [2] */
+		FN_SEL_I2C3_A,		FN_SEL_I2C3_B,
+		FN_SEL_I2C3_C,		0,
+		/* SEL_2_1 (I2C2) [2] */
+		FN_SEL_I2C2_A,		FN_SEL_I2C2_B,
+		FN_SEL_I2C2_C,		0,
+		/* SEL_0 (I2C1) [1] */
+		FN_SEL_I2C1_A,		FN_SEL_I2C1_B,
+		}
+	},
+	{ },
+};
+
+const struct sh_pfc_soc_info r8a7778_pinmux_info = {
+	.name = "r8a7778_pfc",
+
+	.unlock_reg = 0xfffc0000, /* PMMR */
+
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.pins = pinmux_pins,
+	.nr_pins = ARRAY_SIZE(pinmux_pins),
+
+	.groups = pinmux_groups,
+	.nr_groups = ARRAY_SIZE(pinmux_groups),
+
+	.functions = pinmux_functions,
+	.nr_functions = ARRAY_SIZE(pinmux_functions),
+
+	.cfg_regs = pinmux_config_regs,
+
+	.gpio_data = pinmux_data,
+	.gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
-- 
1.8.2.1

[PATCH 017/130] sh-pfc: r8a7740: Add SCIFA1 data group

[Simon Horman]

From: Bastian Hecht <hechtb@gmail.com>

Add SCIFA1 as preparation to switch to pinctrl in board files.

Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index d95040c..4753f54 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -1999,6 +1999,14 @@ static const unsigned int mmc0_ctrl_1_pins[] = {
 static const unsigned int mmc0_ctrl_1_mux[] = {
 	MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
 };
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+	/* RXD, TXD */
+	195, 196,
+};
+static const unsigned int scifa1_data_mux[] = {
+	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
 /* - SDHI0 ------------------------------------------------------------------ */
 static const unsigned int sdhi0_data1_pins[] = {
 	/* D0 */
@@ -2204,6 +2212,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(mmc0_data4_1),
 	SH_PFC_PIN_GROUP(mmc0_data8_1),
 	SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+	SH_PFC_PIN_GROUP(scifa1_data),
 	SH_PFC_PIN_GROUP(sdhi0_data1),
 	SH_PFC_PIN_GROUP(sdhi0_data4),
 	SH_PFC_PIN_GROUP(sdhi0_ctrl),
@@ -2316,6 +2325,10 @@ static const char * const mmc0_groups[] = {
 	"mmc0_ctrl_1",
 };
 
+static const char * const scifa1_groups[] = {
+	"scifa1_data",
+};
+
 static const char * const sdhi0_groups[] = {
 	"sdhi0_data1",
 	"sdhi0_data4",
@@ -2346,6 +2359,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(lcd0),
 	SH_PFC_FUNCTION(lcd1),
 	SH_PFC_FUNCTION(mmc0),
+	SH_PFC_FUNCTION(scifa1),
 	SH_PFC_FUNCTION(sdhi0),
 	SH_PFC_FUNCTION(sdhi1),
 	SH_PFC_FUNCTION(sdhi2),
-- 
1.8.2.1

[PATCH 018/130] sh-pfc: r8a7779: Replace hardcoded pin numbers with RCAR_GP_PIN macro

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Use the RCAR_GP_PIN macro to convert from the documentation pin number
space to the linear pinctrl space.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 300 +++++++++++++++++++----------------
 1 file changed, 167 insertions(+), 133 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 8cd90e7..e1491a5 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -19,6 +19,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/platform_data/gpio-rcar.h>
 
 #include "sh_pfc.h"
 
@@ -1472,9 +1473,12 @@ static struct sh_pfc_pin pinmux_pins[] = {
 /* - DU0 -------------------------------------------------------------------- */
 static const unsigned int du0_rgb666_pins[] = {
 	/* R[7:2], G[7:2], B[7:2] */
-	188, 187, 186, 185, 184, 183,
-	194, 193, 192, 191, 190, 189,
-	200, 199, 198, 197, 196, 195,
+	RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
+	RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
+	RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),
+	RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29),
+	RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),  RCAR_GP_PIN(6, 6),
+	RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),  RCAR_GP_PIN(6, 3),
 };
 static const unsigned int du0_rgb666_mux[] = {
 	DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
@@ -1486,9 +1490,14 @@ static const unsigned int du0_rgb666_mux[] = {
 };
 static const unsigned int du0_rgb888_pins[] = {
 	/* R[7:0], G[7:0], B[7:0] */
-	188, 187, 186, 185, 184, 183, 24, 23,
-	194, 193, 192, 191, 190, 189, 26, 25,
-	200, 199, 198, 197, 196, 195, 28, 27,
+	RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
+	RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
+	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), RCAR_GP_PIN(6, 2),
+	RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),  RCAR_GP_PIN(5, 31),
+	RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), RCAR_GP_PIN(0, 26),
+	RCAR_GP_PIN(0, 25), RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),
+	RCAR_GP_PIN(6, 6),  RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),
+	RCAR_GP_PIN(6, 3),  RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 27),
 };
 static const unsigned int du0_rgb888_mux[] = {
 	DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
@@ -1500,28 +1509,28 @@ static const unsigned int du0_rgb888_mux[] = {
 };
 static const unsigned int du0_clk_in_pins[] = {
 	/* CLKIN */
-	29,
+	RCAR_GP_PIN(0, 29),
 };
 static const unsigned int du0_clk_in_mux[] = {
 	DU0_DOTCLKIN_MARK,
 };
 static const unsigned int du0_clk_out_0_pins[] = {
 	/* CLKOUT */
-	180,
+	RCAR_GP_PIN(5, 20),
 };
 static const unsigned int du0_clk_out_0_mux[] = {
 	DU0_DOTCLKOUT0_MARK,
 };
 static const unsigned int du0_clk_out_1_pins[] = {
 	/* CLKOUT */
-	30,
+	RCAR_GP_PIN(0, 30),
 };
 static const unsigned int du0_clk_out_1_mux[] = {
 	DU0_DOTCLKOUT1_MARK,
 };
 static const unsigned int du0_sync_0_pins[] = {
 	/* VSYNC, HSYNC, DISP */
-	182, 181, 31,
+	RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(0, 31),
 };
 static const unsigned int du0_sync_0_mux[] = {
 	DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
@@ -1529,7 +1538,7 @@ static const unsigned int du0_sync_0_mux[] = {
 };
 static const unsigned int du0_sync_1_pins[] = {
 	/* VSYNC, HSYNC, DISP */
-	182, 181, 32,
+	RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(1, 0),
 };
 static const unsigned int du0_sync_1_mux[] = {
 	DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
@@ -1537,14 +1546,14 @@ static const unsigned int du0_sync_1_mux[] = {
 };
 static const unsigned int du0_oddf_pins[] = {
 	/* ODDF */
-	31,
+	RCAR_GP_PIN(0, 31),
 };
 static const unsigned int du0_oddf_mux[] = {
 	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
 };
 static const unsigned int du0_cde_pins[] = {
 	/* CDE */
-	33,
+	RCAR_GP_PIN(1, 1),
 };
 static const unsigned int du0_cde_mux[] = {
 	DU0_CDE_MARK
@@ -1552,9 +1561,12 @@ static const unsigned int du0_cde_mux[] = {
 /* - DU1 -------------------------------------------------------------------- */
 static const unsigned int du1_rgb666_pins[] = {
 	/* R[7:2], G[7:2], B[7:2] */
-	41, 40, 39, 38, 37, 36,
-	49, 48, 47, 46, 45, 44,
-	57, 56, 55, 54, 53, 52,
+	RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
+	RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
+	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
+	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
+	RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
+	RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 20),
 };
 static const unsigned int du1_rgb666_mux[] = {
 	DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
@@ -1566,9 +1578,14 @@ static const unsigned int du1_rgb666_mux[] = {
 };
 static const unsigned int du1_rgb888_pins[] = {
 	/* R[7:0], G[7:0], B[7:0] */
-	41, 40, 39, 38, 37, 36, 35, 34,
-	49, 48, 47, 46, 45, 44, 43, 32,
-	57, 56, 55, 54, 53, 52, 51, 50,
+	RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
+	RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
+	RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 17),
+	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
+	RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11),
+	RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24),
+	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
+	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
 };
 static const unsigned int du1_rgb888_mux[] = {
 	DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
@@ -1580,21 +1597,21 @@ static const unsigned int du1_rgb888_mux[] = {
 };
 static const unsigned int du1_clk_in_pins[] = {
 	/* CLKIN */
-	58,
+	RCAR_GP_PIN(1, 26),
 };
 static const unsigned int du1_clk_in_mux[] = {
 	DU1_DOTCLKIN_MARK,
 };
 static const unsigned int du1_clk_out_pins[] = {
 	/* CLKOUT */
-	59,
+	RCAR_GP_PIN(1, 27),
 };
 static const unsigned int du1_clk_out_mux[] = {
 	DU1_DOTCLKOUT_MARK,
 };
 static const unsigned int du1_sync_0_pins[] = {
 	/* VSYNC, HSYNC, DISP */
-	61, 60, 62,
+	RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 30),
 };
 static const unsigned int du1_sync_0_mux[] = {
 	DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
@@ -1602,7 +1619,7 @@ static const unsigned int du1_sync_0_mux[] = {
 };
 static const unsigned int du1_sync_1_pins[] = {
 	/* VSYNC, HSYNC, DISP */
-	61, 60, 63,
+	RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 31),
 };
 static const unsigned int du1_sync_1_mux[] = {
 	DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
@@ -1610,14 +1627,14 @@ static const unsigned int du1_sync_1_mux[] = {
 };
 static const unsigned int du1_oddf_pins[] = {
 	/* ODDF */
-	62,
+	RCAR_GP_PIN(1, 30),
 };
 static const unsigned int du1_oddf_mux[] = {
 	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
 };
 static const unsigned int du1_cde_pins[] = {
 	/* CDE */
-	64,
+	RCAR_GP_PIN(2, 0),
 };
 static const unsigned int du1_cde_mux[] = {
 	DU1_CDE_MARK
@@ -1625,7 +1642,8 @@ static const unsigned int du1_cde_mux[] = {
 /* - HSPI0 ------------------------------------------------------------------ */
 static const unsigned int hspi0_pins[] = {
 	/* CLK, CS, RX, TX */
-	150, 151, 153, 152,
+	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 25),
+	RCAR_GP_PIN(4, 24),
 };
 static const unsigned int hspi0_mux[] = {
 	HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK,
@@ -1633,28 +1651,32 @@ static const unsigned int hspi0_mux[] = {
 /* - HSPI1 ------------------------------------------------------------------ */
 static const unsigned int hspi1_pins[] = {
 	/* CLK, CS, RX, TX */
-	63, 58, 64, 62,
+	RCAR_GP_PIN(1, 31), RCAR_GP_PIN(1, 26), RCAR_GP_PIN(2, 0),
+	RCAR_GP_PIN(1, 30),
 };
 static const unsigned int hspi1_mux[] = {
 	HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK,
 };
 static const unsigned int hspi1_b_pins[] = {
 	/* CLK, CS, RX, TX */
-	90, 91, 93, 92,
+	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 29),
+	RCAR_GP_PIN(2, 28),
 };
 static const unsigned int hspi1_b_mux[] = {
 	HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK,
 };
 static const unsigned int hspi1_c_pins[] = {
 	/* CLK, CS, RX, TX */
-	141, 142, 144, 143,
+	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 16),
+	RCAR_GP_PIN(4, 15),
 };
 static const unsigned int hspi1_c_mux[] = {
 	HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK,
 };
 static const unsigned int hspi1_d_pins[] = {
 	/* CLK, CS, RX, TX */
-	101, 102, 104, 103,
+	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 8),
+	RCAR_GP_PIN(3, 7),
 };
 static const unsigned int hspi1_d_mux[] = {
 	HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK,
@@ -1662,14 +1684,16 @@ static const unsigned int hspi1_d_mux[] = {
 /* - HSPI2 ------------------------------------------------------------------ */
 static const unsigned int hspi2_pins[] = {
 	/* CLK, CS, RX, TX */
-	9, 10, 11, 14,
+	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+	RCAR_GP_PIN(0, 14),
 };
 static const unsigned int hspi2_mux[] = {
 	HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK,
 };
 static const unsigned int hspi2_b_pins[] = {
 	/* CLK, CS, RX, TX */
-	7, 13, 8, 6,
+	RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 8),
+	RCAR_GP_PIN(0, 6),
 };
 static const unsigned int hspi2_b_mux[] = {
 	HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
@@ -1677,56 +1701,56 @@ static const unsigned int hspi2_b_mux[] = {
 /* - INTC ------------------------------------------------------------------- */
 static const unsigned int intc_irq0_pins[] = {
 	/* IRQ */
-	78,
+	RCAR_GP_PIN(2, 14),
 };
 static const unsigned int intc_irq0_mux[] = {
 	IRQ0_MARK,
 };
 static const unsigned int intc_irq0_b_pins[] = {
 	/* IRQ */
-	141,
+	RCAR_GP_PIN(4, 13),
 };
 static const unsigned int intc_irq0_b_mux[] = {
 	IRQ0_B_MARK,
 };
 static const unsigned int intc_irq1_pins[] = {
 	/* IRQ */
-	79,
+	RCAR_GP_PIN(2, 15),
 };
 static const unsigned int intc_irq1_mux[] = {
 	IRQ1_MARK,
 };
 static const unsigned int intc_irq1_b_pins[] = {
 	/* IRQ */
-	142,
+	RCAR_GP_PIN(4, 14),
 };
 static const unsigned int intc_irq1_b_mux[] = {
 	IRQ1_B_MARK,
 };
 static const unsigned int intc_irq2_pins[] = {
 	/* IRQ */
-	88,
+	RCAR_GP_PIN(2, 24),
 };
 static const unsigned int intc_irq2_mux[] = {
 	IRQ2_MARK,
 };
 static const unsigned int intc_irq2_b_pins[] = {
 	/* IRQ */
-	143,
+	RCAR_GP_PIN(4, 15),
 };
 static const unsigned int intc_irq2_b_mux[] = {
 	IRQ2_B_MARK,
 };
 static const unsigned int intc_irq3_pins[] = {
 	/* IRQ */
-	89,
+	RCAR_GP_PIN(2, 25),
 };
 static const unsigned int intc_irq3_mux[] = {
 	IRQ3_MARK,
 };
 static const unsigned int intc_irq3_b_pins[] = {
 	/* IRQ */
-	144,
+	RCAR_GP_PIN(4, 16),
 };
 static const unsigned int intc_irq3_b_mux[] = {
 	IRQ3_B_MARK,
@@ -1734,56 +1758,56 @@ static const unsigned int intc_irq3_b_mux[] = {
 /* - LSBC ------------------------------------------------------------------- */
 static const unsigned int lbsc_cs0_pins[] = {
 	/* CS */
-	13,
+	RCAR_GP_PIN(0, 13),
 };
 static const unsigned int lbsc_cs0_mux[] = {
 	CS0_MARK,
 };
 static const unsigned int lbsc_cs1_pins[] = {
 	/* CS */
-	14,
+	RCAR_GP_PIN(0, 14),
 };
 static const unsigned int lbsc_cs1_mux[] = {
 	CS1_A26_MARK,
 };
 static const unsigned int lbsc_ex_cs0_pins[] = {
 	/* CS */
-	15,
+	RCAR_GP_PIN(0, 15),
 };
 static const unsigned int lbsc_ex_cs0_mux[] = {
 	EX_CS0_MARK,
 };
 static const unsigned int lbsc_ex_cs1_pins[] = {
 	/* CS */
-	16,
+	RCAR_GP_PIN(0, 16),
 };
 static const unsigned int lbsc_ex_cs1_mux[] = {
 	EX_CS1_MARK,
 };
 static const unsigned int lbsc_ex_cs2_pins[] = {
 	/* CS */
-	17,
+	RCAR_GP_PIN(0, 17),
 };
 static const unsigned int lbsc_ex_cs2_mux[] = {
 	EX_CS2_MARK,
 };
 static const unsigned int lbsc_ex_cs3_pins[] = {
 	/* CS */
-	18,
+	RCAR_GP_PIN(0, 18),
 };
 static const unsigned int lbsc_ex_cs3_mux[] = {
 	EX_CS3_MARK,
 };
 static const unsigned int lbsc_ex_cs4_pins[] = {
 	/* CS */
-	19,
+	RCAR_GP_PIN(0, 19),
 };
 static const unsigned int lbsc_ex_cs4_mux[] = {
 	EX_CS4_MARK,
 };
 static const unsigned int lbsc_ex_cs5_pins[] = {
 	/* CS */
-	20,
+	RCAR_GP_PIN(0, 20),
 };
 static const unsigned int lbsc_ex_cs5_mux[] = {
 	EX_CS5_MARK,
@@ -1791,21 +1815,24 @@ static const unsigned int lbsc_ex_cs5_mux[] = {
 /* - MMCIF ------------------------------------------------------------------ */
 static const unsigned int mmc0_data1_pins[] = {
 	/* D[0] */
-	19,
+	RCAR_GP_PIN(0, 19),
 };
 static const unsigned int mmc0_data1_mux[] = {
 	MMC0_D0_MARK,
 };
 static const unsigned int mmc0_data4_pins[] = {
 	/* D[0:3] */
-	19, 20, 21, 2,
+	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
+	RCAR_GP_PIN(0, 2),
 };
 static const unsigned int mmc0_data4_mux[] = {
 	MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
 };
 static const unsigned int mmc0_data8_pins[] = {
 	/* D[0:7] */
-	19, 20, 21, 2, 10, 11, 15, 16,
+	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
+	RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
 };
 static const unsigned int mmc0_data8_mux[] = {
 	MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
@@ -1813,28 +1840,31 @@ static const unsigned int mmc0_data8_mux[] = {
 };
 static const unsigned int mmc0_ctrl_pins[] = {
 	/* CMD, CLK */
-	18, 17,
+	RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
 };
 static const unsigned int mmc0_ctrl_mux[] = {
 	MMC0_CMD_MARK, MMC0_CLK_MARK,
 };
 static const unsigned int mmc1_data1_pins[] = {
 	/* D[0] */
-	72,
+	RCAR_GP_PIN(2, 8),
 };
 static const unsigned int mmc1_data1_mux[] = {
 	MMC1_D0_MARK,
 };
 static const unsigned int mmc1_data4_pins[] = {
 	/* D[0:3] */
-	72, 73, 74, 75,
+	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+	RCAR_GP_PIN(2, 11),
 };
 static const unsigned int mmc1_data4_mux[] = {
 	MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
 };
 static const unsigned int mmc1_data8_pins[] = {
 	/* D[0:7] */
-	72, 73, 74, 75, 76, 77, 80, 81,
+	RCAR_GP_PIN(2, 8),  RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10),
+	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
 };
 static const unsigned int mmc1_data8_mux[] = {
 	MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
@@ -1842,7 +1872,7 @@ static const unsigned int mmc1_data8_mux[] = {
 };
 static const unsigned int mmc1_ctrl_pins[] = {
 	/* CMD, CLK */
-	68, 65,
+	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 1),
 };
 static const unsigned int mmc1_ctrl_mux[] = {
 	MMC1_CMD_MARK, MMC1_CLK_MARK,
@@ -1850,84 +1880,84 @@ static const unsigned int mmc1_ctrl_mux[] = {
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
 	/* RXD, TXD */
-	153, 152,
+	RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
 };
 static const unsigned int scif0_data_mux[] = {
 	RX0_MARK, TX0_MARK,
 };
 static const unsigned int scif0_clk_pins[] = {
 	/* SCK */
-	156,
+	RCAR_GP_PIN(4, 28),
 };
 static const unsigned int scif0_clk_mux[] = {
 	SCK0_MARK,
 };
 static const unsigned int scif0_ctrl_pins[] = {
 	/* RTS, CTS */
-	151, 150,
+	RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22),
 };
 static const unsigned int scif0_ctrl_mux[] = {
 	RTS0_TANS_MARK, CTS0_MARK,
 };
 static const unsigned int scif0_data_b_pins[] = {
 	/* RXD, TXD */
-	20, 19,
+	RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
 };
 static const unsigned int scif0_data_b_mux[] = {
 	RX0_B_MARK, TX0_B_MARK,
 };
 static const unsigned int scif0_clk_b_pins[] = {
 	/* SCK */
-	33,
+	RCAR_GP_PIN(1, 1),
 };
 static const unsigned int scif0_clk_b_mux[] = {
 	SCK0_B_MARK,
 };
 static const unsigned int scif0_ctrl_b_pins[] = {
 	/* RTS, CTS */
-	18, 11,
+	RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
 };
 static const unsigned int scif0_ctrl_b_mux[] = {
 	RTS0_B_TANS_B_MARK, CTS0_B_MARK,
 };
 static const unsigned int scif0_data_c_pins[] = {
 	/* RXD, TXD */
-	146, 147,
+	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
 };
 static const unsigned int scif0_data_c_mux[] = {
 	RX0_C_MARK, TX0_C_MARK,
 };
 static const unsigned int scif0_clk_c_pins[] = {
 	/* SCK */
-	145,
+	RCAR_GP_PIN(4, 17),
 };
 static const unsigned int scif0_clk_c_mux[] = {
 	SCK0_C_MARK,
 };
 static const unsigned int scif0_ctrl_c_pins[] = {
 	/* RTS, CTS */
-	149, 148,
+	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
 };
 static const unsigned int scif0_ctrl_c_mux[] = {
 	RTS0_C_TANS_C_MARK, CTS0_C_MARK,
 };
 static const unsigned int scif0_data_d_pins[] = {
 	/* RXD, TXD */
-	43, 42,
+	RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
 };
 static const unsigned int scif0_data_d_mux[] = {
 	RX0_D_MARK, TX0_D_MARK,
 };
 static const unsigned int scif0_clk_d_pins[] = {
 	/* SCK */
-	50,
+	RCAR_GP_PIN(1, 18),
 };
 static const unsigned int scif0_clk_d_mux[] = {
 	SCK0_D_MARK,
 };
 static const unsigned int scif0_ctrl_d_pins[] = {
 	/* RTS, CTS */
-	51, 35,
+	RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 3),
 };
 static const unsigned int scif0_ctrl_d_mux[] = {
 	RTS0_D_TANS_D_MARK, CTS0_D_MARK,
@@ -1935,63 +1965,63 @@ static const unsigned int scif0_ctrl_d_mux[] = {
 /* - SCIF1 ------------------------------------------------------------------ */
 static const unsigned int scif1_data_pins[] = {
 	/* RXD, TXD */
-	149, 148,
+	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
 };
 static const unsigned int scif1_data_mux[] = {
 	RX1_MARK, TX1_MARK,
 };
 static const unsigned int scif1_clk_pins[] = {
 	/* SCK */
-	145,
+	RCAR_GP_PIN(4, 17),
 };
 static const unsigned int scif1_clk_mux[] = {
 	SCK1_MARK,
 };
 static const unsigned int scif1_ctrl_pins[] = {
 	/* RTS, CTS */
-	147, 146,
+	RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
 };
 static const unsigned int scif1_ctrl_mux[] = {
 	RTS1_TANS_MARK, CTS1_MARK,
 };
 static const unsigned int scif1_data_b_pins[] = {
 	/* RXD, TXD */
-	117, 114,
+	RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 18),
 };
 static const unsigned int scif1_data_b_mux[] = {
 	RX1_B_MARK, TX1_B_MARK,
 };
 static const unsigned int scif1_clk_b_pins[] = {
 	/* SCK */
-	113,
+	RCAR_GP_PIN(3, 17),
 };
 static const unsigned int scif1_clk_b_mux[] = {
 	SCK1_B_MARK,
 };
 static const unsigned int scif1_ctrl_b_pins[] = {
 	/* RTS, CTS */
-	115, 116,
+	RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
 };
 static const unsigned int scif1_ctrl_b_mux[] = {
 	RTS1_B_TANS_B_MARK, CTS1_B_MARK,
 };
 static const unsigned int scif1_data_c_pins[] = {
 	/* RXD, TXD */
-	67, 66,
+	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
 };
 static const unsigned int scif1_data_c_mux[] = {
 	RX1_C_MARK, TX1_C_MARK,
 };
 static const unsigned int scif1_clk_c_pins[] = {
 	/* SCK */
-	86,
+	RCAR_GP_PIN(2, 22),
 };
 static const unsigned int scif1_clk_c_mux[] = {
 	SCK1_C_MARK,
 };
 static const unsigned int scif1_ctrl_c_pins[] = {
 	/* RTS, CTS */
-	69, 68,
+	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
 };
 static const unsigned int scif1_ctrl_c_mux[] = {
 	RTS1_C_TANS_C_MARK, CTS1_C_MARK,
@@ -1999,63 +2029,63 @@ static const unsigned int scif1_ctrl_c_mux[] = {
 /* - SCIF2 ------------------------------------------------------------------ */
 static const unsigned int scif2_data_pins[] = {
 	/* RXD, TXD */
-	106, 105,
+	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 9),
 };
 static const unsigned int scif2_data_mux[] = {
 	RX2_MARK, TX2_MARK,
 };
 static const unsigned int scif2_clk_pins[] = {
 	/* SCK */
-	107,
+	RCAR_GP_PIN(3, 11),
 };
 static const unsigned int scif2_clk_mux[] = {
 	SCK2_MARK,
 };
 static const unsigned int scif2_data_b_pins[] = {
 	/* RXD, TXD */
-	120, 119,
+	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 23),
 };
 static const unsigned int scif2_data_b_mux[] = {
 	RX2_B_MARK, TX2_B_MARK,
 };
 static const unsigned int scif2_clk_b_pins[] = {
 	/* SCK */
-	118,
+	RCAR_GP_PIN(3, 22),
 };
 static const unsigned int scif2_clk_b_mux[] = {
 	SCK2_B_MARK,
 };
 static const unsigned int scif2_data_c_pins[] = {
 	/* RXD, TXD */
-	33, 31,
+	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(0, 31),
 };
 static const unsigned int scif2_data_c_mux[] = {
 	RX2_C_MARK, TX2_C_MARK,
 };
 static const unsigned int scif2_clk_c_pins[] = {
 	/* SCK */
-	32,
+	RCAR_GP_PIN(1, 0),
 };
 static const unsigned int scif2_clk_c_mux[] = {
 	SCK2_C_MARK,
 };
 static const unsigned int scif2_data_d_pins[] = {
 	/* RXD, TXD */
-	64, 62,
+	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
 };
 static const unsigned int scif2_data_d_mux[] = {
 	RX2_D_MARK, TX2_D_MARK,
 };
 static const unsigned int scif2_clk_d_pins[] = {
 	/* SCK */
-	63,
+	RCAR_GP_PIN(1, 31),
 };
 static const unsigned int scif2_clk_d_mux[] = {
 	SCK2_D_MARK,
 };
 static const unsigned int scif2_data_e_pins[] = {
 	/* RXD, TXD */
-	20, 19,
+	RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
 };
 static const unsigned int scif2_data_e_mux[] = {
 	RX2_E_MARK, TX2_E_MARK,
@@ -2063,14 +2093,14 @@ static const unsigned int scif2_data_e_mux[] = {
 /* - SCIF3 ------------------------------------------------------------------ */
 static const unsigned int scif3_data_pins[] = {
 	/* RXD, TXD */
-	137, 136,
+	RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8),
 };
 static const unsigned int scif3_data_mux[] = {
 	RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK,
 };
 static const unsigned int scif3_clk_pins[] = {
 	/* SCK */
-	135,
+	RCAR_GP_PIN(4, 7),
 };
 static const unsigned int scif3_clk_mux[] = {
 	SCK3_MARK,
@@ -2078,35 +2108,35 @@ static const unsigned int scif3_clk_mux[] = {
 
 static const unsigned int scif3_data_b_pins[] = {
 	/* RXD, TXD */
-	64, 62,
+	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
 };
 static const unsigned int scif3_data_b_mux[] = {
 	RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK,
 };
 static const unsigned int scif3_data_c_pins[] = {
 	/* RXD, TXD */
-	15, 12,
+	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 12),
 };
 static const unsigned int scif3_data_c_mux[] = {
 	RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK,
 };
 static const unsigned int scif3_data_d_pins[] = {
 	/* RXD, TXD */
-	30, 29,
+	RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 29),
 };
 static const unsigned int scif3_data_d_mux[] = {
 	RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK,
 };
 static const unsigned int scif3_data_e_pins[] = {
 	/* RXD, TXD */
-	35, 34,
+	RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
 };
 static const unsigned int scif3_data_e_mux[] = {
 	RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK,
 };
 static const unsigned int scif3_clk_e_pins[] = {
 	/* SCK */
-	42,
+	RCAR_GP_PIN(1, 10),
 };
 static const unsigned int scif3_clk_e_mux[] = {
 	SCK3_E_MARK,
@@ -2114,42 +2144,42 @@ static const unsigned int scif3_clk_e_mux[] = {
 /* - SCIF4 ------------------------------------------------------------------ */
 static const unsigned int scif4_data_pins[] = {
 	/* RXD, TXD */
-	123, 122,
+	RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 26),
 };
 static const unsigned int scif4_data_mux[] = {
 	RX4_MARK, TX4_MARK,
 };
 static const unsigned int scif4_clk_pins[] = {
 	/* SCK */
-	121,
+	RCAR_GP_PIN(3, 25),
 };
 static const unsigned int scif4_clk_mux[] = {
 	SCK4_MARK,
 };
 static const unsigned int scif4_data_b_pins[] = {
 	/* RXD, TXD */
-	111, 110,
+	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
 };
 static const unsigned int scif4_data_b_mux[] = {
 	RX4_B_MARK, TX4_B_MARK,
 };
 static const unsigned int scif4_clk_b_pins[] = {
 	/* SCK */
-	112,
+	RCAR_GP_PIN(3, 16),
 };
 static const unsigned int scif4_clk_b_mux[] = {
 	SCK4_B_MARK,
 };
 static const unsigned int scif4_data_c_pins[] = {
 	/* RXD, TXD */
-	22, 21,
+	RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
 };
 static const unsigned int scif4_data_c_mux[] = {
 	RX4_C_MARK, TX4_C_MARK,
 };
 static const unsigned int scif4_data_d_pins[] = {
 	/* RXD, TXD */
-	69, 68,
+	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
 };
 static const unsigned int scif4_data_d_mux[] = {
 	RX4_D_MARK, TX4_D_MARK,
@@ -2157,56 +2187,56 @@ static const unsigned int scif4_data_d_mux[] = {
 /* - SCIF5 ------------------------------------------------------------------ */
 static const unsigned int scif5_data_pins[] = {
 	/* RXD, TXD */
-	51, 50,
+	RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
 };
 static const unsigned int scif5_data_mux[] = {
 	RX5_MARK, TX5_MARK,
 };
 static const unsigned int scif5_clk_pins[] = {
 	/* SCK */
-	43,
+	RCAR_GP_PIN(1, 11),
 };
 static const unsigned int scif5_clk_mux[] = {
 	SCK5_MARK,
 };
 static const unsigned int scif5_data_b_pins[] = {
 	/* RXD, TXD */
-	18, 11,
+	RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
 };
 static const unsigned int scif5_data_b_mux[] = {
 	RX5_B_MARK, TX5_B_MARK,
 };
 static const unsigned int scif5_clk_b_pins[] = {
 	/* SCK */
-	19,
+	RCAR_GP_PIN(0, 19),
 };
 static const unsigned int scif5_clk_b_mux[] = {
 	SCK5_B_MARK,
 };
 static const unsigned int scif5_data_c_pins[] = {
 	/* RXD, TXD */
-	24, 23,
+	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23),
 };
 static const unsigned int scif5_data_c_mux[] = {
 	RX5_C_MARK, TX5_C_MARK,
 };
 static const unsigned int scif5_clk_c_pins[] = {
 	/* SCK */
-	28,
+	RCAR_GP_PIN(0, 28),
 };
 static const unsigned int scif5_clk_c_mux[] = {
 	SCK5_C_MARK,
 };
 static const unsigned int scif5_data_d_pins[] = {
 	/* RXD, TXD */
-	8, 6,
+	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6),
 };
 static const unsigned int scif5_data_d_mux[] = {
 	RX5_D_MARK, TX5_D_MARK,
 };
 static const unsigned int scif5_clk_d_pins[] = {
 	/* SCK */
-	7,
+	RCAR_GP_PIN(0, 7),
 };
 static const unsigned int scif5_clk_d_mux[] = {
 	SCK5_D_MARK,
@@ -2214,35 +2244,36 @@ static const unsigned int scif5_clk_d_mux[] = {
 /* - SDHI0 ------------------------------------------------------------------ */
 static const unsigned int sdhi0_data1_pins[] = {
 	/* D0 */
-	117,
+	RCAR_GP_PIN(3, 21),
 };
 static const unsigned int sdhi0_data1_mux[] = {
 	SD0_DAT0_MARK,
 };
 static const unsigned int sdhi0_data4_pins[] = {
 	/* D[0:3] */
-	117, 118, 119, 120,
+	RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
+	RCAR_GP_PIN(3, 24),
 };
 static const unsigned int sdhi0_data4_mux[] = {
 	SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
 };
 static const unsigned int sdhi0_ctrl_pins[] = {
 	/* CMD, CLK */
-	114, 113,
+	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 17),
 };
 static const unsigned int sdhi0_ctrl_mux[] = {
 	SD0_CMD_MARK, SD0_CLK_MARK,
 };
 static const unsigned int sdhi0_cd_pins[] = {
 	/* CD */
-	115,
+	RCAR_GP_PIN(3, 19),
 };
 static const unsigned int sdhi0_cd_mux[] = {
 	SD0_CD_MARK,
 };
 static const unsigned int sdhi0_wp_pins[] = {
 	/* WP */
-	116,
+	RCAR_GP_PIN(3, 20),
 };
 static const unsigned int sdhi0_wp_mux[] = {
 	SD0_WP_MARK,
@@ -2250,35 +2281,36 @@ static const unsigned int sdhi0_wp_mux[] = {
 /* - SDHI1 ------------------------------------------------------------------ */
 static const unsigned int sdhi1_data1_pins[] = {
 	/* D0 */
-	19,
+	RCAR_GP_PIN(0, 19),
 };
 static const unsigned int sdhi1_data1_mux[] = {
 	SD1_DAT0_MARK,
 };
 static const unsigned int sdhi1_data4_pins[] = {
 	/* D[0:3] */
-	19, 20, 21, 2,
+	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
+	RCAR_GP_PIN(0, 2),
 };
 static const unsigned int sdhi1_data4_mux[] = {
 	SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
 };
 static const unsigned int sdhi1_ctrl_pins[] = {
 	/* CMD, CLK */
-	18, 17,
+	RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
 };
 static const unsigned int sdhi1_ctrl_mux[] = {
 	SD1_CMD_MARK, SD1_CLK_MARK,
 };
 static const unsigned int sdhi1_cd_pins[] = {
 	/* CD */
-	10,
+	RCAR_GP_PIN(0, 10),
 };
 static const unsigned int sdhi1_cd_mux[] = {
 	SD1_CD_MARK,
 };
 static const unsigned int sdhi1_wp_pins[] = {
 	/* WP */
-	11,
+	RCAR_GP_PIN(0, 11),
 };
 static const unsigned int sdhi1_wp_mux[] = {
 	SD1_WP_MARK,
@@ -2286,35 +2318,36 @@ static const unsigned int sdhi1_wp_mux[] = {
 /* - SDHI2 ------------------------------------------------------------------ */
 static const unsigned int sdhi2_data1_pins[] = {
 	/* D0 */
-	97,
+	RCAR_GP_PIN(3, 1),
 };
 static const unsigned int sdhi2_data1_mux[] = {
 	SD2_DAT0_MARK,
 };
 static const unsigned int sdhi2_data4_pins[] = {
 	/* D[0:3] */
-	97, 98, 99, 100,
+	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+	RCAR_GP_PIN(3, 4),
 };
 static const unsigned int sdhi2_data4_mux[] = {
 	SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
 };
 static const unsigned int sdhi2_ctrl_pins[] = {
 	/* CMD, CLK */
-	102, 101,
+	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
 };
 static const unsigned int sdhi2_ctrl_mux[] = {
 	SD2_CMD_MARK, SD2_CLK_MARK,
 };
 static const unsigned int sdhi2_cd_pins[] = {
 	/* CD */
-	103,
+	RCAR_GP_PIN(3, 7),
 };
 static const unsigned int sdhi2_cd_mux[] = {
 	SD2_CD_MARK,
 };
 static const unsigned int sdhi2_wp_pins[] = {
 	/* WP */
-	104,
+	RCAR_GP_PIN(3, 8),
 };
 static const unsigned int sdhi2_wp_mux[] = {
 	SD2_WP_MARK,
@@ -2322,35 +2355,36 @@ static const unsigned int sdhi2_wp_mux[] = {
 /* - SDHI3 ------------------------------------------------------------------ */
 static const unsigned int sdhi3_data1_pins[] = {
 	/* D0 */
-	50,
+	RCAR_GP_PIN(1, 18),
 };
 static const unsigned int sdhi3_data1_mux[] = {
 	SD3_DAT0_MARK,
 };
 static const unsigned int sdhi3_data4_pins[] = {
 	/* D[0:3] */
-	50, 51, 52, 53,
+	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20),
+	RCAR_GP_PIN(1, 21),
 };
 static const unsigned int sdhi3_data4_mux[] = {
 	SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
 };
 static const unsigned int sdhi3_ctrl_pins[] = {
 	/* CMD, CLK */
-	35, 34,
+	RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
 };
 static const unsigned int sdhi3_ctrl_mux[] = {
 	SD3_CMD_MARK, SD3_CLK_MARK,
 };
 static const unsigned int sdhi3_cd_pins[] = {
 	/* CD */
-	62,
+	RCAR_GP_PIN(1, 30),
 };
 static const unsigned int sdhi3_cd_mux[] = {
 	SD3_CD_MARK,
 };
 static const unsigned int sdhi3_wp_pins[] = {
 	/* WP */
-	64,
+	RCAR_GP_PIN(2, 0),
 };
 static const unsigned int sdhi3_wp_mux[] = {
 	SD3_WP_MARK,
@@ -2358,14 +2392,14 @@ static const unsigned int sdhi3_wp_mux[] = {
 /* - USB0 ------------------------------------------------------------------- */
 static const unsigned int usb0_pins[] = {
 	/* PENC */
-	154,
+	RCAR_GP_PIN(4, 26),
 };
 static const unsigned int usb0_mux[] = {
 	USB_PENC0_MARK,
 };
 static const unsigned int usb0_ovc_pins[] = {
 	/* USB_OVC */
-	150
+	RCAR_GP_PIN(4, 22),
 };
 static const unsigned int usb0_ovc_mux[] = {
 	USB_OVC0_MARK,
@@ -2373,14 +2407,14 @@ static const unsigned int usb0_ovc_mux[] = {
 /* - USB1 ------------------------------------------------------------------- */
 static const unsigned int usb1_pins[] = {
 	/* PENC */
-	155,
+	RCAR_GP_PIN(4, 27),
 };
 static const unsigned int usb1_mux[] = {
 	USB_PENC1_MARK,
 };
 static const unsigned int usb1_ovc_pins[] = {
 	/* USB_OVC */
-	152,
+	RCAR_GP_PIN(4, 24),
 };
 static const unsigned int usb1_ovc_mux[] = {
 	USB_OVC1_MARK,
@@ -2388,14 +2422,14 @@ static const unsigned int usb1_ovc_mux[] = {
 /* - USB2 ------------------------------------------------------------------- */
 static const unsigned int usb2_pins[] = {
 	/* PENC */
-	156,
+	RCAR_GP_PIN(4, 28),
 };
 static const unsigned int usb2_mux[] = {
 	USB_PENC2_MARK,
 };
 static const unsigned int usb2_ovc_pins[] = {
 	/* USB_OVC */
-	125,
+	RCAR_GP_PIN(3, 29),
 };
 static const unsigned int usb2_ovc_mux[] = {
 	USB_OVC2_MARK,
-- 
1.8.2.1

[PATCH 019/130] sh-pfc: r8a7779: use RCAR_GP_PIN() on _GP_GPIO() macro

[Simon Horman]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index e1491a5..1590d6c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -80,7 +80,7 @@
 #define _GP_PORT_ALL(bank, pin, name, sfx)	name##_##sfx
 
 #define _GP_GPIO(bank, pin, _name, sfx)					\
-	[(bank * 32) + pin] = {						\
+	[RCAR_GP_PIN(bank, pin)] = {					\
 		.name = __stringify(_name),				\
 		.enum_id = _name##_DATA,				\
 	}
-- 
1.8.2.1

[PATCH 020/130] sh-pfc: r8a7779: add VIN pin groups

[Simon Horman]

From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>

Add VIN DATA[0:7]/CLK/HSYNC/VSYNC pin groups to R8A7779 PFC driver.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
[horms+renesas@verge.net.au: trivial rebase on top of
 "sh-pfc: r8a7779: Don't group USB OVC and PENC pins"]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 147 ++++++++++++++++++++++++++++++++++-
 1 file changed, 146 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 1590d6c..37ba571 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1,8 +1,9 @@
 /*
  * r8a7779 processor support - PFC hardware block
  *
- * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011, 2013  Renesas Solutions Corp.
  * Copyright (C) 2011  Magnus Damm
+ * Copyright (C) 2013  Cogent Embedded, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -2434,6 +2435,110 @@ static const unsigned int usb2_ovc_pins[] = {
 static const unsigned int usb2_ovc_mux[] = {
 	USB_OVC2_MARK,
 };
+/* - VIN0 ------------------------------------------------------------------- */
+static const unsigned int vin0_data8_pins[] = {
+	/* D[0:7] */
+	RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 8),
+	RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int vin0_data8_mux[] = {
+	VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK,
+	VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
+	VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
+};
+static const unsigned int vin0_clk_pins[] = {
+	/* CLK */
+	RCAR_GP_PIN(2, 1),
+};
+static const unsigned int vin0_clk_mux[] = {
+	VI0_CLK_MARK,
+};
+static const unsigned int vin0_sync_pins[] = {
+	/* HSYNC, VSYNC */
+	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+};
+static const unsigned int vin0_sync_mux[] = {
+	VI0_HSYNC_MARK, VI0_VSYNC_MARK,
+};
+/* - VIN1 ------------------------------------------------------------------- */
+static const unsigned int vin1_data8_pins[] = {
+	/* D[0:7] */
+	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
+	RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
+};
+static const unsigned int vin1_data8_mux[] = {
+	VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK,
+	VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
+	VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
+};
+static const unsigned int vin1_clk_pins[] = {
+	/* CLK */
+	RCAR_GP_PIN(2, 30),
+};
+static const unsigned int vin1_clk_mux[] = {
+	VI1_CLK_MARK,
+};
+static const unsigned int vin1_sync_pins[] = {
+	/* HSYNC, VSYNC */
+	RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0),
+};
+static const unsigned int vin1_sync_mux[] = {
+	VI1_HSYNC_MARK, VI1_VSYNC_MARK,
+};
+/* - VIN2 ------------------------------------------------------------------- */
+static const unsigned int vin2_data8_pins[] = {
+	/* D[0:7] */
+	RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
+	RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
+	RCAR_GP_PIN(1, 31), RCAR_GP_PIN(2, 0),
+};
+static const unsigned int vin2_data8_mux[] = {
+	VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK,
+	VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
+	VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
+};
+static const unsigned int vin2_clk_pins[] = {
+	/* CLK */
+	RCAR_GP_PIN(1, 30),
+};
+static const unsigned int vin2_clk_mux[] = {
+	VI2_CLK_MARK,
+};
+static const unsigned int vin2_sync_pins[] = {
+	/* HSYNC, VSYNC */
+	RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
+};
+static const unsigned int vin2_sync_mux[] = {
+	VI2_HSYNC_MARK, VI2_VSYNC_MARK,
+};
+/* - VIN3 ------------------------------------------------------------------- */
+static const unsigned int vin3_data8_pins[] = {
+	/* D[0:7] */
+	RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
+};
+static const unsigned int vin3_data8_mux[] = {
+	VI3_DATA0_MARK, VI3_DATA1_MARK, VI3_DATA2_MARK,
+	VI3_DATA3_MARK, VI3_DATA4_MARK, VI3_DATA5_MARK,
+	VI3_DATA6_MARK, VI3_DATA7_MARK,
+};
+static const unsigned int vin3_clk_pins[] = {
+	/* CLK */
+	RCAR_GP_PIN(2, 31),
+};
+static const unsigned int vin3_clk_mux[] = {
+	VI3_CLK_MARK,
+};
+static const unsigned int vin3_sync_pins[] = {
+	/* HSYNC, VSYNC */
+	RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
+};
+static const unsigned int vin3_sync_mux[] = {
+	VI3_HSYNC_MARK, VI3_VSYNC_MARK,
+};
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(du0_rgb666),
@@ -2561,6 +2666,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(usb1_ovc),
 	SH_PFC_PIN_GROUP(usb2),
 	SH_PFC_PIN_GROUP(usb2_ovc),
+	SH_PFC_PIN_GROUP(vin0_data8),
+	SH_PFC_PIN_GROUP(vin0_clk),
+	SH_PFC_PIN_GROUP(vin0_sync),
+	SH_PFC_PIN_GROUP(vin1_data8),
+	SH_PFC_PIN_GROUP(vin1_clk),
+	SH_PFC_PIN_GROUP(vin1_sync),
+	SH_PFC_PIN_GROUP(vin2_data8),
+	SH_PFC_PIN_GROUP(vin2_clk),
+	SH_PFC_PIN_GROUP(vin2_sync),
+	SH_PFC_PIN_GROUP(vin3_data8),
+	SH_PFC_PIN_GROUP(vin3_clk),
+	SH_PFC_PIN_GROUP(vin3_sync),
 };
 
 static const char * const du0_groups[] = {
@@ -2754,6 +2871,30 @@ static const char * const usb2_groups[] = {
 	"usb2_ovc",
 };
 
+static const char * const vin0_groups[] = {
+	"vin0_data8",
+	"vin0_clk",
+	"vin0_sync",
+};
+
+static const char * const vin1_groups[] = {
+	"vin1_data8",
+	"vin1_clk",
+	"vin1_sync",
+};
+
+static const char * const vin2_groups[] = {
+	"vin2_data8",
+	"vin2_clk",
+	"vin2_sync",
+};
+
+static const char * const vin3_groups[] = {
+	"vin3_data8",
+	"vin3_clk",
+	"vin3_sync",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(du0),
 	SH_PFC_FUNCTION(du1),
@@ -2777,6 +2918,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(usb0),
 	SH_PFC_FUNCTION(usb1),
 	SH_PFC_FUNCTION(usb2),
+	SH_PFC_FUNCTION(vin0),
+	SH_PFC_FUNCTION(vin1),
+	SH_PFC_FUNCTION(vin2),
+	SH_PFC_FUNCTION(vin3),
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
1.8.2.1

[PATCH 021/130] sh-pfc: r8a7778: add common PFC macro helper

[Simon Horman]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

pfc-r8a7778 will have many devices pfc support in the future,
and current pfc-r8a7778 is using pin/mux definition macro for SCIF.
The device definition style using macro is readable code IMO,
but creating new macro for each devices is not good sense.
This patch adds common SH_PFC_xx() macro for each new feature devices

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 26 ++++++++++++++++++--------
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index ddbd27b..139f9dd 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -1303,15 +1303,25 @@ static struct sh_pfc_pin pinmux_pins[] = {
  */
 #define PIN_NUMBER(row, col)		(1000+((row)-1)*25+(col)-1)
 
-/* - SCIF macro ------------------------------------------------------------- */
-#define SCIF_PFC_PIN(name, args...)					\
+/* - macro */
+#define SH_PFC_PINS(name, args...) \
 	static const unsigned int name ##_pins[] = { args }
-#define SCIF_PFC_DAT(name, tx, rx)					\
-	static const unsigned int name ##_mux[]  = { tx##_MARK, rx##_MARK, }
-#define SCIF_PFC_CTR(name, cts, rts)					\
-	static const unsigned int name ##_mux[]  = { cts##_MARK, rts##_MARK, }
-#define SCIF_PFC_CLK(name, sck)					\
-	static const unsigned int name ##_mux[]  = { sck##_MARK, }
+#define SH_PFC_MUX1(name, arg1)					\
+	static const unsigned int name ##_mux[]  = { arg1##_MARK }
+#define SH_PFC_MUX2(name, arg1, arg2)					\
+	static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, }
+#define SH_PFC_MUX3(name, arg1, arg2, arg3)					\
+	static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK,	\
+						     arg3##_MARK }
+#define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4)			\
+	static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
+						     arg3##_MARK, arg4##_MARK }
+
+/* - SCIF macro ------------------------------------------------------------- */
+#define SCIF_PFC_PIN(name, args...)	SH_PFC_PINS(name, args)
+#define SCIF_PFC_DAT(name, tx, rx)	SH_PFC_MUX2(name, tx, rx)
+#define SCIF_PFC_CTR(name, cts, rts)	SH_PFC_MUX2(name, cts, rts)
+#define SCIF_PFC_CLK(name, sck)		SH_PFC_MUX1(name, sck)
 
 /* - HSCIF0 ----------------------------------------------------------------- */
 SCIF_PFC_PIN(hscif0_data_a,	RCAR_GP_PIN(1, 17),	RCAR_GP_PIN(1, 18));
-- 
1.8.2.1

[PATCH 022/130] sh-pfc: r8a7778: add SDHI support

[Simon Horman]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 141 +++++++++++++++++++++++++++++++++++
 1 file changed, 141 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index 139f9dd..b1925cc 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -1427,6 +1427,84 @@ SCIF_PFC_DAT(scif5_data_a,	TX5_A,			RX5_A);
 SCIF_PFC_PIN(scif5_data_b,	RCAR_GP_PIN(1, 15),	RCAR_GP_PIN(1, 14));
 SCIF_PFC_DAT(scif5_data_b,	TX5_B,			RX5_B);
 
+/* - SDHI macro ------------------------------------------------------------- */
+#define SDHI_PFC_PINS(name, args...)		SH_PFC_PINS(name, args)
+#define SDHI_PFC_DAT1(name, d0)			SH_PFC_MUX1(name, d0)
+#define SDHI_PFC_DAT4(name, d0, d1, d2, d3)	SH_PFC_MUX4(name, d0, d1, d2, d3)
+#define SDHI_PFC_CTRL(name, clk, cmd)		SH_PFC_MUX2(name, clk, cmd)
+#define SDHI_PFC_CDPN(name, cd)			SH_PFC_MUX1(name, cd)
+#define SDHI_PFC_WPPN(name, wp)			SH_PFC_MUX1(name, wp)
+
+/* - SDHI0 ------------------------------------------------------------------ */
+SDHI_PFC_PINS(sdhi0_cd,		RCAR_GP_PIN(3, 17));
+SDHI_PFC_CDPN(sdhi0_cd,		SD0_CD);
+SDHI_PFC_PINS(sdhi0_ctrl,	RCAR_GP_PIN(3, 11),	RCAR_GP_PIN(3, 12));
+SDHI_PFC_CTRL(sdhi0_ctrl,	SD0_CLK,		SD0_CMD);
+SDHI_PFC_PINS(sdhi0_data1,	RCAR_GP_PIN(3, 13));
+SDHI_PFC_DAT1(sdhi0_data1,	SD0_DAT0);
+SDHI_PFC_PINS(sdhi0_data4,	RCAR_GP_PIN(3, 13),	RCAR_GP_PIN(3, 14),
+				RCAR_GP_PIN(3, 15),	RCAR_GP_PIN(3, 16));
+SDHI_PFC_DAT4(sdhi0_data4,	SD0_DAT0,		SD0_DAT1,
+				SD0_DAT2,		SD0_DAT3);
+SDHI_PFC_PINS(sdhi0_wp,		RCAR_GP_PIN(3, 18));
+SDHI_PFC_WPPN(sdhi0_wp,		SD0_WP);
+
+/* - SDHI1 ------------------------------------------------------------------ */
+SDHI_PFC_PINS(sdhi1_a_cd,	RCAR_GP_PIN(0, 30));
+SDHI_PFC_CDPN(sdhi1_a_cd,	SD1_CD_A);
+SDHI_PFC_PINS(sdhi1_a_ctrl,	RCAR_GP_PIN(1, 5),	RCAR_GP_PIN(1, 6));
+SDHI_PFC_CTRL(sdhi1_a_ctrl,	SD1_CLK_A,		SD1_CMD_A);
+SDHI_PFC_PINS(sdhi1_a_data1,	RCAR_GP_PIN(1, 7));
+SDHI_PFC_DAT1(sdhi1_a_data1,	SD1_DAT0_A);
+SDHI_PFC_PINS(sdhi1_a_data4,	RCAR_GP_PIN(1, 7),	RCAR_GP_PIN(1, 8),
+				RCAR_GP_PIN(0, 5),	RCAR_GP_PIN(0, 6));
+SDHI_PFC_DAT4(sdhi1_a_data4,	SD1_DAT0_A,		SD1_DAT1_A,
+				SD1_DAT2_A,		SD1_DAT3_A);
+SDHI_PFC_PINS(sdhi1_a_wp,	RCAR_GP_PIN(0, 31));
+SDHI_PFC_WPPN(sdhi1_a_wp,	SD1_WP_A);
+
+SDHI_PFC_PINS(sdhi1_b_cd,	RCAR_GP_PIN(2, 24));
+SDHI_PFC_CDPN(sdhi1_b_cd,	SD1_CD_B);
+SDHI_PFC_PINS(sdhi1_b_ctrl,	RCAR_GP_PIN(1, 17),	RCAR_GP_PIN(1, 16));
+SDHI_PFC_CTRL(sdhi1_b_ctrl,	SD1_CLK_B,		SD1_CMD_B);
+SDHI_PFC_PINS(sdhi1_b_data1,	RCAR_GP_PIN(1, 18));
+SDHI_PFC_DAT1(sdhi1_b_data1,	SD1_DAT0_B);
+SDHI_PFC_PINS(sdhi1_b_data4,	RCAR_GP_PIN(1, 18),	RCAR_GP_PIN(1, 19),
+				RCAR_GP_PIN(1, 20),	RCAR_GP_PIN(1, 21));
+SDHI_PFC_DAT4(sdhi1_b_data4,	SD1_DAT0_B,		SD1_DAT1_B,
+				SD1_DAT2_B,		SD1_DAT3_B);
+SDHI_PFC_PINS(sdhi1_b_wp,	RCAR_GP_PIN(2, 25));
+SDHI_PFC_WPPN(sdhi1_b_wp,	SD1_WP_B);
+
+
+/* - SDH2 ------------------------------------------------------------------- */
+SDHI_PFC_PINS(sdhi2_a_cd,	RCAR_GP_PIN(4, 23));
+SDHI_PFC_CDPN(sdhi2_a_cd,	SD2_CD_A);
+SDHI_PFC_PINS(sdhi2_a_ctrl,	RCAR_GP_PIN(4, 17),	RCAR_GP_PIN(4, 18));
+SDHI_PFC_CTRL(sdhi2_a_ctrl,	SD2_CLK_A,		SD2_CMD_A);
+SDHI_PFC_PINS(sdhi2_a_data1,	RCAR_GP_PIN(4, 19));
+SDHI_PFC_DAT1(sdhi2_a_data1,	SD2_DAT0_A);
+SDHI_PFC_PINS(sdhi2_a_data4,	RCAR_GP_PIN(4, 19),	RCAR_GP_PIN(4, 20),
+				RCAR_GP_PIN(4, 21),	RCAR_GP_PIN(4, 22));
+SDHI_PFC_DAT4(sdhi2_a_data4,	SD2_DAT0_A,		SD2_DAT1_A,
+				SD2_DAT2_A,		SD2_DAT3_A);
+SDHI_PFC_PINS(sdhi2_a_wp,	RCAR_GP_PIN(4, 24));
+SDHI_PFC_WPPN(sdhi2_a_wp,	SD2_WP_A);
+
+SDHI_PFC_PINS(sdhi2_b_cd,	RCAR_GP_PIN(3, 27));
+SDHI_PFC_CDPN(sdhi2_b_cd,	SD2_CD_B);
+SDHI_PFC_PINS(sdhi2_b_ctrl,	RCAR_GP_PIN(4, 5),	RCAR_GP_PIN(4, 6));
+SDHI_PFC_CTRL(sdhi2_b_ctrl,	SD2_CLK_B,		SD2_CMD_B);
+SDHI_PFC_PINS(sdhi2_b_data1,	RCAR_GP_PIN(4, 7));
+SDHI_PFC_DAT1(sdhi2_b_data1,	SD2_DAT0_B);
+SDHI_PFC_PINS(sdhi2_b_data4,	RCAR_GP_PIN(4, 7),	RCAR_GP_PIN(4, 8),
+				RCAR_GP_PIN(3, 25),	RCAR_GP_PIN(3, 26));
+SDHI_PFC_DAT4(sdhi2_b_data4,	SD2_DAT0_B,		SD2_DAT1_B,
+				SD2_DAT2_B,		SD2_DAT3_B);
+SDHI_PFC_PINS(sdhi2_b_wp,	RCAR_GP_PIN(3, 28));
+SDHI_PFC_WPPN(sdhi2_b_wp,	SD2_WP_B);
+
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(hscif0_data_a),
 	SH_PFC_PIN_GROUP(hscif0_data_b),
@@ -1471,6 +1549,31 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(scif4_data_c),
 	SH_PFC_PIN_GROUP(scif5_data_a),
 	SH_PFC_PIN_GROUP(scif5_data_b),
+	SH_PFC_PIN_GROUP(sdhi0_cd),
+	SH_PFC_PIN_GROUP(sdhi0_ctrl),
+	SH_PFC_PIN_GROUP(sdhi0_data1),
+	SH_PFC_PIN_GROUP(sdhi0_data4),
+	SH_PFC_PIN_GROUP(sdhi0_wp),
+	SH_PFC_PIN_GROUP(sdhi1_a_cd),
+	SH_PFC_PIN_GROUP(sdhi1_a_ctrl),
+	SH_PFC_PIN_GROUP(sdhi1_a_data1),
+	SH_PFC_PIN_GROUP(sdhi1_a_data4),
+	SH_PFC_PIN_GROUP(sdhi1_a_wp),
+	SH_PFC_PIN_GROUP(sdhi1_b_cd),
+	SH_PFC_PIN_GROUP(sdhi1_b_ctrl),
+	SH_PFC_PIN_GROUP(sdhi1_b_data1),
+	SH_PFC_PIN_GROUP(sdhi1_b_data4),
+	SH_PFC_PIN_GROUP(sdhi1_b_wp),
+	SH_PFC_PIN_GROUP(sdhi2_a_cd),
+	SH_PFC_PIN_GROUP(sdhi2_a_ctrl),
+	SH_PFC_PIN_GROUP(sdhi2_a_data1),
+	SH_PFC_PIN_GROUP(sdhi2_a_data4),
+	SH_PFC_PIN_GROUP(sdhi2_a_wp),
+	SH_PFC_PIN_GROUP(sdhi2_b_cd),
+	SH_PFC_PIN_GROUP(sdhi2_b_ctrl),
+	SH_PFC_PIN_GROUP(sdhi2_b_data1),
+	SH_PFC_PIN_GROUP(sdhi2_b_data4),
+	SH_PFC_PIN_GROUP(sdhi2_b_wp),
 };
 
 static const char * const hscif0_groups[] = {
@@ -1543,6 +1646,41 @@ static const char * const scif5_groups[] = {
 	"scif5_data_b",
 };
 
+
+static const char * const sdhi0_groups[] = {
+	"sdhi0_cd",
+	"sdhi0_ctrl",
+	"sdhi0_data1",
+	"sdhi0_data4",
+	"sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+	"sdhi1_a_cd",
+	"sdhi1_a_ctrl",
+	"sdhi1_a_data1",
+	"sdhi1_a_data4",
+	"sdhi1_a_wp",
+	"sdhi1_b_cd",
+	"sdhi1_b_ctrl",
+	"sdhi1_b_data1",
+	"sdhi1_b_data4",
+	"sdhi1_b_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+	"sdhi2_a_cd",
+	"sdhi2_a_ctrl",
+	"sdhi2_a_data1",
+	"sdhi2_a_data4",
+	"sdhi2_a_wp",
+	"sdhi2_b_cd",
+	"sdhi2_b_ctrl",
+	"sdhi2_b_data1",
+	"sdhi2_b_data4",
+	"sdhi2_b_wp",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(hscif0),
 	SH_PFC_FUNCTION(hscif1),
@@ -1553,6 +1691,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(scif3),
 	SH_PFC_FUNCTION(scif4),
 	SH_PFC_FUNCTION(scif5),
+	SH_PFC_FUNCTION(sdhi0),
+	SH_PFC_FUNCTION(sdhi1),
+	SH_PFC_FUNCTION(sdhi2),
 };
 
 static struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
1.8.2.1

[PATCH 023/130] sh-pfc: sh7372: Add BSC pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-sh7372.c | 124 ++++++++++++++++++++++++++++++++++++
 1 file changed, 124 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index df0ae21..9545b3c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -933,6 +933,102 @@ static struct sh_pfc_pin pinmux_pins[] = {
 	GPIO_PORT_ALL(),
 };
 
+/* - BSC -------------------------------------------------------------------- */
+static const unsigned int bsc_data8_pins[] = {
+	/* D[0:7] */
+	46, 47, 48, 49, 50, 51, 52, 53,
+};
+static const unsigned int bsc_data8_mux[] = {
+	D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+	D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+};
+static const unsigned int bsc_data16_pins[] = {
+	/* D[0:15] */
+	46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
+};
+static const unsigned int bsc_data16_mux[] = {
+	D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+	D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+	D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+	D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+};
+static const unsigned int bsc_cs0_pins[] = {
+	/* CS */
+	62,
+};
+static const unsigned int bsc_cs0_mux[] = {
+	CS0_MARK,
+};
+static const unsigned int bsc_cs2_pins[] = {
+	/* CS */
+	63,
+};
+static const unsigned int bsc_cs2_mux[] = {
+	CS2_MARK,
+};
+static const unsigned int bsc_cs4_pins[] = {
+	/* CS */
+	64,
+};
+static const unsigned int bsc_cs4_mux[] = {
+	CS4_MARK,
+};
+static const unsigned int bsc_cs5a_pins[] = {
+	/* CS */
+	65,
+};
+static const unsigned int bsc_cs5a_mux[] = {
+	CS5A_MARK,
+};
+static const unsigned int bsc_cs5b_pins[] = {
+	/* CS */
+	66,
+};
+static const unsigned int bsc_cs5b_mux[] = {
+	CS5B_MARK,
+};
+static const unsigned int bsc_cs6a_pins[] = {
+	/* CS */
+	67,
+};
+static const unsigned int bsc_cs6a_mux[] = {
+	CS6A_MARK,
+};
+static const unsigned int bsc_rd_we8_pins[] = {
+	/* RD, WE[0] */
+	69, 70,
+};
+static const unsigned int bsc_rd_we8_mux[] = {
+	RD_FSC_MARK, WE0_FWE_MARK,
+};
+static const unsigned int bsc_rd_we16_pins[] = {
+	/* RD, WE[0:1] */
+	69, 70, 71,
+};
+static const unsigned int bsc_rd_we16_mux[] = {
+	RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
+};
+static const unsigned int bsc_bs_pins[] = {
+	/* BS */
+	19,
+};
+static const unsigned int bsc_bs_mux[] = {
+	BS_MARK,
+};
+static const unsigned int bsc_rdwr_pins[] = {
+	/* RDWR */
+	75,
+};
+static const unsigned int bsc_rdwr_mux[] = {
+	RDWR_MARK,
+};
+static const unsigned int bsc_wait_pins[] = {
+	/* WAIT */
+	74,
+};
+static const unsigned int bsc_wait_mux[] = {
+	WAIT_MARK,
+};
 /* - MMCIF ------------------------------------------------------------------ */
 static const unsigned int mmc0_data1_0_pins[] = {
 	/* D[0] */
@@ -1075,6 +1171,18 @@ static const unsigned int sdhi2_ctrl_mux[] = {
 };
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SH_PFC_PIN_GROUP(bsc_data8),
+	SH_PFC_PIN_GROUP(bsc_data16),
+	SH_PFC_PIN_GROUP(bsc_cs0),
+	SH_PFC_PIN_GROUP(bsc_cs2),
+	SH_PFC_PIN_GROUP(bsc_cs4),
+	SH_PFC_PIN_GROUP(bsc_cs5a),
+	SH_PFC_PIN_GROUP(bsc_cs5b),
+	SH_PFC_PIN_GROUP(bsc_cs6a),
+	SH_PFC_PIN_GROUP(bsc_rd_we8),
+	SH_PFC_PIN_GROUP(bsc_rd_we16),
+	SH_PFC_PIN_GROUP(bsc_bs),
+	SH_PFC_PIN_GROUP(bsc_rdwr),
 	SH_PFC_PIN_GROUP(mmc0_data1_0),
 	SH_PFC_PIN_GROUP(mmc0_data4_0),
 	SH_PFC_PIN_GROUP(mmc0_data8_0),
@@ -1096,6 +1204,21 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(sdhi2_ctrl),
 };
 
+static const char * const bsc_groups[] = {
+	"bsc_data8",
+	"bsc_data16",
+	"bsc_cs0",
+	"bsc_cs2",
+	"bsc_cs4",
+	"bsc_cs5a",
+	"bsc_cs5b",
+	"bsc_cs6a",
+	"bsc_rd_we8",
+	"bsc_rd_we16",
+	"bsc_bs",
+	"bsc_rdwr",
+};
+
 static const char * const mmc0_groups[] = {
 	"mmc0_data1_0",
 	"mmc0_data4_0",
@@ -1128,6 +1251,7 @@ static const char * const sdhi2_groups[] = {
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(bsc),
 	SH_PFC_FUNCTION(mmc0),
 	SH_PFC_FUNCTION(sdhi0),
 	SH_PFC_FUNCTION(sdhi1),
-- 
1.8.2.1

[PATCH 024/130] sh-pfc: sh7372: Add CEU pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-sh7372.c | 70 +++++++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index 9545b3c..3da8319 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -1029,6 +1029,58 @@ static const unsigned int bsc_wait_pins[] = {
 static const unsigned int bsc_wait_mux[] = {
 	WAIT_MARK,
 };
+/* - CEU -------------------------------------------------------------------- */
+static const unsigned int ceu_data_0_7_pins[] = {
+	/* D[0:7] */
+	102, 103, 104, 105, 106, 107, 108, 109,
+};
+static const unsigned int ceu_data_0_7_mux[] = {
+	VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK,
+	VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK,
+};
+static const unsigned int ceu_data_8_15_pins[] = {
+	/* D[8:15] */
+	110, 111, 112, 113, 114, 115, 116, 117,
+};
+static const unsigned int ceu_data_8_15_mux[] = {
+	VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
+	VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK,
+};
+static const unsigned int ceu_clk_0_pins[] = {
+	/* CKO */
+	120,
+};
+static const unsigned int ceu_clk_0_mux[] = {
+	VIO_CKO_MARK,
+};
+static const unsigned int ceu_clk_1_pins[] = {
+	/* CKO */
+	16,
+};
+static const unsigned int ceu_clk_1_mux[] = {
+	VIO_CKO1_MARK,
+};
+static const unsigned int ceu_clk_2_pins[] = {
+	/* CKO */
+	17,
+};
+static const unsigned int ceu_clk_2_mux[] = {
+	VIO_CKO2_MARK,
+};
+static const unsigned int ceu_sync_pins[] = {
+	/* CLK, VD, HD */
+	118, 100, 101,
+};
+static const unsigned int ceu_sync_mux[] = {
+	VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK,
+};
+static const unsigned int ceu_field_pins[] = {
+	/* FIELD */
+	119,
+};
+static const unsigned int ceu_field_mux[] = {
+	VIO_FIELD_MARK,
+};
 /* - MMCIF ------------------------------------------------------------------ */
 static const unsigned int mmc0_data1_0_pins[] = {
 	/* D[0] */
@@ -1183,6 +1235,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(bsc_rd_we16),
 	SH_PFC_PIN_GROUP(bsc_bs),
 	SH_PFC_PIN_GROUP(bsc_rdwr),
+	SH_PFC_PIN_GROUP(ceu_data_0_7),
+	SH_PFC_PIN_GROUP(ceu_data_8_15),
+	SH_PFC_PIN_GROUP(ceu_clk_0),
+	SH_PFC_PIN_GROUP(ceu_clk_1),
+	SH_PFC_PIN_GROUP(ceu_clk_2),
+	SH_PFC_PIN_GROUP(ceu_sync),
+	SH_PFC_PIN_GROUP(ceu_field),
 	SH_PFC_PIN_GROUP(mmc0_data1_0),
 	SH_PFC_PIN_GROUP(mmc0_data4_0),
 	SH_PFC_PIN_GROUP(mmc0_data8_0),
@@ -1219,6 +1278,16 @@ static const char * const bsc_groups[] = {
 	"bsc_rdwr",
 };
 
+static const char * const ceu_groups[] = {
+	"ceu_data_0_7",
+	"ceu_data_8_15",
+	"ceu_clk_0",
+	"ceu_clk_1",
+	"ceu_clk_2",
+	"ceu_sync",
+	"ceu_field",
+};
+
 static const char * const mmc0_groups[] = {
 	"mmc0_data1_0",
 	"mmc0_data4_0",
@@ -1252,6 +1321,7 @@ static const char * const sdhi2_groups[] = {
 
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(bsc),
+	SH_PFC_FUNCTION(ceu),
 	SH_PFC_FUNCTION(mmc0),
 	SH_PFC_FUNCTION(sdhi0),
 	SH_PFC_FUNCTION(sdhi1),
-- 
1.8.2.1

[PATCH 025/130] sh-pfc: sh7372: Add FLCTL pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-sh7372.c | 44 +++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index 3da8319..9948699 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -1081,6 +1081,38 @@ static const unsigned int ceu_field_pins[] = {
 static const unsigned int ceu_field_mux[] = {
 	VIO_FIELD_MARK,
 };
+/* - FLCTL ------------------------------------------------------------------ */
+static const unsigned int flctl_data_pins[] = {
+	/* NAF[0:15] */
+	46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
+};
+static const unsigned int flctl_data_mux[] = {
+	D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+	D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+	D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+	D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+};
+static const unsigned int flctl_ce0_pins[] = {
+	/* CE */
+	68,
+};
+static const unsigned int flctl_ce0_mux[] = {
+	FCE0_MARK,
+};
+static const unsigned int flctl_ce1_pins[] = {
+	/* CE */
+	66,
+};
+static const unsigned int flctl_ce1_mux[] = {
+	FCE1_MARK,
+};
+static const unsigned int flctl_ctrl_pins[] = {
+	/* FCDE, FOE, FSC, FWE, FRB */
+	24, 23, 69, 70, 73,
+};
+static const unsigned int flctl_ctrl_mux[] = {
+	A5_FCDE_MARK, A4_FOE_MARK, RD_FSC_MARK, WE0_FWE_MARK, FRB_MARK,
+};
 /* - MMCIF ------------------------------------------------------------------ */
 static const unsigned int mmc0_data1_0_pins[] = {
 	/* D[0] */
@@ -1242,6 +1274,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(ceu_clk_2),
 	SH_PFC_PIN_GROUP(ceu_sync),
 	SH_PFC_PIN_GROUP(ceu_field),
+	SH_PFC_PIN_GROUP(flctl_data),
+	SH_PFC_PIN_GROUP(flctl_ce0),
+	SH_PFC_PIN_GROUP(flctl_ce1),
+	SH_PFC_PIN_GROUP(flctl_ctrl),
 	SH_PFC_PIN_GROUP(mmc0_data1_0),
 	SH_PFC_PIN_GROUP(mmc0_data4_0),
 	SH_PFC_PIN_GROUP(mmc0_data8_0),
@@ -1288,6 +1324,13 @@ static const char * const ceu_groups[] = {
 	"ceu_field",
 };
 
+static const char * const flctl_groups[] = {
+	"flctl_data",
+	"flctl_ce0",
+	"flctl_ce1",
+	"flctl_ctrl",
+};
+
 static const char * const mmc0_groups[] = {
 	"mmc0_data1_0",
 	"mmc0_data4_0",
@@ -1322,6 +1365,7 @@ static const char * const sdhi2_groups[] = {
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(bsc),
 	SH_PFC_FUNCTION(ceu),
+	SH_PFC_FUNCTION(flctl),
 	SH_PFC_FUNCTION(mmc0),
 	SH_PFC_FUNCTION(sdhi0),
 	SH_PFC_FUNCTION(sdhi1),
-- 
1.8.2.1

[PATCH 026/130] sh-pfc: sh7372: Add FSI pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-sh7372.c | 91 +++++++++++++++++++++++++++++++++++++
 1 file changed, 91 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index 9948699..641f6ee 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -1113,6 +1113,71 @@ static const unsigned int flctl_ctrl_pins[] = {
 static const unsigned int flctl_ctrl_mux[] = {
 	A5_FCDE_MARK, A4_FOE_MARK, RD_FSC_MARK, WE0_FWE_MARK, FRB_MARK,
 };
+/* - FSIA ------------------------------------------------------------------- */
+static const unsigned int fsia_mclk_in_pins[] = {
+	/* CK */
+	4,
+};
+static const unsigned int fsia_mclk_in_mux[] = {
+	FSIACK_MARK,
+};
+static const unsigned int fsia_mclk_out_pins[] = {
+	/* OMC */
+	8,
+};
+static const unsigned int fsia_mclk_out_mux[] = {
+	FSIAOMC_MARK,
+};
+static const unsigned int fsia_sclk_in_pins[] = {
+	/* ILR, IBT */
+	5, 6,
+};
+static const unsigned int fsia_sclk_in_mux[] = {
+	FSIAILR_MARK, FSIAIBT_MARK,
+};
+static const unsigned int fsia_sclk_out_pins[] = {
+	/* OLR, OBT */
+	9, 10,
+};
+static const unsigned int fsia_sclk_out_mux[] = {
+	FSIAOLR_MARK, FSIAOBT_MARK,
+};
+static const unsigned int fsia_data_in_pins[] = {
+	/* ISLD */
+	7,
+};
+static const unsigned int fsia_data_in_mux[] = {
+	FSIAISLD_MARK,
+};
+static const unsigned int fsia_data_out_pins[] = {
+	/* OSLD */
+	11,
+};
+static const unsigned int fsia_data_out_mux[] = {
+	FSIAOSLD_MARK,
+};
+static const unsigned int fsia_spdif_0_pins[] = {
+	/* SPDIF */
+	11,
+};
+static const unsigned int fsia_spdif_0_mux[] = {
+	FSIASPDIF_11_MARK,
+};
+static const unsigned int fsia_spdif_1_pins[] = {
+	/* SPDIF */
+	15,
+};
+static const unsigned int fsia_spdif_1_mux[] = {
+	FSIASPDIF_15_MARK,
+};
+/* - FSIB ------------------------------------------------------------------- */
+static const unsigned int fsib_mclk_in_pins[] = {
+	/* CK */
+	4,
+};
+static const unsigned int fsib_mclk_in_mux[] = {
+	FSIBCK_MARK,
+};
 /* - MMCIF ------------------------------------------------------------------ */
 static const unsigned int mmc0_data1_0_pins[] = {
 	/* D[0] */
@@ -1278,6 +1343,15 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(flctl_ce0),
 	SH_PFC_PIN_GROUP(flctl_ce1),
 	SH_PFC_PIN_GROUP(flctl_ctrl),
+	SH_PFC_PIN_GROUP(fsia_mclk_in),
+	SH_PFC_PIN_GROUP(fsia_mclk_out),
+	SH_PFC_PIN_GROUP(fsia_sclk_in),
+	SH_PFC_PIN_GROUP(fsia_sclk_out),
+	SH_PFC_PIN_GROUP(fsia_data_in),
+	SH_PFC_PIN_GROUP(fsia_data_out),
+	SH_PFC_PIN_GROUP(fsia_spdif_0),
+	SH_PFC_PIN_GROUP(fsia_spdif_1),
+	SH_PFC_PIN_GROUP(fsib_mclk_in),
 	SH_PFC_PIN_GROUP(mmc0_data1_0),
 	SH_PFC_PIN_GROUP(mmc0_data4_0),
 	SH_PFC_PIN_GROUP(mmc0_data8_0),
@@ -1331,6 +1405,21 @@ static const char * const flctl_groups[] = {
 	"flctl_ctrl",
 };
 
+static const char * const fsia_groups[] = {
+	"fsia_mclk_in",
+	"fsia_mclk_out",
+	"fsia_sclk_in",
+	"fsia_sclk_out",
+	"fsia_data_in",
+	"fsia_data_out",
+	"fsia_spdif_0",
+	"fsia_spdif_1",
+};
+
+static const char * const fsib_groups[] = {
+	"fsib_mclk_in",
+};
+
 static const char * const mmc0_groups[] = {
 	"mmc0_data1_0",
 	"mmc0_data4_0",
@@ -1366,6 +1455,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(bsc),
 	SH_PFC_FUNCTION(ceu),
 	SH_PFC_FUNCTION(flctl),
+	SH_PFC_FUNCTION(fsia),
+	SH_PFC_FUNCTION(fsib),
 	SH_PFC_FUNCTION(mmc0),
 	SH_PFC_FUNCTION(sdhi0),
 	SH_PFC_FUNCTION(sdhi1),
-- 
1.8.2.1

[PATCH 027/130] sh-pfc: sh7372: Add HDMI pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-sh7372.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index 641f6ee..73b9e25 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -1178,6 +1178,14 @@ static const unsigned int fsib_mclk_in_pins[] = {
 static const unsigned int fsib_mclk_in_mux[] = {
 	FSIBCK_MARK,
 };
+/* - HDMI ------------------------------------------------------------------- */
+static const unsigned int hdmi_pins[] = {
+	/* HPD, CEC */
+	169, 170,
+};
+static const unsigned int hdmi_mux[] = {
+	HDMI_HPD_MARK, HDMI_CEC_MARK,
+};
 /* - MMCIF ------------------------------------------------------------------ */
 static const unsigned int mmc0_data1_0_pins[] = {
 	/* D[0] */
@@ -1352,6 +1360,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(fsia_spdif_0),
 	SH_PFC_PIN_GROUP(fsia_spdif_1),
 	SH_PFC_PIN_GROUP(fsib_mclk_in),
+	SH_PFC_PIN_GROUP(hdmi),
 	SH_PFC_PIN_GROUP(mmc0_data1_0),
 	SH_PFC_PIN_GROUP(mmc0_data4_0),
 	SH_PFC_PIN_GROUP(mmc0_data8_0),
@@ -1420,6 +1429,10 @@ static const char * const fsib_groups[] = {
 	"fsib_mclk_in",
 };
 
+static const char * const hdmi_groups[] = {
+	"hdmi",
+};
+
 static const char * const mmc0_groups[] = {
 	"mmc0_data1_0",
 	"mmc0_data4_0",
@@ -1457,6 +1470,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(flctl),
 	SH_PFC_FUNCTION(fsia),
 	SH_PFC_FUNCTION(fsib),
+	SH_PFC_FUNCTION(hdmi),
 	SH_PFC_FUNCTION(mmc0),
 	SH_PFC_FUNCTION(sdhi0),
 	SH_PFC_FUNCTION(sdhi1),
-- 
1.8.2.1

[PATCH 028/130] sh-pfc: sh7372: Add INTC pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-sh7372.c | 161 ++++++++++++++++++++++++++++++++++++
 1 file changed, 161 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index 73b9e25..def6e2c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -34,6 +34,28 @@
 	PORT_10(fn, pfx##16, sfx),	PORT_10(fn, pfx##17, sfx), \
 	PORT_10(fn, pfx##18, sfx),	PORT_1(fn, pfx##190, sfx)
 
+#define IRQC_PIN_MUX(irq, pin)						\
+static const unsigned int intc_irq##irq##_pins[] = {			\
+	pin,								\
+};									\
+static const unsigned int intc_irq##irq##_mux[] = {			\
+	IRQ##irq##_MARK,						\
+}
+
+#define IRQC_PINS_MUX(irq, pin0, pin1)					\
+static const unsigned int intc_irq##irq##_0_pins[] = {			\
+	pin0,								\
+};									\
+static const unsigned int intc_irq##irq##_0_mux[] = {			\
+	IRQ##irq##_##pin0##_MARK,					\
+};									\
+static const unsigned int intc_irq##irq##_1_pins[] = {			\
+	pin1,								\
+};									\
+static const unsigned int intc_irq##irq##_1_mux[] = {			\
+	IRQ##irq##_##pin1##_MARK,					\
+}
+
 enum {
 	PINMUX_RESERVED = 0,
 
@@ -1186,6 +1208,39 @@ static const unsigned int hdmi_pins[] = {
 static const unsigned int hdmi_mux[] = {
 	HDMI_HPD_MARK, HDMI_CEC_MARK,
 };
+/* - INTC ------------------------------------------------------------------- */
+IRQC_PINS_MUX(0, 6, 162);
+IRQC_PIN_MUX(1, 12);
+IRQC_PINS_MUX(2, 4, 5);
+IRQC_PINS_MUX(3, 8, 16);
+IRQC_PINS_MUX(4, 17, 163);
+IRQC_PIN_MUX(5, 18);
+IRQC_PINS_MUX(6, 39, 164);
+IRQC_PINS_MUX(7, 40, 167);
+IRQC_PINS_MUX(8, 41, 168);
+IRQC_PINS_MUX(9, 42, 169);
+IRQC_PIN_MUX(10, 65);
+IRQC_PIN_MUX(11, 67);
+IRQC_PINS_MUX(12, 80, 137);
+IRQC_PINS_MUX(13, 81, 145);
+IRQC_PINS_MUX(14, 82, 146);
+IRQC_PINS_MUX(15, 83, 147);
+IRQC_PINS_MUX(16, 84, 170);
+IRQC_PIN_MUX(17, 85);
+IRQC_PIN_MUX(18, 86);
+IRQC_PIN_MUX(19, 87);
+IRQC_PIN_MUX(20, 92);
+IRQC_PIN_MUX(21, 93);
+IRQC_PIN_MUX(22, 94);
+IRQC_PIN_MUX(23, 95);
+IRQC_PIN_MUX(24, 112);
+IRQC_PIN_MUX(25, 119);
+IRQC_PINS_MUX(26, 121, 172);
+IRQC_PINS_MUX(27, 122, 180);
+IRQC_PINS_MUX(28, 123, 181);
+IRQC_PINS_MUX(29, 129, 182);
+IRQC_PINS_MUX(30, 130, 183);
+IRQC_PINS_MUX(31, 138, 184);
 /* - MMCIF ------------------------------------------------------------------ */
 static const unsigned int mmc0_data1_0_pins[] = {
 	/* D[0] */
@@ -1361,6 +1416,57 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(fsia_spdif_1),
 	SH_PFC_PIN_GROUP(fsib_mclk_in),
 	SH_PFC_PIN_GROUP(hdmi),
+	SH_PFC_PIN_GROUP(intc_irq0_0),
+	SH_PFC_PIN_GROUP(intc_irq0_1),
+	SH_PFC_PIN_GROUP(intc_irq1),
+	SH_PFC_PIN_GROUP(intc_irq2_0),
+	SH_PFC_PIN_GROUP(intc_irq2_1),
+	SH_PFC_PIN_GROUP(intc_irq3_0),
+	SH_PFC_PIN_GROUP(intc_irq3_1),
+	SH_PFC_PIN_GROUP(intc_irq4_0),
+	SH_PFC_PIN_GROUP(intc_irq4_1),
+	SH_PFC_PIN_GROUP(intc_irq5),
+	SH_PFC_PIN_GROUP(intc_irq6_0),
+	SH_PFC_PIN_GROUP(intc_irq6_1),
+	SH_PFC_PIN_GROUP(intc_irq7_0),
+	SH_PFC_PIN_GROUP(intc_irq7_1),
+	SH_PFC_PIN_GROUP(intc_irq8_0),
+	SH_PFC_PIN_GROUP(intc_irq8_1),
+	SH_PFC_PIN_GROUP(intc_irq9_0),
+	SH_PFC_PIN_GROUP(intc_irq9_1),
+	SH_PFC_PIN_GROUP(intc_irq10),
+	SH_PFC_PIN_GROUP(intc_irq11),
+	SH_PFC_PIN_GROUP(intc_irq12_0),
+	SH_PFC_PIN_GROUP(intc_irq12_1),
+	SH_PFC_PIN_GROUP(intc_irq13_0),
+	SH_PFC_PIN_GROUP(intc_irq13_1),
+	SH_PFC_PIN_GROUP(intc_irq14_0),
+	SH_PFC_PIN_GROUP(intc_irq14_1),
+	SH_PFC_PIN_GROUP(intc_irq15_0),
+	SH_PFC_PIN_GROUP(intc_irq15_1),
+	SH_PFC_PIN_GROUP(intc_irq16_0),
+	SH_PFC_PIN_GROUP(intc_irq16_1),
+	SH_PFC_PIN_GROUP(intc_irq17),
+	SH_PFC_PIN_GROUP(intc_irq18),
+	SH_PFC_PIN_GROUP(intc_irq19),
+	SH_PFC_PIN_GROUP(intc_irq20),
+	SH_PFC_PIN_GROUP(intc_irq21),
+	SH_PFC_PIN_GROUP(intc_irq22),
+	SH_PFC_PIN_GROUP(intc_irq23),
+	SH_PFC_PIN_GROUP(intc_irq24),
+	SH_PFC_PIN_GROUP(intc_irq25),
+	SH_PFC_PIN_GROUP(intc_irq26_0),
+	SH_PFC_PIN_GROUP(intc_irq26_1),
+	SH_PFC_PIN_GROUP(intc_irq27_0),
+	SH_PFC_PIN_GROUP(intc_irq27_1),
+	SH_PFC_PIN_GROUP(intc_irq28_0),
+	SH_PFC_PIN_GROUP(intc_irq28_1),
+	SH_PFC_PIN_GROUP(intc_irq29_0),
+	SH_PFC_PIN_GROUP(intc_irq29_1),
+	SH_PFC_PIN_GROUP(intc_irq30_0),
+	SH_PFC_PIN_GROUP(intc_irq30_1),
+	SH_PFC_PIN_GROUP(intc_irq31_0),
+	SH_PFC_PIN_GROUP(intc_irq31_1),
 	SH_PFC_PIN_GROUP(mmc0_data1_0),
 	SH_PFC_PIN_GROUP(mmc0_data4_0),
 	SH_PFC_PIN_GROUP(mmc0_data8_0),
@@ -1433,6 +1539,60 @@ static const char * const hdmi_groups[] = {
 	"hdmi",
 };
 
+static const char * const intc_groups[] = {
+	"intc_irq0_0",
+	"intc_irq0_1",
+	"intc_irq1",
+	"intc_irq2_0",
+	"intc_irq2_1",
+	"intc_irq3_0",
+	"intc_irq3_1",
+	"intc_irq4_0",
+	"intc_irq4_1",
+	"intc_irq5",
+	"intc_irq6_0",
+	"intc_irq6_1",
+	"intc_irq7_0",
+	"intc_irq7_1",
+	"intc_irq8_0",
+	"intc_irq8_1",
+	"intc_irq9_0",
+	"intc_irq9_1",
+	"intc_irq10",
+	"intc_irq11",
+	"intc_irq12_0",
+	"intc_irq12_1",
+	"intc_irq13_0",
+	"intc_irq13_1",
+	"intc_irq14_0",
+	"intc_irq14_1",
+	"intc_irq15_0",
+	"intc_irq15_1",
+	"intc_irq16_0",
+	"intc_irq16_1",
+	"intc_irq17",
+	"intc_irq18",
+	"intc_irq19",
+	"intc_irq20",
+	"intc_irq21",
+	"intc_irq22",
+	"intc_irq23",
+	"intc_irq24",
+	"intc_irq25",
+	"intc_irq26_0",
+	"intc_irq26_1",
+	"intc_irq27_0",
+	"intc_irq27_1",
+	"intc_irq28_0",
+	"intc_irq28_1",
+	"intc_irq29_0",
+	"intc_irq29_1",
+	"intc_irq30_0",
+	"intc_irq30_1",
+	"intc_irq31_0",
+	"intc_irq31_1",
+};
+
 static const char * const mmc0_groups[] = {
 	"mmc0_data1_0",
 	"mmc0_data4_0",
@@ -1471,6 +1631,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(fsia),
 	SH_PFC_FUNCTION(fsib),
 	SH_PFC_FUNCTION(hdmi),
+	SH_PFC_FUNCTION(intc),
 	SH_PFC_FUNCTION(mmc0),
 	SH_PFC_FUNCTION(sdhi0),
 	SH_PFC_FUNCTION(sdhi1),
-- 
1.8.2.1

[PATCH 029/130] sh-pfc: sh7372: Add KEYSC pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-sh7372.c | 91 +++++++++++++++++++++++++++++++++++++
 1 file changed, 91 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index def6e2c..50cbff6 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -1241,6 +1241,75 @@ IRQC_PINS_MUX(28, 123, 181);
 IRQC_PINS_MUX(29, 129, 182);
 IRQC_PINS_MUX(30, 130, 183);
 IRQC_PINS_MUX(31, 138, 184);
+/* - KEYSC ------------------------------------------------------------------ */
+static const unsigned int keysc_in04_0_pins[] = {
+	/* KEYIN[0:4] */
+	136, 135, 134, 133, 132,
+};
+static const unsigned int keysc_in04_0_mux[] = {
+	KEYIN0_136_MARK, KEYIN1_135_MARK, KEYIN2_134_MARK, KEYIN3_133_MARK,
+	KEYIN4_MARK,
+};
+static const unsigned int keysc_in04_1_pins[] = {
+	/* KEYIN[0:4] */
+	121, 122, 123, 124, 132,
+};
+static const unsigned int keysc_in04_1_mux[] = {
+	KEYIN0_121_MARK, KEYIN1_122_MARK, KEYIN2_123_MARK, KEYIN3_124_MARK,
+	KEYIN4_MARK,
+};
+static const unsigned int keysc_in5_pins[] = {
+	/* KEYIN5 */
+	131,
+};
+static const unsigned int keysc_in5_mux[] = {
+	KEYIN5_MARK,
+};
+static const unsigned int keysc_in6_pins[] = {
+	/* KEYIN6 */
+	130,
+};
+static const unsigned int keysc_in6_mux[] = {
+	KEYIN6_MARK,
+};
+static const unsigned int keysc_in7_pins[] = {
+	/* KEYIN7 */
+	129,
+};
+static const unsigned int keysc_in7_mux[] = {
+	KEYIN7_MARK,
+};
+static const unsigned int keysc_out4_pins[] = {
+	/* KEYOUT[0:3] */
+	128, 127, 126, 125,
+};
+static const unsigned int keysc_out4_mux[] = {
+	KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+};
+static const unsigned int keysc_out5_pins[] = {
+	/* KEYOUT[0:4] */
+	128, 127, 126, 125, 124,
+};
+static const unsigned int keysc_out5_mux[] = {
+	KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+	KEYOUT4_MARK,
+};
+static const unsigned int keysc_out6_pins[] = {
+	/* KEYOUT[0:5] */
+	128, 127, 126, 125, 124, 123,
+};
+static const unsigned int keysc_out6_mux[] = {
+	KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+	KEYOUT4_MARK, KEYOUT5_MARK,
+};
+static const unsigned int keysc_out8_pins[] = {
+	/* KEYOUT[0:7] */
+	128, 127, 126, 125, 124, 123, 122, 121,
+};
+static const unsigned int keysc_out8_mux[] = {
+	KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+	KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
+};
 /* - MMCIF ------------------------------------------------------------------ */
 static const unsigned int mmc0_data1_0_pins[] = {
 	/* D[0] */
@@ -1467,6 +1536,15 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(intc_irq30_1),
 	SH_PFC_PIN_GROUP(intc_irq31_0),
 	SH_PFC_PIN_GROUP(intc_irq31_1),
+	SH_PFC_PIN_GROUP(keysc_in04_0),
+	SH_PFC_PIN_GROUP(keysc_in04_1),
+	SH_PFC_PIN_GROUP(keysc_in5),
+	SH_PFC_PIN_GROUP(keysc_in6),
+	SH_PFC_PIN_GROUP(keysc_in7),
+	SH_PFC_PIN_GROUP(keysc_out4),
+	SH_PFC_PIN_GROUP(keysc_out5),
+	SH_PFC_PIN_GROUP(keysc_out6),
+	SH_PFC_PIN_GROUP(keysc_out8),
 	SH_PFC_PIN_GROUP(mmc0_data1_0),
 	SH_PFC_PIN_GROUP(mmc0_data4_0),
 	SH_PFC_PIN_GROUP(mmc0_data8_0),
@@ -1593,6 +1671,18 @@ static const char * const intc_groups[] = {
 	"intc_irq31_1",
 };
 
+static const char * const keysc_groups[] = {
+	"keysc_in04_0",
+	"keysc_in04_1",
+	"keysc_in5",
+	"keysc_in6",
+	"keysc_in7",
+	"keysc_out4",
+	"keysc_out5",
+	"keysc_out6",
+	"keysc_out8",
+};
+
 static const char * const mmc0_groups[] = {
 	"mmc0_data1_0",
 	"mmc0_data4_0",
@@ -1632,6 +1722,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(fsib),
 	SH_PFC_FUNCTION(hdmi),
 	SH_PFC_FUNCTION(intc),
+	SH_PFC_FUNCTION(keysc),
 	SH_PFC_FUNCTION(mmc0),
 	SH_PFC_FUNCTION(sdhi0),
 	SH_PFC_FUNCTION(sdhi1),
-- 
1.8.2.1

[PATCH 030/130] sh-pfc: sh7372: Add LCDC pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-sh7372.c | 121 ++++++++++++++++++++++++++++++++++++
 1 file changed, 121 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index 50cbff6..8503747 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -1310,6 +1310,103 @@ static const unsigned int keysc_out8_mux[] = {
 	KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
 	KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
 };
+/* - LCD -------------------------------------------------------------------- */
+static const unsigned int lcd_data8_pins[] = {
+	/* D[0:7] */
+	121, 122, 123, 124, 125, 126, 127, 128,
+};
+static const unsigned int lcd_data8_mux[] = {
+	/* LCDC */
+	LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+	LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+};
+static const unsigned int lcd_data9_pins[] = {
+	/* D[0:8] */
+	121, 122, 123, 124, 125, 126, 127, 128,
+	129,
+	137, 138, 139, 140, 141, 142, 143, 144,
+};
+static const unsigned int lcd_data9_mux[] = {
+	LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+	LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+	LCDD8_MARK,
+};
+static const unsigned int lcd_data12_pins[] = {
+	/* D[0:11] */
+	121, 122, 123, 124, 125, 126, 127, 128,
+	129, 130, 131, 132,
+};
+static const unsigned int lcd_data12_mux[] = {
+	LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+	LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+	LCDD8_MARK, LCDD9_MARK,	LCDD10_MARK, LCDD11_MARK,
+};
+static const unsigned int lcd_data16_pins[] = {
+	/* D[0:15] */
+	121, 122, 123, 124, 125, 126, 127, 128,
+	129, 130, 131, 132, 133, 134, 135, 136,
+};
+static const unsigned int lcd_data16_mux[] = {
+	LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+	LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+	LCDD8_MARK, LCDD9_MARK,	LCDD10_MARK, LCDD11_MARK,
+	LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+};
+static const unsigned int lcd_data18_pins[] = {
+	/* D[0:17] */
+	121, 122, 123, 124, 125, 126, 127, 128,
+	129, 130, 131, 132, 133, 134, 135, 136,
+	137, 138,
+};
+static const unsigned int lcd_data18_mux[] = {
+	LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+	LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+	LCDD8_MARK, LCDD9_MARK,	LCDD10_MARK, LCDD11_MARK,
+	LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+	LCDD16_MARK, LCDD17_MARK,
+};
+static const unsigned int lcd_data24_pins[] = {
+	/* D[0:23] */
+	121, 122, 123, 124, 125, 126, 127, 128,
+	129, 130, 131, 132, 133, 134, 135, 136,
+	137, 138, 139, 140, 141, 142, 143, 144,
+};
+static const unsigned int lcd_data24_mux[] = {
+	LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+	LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+	LCDD8_MARK, LCDD9_MARK,	LCDD10_MARK, LCDD11_MARK,
+	LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+	LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
+	LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
+};
+static const unsigned int lcd_display_pins[] = {
+	/* DON */
+	151,
+};
+static const unsigned int lcd_display_mux[] = {
+	LCDDON_MARK,
+};
+static const unsigned int lcd_lclk_pins[] = {
+	/* LCLK */
+	150,
+};
+static const unsigned int lcd_lclk_mux[] = {
+	LCDLCLK_MARK,
+};
+static const unsigned int lcd_sync_pins[] = {
+	/* VSYN, HSYN, DCK, DISP */
+	146, 145, 147, 149,
+};
+static const unsigned int lcd_sync_mux[] = {
+	LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
+};
+static const unsigned int lcd_sys_pins[] = {
+	/* CS, WR, RD, RS */
+	145, 147, 148, 149,
+};
+static const unsigned int lcd_sys_mux[] = {
+	LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, LCDRS_MARK,
+};
 /* - MMCIF ------------------------------------------------------------------ */
 static const unsigned int mmc0_data1_0_pins[] = {
 	/* D[0] */
@@ -1545,6 +1642,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(keysc_out5),
 	SH_PFC_PIN_GROUP(keysc_out6),
 	SH_PFC_PIN_GROUP(keysc_out8),
+	SH_PFC_PIN_GROUP(lcd_data8),
+	SH_PFC_PIN_GROUP(lcd_data9),
+	SH_PFC_PIN_GROUP(lcd_data12),
+	SH_PFC_PIN_GROUP(lcd_data16),
+	SH_PFC_PIN_GROUP(lcd_data18),
+	SH_PFC_PIN_GROUP(lcd_data24),
+	SH_PFC_PIN_GROUP(lcd_display),
+	SH_PFC_PIN_GROUP(lcd_lclk),
+	SH_PFC_PIN_GROUP(lcd_sync),
+	SH_PFC_PIN_GROUP(lcd_sys),
 	SH_PFC_PIN_GROUP(mmc0_data1_0),
 	SH_PFC_PIN_GROUP(mmc0_data4_0),
 	SH_PFC_PIN_GROUP(mmc0_data8_0),
@@ -1683,6 +1790,19 @@ static const char * const keysc_groups[] = {
 	"keysc_out8",
 };
 
+static const char * const lcd_groups[] = {
+	"lcd_data8",
+	"lcd_data9",
+	"lcd_data12",
+	"lcd_data16",
+	"lcd_data18",
+	"lcd_data24",
+	"lcd_display",
+	"lcd_lclk",
+	"lcd_sync",
+	"lcd_sys",
+};
+
 static const char * const mmc0_groups[] = {
 	"mmc0_data1_0",
 	"mmc0_data4_0",
@@ -1723,6 +1843,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(hdmi),
 	SH_PFC_FUNCTION(intc),
 	SH_PFC_FUNCTION(keysc),
+	SH_PFC_FUNCTION(lcd),
 	SH_PFC_FUNCTION(mmc0),
 	SH_PFC_FUNCTION(sdhi0),
 	SH_PFC_FUNCTION(sdhi1),
-- 
1.8.2.1

[PATCH 031/130] sh-pfc: sh7372: Add SCIF pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-sh7372.c | 197 ++++++++++++++++++++++++++++++++++++
 1 file changed, 197 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index 8503747..46466bb 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -1467,6 +1467,139 @@ static const unsigned int mmc0_ctrl_1_pins[] = {
 static const unsigned int mmc0_ctrl_1_mux[] = {
 	MMCCMD1_MARK, MMCCLK1_MARK,
 };
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+	/* RXD, TXD */
+	153, 152,
+};
+static const unsigned int scifa0_data_mux[] = {
+	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+	/* SCK */
+	156,
+};
+static const unsigned int scifa0_clk_mux[] = {
+	SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+	/* RTS, CTS */
+	157, 158,
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+	SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+	/* RXD, TXD */
+	155, 154,
+};
+static const unsigned int scifa1_data_mux[] = {
+	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+	/* SCK */
+	159,
+};
+static const unsigned int scifa1_clk_mux[] = {
+	SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+	/* RTS, CTS */
+	160, 161,
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+	SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_pins[] = {
+	/* RXD, TXD */
+	97, 96,
+};
+static const unsigned int scifa2_data_mux[] = {
+	SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
+};
+static const unsigned int scifa2_clk_pins[] = {
+	/* SCK */
+	98,
+};
+static const unsigned int scifa2_clk_mux[] = {
+	SCIFA2_SCK1_MARK,
+};
+static const unsigned int scifa2_ctrl_pins[] = {
+	/* RTS, CTS */
+	95, 94,
+};
+static const unsigned int scifa2_ctrl_mux[] = {
+	SCIFA2_RTS1_MARK, SCIFA2_CTS1_MARK,
+};
+/* - SCIFA3 ----------------------------------------------------------------- */
+static const unsigned int scifa3_data_pins[] = {
+	/* RXD, TXD */
+	144, 143,
+};
+static const unsigned int scifa3_data_mux[] = {
+	SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
+};
+static const unsigned int scifa3_clk_pins[] = {
+	/* SCK */
+	142,
+};
+static const unsigned int scifa3_clk_mux[] = {
+	SCIFA3_SCK_MARK,
+};
+static const unsigned int scifa3_ctrl_0_pins[] = {
+	/* RTS, CTS */
+	44, 43,
+};
+static const unsigned int scifa3_ctrl_0_mux[] = {
+	SCIFA3_RTS_44_MARK, SCIFA3_CTS_43_MARK,
+};
+static const unsigned int scifa3_ctrl_1_pins[] = {
+	/* RTS, CTS */
+	141, 140,
+};
+static const unsigned int scifa3_ctrl_1_mux[] = {
+	SCIFA3_RTS_141_MARK, SCIFA3_CTS_140_MARK,
+};
+/* - SCIFA4 ----------------------------------------------------------------- */
+static const unsigned int scifa4_data_pins[] = {
+	/* RXD, TXD */
+	5, 6,
+};
+static const unsigned int scifa4_data_mux[] = {
+	SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
+};
+/* - SCIFA5 ----------------------------------------------------------------- */
+static const unsigned int scifa5_data_pins[] = {
+	/* RXD, TXD */
+	8, 12,
+};
+static const unsigned int scifa5_data_mux[] = {
+	SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
+};
+/* - SCIFB ------------------------------------------------------------------ */
+static const unsigned int scifb_data_pins[] = {
+	/* RXD, TXD */
+	166, 165,
+};
+static const unsigned int scifb_data_mux[] = {
+	SCIFB_RXD_MARK, SCIFB_TXD_MARK,
+};
+static const unsigned int scifb_clk_pins[] = {
+	/* SCK */
+	162,
+};
+static const unsigned int scifb_clk_mux[] = {
+	SCIFB_SCK_MARK,
+};
+static const unsigned int scifb_ctrl_pins[] = {
+	/* RTS, CTS */
+	163, 164,
+};
+static const unsigned int scifb_ctrl_mux[] = {
+	SCIFB_RTS_MARK, SCIFB_CTS_MARK,
+};
 /* - SDHI0 ------------------------------------------------------------------ */
 static const unsigned int sdhi0_data1_pins[] = {
 	/* D0 */
@@ -1660,6 +1793,24 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(mmc0_data4_1),
 	SH_PFC_PIN_GROUP(mmc0_data8_1),
 	SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+	SH_PFC_PIN_GROUP(scifa0_data),
+	SH_PFC_PIN_GROUP(scifa0_clk),
+	SH_PFC_PIN_GROUP(scifa0_ctrl),
+	SH_PFC_PIN_GROUP(scifa1_data),
+	SH_PFC_PIN_GROUP(scifa1_clk),
+	SH_PFC_PIN_GROUP(scifa1_ctrl),
+	SH_PFC_PIN_GROUP(scifa2_data),
+	SH_PFC_PIN_GROUP(scifa2_clk),
+	SH_PFC_PIN_GROUP(scifa2_ctrl),
+	SH_PFC_PIN_GROUP(scifa3_data),
+	SH_PFC_PIN_GROUP(scifa3_clk),
+	SH_PFC_PIN_GROUP(scifa3_ctrl_0),
+	SH_PFC_PIN_GROUP(scifa3_ctrl_1),
+	SH_PFC_PIN_GROUP(scifa4_data),
+	SH_PFC_PIN_GROUP(scifa5_data),
+	SH_PFC_PIN_GROUP(scifb_data),
+	SH_PFC_PIN_GROUP(scifb_clk),
+	SH_PFC_PIN_GROUP(scifb_ctrl),
 	SH_PFC_PIN_GROUP(sdhi0_data1),
 	SH_PFC_PIN_GROUP(sdhi0_data4),
 	SH_PFC_PIN_GROUP(sdhi0_ctrl),
@@ -1814,6 +1965,45 @@ static const char * const mmc0_groups[] = {
 	"mmc0_ctrl_1",
 };
 
+static const char * const scifa0_groups[] = {
+	"scifa0_data",
+	"scifa0_clk",
+	"scifa0_ctrl",
+};
+
+static const char * const scifa1_groups[] = {
+	"scifa1_data",
+	"scifa1_clk",
+	"scifa1_ctrl",
+};
+
+static const char * const scifa2_groups[] = {
+	"scifa2_data",
+	"scifa2_clk",
+	"scifa2_ctrl",
+};
+
+static const char * const scifa3_groups[] = {
+	"scifa3_data",
+	"scifa3_clk",
+	"scifa3_ctrl_0",
+	"scifa3_ctrl_1",
+};
+
+static const char * const scifa4_groups[] = {
+	"scifa4_data",
+};
+
+static const char * const scifa5_groups[] = {
+	"scifa5_data",
+};
+
+static const char * const scifb_groups[] = {
+	"scifb_data",
+	"scifb_clk",
+	"scifb_ctrl",
+};
+
 static const char * const sdhi0_groups[] = {
 	"sdhi0_data1",
 	"sdhi0_data4",
@@ -1845,6 +2035,13 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(keysc),
 	SH_PFC_FUNCTION(lcd),
 	SH_PFC_FUNCTION(mmc0),
+	SH_PFC_FUNCTION(scifa0),
+	SH_PFC_FUNCTION(scifa1),
+	SH_PFC_FUNCTION(scifa2),
+	SH_PFC_FUNCTION(scifa3),
+	SH_PFC_FUNCTION(scifa4),
+	SH_PFC_FUNCTION(scifa5),
+	SH_PFC_FUNCTION(scifb),
 	SH_PFC_FUNCTION(sdhi0),
 	SH_PFC_FUNCTION(sdhi1),
 	SH_PFC_FUNCTION(sdhi2),
-- 
1.8.2.1

[PATCH 032/130] sh-pfc: sh7372: Add USB pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-sh7372.c | 82 +++++++++++++++++++++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index 46466bb..4dc2ccb 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -1680,6 +1680,64 @@ static const unsigned int sdhi2_ctrl_pins[] = {
 static const unsigned int sdhi2_ctrl_mux[] = {
 	SDHICMD2_MARK, SDHICLK2_MARK,
 };
+/* - USB0 ------------------------------------------------------------------- */
+static const unsigned int usb0_vbus_pins[] = {
+	/* VBUS */
+	167,
+};
+static const unsigned int usb0_vbus_mux[] = {
+	VBUS0_0_MARK,
+};
+static const unsigned int usb0_otg_id_pins[] = {
+	/* IDIN */
+	113,
+};
+static const unsigned int usb0_otg_id_mux[] = {
+	IDIN_0_MARK,
+};
+static const unsigned int usb0_otg_ctrl_pins[] = {
+	/* PWEN, EXTLP, OVCN, OVCN2 */
+	116, 114, 117, 115,
+};
+static const unsigned int usb0_otg_ctrl_mux[] = {
+	PWEN_0_MARK, EXTLP_0_MARK, OVCN_0_MARK, OVCN2_0_MARK,
+};
+/* - USB1 ------------------------------------------------------------------- */
+static const unsigned int usb1_vbus_pins[] = {
+	/* VBUS */
+	168,
+};
+static const unsigned int usb1_vbus_mux[] = {
+	VBUS0_1_MARK,
+};
+static const unsigned int usb1_otg_id_0_pins[] = {
+	/* IDIN */
+	113,
+};
+static const unsigned int usb1_otg_id_0_mux[] = {
+	IDIN_1_113_MARK,
+};
+static const unsigned int usb1_otg_id_1_pins[] = {
+	/* IDIN */
+	18,
+};
+static const unsigned int usb1_otg_id_1_mux[] = {
+	IDIN_1_18_MARK,
+};
+static const unsigned int usb1_otg_ctrl_0_pins[] = {
+	/* PWEN, EXTLP, OVCN, OVCN2 */
+	115, 116, 114, 117, 113,
+};
+static const unsigned int usb1_otg_ctrl_0_mux[] = {
+	PWEN_1_115_MARK, EXTLP_1_MARK, OVCN_1_114_MARK, OVCN2_1_MARK,
+};
+static const unsigned int usb1_otg_ctrl_1_pins[] = {
+	/* PWEN, EXTLP, OVCN, OVCN2 */
+	138, 116, 162, 117, 18,
+};
+static const unsigned int usb1_otg_ctrl_1_mux[] = {
+	PWEN_1_138_MARK, EXTLP_1_MARK, OVCN_1_162_MARK, OVCN2_1_MARK,
+};
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(bsc_data8),
@@ -1822,6 +1880,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(sdhi2_data1),
 	SH_PFC_PIN_GROUP(sdhi2_data4),
 	SH_PFC_PIN_GROUP(sdhi2_ctrl),
+	SH_PFC_PIN_GROUP(usb0_vbus),
+	SH_PFC_PIN_GROUP(usb0_otg_id),
+	SH_PFC_PIN_GROUP(usb0_otg_ctrl),
+	SH_PFC_PIN_GROUP(usb1_vbus),
+	SH_PFC_PIN_GROUP(usb1_otg_id_0),
+	SH_PFC_PIN_GROUP(usb1_otg_id_1),
+	SH_PFC_PIN_GROUP(usb1_otg_ctrl_0),
+	SH_PFC_PIN_GROUP(usb1_otg_ctrl_1),
 };
 
 static const char * const bsc_groups[] = {
@@ -2024,6 +2090,20 @@ static const char * const sdhi2_groups[] = {
 	"sdhi2_ctrl",
 };
 
+static const char * const usb0_groups[] = {
+	"usb0_vbus",
+	"usb0_otg_id",
+	"usb0_otg_ctrl",
+};
+
+static const char * const usb1_groups[] = {
+	"usb1_vbus",
+	"usb1_otg_id_0",
+	"usb1_otg_id_1",
+	"usb1_otg_ctrl_0",
+	"usb1_otg_ctrl_1",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(bsc),
 	SH_PFC_FUNCTION(ceu),
@@ -2045,6 +2125,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(sdhi0),
 	SH_PFC_FUNCTION(sdhi1),
 	SH_PFC_FUNCTION(sdhi2),
+	SH_PFC_FUNCTION(usb0),
+	SH_PFC_FUNCTION(usb1),
 };
 
 #define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-- 
1.8.2.1

[PATCH 033/130] ARM: shmobile: mackerel: Register pinctrl mapping for the ADXL34X

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based ADXL34X pinmux configuration by a pinctrl
mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-mackerel.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index fa3407d..d40d9da 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1309,6 +1309,9 @@ static struct i2c_board_info i2c1_devices[] = {
 };
 
 static const struct pinctrl_map mackerel_pinctrl_map[] = {
+	/* ADXL34X */
+	PIN_MAP_MUX_GROUP_DEFAULT("1-0053", "pfc-sh7372",
+				  "intc_irq21", "intc"),
 	/* SDHI0 */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
 				  "sdhi0_data4", "sdhi0"),
@@ -1460,8 +1463,7 @@ static void __init mackerel_init(void)
 	gpio_request(GPIO_FN_IRQ7_40,	NULL);
 	irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
 
-	/* enable Accelerometer */
-	gpio_request(GPIO_FN_IRQ21,	NULL);
+	/* Accelerometer */
 	irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
 
 	/* SDHI0 PORT172 card-detect IRQ26 */
-- 
1.8.2.1

[PATCH 034/130] ARM: shmobile: mackerel: Register pinctrl mapping for CEU

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based CEU pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-mackerel.c | 24 +++++++++---------------
 1 file changed, 9 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index d40d9da..fdd7e3f 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1312,6 +1312,15 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
 	/* ADXL34X */
 	PIN_MAP_MUX_GROUP_DEFAULT("1-0053", "pfc-sh7372",
 				  "intc_irq21", "intc"),
+	/* CEU */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+				  "ceu_data_0_7", "ceu"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+				  "ceu_clk_0", "ceu"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+				  "ceu_sync", "ceu"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+				  "ceu_field", "ceu"),
 	/* SDHI0 */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
 				  "sdhi0_data4", "sdhi0"),
@@ -1497,21 +1506,6 @@ static void __init mackerel_init(void)
 	gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
 	gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
 
-	/* CEU */
-	gpio_request(GPIO_FN_VIO_CLK, NULL);
-	gpio_request(GPIO_FN_VIO_VD, NULL);
-	gpio_request(GPIO_FN_VIO_HD, NULL);
-	gpio_request(GPIO_FN_VIO_FIELD, NULL);
-	gpio_request(GPIO_FN_VIO_CKO, NULL);
-	gpio_request(GPIO_FN_VIO_D7, NULL);
-	gpio_request(GPIO_FN_VIO_D6, NULL);
-	gpio_request(GPIO_FN_VIO_D5, NULL);
-	gpio_request(GPIO_FN_VIO_D4, NULL);
-	gpio_request(GPIO_FN_VIO_D3, NULL);
-	gpio_request(GPIO_FN_VIO_D2, NULL);
-	gpio_request(GPIO_FN_VIO_D1, NULL);
-	gpio_request(GPIO_FN_VIO_D0, NULL);
-
 	/* HDMI */
 	gpio_request(GPIO_FN_HDMI_HPD, NULL);
 	gpio_request(GPIO_FN_HDMI_CEC, NULL);
-- 
1.8.2.1

[PATCH 035/130] ARM: shmobile: mackerel: Register pinctrl mapping for FLCTL

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based FLCTL pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-mackerel.c | 31 +++++++------------------------
 1 file changed, 7 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index fdd7e3f..955fefd 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1321,6 +1321,13 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
 				  "ceu_sync", "ceu"),
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
 				  "ceu_field", "ceu"),
+	/* FLCTL */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
+				  "flctl_data", "flctl"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
+				  "flctl_ce0", "flctl"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
+				  "flctl_ctrl", "flctl"),
 	/* SDHI0 */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
 				  "sdhi0_data4", "sdhi0"),
@@ -1478,30 +1485,6 @@ static void __init mackerel_init(void)
 	/* SDHI0 PORT172 card-detect IRQ26 */
 	gpio_request(GPIO_FN_IRQ26_172, NULL);
 
-	/* FLCTL */
-	gpio_request(GPIO_FN_D0_NAF0, NULL);
-	gpio_request(GPIO_FN_D1_NAF1, NULL);
-	gpio_request(GPIO_FN_D2_NAF2, NULL);
-	gpio_request(GPIO_FN_D3_NAF3, NULL);
-	gpio_request(GPIO_FN_D4_NAF4, NULL);
-	gpio_request(GPIO_FN_D5_NAF5, NULL);
-	gpio_request(GPIO_FN_D6_NAF6, NULL);
-	gpio_request(GPIO_FN_D7_NAF7, NULL);
-	gpio_request(GPIO_FN_D8_NAF8, NULL);
-	gpio_request(GPIO_FN_D9_NAF9, NULL);
-	gpio_request(GPIO_FN_D10_NAF10, NULL);
-	gpio_request(GPIO_FN_D11_NAF11, NULL);
-	gpio_request(GPIO_FN_D12_NAF12, NULL);
-	gpio_request(GPIO_FN_D13_NAF13, NULL);
-	gpio_request(GPIO_FN_D14_NAF14, NULL);
-	gpio_request(GPIO_FN_D15_NAF15, NULL);
-	gpio_request(GPIO_FN_FCE0, NULL);
-	gpio_request(GPIO_FN_WE0_FWE, NULL);
-	gpio_request(GPIO_FN_FRB, NULL);
-	gpio_request(GPIO_FN_A4_FOE, NULL);
-	gpio_request(GPIO_FN_A5_FCDE, NULL);
-	gpio_request(GPIO_FN_RD_FSC, NULL);
-
 	/* enable GPS module (GT-720F) */
 	gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
 	gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
-- 
1.8.2.1

[PATCH 036/130] ARM: shmobile: mackerel: Register pinctrl mapping for FSI

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based FSI pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-mackerel.c | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 955fefd..f2e8740 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1328,6 +1328,16 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
 				  "flctl_ce0", "flctl"),
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
 				  "flctl_ctrl", "flctl"),
+	/* FSIA (AK4643) */
+	PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+				  "fsia_sclk_in", "fsia"),
+	PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+				  "fsia_data_in", "fsia"),
+	PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+				  "fsia_data_out", "fsia"),
+	/* FSIB (HDMI) */
+	PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372",
+				  "fsib_mclk_in", "fsib"),
 	/* SDHI0 */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
 				  "sdhi0_data4", "sdhi0"),
@@ -1446,11 +1456,7 @@ static void __init mackerel_init(void)
 	gpio_request_pulldown(GPIO_PORT167CR); /* VBUS0_1 pull down */
 	gpio_request(GPIO_FN_IDIN_1_113, NULL);
 
-	/* enable FSI2 port A (ak4643) */
-	gpio_request(GPIO_FN_FSIAIBT,	NULL);
-	gpio_request(GPIO_FN_FSIAILR,	NULL);
-	gpio_request(GPIO_FN_FSIAISLD,	NULL);
-	gpio_request(GPIO_FN_FSIAOSLD,	NULL);
+	/* FSI2 port A (ak4643) */
 	gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
 
 	gpio_request(9,  NULL);
@@ -1460,8 +1466,7 @@ static void __init mackerel_init(void)
 
 	intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */
 
-	/* setup FSI2 port B (HDMI) */
-	gpio_request(GPIO_FN_FSIBCK, NULL);
+	/* FSI2 port B (HDMI) */
 	__raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
 
 	/* set SPU2 clock to 119.6 MHz */
-- 
1.8.2.1

[PATCH 037/130] ARM: shmobile: mackerel: Register pinctrl mapping for HDMI

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based HDMI pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-mackerel.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index f2e8740..e5bcd18 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1338,6 +1338,9 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
 	/* FSIB (HDMI) */
 	PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372",
 				  "fsib_mclk_in", "fsib"),
+	/* HDMI */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372",
+				  "hdmi", "hdmi"),
 	/* SDHI0 */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
 				  "sdhi0_data4", "sdhi0"),
@@ -1494,10 +1497,6 @@ static void __init mackerel_init(void)
 	gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
 	gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
 
-	/* HDMI */
-	gpio_request(GPIO_FN_HDMI_HPD, NULL);
-	gpio_request(GPIO_FN_HDMI_CEC, NULL);
-
 	/* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
 	srcr4 = __raw_readl(SRCR4);
 	__raw_writel(srcr4 | (1 << 13), SRCR4);
-- 
1.8.2.1

[PATCH 038/130] ARM: shmobile: mackerel: Register pinctrl mapping for LCD

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based LCD pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-mackerel.c | 33 +++++----------------------------
 1 file changed, 5 insertions(+), 28 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index e5bcd18..07eeb55 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1341,6 +1341,11 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
 	/* HDMI */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372",
 				  "hdmi", "hdmi"),
+	/* LCDC */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+				  "lcd_data24", "lcd"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+				  "lcd_sync", "lcd"),
 	/* SDHI0 */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
 				  "sdhi0_data4", "sdhi0"),
@@ -1417,34 +1422,6 @@ static void __init mackerel_init(void)
 	gpio_request(GPIO_FN_CS5A,	NULL);
 	gpio_request(GPIO_FN_IRQ6_39,	NULL);
 
-	/* LCDC */
-	gpio_request(GPIO_FN_LCDD23,   NULL);
-	gpio_request(GPIO_FN_LCDD22,   NULL);
-	gpio_request(GPIO_FN_LCDD21,   NULL);
-	gpio_request(GPIO_FN_LCDD20,   NULL);
-	gpio_request(GPIO_FN_LCDD19,   NULL);
-	gpio_request(GPIO_FN_LCDD18,   NULL);
-	gpio_request(GPIO_FN_LCDD17,   NULL);
-	gpio_request(GPIO_FN_LCDD16,   NULL);
-	gpio_request(GPIO_FN_LCDD15,   NULL);
-	gpio_request(GPIO_FN_LCDD14,   NULL);
-	gpio_request(GPIO_FN_LCDD13,   NULL);
-	gpio_request(GPIO_FN_LCDD12,   NULL);
-	gpio_request(GPIO_FN_LCDD11,   NULL);
-	gpio_request(GPIO_FN_LCDD10,   NULL);
-	gpio_request(GPIO_FN_LCDD9,    NULL);
-	gpio_request(GPIO_FN_LCDD8,    NULL);
-	gpio_request(GPIO_FN_LCDD7,    NULL);
-	gpio_request(GPIO_FN_LCDD6,    NULL);
-	gpio_request(GPIO_FN_LCDD5,    NULL);
-	gpio_request(GPIO_FN_LCDD4,    NULL);
-	gpio_request(GPIO_FN_LCDD3,    NULL);
-	gpio_request(GPIO_FN_LCDD2,    NULL);
-	gpio_request(GPIO_FN_LCDD1,    NULL);
-	gpio_request(GPIO_FN_LCDD0,    NULL);
-	gpio_request(GPIO_FN_LCDDISP,  NULL);
-	gpio_request(GPIO_FN_LCDDCK,   NULL);
-
 	/* backlight, off by default */
 	gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL);
 
-- 
1.8.2.1

[PATCH 039/130] ARM: shmobile: mackerel: Register pinctrl mapping for SCIF

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based SCIF pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-mackerel.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 07eeb55..bd3666b 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1346,6 +1346,12 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
 				  "lcd_data24", "lcd"),
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
 				  "lcd_sync", "lcd"),
+	/* SCIFA0 */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372",
+				  "scifa0_data", "scifa0"),
+	/* SCIFA2 (GT-720F GPS module) */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh7372",
+				  "scifa2_data", "scifa2"),
 	/* SDHI0 */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
 				  "sdhi0_data4", "sdhi0"),
@@ -1414,10 +1420,6 @@ static void __init mackerel_init(void)
 				  ARRAY_SIZE(mackerel_pinctrl_map));
 	sh7372_pinmux_init();
 
-	/* enable SCIFA0 */
-	gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
-	gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
-
 	/* enable SMSC911X */
 	gpio_request(GPIO_FN_CS5A,	NULL);
 	gpio_request(GPIO_FN_IRQ6_39,	NULL);
@@ -1470,10 +1472,6 @@ static void __init mackerel_init(void)
 	/* SDHI0 PORT172 card-detect IRQ26 */
 	gpio_request(GPIO_FN_IRQ26_172, NULL);
 
-	/* enable GPS module (GT-720F) */
-	gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
-	gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
-
 	/* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
 	srcr4 = __raw_readl(SRCR4);
 	__raw_writel(srcr4 | (1 << 13), SRCR4);
-- 
1.8.2.1

[PATCH 040/130] ARM: shmobile: mackerel: Register IRQ pinctrl mapping for SDHI0

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based SDHI0 IRQ pinmux configuration by a pinctrl
mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-mackerel.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index bd3666b..4be236d 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1359,6 +1359,8 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
 				  "sdhi0_ctrl", "sdhi0"),
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
 				  "sdhi0_wp", "sdhi0"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+				  "intc_irq26_1", "intc"),
 	/* SDHI1 */
 #if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
@@ -1469,9 +1471,6 @@ static void __init mackerel_init(void)
 	/* Accelerometer */
 	irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
 
-	/* SDHI0 PORT172 card-detect IRQ26 */
-	gpio_request(GPIO_FN_IRQ26_172, NULL);
-
 	/* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
 	srcr4 = __raw_readl(SRCR4);
 	__raw_writel(srcr4 | (1 << 13), SRCR4);
-- 
1.8.2.1

[PATCH 041/130] ARM: shmobile: mackerel: Register pinctrl mapping for SMSC911x

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based SMSC911x pinmux configuration by a pinctrl
mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-mackerel.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 4be236d..49b66a8 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1379,6 +1379,11 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
 				  "sdhi2_data4", "sdhi2"),
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
 				  "sdhi2_ctrl", "sdhi2"),
+	/* SMSC911X */
+	PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+				  "bsc_cs5a", "bsc"),
+	PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+				  "intc_irq6_0", "intc"),
 };
 
 #define GPIO_PORT9CR	IOMEM(0xE6051009)
@@ -1422,10 +1427,6 @@ static void __init mackerel_init(void)
 				  ARRAY_SIZE(mackerel_pinctrl_map));
 	sh7372_pinmux_init();
 
-	/* enable SMSC911X */
-	gpio_request(GPIO_FN_CS5A,	NULL);
-	gpio_request(GPIO_FN_IRQ6_39,	NULL);
-
 	/* backlight, off by default */
 	gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL);
 
-- 
1.8.2.1

[PATCH 042/130] ARM: shmobile: mackerel: Register pinctrl mapping for ST1232

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based ST1232 pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-mackerel.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 49b66a8..8350635 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1384,6 +1384,9 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
 				  "bsc_cs5a", "bsc"),
 	PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
 				  "intc_irq6_0", "intc"),
+	/* ST1232 */
+	PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-sh7372",
+				  "intc_irq7_0", "intc"),
 };
 
 #define GPIO_PORT9CR	IOMEM(0xE6051009)
@@ -1465,8 +1468,7 @@ static void __init mackerel_init(void)
 	gpio_request(GPIO_FN_IRQ9_42,	NULL);
 	irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
 
-	/* enable Touchscreen */
-	gpio_request(GPIO_FN_IRQ7_40,	NULL);
+	/* Touchscreen */
 	irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
 
 	/* Accelerometer */
-- 
1.8.2.1

[PATCH 043/130] ARM: shmobile: mackerel: Register pinctrl mapping for TCA6416

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based TCA6416 pinmux configuration by a pinctrl
mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-mackerel.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 8350635..397e73c 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1387,6 +1387,9 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
 	/* ST1232 */
 	PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-sh7372",
 				  "intc_irq7_0", "intc"),
+	/* TCA6416 */
+	PIN_MAP_MUX_GROUP_DEFAULT("0-0020", "pfc-sh7372",
+				  "intc_irq9_0", "intc"),
 };
 
 #define GPIO_PORT9CR	IOMEM(0xE6051009)
@@ -1464,8 +1467,7 @@ static void __init mackerel_init(void)
 		clk_put(clk);
 	}
 
-	/* enable Keypad */
-	gpio_request(GPIO_FN_IRQ9_42,	NULL);
+	/* Keypad */
 	irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
 
 	/* Touchscreen */
-- 
1.8.2.1

[PATCH 044/130] ARM: shmobile: mackerel: Register pinctrl mapping for USBHS

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based USBHS pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-mackerel.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 397e73c..85f51a8 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1390,6 +1390,14 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
 	/* TCA6416 */
 	PIN_MAP_MUX_GROUP_DEFAULT("0-0020", "pfc-sh7372",
 				  "intc_irq9_0", "intc"),
+	/* USBHS0 */
+	PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372",
+				  "usb0_vbus", "usb0"),
+	/* USBHS1 */
+	PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
+				  "usb1_vbus", "usb1"),
+	PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
+				  "usb1_otg_id_0", "usb1"),
 };
 
 #define GPIO_PORT9CR	IOMEM(0xE6051009)
@@ -1439,13 +1447,10 @@ static void __init mackerel_init(void)
 	gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
 
 	/* USBHS0 */
-	gpio_request(GPIO_FN_VBUS0_0, NULL);
 	gpio_request_pulldown(GPIO_PORT168CR); /* VBUS0_0 pull down */
 
 	/* USBHS1 */
-	gpio_request(GPIO_FN_VBUS0_1, NULL);
 	gpio_request_pulldown(GPIO_PORT167CR); /* VBUS0_1 pull down */
-	gpio_request(GPIO_FN_IDIN_1_113, NULL);
 
 	/* FSI2 port A (ak4643) */
 	gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
-- 
1.8.2.1

[PATCH 045/130] ARM: shmobile: ap4evb: Register pinctrl mapping for CEU

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based CEU pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-ap4evb.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 45f78ca..f42e731 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1086,6 +1086,9 @@ static struct i2c_board_info i2c1_devices[] = {
 
 
 static const struct pinctrl_map ap4evb_pinctrl_map[] = {
+	/* CEU */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+				  "ceu_clk_0", "ceu"),
 	/* MMCIF */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
 				  "mmc0_data8_0", "mmc0"),
@@ -1288,8 +1291,6 @@ static void __init ap4evb_init(void)
 	 */
 
 	/* MIPI-CSI stuff */
-	gpio_request(GPIO_FN_VIO_CKO, NULL);
-
 	clk = clk_get(NULL, "vck1_clk");
 	if (!IS_ERR(clk)) {
 		clk_set_rate(clk, clk_round_rate(clk, 13000000));
-- 
1.8.2.1

[PATCH 046/130] ARM: shmobile: ap4evb: Register pinctrl mapping for FSI

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based FSI pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-ap4evb.c | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index f42e731..2f03685 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1089,6 +1089,16 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = {
 	/* CEU */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
 				  "ceu_clk_0", "ceu"),
+	/* FSIA (AK4643) */
+	PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+				  "fsia_sclk_in", "fsia"),
+	PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+				  "fsia_data_in", "fsia"),
+	PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+				  "fsia_data_out", "fsia"),
+	/* FSIB (HDMI) */
+	PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372",
+				  "fsib_mclk_in", "fsib"),
 	/* MMCIF */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
 				  "mmc0_data8_0", "mmc0"),
@@ -1165,11 +1175,7 @@ static void __init ap4evb_init(void)
 	/* setup USB phy */
 	__raw_writew(0x8a0a, IOMEM(0xE6058130));	/* USBCR4 */
 
-	/* enable FSI2 port A (ak4643) */
-	gpio_request(GPIO_FN_FSIAIBT,	NULL);
-	gpio_request(GPIO_FN_FSIAILR,	NULL);
-	gpio_request(GPIO_FN_FSIAISLD,	NULL);
-	gpio_request(GPIO_FN_FSIAOSLD,	NULL);
+	/* FSI2 port A (ak4643) */
 	gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
 
 	gpio_request(9, NULL);
@@ -1180,8 +1186,7 @@ static void __init ap4evb_init(void)
 	/* card detect pin for MMC slot (CN7) */
 	gpio_request_one(41, GPIOF_IN, NULL);
 
-	/* setup FSI2 port B (HDMI) */
-	gpio_request(GPIO_FN_FSIBCK, NULL);
+	/* FSI2 port B (HDMI) */
 	__raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
 
 	/* set SPU2 clock to 119.6 MHz */
-- 
1.8.2.1

[PATCH 047/130] ARM: shmobile: ap4evb: Register pinctrl mapping for HDMI

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based HDMI pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-ap4evb.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 2f03685..2dfa235 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1099,6 +1099,9 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = {
 	/* FSIB (HDMI) */
 	PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372",
 				  "fsib_mclk_in", "fsib"),
+	/* HDMI */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372",
+				  "hdmi", "hdmi"),
 	/* MMCIF */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
 				  "mmc0_data8_0", "mmc0"),
@@ -1305,10 +1308,6 @@ static void __init ap4evb_init(void)
 
 	sh7372_add_standard_devices();
 
-	/* HDMI */
-	gpio_request(GPIO_FN_HDMI_HPD, NULL);
-	gpio_request(GPIO_FN_HDMI_CEC, NULL);
-
 	/* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
 #define SRCR4 IOMEM(0xe61580bc)
 	srcr4 = __raw_readl(SRCR4);
-- 
1.8.2.1

[PATCH 048/130] ARM: shmobile: ap4evb: Register pinctrl mapping for KEYSC

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based KEYSC pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-ap4evb.c | 17 +++++------------
 1 file changed, 5 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 2dfa235..c7a9efc 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1102,6 +1102,11 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = {
 	/* HDMI */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372",
 				  "hdmi", "hdmi"),
+	/* KEYSC */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372",
+				  "keysc_in04_0", "keysc"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372",
+				  "keysc_out5", "keysc"),
 	/* MMCIF */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
 				  "mmc0_data8_0", "mmc0"),
@@ -1219,18 +1224,6 @@ static void __init ap4evb_init(void)
 	 * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON.
 	 */
 
-	/* enable KEYSC */
-	gpio_request(GPIO_FN_KEYOUT0, NULL);
-	gpio_request(GPIO_FN_KEYOUT1, NULL);
-	gpio_request(GPIO_FN_KEYOUT2, NULL);
-	gpio_request(GPIO_FN_KEYOUT3, NULL);
-	gpio_request(GPIO_FN_KEYOUT4, NULL);
-	gpio_request(GPIO_FN_KEYIN0_136, NULL);
-	gpio_request(GPIO_FN_KEYIN1_135, NULL);
-	gpio_request(GPIO_FN_KEYIN2_134, NULL);
-	gpio_request(GPIO_FN_KEYIN3_133, NULL);
-	gpio_request(GPIO_FN_KEYIN4,     NULL);
-
 	/* enable TouchScreen */
 	irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
 
-- 
1.8.2.1

[PATCH 049/130] ARM: shmobile: ap4evb: Register pinctrl mapping for LCD

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based LCD pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-ap4evb.c | 29 +++++++----------------------
 1 file changed, 7 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index c7a9efc..c6e1e44 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1107,6 +1107,13 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = {
 				  "keysc_in04_0", "keysc"),
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372",
 				  "keysc_out5", "keysc"),
+#ifndef CONFIG_AP4EVB_QHD
+	/* LCDC */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+				  "lcd_data18", "lcd"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+				  "lcd_sync", "lcd"),
+#endif
 	/* MMCIF */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
 				  "mmc0_data8_0", "mmc0"),
@@ -1245,28 +1252,6 @@ static void __init ap4evb_init(void)
 	 * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and
 	 * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF.
 	 */
-
-	gpio_request(GPIO_FN_LCDD17,   NULL);
-	gpio_request(GPIO_FN_LCDD16,   NULL);
-	gpio_request(GPIO_FN_LCDD15,   NULL);
-	gpio_request(GPIO_FN_LCDD14,   NULL);
-	gpio_request(GPIO_FN_LCDD13,   NULL);
-	gpio_request(GPIO_FN_LCDD12,   NULL);
-	gpio_request(GPIO_FN_LCDD11,   NULL);
-	gpio_request(GPIO_FN_LCDD10,   NULL);
-	gpio_request(GPIO_FN_LCDD9,    NULL);
-	gpio_request(GPIO_FN_LCDD8,    NULL);
-	gpio_request(GPIO_FN_LCDD7,    NULL);
-	gpio_request(GPIO_FN_LCDD6,    NULL);
-	gpio_request(GPIO_FN_LCDD5,    NULL);
-	gpio_request(GPIO_FN_LCDD4,    NULL);
-	gpio_request(GPIO_FN_LCDD3,    NULL);
-	gpio_request(GPIO_FN_LCDD2,    NULL);
-	gpio_request(GPIO_FN_LCDD1,    NULL);
-	gpio_request(GPIO_FN_LCDD0,    NULL);
-	gpio_request(GPIO_FN_LCDDISP,  NULL);
-	gpio_request(GPIO_FN_LCDDCK,   NULL);
-
 	gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
 	gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
 
-- 
1.8.2.1

[PATCH 050/130] ARM: shmobile: ap4evb: Register pinctrl mapping for SCIF

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based SCIF pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-ap4evb.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index c6e1e44..3163983 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1119,6 +1119,9 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = {
 				  "mmc0_data8_0", "mmc0"),
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
 				  "mmc0_ctrl_0", "mmc0"),
+	/* SCIFA0 */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372",
+				  "scifa0_data", "scifa0"),
 	/* SDHI0 */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
 				  "sdhi0_data4", "sdhi0"),
@@ -1165,10 +1168,6 @@ static void __init ap4evb_init(void)
 				  ARRAY_SIZE(ap4evb_pinctrl_map));
 	sh7372_pinmux_init();
 
-	/* enable SCIFA0 */
-	gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
-	gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
-
 	/* enable SMSC911X */
 	gpio_request(GPIO_FN_CS5A,	NULL);
 	gpio_request(GPIO_FN_IRQ6_39,	NULL);
-- 
1.8.2.1

[PATCH 051/130] ARM: shmobile: ap4evb: Register pinctrl mapping for SMSC911x

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based SMSC911x pinmux configuration by a pinctrl
mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-ap4evb.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 3163983..9ee8bcd 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1136,6 +1136,11 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = {
 				  "sdhi1_data4", "sdhi1"),
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
 				  "sdhi1_ctrl", "sdhi1"),
+	/* SMSC911X */
+	PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+				  "bsc_cs5a", "bsc"),
+	PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+				  "intc_irq6_0", "intc"),
 };
 
 #define GPIO_PORT9CR	IOMEM(0xE6051009)
@@ -1168,10 +1173,6 @@ static void __init ap4evb_init(void)
 				  ARRAY_SIZE(ap4evb_pinctrl_map));
 	sh7372_pinmux_init();
 
-	/* enable SMSC911X */
-	gpio_request(GPIO_FN_CS5A,	NULL);
-	gpio_request(GPIO_FN_IRQ6_39,	NULL);
-
 	/* enable Debug switch (S6) */
 	gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL);
 	gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL);
-- 
1.8.2.1

[PATCH 052/130] ARM: shmobile: ap4evb: Simplify tsc2007 pen state read function

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The pen state is retrieved by reading the state of a pin used as an IRQ.
There's no need to reconfigure the pin as a pure GPIO, as the IRQ pin
state can be read.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-ap4evb.c | 13 ++-----------
 1 file changed, 2 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 9ee8bcd..0109bb3 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1037,22 +1037,13 @@ out:
 #define IRQ7	evt2irq(0x02e0) /* IRQ7A */
 static int ts_get_pendown_state(void)
 {
-	int val;
-
-	gpio_free(GPIO_TSC_IRQ);
-
-	gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL);
-
-	val = gpio_get_value(GPIO_TSC_PORT);
-
-	gpio_request(GPIO_TSC_IRQ, NULL);
-
-	return !val;
+	return !gpio_get_value(GPIO_TSC_PORT);
 }
 
 static int ts_init(void)
 {
 	gpio_request(GPIO_TSC_IRQ, NULL);
+	gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL);
 
 	return 0;
 }
-- 
1.8.2.1

[PATCH 053/130] ARM: shmobile: ap4evb: Register pinctrl mapping for TSC2007

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based TSC2007 pinmux configuration by a pinctrl
mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-ap4evb.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 0109bb3..152a5f7 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1026,10 +1026,8 @@ out:
 
 /* TouchScreen */
 #ifdef CONFIG_AP4EVB_QHD
-# define GPIO_TSC_IRQ	GPIO_FN_IRQ28_123
 # define GPIO_TSC_PORT	123
 #else /* WVGA */
-# define GPIO_TSC_IRQ	GPIO_FN_IRQ7_40
 # define GPIO_TSC_PORT	40
 #endif
 
@@ -1042,7 +1040,6 @@ static int ts_get_pendown_state(void)
 
 static int ts_init(void)
 {
-	gpio_request(GPIO_TSC_IRQ, NULL);
 	gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL);
 
 	return 0;
@@ -1132,6 +1129,14 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = {
 				  "bsc_cs5a", "bsc"),
 	PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
 				  "intc_irq6_0", "intc"),
+	/* TSC2007 */
+#ifdef CONFIG_AP4EVB_QHD
+	PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372",
+				  "intc_irq28_0", "intc"),
+#else /* WVGA */
+	PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372",
+				  "intc_irq7_0", "intc"),
+#endif
 };
 
 #define GPIO_PORT9CR	IOMEM(0xE6051009)
-- 
1.8.2.1

[PATCH 054/130] ARM: shmobile: ap4evb: Register pinctrl mapping for USBHS

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based USBHS pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-ap4evb.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 152a5f7..297bf5e 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1137,6 +1137,13 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = {
 	PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372",
 				  "intc_irq7_0", "intc"),
 #endif
+	/* USBHS1 */
+	PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372",
+				  "usb1_vbus", "usb1"),
+	PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372",
+				  "usb1_otg_id_0", "usb1"),
+	PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372",
+				  "usb1_otg_ctrl_0", "usb1"),
 };
 
 #define GPIO_PORT9CR	IOMEM(0xE6051009)
@@ -1175,14 +1182,6 @@ static void __init ap4evb_init(void)
 	gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL);
 	gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL);
 
-	/* USB enable */
-	gpio_request(GPIO_FN_VBUS0_1,    NULL);
-	gpio_request(GPIO_FN_IDIN_1_18,  NULL);
-	gpio_request(GPIO_FN_PWEN_1_115, NULL);
-	gpio_request(GPIO_FN_OVCN_1_114, NULL);
-	gpio_request(GPIO_FN_EXTLP_1,    NULL);
-	gpio_request(GPIO_FN_OVCN2_1,    NULL);
-
 	/* setup USB phy */
 	__raw_writew(0x8a0a, IOMEM(0xE6058130));	/* USBCR4 */
 
-- 
1.8.2.1

[PATCH 055/130] sh-pfc: sh7372: Replace GPIO_PORTx enum with GPIO port numbers

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The PFC GPIO API implementation moved to using port numbers. Replace all
GPIO_PORTx enum usage with the corresponding port number. The GPIO_PORTx
enum values are identical to the port number on this platform.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-sh7372.c | 71 ++++++++++++++++++++-----------------
 1 file changed, 39 insertions(+), 32 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index 4dc2ccb..70477ce 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -34,6 +34,13 @@
 	PORT_10(fn, pfx##16, sfx),	PORT_10(fn, pfx##17, sfx), \
 	PORT_10(fn, pfx##18, sfx),	PORT_1(fn, pfx##190, sfx)
 
+#undef _GPIO_PORT
+#define _GPIO_PORT(gpio, sfx)						\
+	[gpio] = {							\
+		.name = __stringify(PORT##gpio),			\
+		.enum_id = PORT##gpio##_DATA,				\
+	}
+
 #define IRQC_PIN_MUX(irq, pin)						\
 static const unsigned int intc_irq##irq##_pins[] = {			\
 	pin,								\
@@ -2771,38 +2778,38 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
 #define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
 #define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
 static const struct pinmux_irq pinmux_irqs[] = {
-	PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162),
-	PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12),
-	PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5),
-	PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT8, GPIO_PORT16),
-	PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT17, GPIO_PORT163),
-	PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT18),
-	PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT39, GPIO_PORT164),
-	PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT40, GPIO_PORT167),
-	PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT41, GPIO_PORT168),
-	PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT42, GPIO_PORT169),
-	PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT65),
-	PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT67),
-	PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT80, GPIO_PORT137),
-	PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT81, GPIO_PORT145),
-	PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT82, GPIO_PORT146),
-	PINMUX_IRQ(EXT_IRQ16L(15), GPIO_PORT83, GPIO_PORT147),
-	PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT84, GPIO_PORT170),
-	PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT85),
-	PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT86),
-	PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT87),
-	PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT92),
-	PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT93),
-	PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT94),
-	PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT95),
-	PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT112),
-	PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT119),
-	PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT121, GPIO_PORT172),
-	PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT122, GPIO_PORT180),
-	PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT123, GPIO_PORT181),
-	PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT129, GPIO_PORT182),
-	PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT130, GPIO_PORT183),
-	PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184),
+	PINMUX_IRQ(EXT_IRQ16L(0), 6, 162),
+	PINMUX_IRQ(EXT_IRQ16L(1), 12),
+	PINMUX_IRQ(EXT_IRQ16L(2), 4, 5),
+	PINMUX_IRQ(EXT_IRQ16L(3), 8, 16),
+	PINMUX_IRQ(EXT_IRQ16L(4), 17, 163),
+	PINMUX_IRQ(EXT_IRQ16L(5), 18),
+	PINMUX_IRQ(EXT_IRQ16L(6), 39, 164),
+	PINMUX_IRQ(EXT_IRQ16L(7), 40, 167),
+	PINMUX_IRQ(EXT_IRQ16L(8), 41, 168),
+	PINMUX_IRQ(EXT_IRQ16L(9), 42, 169),
+	PINMUX_IRQ(EXT_IRQ16L(10), 65),
+	PINMUX_IRQ(EXT_IRQ16L(11), 67),
+	PINMUX_IRQ(EXT_IRQ16L(12), 80, 137),
+	PINMUX_IRQ(EXT_IRQ16L(13), 81, 145),
+	PINMUX_IRQ(EXT_IRQ16L(14), 82, 146),
+	PINMUX_IRQ(EXT_IRQ16L(15), 83, 147),
+	PINMUX_IRQ(EXT_IRQ16H(16), 84, 170),
+	PINMUX_IRQ(EXT_IRQ16H(17), 85),
+	PINMUX_IRQ(EXT_IRQ16H(18), 86),
+	PINMUX_IRQ(EXT_IRQ16H(19), 87),
+	PINMUX_IRQ(EXT_IRQ16H(20), 92),
+	PINMUX_IRQ(EXT_IRQ16H(21), 93),
+	PINMUX_IRQ(EXT_IRQ16H(22), 94),
+	PINMUX_IRQ(EXT_IRQ16H(23), 95),
+	PINMUX_IRQ(EXT_IRQ16H(24), 112),
+	PINMUX_IRQ(EXT_IRQ16H(25), 119),
+	PINMUX_IRQ(EXT_IRQ16H(26), 121, 172),
+	PINMUX_IRQ(EXT_IRQ16H(27), 122, 180),
+	PINMUX_IRQ(EXT_IRQ16H(28), 123, 181),
+	PINMUX_IRQ(EXT_IRQ16H(29), 129, 182),
+	PINMUX_IRQ(EXT_IRQ16H(30), 130, 183),
+	PINMUX_IRQ(EXT_IRQ16H(31), 138, 184),
 };
 
 const struct sh_pfc_soc_info sh7372_pinmux_info = {
-- 
1.8.2.1

[PATCH 056/130] sh-pfc: sh7372: Remove function GPIOs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

No sh7372 platform use the function GPIOs API. Remove it.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-sh7372.c | 247 ------------------------------------
 1 file changed, 247 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index 70477ce..9496067 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -2136,250 +2136,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(usb1),
 };
 
-#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	/* IRQ */
-	GPIO_FN(IRQ0_6),	GPIO_FN(IRQ0_162),	GPIO_FN(IRQ1),
-	GPIO_FN(IRQ2_4),	GPIO_FN(IRQ2_5),	GPIO_FN(IRQ3_8),
-	GPIO_FN(IRQ3_16),	GPIO_FN(IRQ4_17),	GPIO_FN(IRQ4_163),
-	GPIO_FN(IRQ5),		GPIO_FN(IRQ6_39),	GPIO_FN(IRQ6_164),
-	GPIO_FN(IRQ7_40),	GPIO_FN(IRQ7_167),	GPIO_FN(IRQ8_41),
-	GPIO_FN(IRQ8_168),	GPIO_FN(IRQ9_42),	GPIO_FN(IRQ9_169),
-	GPIO_FN(IRQ10),		GPIO_FN(IRQ11),		GPIO_FN(IRQ12_80),
-	GPIO_FN(IRQ12_137),	GPIO_FN(IRQ13_81),	GPIO_FN(IRQ13_145),
-	GPIO_FN(IRQ14_82),	GPIO_FN(IRQ14_146),	GPIO_FN(IRQ15_83),
-	GPIO_FN(IRQ15_147),	GPIO_FN(IRQ16_84),	GPIO_FN(IRQ16_170),
-	GPIO_FN(IRQ17),		GPIO_FN(IRQ18),		GPIO_FN(IRQ19),
-	GPIO_FN(IRQ20),		GPIO_FN(IRQ21),		GPIO_FN(IRQ22),
-	GPIO_FN(IRQ23),		GPIO_FN(IRQ24),		GPIO_FN(IRQ25),
-	GPIO_FN(IRQ26_121),	GPIO_FN(IRQ26_172),	GPIO_FN(IRQ27_122),
-	GPIO_FN(IRQ27_180),	GPIO_FN(IRQ28_123),	GPIO_FN(IRQ28_181),
-	GPIO_FN(IRQ29_129),	GPIO_FN(IRQ29_182),	GPIO_FN(IRQ30_130),
-	GPIO_FN(IRQ30_183),	GPIO_FN(IRQ31_138),	GPIO_FN(IRQ31_184),
-
-	/* MSIOF0 */
-	GPIO_FN(MSIOF0_TSYNC),	GPIO_FN(MSIOF0_TSCK),	GPIO_FN(MSIOF0_RXD),
-	GPIO_FN(MSIOF0_RSCK),	GPIO_FN(MSIOF0_RSYNC),	GPIO_FN(MSIOF0_MCK0),
-	GPIO_FN(MSIOF0_MCK1),	GPIO_FN(MSIOF0_SS1),	GPIO_FN(MSIOF0_SS2),
-	GPIO_FN(MSIOF0_TXD),
-
-	/* MSIOF1 */
-	GPIO_FN(MSIOF1_TSCK_39),	GPIO_FN(MSIOF1_TSCK_88),
-	GPIO_FN(MSIOF1_TSYNC_40),	GPIO_FN(MSIOF1_TSYNC_89),
-	GPIO_FN(MSIOF1_TXD_41),		GPIO_FN(MSIOF1_TXD_90),
-	GPIO_FN(MSIOF1_RXD_42),		GPIO_FN(MSIOF1_RXD_91),
-	GPIO_FN(MSIOF1_SS1_43),		GPIO_FN(MSIOF1_SS1_92),
-	GPIO_FN(MSIOF1_SS2_44),		GPIO_FN(MSIOF1_SS2_93),
-	GPIO_FN(MSIOF1_RSCK),		GPIO_FN(MSIOF1_RSYNC),
-	GPIO_FN(MSIOF1_MCK0),		GPIO_FN(MSIOF1_MCK1),
-
-	/* MSIOF2 */
-	GPIO_FN(MSIOF2_RSCK),	GPIO_FN(MSIOF2_RSYNC),	GPIO_FN(MSIOF2_MCK0),
-	GPIO_FN(MSIOF2_MCK1),	GPIO_FN(MSIOF2_SS1),	GPIO_FN(MSIOF2_SS2),
-	GPIO_FN(MSIOF2_TSYNC),	GPIO_FN(MSIOF2_TSCK),	GPIO_FN(MSIOF2_RXD),
-	GPIO_FN(MSIOF2_TXD),
-
-	/* BBIF1 */
-	GPIO_FN(BBIF1_RXD),	GPIO_FN(BBIF1_TSYNC),	GPIO_FN(BBIF1_TSCK),
-	GPIO_FN(BBIF1_TXD),	GPIO_FN(BBIF1_RSCK),	GPIO_FN(BBIF1_RSYNC),
-	GPIO_FN(BBIF1_FLOW),	GPIO_FN(BB_RX_FLOW_N),
-
-	/* BBIF2 */
-	GPIO_FN(BBIF2_TSCK1),	GPIO_FN(BBIF2_TSYNC1),
-	GPIO_FN(BBIF2_TXD1),	GPIO_FN(BBIF2_RXD),
-
-	/* FSI */
-	GPIO_FN(FSIACK),	GPIO_FN(FSIBCK),	GPIO_FN(FSIAILR),
-	GPIO_FN(FSIAIBT),	GPIO_FN(FSIAISLD),	GPIO_FN(FSIAOMC),
-	GPIO_FN(FSIAOLR),	GPIO_FN(FSIAOBT),	GPIO_FN(FSIAOSLD),
-	GPIO_FN(FSIASPDIF_11),	GPIO_FN(FSIASPDIF_15),
-
-	/* FMSI */
-	GPIO_FN(FMSOCK),	GPIO_FN(FMSOOLR),	GPIO_FN(FMSIOLR),
-	GPIO_FN(FMSOOBT),	GPIO_FN(FMSIOBT),	GPIO_FN(FMSOSLD),
-	GPIO_FN(FMSOILR),	GPIO_FN(FMSIILR),	GPIO_FN(FMSOIBT),
-	GPIO_FN(FMSIIBT),	GPIO_FN(FMSISLD),	GPIO_FN(FMSICK),
-
-	/* SCIFA0 */
-	GPIO_FN(SCIFA0_TXD),	GPIO_FN(SCIFA0_RXD),	GPIO_FN(SCIFA0_SCK),
-	GPIO_FN(SCIFA0_RTS),	GPIO_FN(SCIFA0_CTS),
-
-	/* SCIFA1 */
-	GPIO_FN(SCIFA1_TXD),	GPIO_FN(SCIFA1_RXD),	GPIO_FN(SCIFA1_SCK),
-	GPIO_FN(SCIFA1_RTS),	GPIO_FN(SCIFA1_CTS),
-
-	/* SCIFA2 */
-	GPIO_FN(SCIFA2_CTS1),	GPIO_FN(SCIFA2_RTS1),	GPIO_FN(SCIFA2_TXD1),
-	GPIO_FN(SCIFA2_RXD1),	GPIO_FN(SCIFA2_SCK1),
-
-	/* SCIFA3 */
-	GPIO_FN(SCIFA3_CTS_43),		GPIO_FN(SCIFA3_CTS_140),
-	GPIO_FN(SCIFA3_RTS_44),		GPIO_FN(SCIFA3_RTS_141),
-	GPIO_FN(SCIFA3_SCK),		GPIO_FN(SCIFA3_TXD),
-	GPIO_FN(SCIFA3_RXD),
-
-	/* SCIFA4 */
-	GPIO_FN(SCIFA4_RXD),	GPIO_FN(SCIFA4_TXD),
-
-	/* SCIFA5 */
-	GPIO_FN(SCIFA5_RXD),	GPIO_FN(SCIFA5_TXD),
-
-	/* SCIFB */
-	GPIO_FN(SCIFB_SCK),	GPIO_FN(SCIFB_RTS),	GPIO_FN(SCIFB_CTS),
-	GPIO_FN(SCIFB_TXD),	GPIO_FN(SCIFB_RXD),
-
-	/* CEU */
-	GPIO_FN(VIO_HD),	GPIO_FN(VIO_CKO1),	GPIO_FN(VIO_CKO2),
-	GPIO_FN(VIO_VD),	GPIO_FN(VIO_CLK),	GPIO_FN(VIO_FIELD),
-	GPIO_FN(VIO_CKO),	GPIO_FN(VIO_D0),	GPIO_FN(VIO_D1),
-	GPIO_FN(VIO_D2),	GPIO_FN(VIO_D3),	GPIO_FN(VIO_D4),
-	GPIO_FN(VIO_D5),	GPIO_FN(VIO_D6),	GPIO_FN(VIO_D7),
-	GPIO_FN(VIO_D8),	GPIO_FN(VIO_D9),	GPIO_FN(VIO_D10),
-	GPIO_FN(VIO_D11),	GPIO_FN(VIO_D12),	GPIO_FN(VIO_D13),
-	GPIO_FN(VIO_D14),	GPIO_FN(VIO_D15),
-
-	/* USB0 */
-	GPIO_FN(IDIN_0),	GPIO_FN(EXTLP_0),	GPIO_FN(OVCN2_0),
-	GPIO_FN(PWEN_0),	GPIO_FN(OVCN_0),	GPIO_FN(VBUS0_0),
-
-	/* USB1 */
-	GPIO_FN(IDIN_1_18),	GPIO_FN(IDIN_1_113),
-	GPIO_FN(OVCN_1_114),	GPIO_FN(OVCN_1_162),
-	GPIO_FN(PWEN_1_115),	GPIO_FN(PWEN_1_138),
-	GPIO_FN(EXTLP_1),	GPIO_FN(OVCN2_1),
-	GPIO_FN(VBUS0_1),
-
-	/* GPIO */
-	GPIO_FN(GPI0),	GPIO_FN(GPI1),	GPIO_FN(GPO0),	GPIO_FN(GPO1),
-
-	/* BSC */
-	GPIO_FN(BS),	GPIO_FN(WE1),	GPIO_FN(CKO),
-	GPIO_FN(WAIT),	GPIO_FN(RDWR),
-
-	GPIO_FN(A0),	GPIO_FN(A1),	GPIO_FN(A2),
-	GPIO_FN(A3),	GPIO_FN(A6),	GPIO_FN(A7),
-	GPIO_FN(A8),	GPIO_FN(A9),	GPIO_FN(A10),
-	GPIO_FN(A11),	GPIO_FN(A12),	GPIO_FN(A13),
-	GPIO_FN(A14),	GPIO_FN(A15),	GPIO_FN(A16),
-	GPIO_FN(A17),	GPIO_FN(A18),	GPIO_FN(A19),
-	GPIO_FN(A20),	GPIO_FN(A21),	GPIO_FN(A22),
-	GPIO_FN(A23),	GPIO_FN(A24),	GPIO_FN(A25),
-	GPIO_FN(A26),
-
-	GPIO_FN(CS0),	GPIO_FN(CS2),	GPIO_FN(CS4),
-	GPIO_FN(CS5A),	GPIO_FN(CS5B),	GPIO_FN(CS6A),
-
-	/* BSC/FLCTL */
-	GPIO_FN(RD_FSC),	GPIO_FN(WE0_FWE),	GPIO_FN(A4_FOE),
-	GPIO_FN(A5_FCDE),	GPIO_FN(D0_NAF0),	GPIO_FN(D1_NAF1),
-	GPIO_FN(D2_NAF2),	GPIO_FN(D3_NAF3),	GPIO_FN(D4_NAF4),
-	GPIO_FN(D5_NAF5),	GPIO_FN(D6_NAF6),	GPIO_FN(D7_NAF7),
-	GPIO_FN(D8_NAF8),	GPIO_FN(D9_NAF9),	GPIO_FN(D10_NAF10),
-	GPIO_FN(D11_NAF11),	GPIO_FN(D12_NAF12),	GPIO_FN(D13_NAF13),
-	GPIO_FN(D14_NAF14),	GPIO_FN(D15_NAF15),
-
-	/* SPU2 */
-	GPIO_FN(VINT_I),
-
-	/* FLCTL */
-	GPIO_FN(FCE1),	GPIO_FN(FCE0),	GPIO_FN(FRB),
-
-	/* HSI */
-	GPIO_FN(GP_RX_FLAG),	GPIO_FN(GP_RX_DATA),	GPIO_FN(GP_TX_READY),
-	GPIO_FN(GP_RX_WAKE),	GPIO_FN(MP_TX_FLAG),	GPIO_FN(MP_TX_DATA),
-	GPIO_FN(MP_RX_READY),	GPIO_FN(MP_TX_WAKE),
-
-	/* MFI */
-	GPIO_FN(MFIv6),
-	GPIO_FN(MFIv4),
-
-	GPIO_FN(MEMC_BUSCLK_MEMC_A0),	GPIO_FN(MEMC_ADV_MEMC_DREQ0),
-	GPIO_FN(MEMC_WAIT_MEMC_DREQ1),	GPIO_FN(MEMC_CS1_MEMC_A1),
-	GPIO_FN(MEMC_CS0),	GPIO_FN(MEMC_NOE),
-	GPIO_FN(MEMC_NWE),	GPIO_FN(MEMC_INT),
-
-	GPIO_FN(MEMC_AD0),	GPIO_FN(MEMC_AD1),	GPIO_FN(MEMC_AD2),
-	GPIO_FN(MEMC_AD3),	GPIO_FN(MEMC_AD4),	GPIO_FN(MEMC_AD5),
-	GPIO_FN(MEMC_AD6),	GPIO_FN(MEMC_AD7),	GPIO_FN(MEMC_AD8),
-	GPIO_FN(MEMC_AD9),	GPIO_FN(MEMC_AD10),	GPIO_FN(MEMC_AD11),
-	GPIO_FN(MEMC_AD12),	GPIO_FN(MEMC_AD13),	GPIO_FN(MEMC_AD14),
-	GPIO_FN(MEMC_AD15),
-
-	/* SIM */
-	GPIO_FN(SIM_RST),	GPIO_FN(SIM_CLK),	GPIO_FN(SIM_D),
-
-	/* TPU */
-	GPIO_FN(TPU0TO0),	GPIO_FN(TPU0TO1),	GPIO_FN(TPU0TO2_93),
-	GPIO_FN(TPU0TO2_99),	GPIO_FN(TPU0TO3),
-
-	/* I2C2 */
-	GPIO_FN(I2C_SCL2),	GPIO_FN(I2C_SDA2),
-
-	/* I2C3(1) */
-	GPIO_FN(I2C_SCL3),	GPIO_FN(I2C_SDA3),
-
-	/* I2C3(2) */
-	GPIO_FN(I2C_SCL3S),	GPIO_FN(I2C_SDA3S),
-
-	/* I2C4(2) */
-	GPIO_FN(I2C_SCL4),	GPIO_FN(I2C_SDA4),
-
-	/* I2C4(2) */
-	GPIO_FN(I2C_SCL4S),	GPIO_FN(I2C_SDA4S),
-
-	/* KEYSC */
-	GPIO_FN(KEYOUT0),	GPIO_FN(KEYIN0_121),	GPIO_FN(KEYIN0_136),
-	GPIO_FN(KEYOUT1),	GPIO_FN(KEYIN1_122),	GPIO_FN(KEYIN1_135),
-	GPIO_FN(KEYOUT2),	GPIO_FN(KEYIN2_123),	GPIO_FN(KEYIN2_134),
-	GPIO_FN(KEYOUT3),	GPIO_FN(KEYIN3_124),	GPIO_FN(KEYIN3_133),
-	GPIO_FN(KEYOUT4),	GPIO_FN(KEYIN4),	GPIO_FN(KEYOUT5),
-	GPIO_FN(KEYIN5),	GPIO_FN(KEYOUT6),	GPIO_FN(KEYIN6),
-	GPIO_FN(KEYOUT7),	GPIO_FN(KEYIN7),
-
-	/* LCDC */
-	GPIO_FN(LCDHSYN),	GPIO_FN(LCDCS),	GPIO_FN(LCDVSYN),
-	GPIO_FN(LCDDCK),	GPIO_FN(LCDWR),	GPIO_FN(LCDRD),
-	GPIO_FN(LCDDISP),	GPIO_FN(LCDRS),	GPIO_FN(LCDLCLK),
-	GPIO_FN(LCDDON),
-
-	GPIO_FN(LCDD0),		GPIO_FN(LCDD1),		GPIO_FN(LCDD2),
-	GPIO_FN(LCDD3),		GPIO_FN(LCDD4),		GPIO_FN(LCDD5),
-	GPIO_FN(LCDD6),		GPIO_FN(LCDD7),		GPIO_FN(LCDD8),
-	GPIO_FN(LCDD9),		GPIO_FN(LCDD10),	GPIO_FN(LCDD11),
-	GPIO_FN(LCDD12),	GPIO_FN(LCDD13),	GPIO_FN(LCDD14),
-	GPIO_FN(LCDD15),	GPIO_FN(LCDD16),	GPIO_FN(LCDD17),
-	GPIO_FN(LCDD18),	GPIO_FN(LCDD19),	GPIO_FN(LCDD20),
-	GPIO_FN(LCDD21),	GPIO_FN(LCDD22),	GPIO_FN(LCDD23),
-
-	GPIO_FN(LCDC0_SELECT),
-	GPIO_FN(LCDC1_SELECT),
-
-	/* IRDA */
-	GPIO_FN(IRDA_OUT),	GPIO_FN(IRDA_IN),	GPIO_FN(IRDA_FIRSEL),
-	GPIO_FN(IROUT_139),	GPIO_FN(IROUT_140),
-
-	/* TSIF1 */
-	GPIO_FN(TS0_1SELECT),
-	GPIO_FN(TS0_2SELECT),
-	GPIO_FN(TS1_1SELECT),
-	GPIO_FN(TS1_2SELECT),
-
-	GPIO_FN(TS_SPSYNC1),	GPIO_FN(TS_SDAT1),
-	GPIO_FN(TS_SDEN1),	GPIO_FN(TS_SCK1),
-
-	/* TSIF2 */
-	GPIO_FN(TS_SPSYNC2),	GPIO_FN(TS_SDAT2),
-	GPIO_FN(TS_SDEN2),	GPIO_FN(TS_SCK2),
-
-	/* HDMI */
-	GPIO_FN(HDMI_HPD),	GPIO_FN(HDMI_CEC),
-
-	/* SDENC */
-	GPIO_FN(SDENC_CPG),
-	GPIO_FN(SDENC_DV_CLKI),
-};
-
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 	PORTCR(0,	0xE6051000), /* PORT0CR */
 	PORTCR(1,	0xE6051001), /* PORT1CR */
@@ -2827,9 +2583,6 @@ const struct sh_pfc_soc_info sh7372_pinmux_info = {
 	.functions = pinmux_functions,
 	.nr_functions = ARRAY_SIZE(pinmux_functions),
 
-	.func_gpios = pinmux_func_gpios,
-	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
 	.cfg_regs = pinmux_config_regs,
 	.data_regs = pinmux_data_regs,
 
-- 
1.8.2.1

[PATCH 057/130] ARM: shmobile: sh7372: Remove all GPIOs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Function GPIOs are not used anymore, and all code use the GPIO numbers
directly. Remove the GPIOs enumeration.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/sh7372.h | 391 ---------------------------
 1 file changed, 391 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index fd7cba0..e882717 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -15,397 +15,6 @@
 #include <linux/pm_domain.h>
 #include <mach/pm-rmobile.h>
 
-/*
- * Pin Function Controller:
- *	GPIO_FN_xx - GPIO used to select pin function
- *	GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
- */
-enum {
-	/* PORT */
-	GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
-	GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
-
-	GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
-	GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
-
-	GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
-	GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
-
-	GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
-	GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
-
-	GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
-	GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
-
-	GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
-	GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
-
-	GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
-	GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
-
-	GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
-	GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
-
-	GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
-	GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
-
-	GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
-	GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
-
-	GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
-	GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
-
-	GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
-	GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
-
-	GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
-	GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
-
-	GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
-	GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
-
-	GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
-	GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
-
-	GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
-	GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
-
-	GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
-	GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
-
-	GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
-	GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
-
-	GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
-	GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
-
-	GPIO_PORT190,
-
-	/* IRQ */
-	GPIO_FN_IRQ0_6,		/* PORT   6 */
-	GPIO_FN_IRQ0_162,	/* PORT 162 */
-	GPIO_FN_IRQ1,		/* PORT  12 */
-	GPIO_FN_IRQ2_4,		/* PORT   4 */
-	GPIO_FN_IRQ2_5,		/* PORT   5 */
-	GPIO_FN_IRQ3_8,		/* PORT   8 */
-	GPIO_FN_IRQ3_16,	/* PORT  16 */
-	GPIO_FN_IRQ4_17,	/* PORT  17 */
-	GPIO_FN_IRQ4_163,	/* PORT 163 */
-	GPIO_FN_IRQ5,		/* PORT  18 */
-	GPIO_FN_IRQ6_39,	/* PORT  39 */
-	GPIO_FN_IRQ6_164,	/* PORT 164 */
-	GPIO_FN_IRQ7_40,	/* PORT  40 */
-	GPIO_FN_IRQ7_167,	/* PORT 167 */
-	GPIO_FN_IRQ8_41,	/* PORT  41 */
-	GPIO_FN_IRQ8_168,	/* PORT 168 */
-	GPIO_FN_IRQ9_42,	/* PORT  42 */
-	GPIO_FN_IRQ9_169,	/* PORT 169 */
-	GPIO_FN_IRQ10,		/* PORT  65 */
-	GPIO_FN_IRQ11,		/* PORT  67 */
-	GPIO_FN_IRQ12_80,	/* PORT  80 */
-	GPIO_FN_IRQ12_137,	/* PORT 137 */
-	GPIO_FN_IRQ13_81,	/* PORT  81 */
-	GPIO_FN_IRQ13_145,	/* PORT 145 */
-	GPIO_FN_IRQ14_82,	/* PORT  82 */
-	GPIO_FN_IRQ14_146,	/* PORT 146 */
-	GPIO_FN_IRQ15_83,	/* PORT  83 */
-	GPIO_FN_IRQ15_147,	/* PORT 147 */
-	GPIO_FN_IRQ16_84,	/* PORT  84 */
-	GPIO_FN_IRQ16_170,	/* PORT 170 */
-	GPIO_FN_IRQ17,		/* PORT  85 */
-	GPIO_FN_IRQ18,		/* PORT  86 */
-	GPIO_FN_IRQ19,		/* PORT  87 */
-	GPIO_FN_IRQ20,		/* PORT  92 */
-	GPIO_FN_IRQ21,		/* PORT  93 */
-	GPIO_FN_IRQ22,		/* PORT  94 */
-	GPIO_FN_IRQ23,		/* PORT  95 */
-	GPIO_FN_IRQ24,		/* PORT 112 */
-	GPIO_FN_IRQ25,		/* PORT 119 */
-	GPIO_FN_IRQ26_121,	/* PORT 121 */
-	GPIO_FN_IRQ26_172,	/* PORT 172 */
-	GPIO_FN_IRQ27_122,	/* PORT 122 */
-	GPIO_FN_IRQ27_180,	/* PORT 180 */
-	GPIO_FN_IRQ28_123,	/* PORT 123 */
-	GPIO_FN_IRQ28_181,	/* PORT 181 */
-	GPIO_FN_IRQ29_129,	/* PORT 129 */
-	GPIO_FN_IRQ29_182,	/* PORT 182 */
-	GPIO_FN_IRQ30_130,	/* PORT 130 */
-	GPIO_FN_IRQ30_183,	/* PORT 183 */
-	GPIO_FN_IRQ31_138,	/* PORT 138 */
-	GPIO_FN_IRQ31_184,	/* PORT 184 */
-
-	/*
-	 * MSIOF0	(PORT 36, 37, 38, 39
-	 * 		      40, 41, 42, 43, 44, 45)
-	 */
-	GPIO_FN_MSIOF0_TSYNC,	GPIO_FN_MSIOF0_TSCK,
-	GPIO_FN_MSIOF0_RXD,	GPIO_FN_MSIOF0_RSCK,
-	GPIO_FN_MSIOF0_RSYNC,	GPIO_FN_MSIOF0_MCK0,
-	GPIO_FN_MSIOF0_MCK1,	GPIO_FN_MSIOF0_SS1,
-	GPIO_FN_MSIOF0_SS2,	GPIO_FN_MSIOF0_TXD,
-
-	/*
-	 * MSIOF1	(PORT 39, 40, 41, 42, 43, 44
-	 * 		      84, 85, 86, 87, 88, 89, 90, 91, 92, 93)
-	 */
-	GPIO_FN_MSIOF1_TSCK_39,	GPIO_FN_MSIOF1_TSYNC_40,
-	GPIO_FN_MSIOF1_TSCK_88,	GPIO_FN_MSIOF1_TSYNC_89,
-	GPIO_FN_MSIOF1_TXD_41,	GPIO_FN_MSIOF1_RXD_42,
-	GPIO_FN_MSIOF1_TXD_90,	GPIO_FN_MSIOF1_RXD_91,
-	GPIO_FN_MSIOF1_SS1_43,	GPIO_FN_MSIOF1_SS2_44,
-	GPIO_FN_MSIOF1_SS1_92,	GPIO_FN_MSIOF1_SS2_93,
-	GPIO_FN_MSIOF1_RSCK,	GPIO_FN_MSIOF1_RSYNC,
-	GPIO_FN_MSIOF1_MCK0,	GPIO_FN_MSIOF1_MCK1,
-
-	/*
-	 * MSIOF2	(PORT 134, 135, 136, 137, 138, 139
-	 *		      148, 149, 150, 151)
-	 */
-	GPIO_FN_MSIOF2_RSCK,	GPIO_FN_MSIOF2_RSYNC,
-	GPIO_FN_MSIOF2_MCK0,	GPIO_FN_MSIOF2_MCK1,
-	GPIO_FN_MSIOF2_SS1,	GPIO_FN_MSIOF2_SS2,
-	GPIO_FN_MSIOF2_TSYNC,	GPIO_FN_MSIOF2_TSCK,
-	GPIO_FN_MSIOF2_RXD,	GPIO_FN_MSIOF2_TXD,
-
-	/* MSIOF3	(PORT 76, 77, 78, 79, 80, 81, 82, 83) */
-	GPIO_FN_BBIF1_RXD,	GPIO_FN_BBIF1_TSYNC,
-	GPIO_FN_BBIF1_TSCK,	GPIO_FN_BBIF1_TXD,
-	GPIO_FN_BBIF1_RSCK,	GPIO_FN_BBIF1_RSYNC,
-	GPIO_FN_BBIF1_FLOW,	GPIO_FN_BB_RX_FLOW_N,
-
-	/* MSIOF4	(PORT 0, 1, 2, 3) */
-	GPIO_FN_BBIF2_TSCK1,	GPIO_FN_BBIF2_TSYNC1,
-	GPIO_FN_BBIF2_TXD1,	GPIO_FN_BBIF2_RXD,
-
-	/* FSI		(PORT 4, 5, 6, 7, 8, 9, 10, 11, 15) */
-	GPIO_FN_FSIACK,		GPIO_FN_FSIBCK,
-	GPIO_FN_FSIAILR,	GPIO_FN_FSIAIBT,
-	GPIO_FN_FSIAISLD,	GPIO_FN_FSIAOMC,
-	GPIO_FN_FSIAOLR,	GPIO_FN_FSIAOBT,
-	GPIO_FN_FSIAOSLD,	GPIO_FN_FSIASPDIF_11,
-	GPIO_FN_FSIASPDIF_15,
-
-	/* FMSI		(PORT 12, 13, 14, 15, 16, 17, 18, 65) */
-	GPIO_FN_FMSOCK,		GPIO_FN_FMSOOLR,
-	GPIO_FN_FMSIOLR,	GPIO_FN_FMSOOBT,
-	GPIO_FN_FMSIOBT,	GPIO_FN_FMSOSLD,
-	GPIO_FN_FMSOILR,	GPIO_FN_FMSIILR,
-	GPIO_FN_FMSOIBT,	GPIO_FN_FMSIIBT,
-	GPIO_FN_FMSISLD,	GPIO_FN_FMSICK,
-
-	/* SCIFA0	(PORT 152, 153, 156, 157, 158) */
-	GPIO_FN_SCIFA0_TXD,	GPIO_FN_SCIFA0_RXD,
-	GPIO_FN_SCIFA0_SCK,	GPIO_FN_SCIFA0_RTS,
-	GPIO_FN_SCIFA0_CTS,
-
-	/* SCIFA1	(PORT 154, 155, 159, 160, 161) */
-	GPIO_FN_SCIFA1_TXD,	GPIO_FN_SCIFA1_RXD,
-	GPIO_FN_SCIFA1_SCK,	GPIO_FN_SCIFA1_RTS,
-	GPIO_FN_SCIFA1_CTS,
-
-	/* SCIFA2	(PORT 94, 95, 96, 97, 98) */
-	GPIO_FN_SCIFA2_CTS1,	GPIO_FN_SCIFA2_RTS1,
-	GPIO_FN_SCIFA2_TXD1,	GPIO_FN_SCIFA2_RXD1,
-	GPIO_FN_SCIFA2_SCK1,
-
-	/* SCIFA3	(PORT 43, 44,
-			     140, 141, 142, 143, 144) */
-	GPIO_FN_SCIFA3_CTS_43,	GPIO_FN_SCIFA3_CTS_140,
-	GPIO_FN_SCIFA3_RTS_44,	GPIO_FN_SCIFA3_RTS_141,
-	GPIO_FN_SCIFA3_SCK,	GPIO_FN_SCIFA3_TXD,
-	GPIO_FN_SCIFA3_RXD,
-
-	/* SCIFA4	(PORT 5, 6) */
-	GPIO_FN_SCIFA4_RXD,	GPIO_FN_SCIFA4_TXD,
-
-	/* SCIFA5	(PORT 8, 12) */
-	GPIO_FN_SCIFA5_RXD,	GPIO_FN_SCIFA5_TXD,
-
-	/* SCIFB	(PORT 162, 163, 164, 165, 166) */
-	GPIO_FN_SCIFB_SCK,	GPIO_FN_SCIFB_RTS,
-	GPIO_FN_SCIFB_CTS,	GPIO_FN_SCIFB_TXD,
-	GPIO_FN_SCIFB_RXD,
-
-	/*
-	 * CEU		(PORT 16, 17,
-	 *		      100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
-	 *		      110, 111, 112, 113, 114, 115, 116, 117, 118, 119,
-	 *		      120)
-	 */
-	GPIO_FN_VIO_HD,		GPIO_FN_VIO_CKO1,	GPIO_FN_VIO_CKO2,
-	GPIO_FN_VIO_VD,		GPIO_FN_VIO_CLK,	GPIO_FN_VIO_FIELD,
-	GPIO_FN_VIO_CKO,
-	GPIO_FN_VIO_D0,		GPIO_FN_VIO_D1,		GPIO_FN_VIO_D2,
-	GPIO_FN_VIO_D3,		GPIO_FN_VIO_D4,		GPIO_FN_VIO_D5,
-	GPIO_FN_VIO_D6,		GPIO_FN_VIO_D7,		GPIO_FN_VIO_D8,
-	GPIO_FN_VIO_D9,		GPIO_FN_VIO_D10,	GPIO_FN_VIO_D11,
-	GPIO_FN_VIO_D12,	GPIO_FN_VIO_D13,	GPIO_FN_VIO_D14,
-	GPIO_FN_VIO_D15,
-
-	/* USB0		(PORT 113, 114, 115, 116, 117, 167) */
-	GPIO_FN_IDIN_0,		GPIO_FN_EXTLP_0,
-	GPIO_FN_OVCN2_0,	GPIO_FN_PWEN_0,
-	GPIO_FN_OVCN_0,		GPIO_FN_VBUS0_0,
-
-	/* USB1		(PORT 18, 113, 114, 115, 116, 117, 138, 162, 168) */
-	GPIO_FN_IDIN_1_18,	GPIO_FN_IDIN_1_113,
-	GPIO_FN_PWEN_1_115,	GPIO_FN_PWEN_1_138,
-	GPIO_FN_OVCN_1_114,	GPIO_FN_OVCN_1_162,
-	GPIO_FN_EXTLP_1,	GPIO_FN_OVCN2_1,
-	GPIO_FN_VBUS0_1,
-
-	/* GPIO		(PORT 41, 42, 43, 44) */
-	GPIO_FN_GPI0,	GPIO_FN_GPI1,	GPIO_FN_GPO0,	GPIO_FN_GPO1,
-
-	/*
-	 * BSC		(PORT 19,
-	 *		      20, 21, 22, 25, 26, 27, 28, 29,
-	 *		      30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
-	 *		      40, 41, 42, 43, 44, 45,
-	 *		      62, 63, 64, 65, 66, 67,
-	 *		      71, 72, 74, 75)
-	 */
-	GPIO_FN_BS,	GPIO_FN_WE1,
-	GPIO_FN_CKO,	GPIO_FN_WAIT,	GPIO_FN_RDWR,
-
-	GPIO_FN_A0,	GPIO_FN_A1,	GPIO_FN_A2,	GPIO_FN_A3,
-	GPIO_FN_A6,	GPIO_FN_A7,	GPIO_FN_A8,	GPIO_FN_A9,
-	GPIO_FN_A10,	GPIO_FN_A11,	GPIO_FN_A12,	GPIO_FN_A13,
-	GPIO_FN_A14,	GPIO_FN_A15,	GPIO_FN_A16,	GPIO_FN_A17,
-	GPIO_FN_A18,	GPIO_FN_A19,	GPIO_FN_A20,	GPIO_FN_A21,
-	GPIO_FN_A22,	GPIO_FN_A23,	GPIO_FN_A24,	GPIO_FN_A25,
-	GPIO_FN_A26,
-
-	GPIO_FN_CS0,	GPIO_FN_CS2,	GPIO_FN_CS4,
-	GPIO_FN_CS5A,	GPIO_FN_CS5B,	GPIO_FN_CS6A,
-
-	/*
-	 * BSC/FLCTL		(PORT 23, 24,
-	 *			      46, 47, 48, 49,
-	 *			      50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
-	 *			      60, 61, 69, 70)
-	 */
-	GPIO_FN_RD_FSC,		GPIO_FN_WE0_FWE,
-	GPIO_FN_A4_FOE,		GPIO_FN_A5_FCDE,
-	GPIO_FN_D0_NAF0,	GPIO_FN_D1_NAF1,	GPIO_FN_D2_NAF2,
-	GPIO_FN_D3_NAF3,	GPIO_FN_D4_NAF4,	GPIO_FN_D5_NAF5,
-	GPIO_FN_D6_NAF6,	GPIO_FN_D7_NAF7,	GPIO_FN_D8_NAF8,
-	GPIO_FN_D9_NAF9,	GPIO_FN_D10_NAF10,	GPIO_FN_D11_NAF11,
-	GPIO_FN_D12_NAF12,	GPIO_FN_D13_NAF13,	GPIO_FN_D14_NAF14,
-	GPIO_FN_D15_NAF15,
-
-	/* SPU2		(PORT 65) */
-	GPIO_FN_VINT_I,
-
-	/* FLCTL	(PORT 66, 68, 73) */
-	GPIO_FN_FCE1,	GPIO_FN_FCE0,	GPIO_FN_FRB,
-
-	/* HSI		(PORT 76, 77, 78, 79, 80, 81, 82, 83) */
-	GPIO_FN_GP_RX_FLAG,	GPIO_FN_GP_RX_DATA,	GPIO_FN_GP_TX_READY,
-	GPIO_FN_GP_RX_WAKE,	GPIO_FN_MP_TX_FLAG,	GPIO_FN_MP_TX_DATA,
-	GPIO_FN_MP_RX_READY,	GPIO_FN_MP_TX_WAKE,
-
-	/*
-	 * MFI		(PORT 76, 77, 78, 79,
-	 *		      80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
-	 *		      90, 91, 92, 93, 94, 95, 96, 97, 98, 99)
-	 */
-	GPIO_FN_MFIv6,	/* see MSEL4CR 6 */
-	GPIO_FN_MFIv4,	/* see MSEL4CR 6 */
-
-	GPIO_FN_MEMC_CS0,		GPIO_FN_MEMC_BUSCLK_MEMC_A0,
-	GPIO_FN_MEMC_CS1_MEMC_A1,	GPIO_FN_MEMC_ADV_MEMC_DREQ0,
-	GPIO_FN_MEMC_WAIT_MEMC_DREQ1,	GPIO_FN_MEMC_NOE,
-	GPIO_FN_MEMC_NWE,		GPIO_FN_MEMC_INT,
-
-	GPIO_FN_MEMC_AD0,	GPIO_FN_MEMC_AD1,	GPIO_FN_MEMC_AD2,
-	GPIO_FN_MEMC_AD3,	GPIO_FN_MEMC_AD4,	GPIO_FN_MEMC_AD5,
-	GPIO_FN_MEMC_AD6,	GPIO_FN_MEMC_AD7,	GPIO_FN_MEMC_AD8,
-	GPIO_FN_MEMC_AD9,	GPIO_FN_MEMC_AD10,	GPIO_FN_MEMC_AD11,
-	GPIO_FN_MEMC_AD12,	GPIO_FN_MEMC_AD13,	GPIO_FN_MEMC_AD14,
-	GPIO_FN_MEMC_AD15,
-
-	/* SIM		(PORT 94, 95, 98) */
-	GPIO_FN_SIM_RST,	GPIO_FN_SIM_CLK,	GPIO_FN_SIM_D,
-
-	/* TPU		(PORT 93, 99, 112, 160, 161) */
-	GPIO_FN_TPU0TO0,	GPIO_FN_TPU0TO1,
-	GPIO_FN_TPU0TO2_93,	GPIO_FN_TPU0TO2_99,
-	GPIO_FN_TPU0TO3,
-
-	/* I2C2		(PORT 110, 111) */
-	GPIO_FN_I2C_SCL2,	GPIO_FN_I2C_SDA2,
-
-	/* I2C3(1)	(PORT 114, 115) */
-	GPIO_FN_I2C_SCL3,	GPIO_FN_I2C_SDA3,
-
-	/* I2C3(2)	(PORT 137, 145) */
-	GPIO_FN_I2C_SCL3S,	GPIO_FN_I2C_SDA3S,
-
-	/* I2C4(2)	(PORT 116, 117) */
-	GPIO_FN_I2C_SCL4,	GPIO_FN_I2C_SDA4,
-
-	/* I2C4(2)	(PORT 146, 147) */
-	GPIO_FN_I2C_SCL4S,	GPIO_FN_I2C_SDA4S,
-
-	/*
-	 * KEYSC	(PORT 121, 122, 123, 124, 125, 126, 127, 128, 129,
-	 *		      130, 131, 132, 133, 134, 135, 136)
-	 */
-	GPIO_FN_KEYOUT0,	GPIO_FN_KEYIN0_121,	GPIO_FN_KEYIN0_136,
-	GPIO_FN_KEYOUT1,	GPIO_FN_KEYIN1_122,	GPIO_FN_KEYIN1_135,
-	GPIO_FN_KEYOUT2,	GPIO_FN_KEYIN2_123,	GPIO_FN_KEYIN2_134,
-	GPIO_FN_KEYOUT3,	GPIO_FN_KEYIN3_124,	GPIO_FN_KEYIN3_133,
-	GPIO_FN_KEYOUT4,	GPIO_FN_KEYIN4,
-	GPIO_FN_KEYOUT5,	GPIO_FN_KEYIN5,
-	GPIO_FN_KEYOUT6,	GPIO_FN_KEYIN6,
-	GPIO_FN_KEYOUT7,	GPIO_FN_KEYIN7,
-
-	/*
-	 * LCDC		(PORT      121, 122, 123, 124, 125, 126, 127, 128, 129,
-	 *		      130, 131, 132, 133, 134, 135, 136, 137, 138, 139,
-	 *		      140, 141, 142, 143, 144, 145, 146, 147, 148, 149,
-	 *		      150, 151)
-	 */
-	GPIO_FN_LCDC0_SELECT, /* LCDC 0 */
-	GPIO_FN_LCDC1_SELECT, /* LCDC 1 */
-	GPIO_FN_LCDHSYN,	GPIO_FN_LCDCS,	GPIO_FN_LCDVSYN,
-	GPIO_FN_LCDDCK,		GPIO_FN_LCDWR,	GPIO_FN_LCDRD,
-	GPIO_FN_LCDDISP,	GPIO_FN_LCDRS,	GPIO_FN_LCDLCLK,
-	GPIO_FN_LCDDON,
-
-	GPIO_FN_LCDD0,	GPIO_FN_LCDD1,	GPIO_FN_LCDD2,	GPIO_FN_LCDD3,
-	GPIO_FN_LCDD4,	GPIO_FN_LCDD5,	GPIO_FN_LCDD6,	GPIO_FN_LCDD7,
-	GPIO_FN_LCDD8,	GPIO_FN_LCDD9,	GPIO_FN_LCDD10,	GPIO_FN_LCDD11,
-	GPIO_FN_LCDD12,	GPIO_FN_LCDD13,	GPIO_FN_LCDD14,	GPIO_FN_LCDD15,
-	GPIO_FN_LCDD16,	GPIO_FN_LCDD17,	GPIO_FN_LCDD18,	GPIO_FN_LCDD19,
-	GPIO_FN_LCDD20,	GPIO_FN_LCDD21,	GPIO_FN_LCDD22,	GPIO_FN_LCDD23,
-
-	/* IRDA		(PORT 139, 140, 141, 142) */
-	GPIO_FN_IRDA_OUT,	GPIO_FN_IRDA_IN,	GPIO_FN_IRDA_FIRSEL,
-	GPIO_FN_IROUT_139,	GPIO_FN_IROUT_140,
-
-	/* TSIF1	(PORT 156, 157, 158, 159) */
-	GPIO_FN_TS0_1SELECT, /* TSIF0 - 1 select */
-	GPIO_FN_TS0_2SELECT, /* TSIF0 - 2 select */
-	GPIO_FN_TS1_1SELECT, /* TSIF1 - 1 select */
-	GPIO_FN_TS1_2SELECT, /* TSIF1 - 2 select */
-
-	GPIO_FN_TS_SPSYNC1,	GPIO_FN_TS_SDAT1,
-	GPIO_FN_TS_SDEN1,	GPIO_FN_TS_SCK1,
-
-	/* TSIF2	(PORT 137, 145, 146, 147) */
-	GPIO_FN_TS_SPSYNC2,	GPIO_FN_TS_SDAT2,
-	GPIO_FN_TS_SDEN2,	GPIO_FN_TS_SCK2,
-
-	/* HDMI		(PORT 169, 170) */
-	GPIO_FN_HDMI_HPD,	GPIO_FN_HDMI_CEC,
-
-	/* SDENC	see MSEL4CR 19 */
-	GPIO_FN_SDENC_CPG,
-	GPIO_FN_SDENC_DV_CLKI,
-};
-
 /* DMA slave IDs */
 enum {
 	SHDMA_SLAVE_INVALID,
-- 
1.8.2.1

[PATCH 058/130] sh-pfc: sh7372: Add bias (pull-up/down) pinconf support

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-sh7372.c | 341 ++++++++++++++++++++++--------------
 1 file changed, 211 insertions(+), 130 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index 9496067..6dfb187 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -20,10 +20,14 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
+#include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
 #include <mach/irqs.h>
 #include <mach/sh7372.h>
 
+#include "core.h"
 #include "sh_pfc.h"
 
 #define CPU_ALL_PORT(fn, pfx, sfx) \
@@ -76,16 +80,6 @@ enum {
 	PORT_ALL(IN),
 	PINMUX_INPUT_END,
 
-	/* PORT0_IN_PU -> PORT190_IN_PU */
-	PINMUX_INPUT_PULLUP_BEGIN,
-	PORT_ALL(IN_PU),
-	PINMUX_INPUT_PULLUP_END,
-
-	/* PORT0_IN_PD -> PORT190_IN_PD */
-	PINMUX_INPUT_PULLDOWN_BEGIN,
-	PORT_ALL(IN_PD),
-	PINMUX_INPUT_PULLDOWN_END,
-
 	/* PORT0_OUT -> PORT190_OUT */
 	PINMUX_OUTPUT_BEGIN,
 	PORT_ALL(OUT),
@@ -397,124 +391,11 @@ enum {
 	PINMUX_MARK_END,
 };
 
-static const pinmux_enum_t pinmux_data[] = {
+#define _PORT_DATA(pfx, sfx)	PORT_DATA_IO(pfx)
+#define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_PORT_DATA, , unused)
 
-	/* specify valid pin states for each pin in GPIO mode */
-	PORT_DATA_IO_PD(0),		PORT_DATA_IO_PD(1),
-	PORT_DATA_O(2),			PORT_DATA_I_PD(3),
-	PORT_DATA_I_PD(4),		PORT_DATA_I_PD(5),
-	PORT_DATA_IO_PU_PD(6),		PORT_DATA_I_PD(7),
-	PORT_DATA_IO_PD(8),		PORT_DATA_O(9),
-
-	PORT_DATA_O(10),		PORT_DATA_O(11),
-	PORT_DATA_IO_PU_PD(12),		PORT_DATA_IO_PD(13),
-	PORT_DATA_IO_PD(14),		PORT_DATA_O(15),
-	PORT_DATA_IO_PD(16),		PORT_DATA_IO_PD(17),
-	PORT_DATA_I_PD(18),		PORT_DATA_IO(19),
-
-	PORT_DATA_IO(20),		PORT_DATA_IO(21),
-	PORT_DATA_IO(22),		PORT_DATA_IO(23),
-	PORT_DATA_IO(24),		PORT_DATA_IO(25),
-	PORT_DATA_IO(26),		PORT_DATA_IO(27),
-	PORT_DATA_IO(28),		PORT_DATA_IO(29),
-
-	PORT_DATA_IO(30),		PORT_DATA_IO(31),
-	PORT_DATA_IO(32),		PORT_DATA_IO(33),
-	PORT_DATA_IO(34),		PORT_DATA_IO(35),
-	PORT_DATA_IO(36),		PORT_DATA_IO(37),
-	PORT_DATA_IO(38),		PORT_DATA_IO(39),
-
-	PORT_DATA_IO(40),		PORT_DATA_IO(41),
-	PORT_DATA_IO(42),		PORT_DATA_IO(43),
-	PORT_DATA_IO(44),		PORT_DATA_IO(45),
-	PORT_DATA_IO_PU(46),		PORT_DATA_IO_PU(47),
-	PORT_DATA_IO_PU(48),		PORT_DATA_IO_PU(49),
-
-	PORT_DATA_IO_PU(50),		PORT_DATA_IO_PU(51),
-	PORT_DATA_IO_PU(52),		PORT_DATA_IO_PU(53),
-	PORT_DATA_IO_PU(54),		PORT_DATA_IO_PU(55),
-	PORT_DATA_IO_PU(56),		PORT_DATA_IO_PU(57),
-	PORT_DATA_IO_PU(58),		PORT_DATA_IO_PU(59),
-
-	PORT_DATA_IO_PU(60),		PORT_DATA_IO_PU(61),
-	PORT_DATA_IO(62),		PORT_DATA_O(63),
-	PORT_DATA_O(64),		PORT_DATA_IO_PU(65),
-	PORT_DATA_O(66),		PORT_DATA_IO_PU(67),  /*66?*/
-	PORT_DATA_O(68),		PORT_DATA_IO(69),
-
-	PORT_DATA_IO(70),		PORT_DATA_IO(71),
-	PORT_DATA_O(72),		PORT_DATA_I_PU(73),
-	PORT_DATA_I_PU_PD(74),		PORT_DATA_IO_PU_PD(75),
-	PORT_DATA_IO_PU_PD(76),		PORT_DATA_IO_PU_PD(77),
-	PORT_DATA_IO_PU_PD(78),		PORT_DATA_IO_PU_PD(79),
-
-	PORT_DATA_IO_PU_PD(80),		PORT_DATA_IO_PU_PD(81),
-	PORT_DATA_IO_PU_PD(82),		PORT_DATA_IO_PU_PD(83),
-	PORT_DATA_IO_PU_PD(84),		PORT_DATA_IO_PU_PD(85),
-	PORT_DATA_IO_PU_PD(86),		PORT_DATA_IO_PU_PD(87),
-	PORT_DATA_IO_PU_PD(88),		PORT_DATA_IO_PU_PD(89),
-
-	PORT_DATA_IO_PU_PD(90),		PORT_DATA_IO_PU_PD(91),
-	PORT_DATA_IO_PU_PD(92),		PORT_DATA_IO_PU_PD(93),
-	PORT_DATA_IO_PU_PD(94),		PORT_DATA_IO_PU_PD(95),
-	PORT_DATA_IO_PU(96),		PORT_DATA_IO_PU_PD(97),
-	PORT_DATA_IO_PU_PD(98),		PORT_DATA_O(99), /*99?*/
-
-	PORT_DATA_IO_PD(100),		PORT_DATA_IO_PD(101),
-	PORT_DATA_IO_PD(102),		PORT_DATA_IO_PD(103),
-	PORT_DATA_IO_PD(104),		PORT_DATA_IO_PD(105),
-	PORT_DATA_IO_PU(106),		PORT_DATA_IO_PU(107),
-	PORT_DATA_IO_PU(108),		PORT_DATA_IO_PU(109),
-
-	PORT_DATA_IO_PU(110),		PORT_DATA_IO_PU(111),
-	PORT_DATA_IO_PD(112),		PORT_DATA_IO_PD(113),
-	PORT_DATA_IO_PU(114),		PORT_DATA_IO_PU(115),
-	PORT_DATA_IO_PU(116),		PORT_DATA_IO_PU(117),
-	PORT_DATA_IO_PU(118),		PORT_DATA_IO_PU(119),
-
-	PORT_DATA_IO_PU(120),		PORT_DATA_IO_PD(121),
-	PORT_DATA_IO_PD(122),		PORT_DATA_IO_PD(123),
-	PORT_DATA_IO_PD(124),		PORT_DATA_IO_PD(125),
-	PORT_DATA_IO_PD(126),		PORT_DATA_IO_PD(127),
-	PORT_DATA_IO_PD(128),		PORT_DATA_IO_PU_PD(129),
-
-	PORT_DATA_IO_PU_PD(130),	PORT_DATA_IO_PU_PD(131),
-	PORT_DATA_IO_PU_PD(132),	PORT_DATA_IO_PU_PD(133),
-	PORT_DATA_IO_PU_PD(134),	PORT_DATA_IO_PU_PD(135),
-	PORT_DATA_IO_PD(136),		PORT_DATA_IO_PD(137),
-	PORT_DATA_IO_PD(138),		PORT_DATA_IO_PD(139),
-
-	PORT_DATA_IO_PD(140),		PORT_DATA_IO_PD(141),
-	PORT_DATA_IO_PD(142),		PORT_DATA_IO_PU_PD(143),
-	PORT_DATA_IO_PD(144),		PORT_DATA_IO_PD(145),
-	PORT_DATA_IO_PD(146),		PORT_DATA_IO_PD(147),
-	PORT_DATA_IO_PD(148),		PORT_DATA_IO_PD(149),
-
-	PORT_DATA_IO_PD(150),		PORT_DATA_IO_PD(151),
-	PORT_DATA_IO_PU_PD(152),	PORT_DATA_I_PD(153),
-	PORT_DATA_IO_PU_PD(154),	PORT_DATA_I_PD(155),
-	PORT_DATA_IO_PD(156),		PORT_DATA_IO_PD(157),
-	PORT_DATA_I_PD(158),		PORT_DATA_IO_PD(159),
-
-	PORT_DATA_O(160),		PORT_DATA_IO_PD(161),
-	PORT_DATA_IO_PD(162),		PORT_DATA_IO_PD(163),
-	PORT_DATA_I_PD(164),		PORT_DATA_IO_PD(165),
-	PORT_DATA_I_PD(166),		PORT_DATA_I_PD(167),
-	PORT_DATA_I_PD(168),		PORT_DATA_I_PD(169),
-
-	PORT_DATA_I_PD(170),		PORT_DATA_O(171),
-	PORT_DATA_IO_PU_PD(172),	PORT_DATA_IO_PU_PD(173),
-	PORT_DATA_IO_PU_PD(174),	PORT_DATA_IO_PU_PD(175),
-	PORT_DATA_IO_PU_PD(176),	PORT_DATA_IO_PU_PD(177),
-	PORT_DATA_IO_PU_PD(178),	PORT_DATA_O(179),
-
-	PORT_DATA_IO_PU_PD(180),	PORT_DATA_IO_PU_PD(181),
-	PORT_DATA_IO_PU_PD(182),	PORT_DATA_IO_PU_PD(183),
-	PORT_DATA_IO_PU_PD(184),	PORT_DATA_O(185),
-	PORT_DATA_IO_PU_PD(186),	PORT_DATA_IO_PU_PD(187),
-	PORT_DATA_IO_PU_PD(188),	PORT_DATA_IO_PU_PD(189),
-
-	PORT_DATA_IO_PU_PD(190),
+static const pinmux_enum_t pinmux_data[] = {
+	PINMUX_DATA_GP_ALL(),
 
 	/* IRQ */
 	PINMUX_DATA(IRQ0_6_MARK,	PORT6_FN0, 	MSEL1CR_0_0),
@@ -958,8 +839,128 @@ static const pinmux_enum_t pinmux_data[] = {
 	PINMUX_DATA(MFIv4_MARK,		MSEL4CR_6_1),
 };
 
+#define SH7372_PIN(pin, cfgs)						\
+	{								\
+		.name = __stringify(PORT##pin),				\
+		.enum_id = PORT##pin##_DATA,				\
+		.configs = cfgs,					\
+	}
+
+#define __I		(SH_PFC_PIN_CFG_INPUT)
+#define __O		(SH_PFC_PIN_CFG_OUTPUT)
+#define __IO		(SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
+#define __PD		(SH_PFC_PIN_CFG_PULL_DOWN)
+#define __PU		(SH_PFC_PIN_CFG_PULL_UP)
+#define __PUD		(SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
+
+#define SH7372_PIN_I_PD(pin)		SH7372_PIN(pin, __I | __PD)
+#define SH7372_PIN_I_PU(pin)		SH7372_PIN(pin, __I | __PU)
+#define SH7372_PIN_I_PU_PD(pin)		SH7372_PIN(pin, __I | __PUD)
+#define SH7372_PIN_IO(pin)		SH7372_PIN(pin, __IO)
+#define SH7372_PIN_IO_PD(pin)		SH7372_PIN(pin, __IO | __PD)
+#define SH7372_PIN_IO_PU(pin)		SH7372_PIN(pin, __IO | __PU)
+#define SH7372_PIN_IO_PU_PD(pin)	SH7372_PIN(pin, __IO | __PUD)
+#define SH7372_PIN_O(pin)		SH7372_PIN(pin, __O)
+#define SH7372_PIN_O_PU_PD(pin)		SH7372_PIN(pin, __O | __PUD)
+
 static struct sh_pfc_pin pinmux_pins[] = {
-	GPIO_PORT_ALL(),
+	/* Table 57-1 (I/O and Pull U/D) */
+	SH7372_PIN_IO_PD(0),		SH7372_PIN_IO_PD(1),
+	SH7372_PIN_O(2),		SH7372_PIN_I_PD(3),
+	SH7372_PIN_I_PD(4),		SH7372_PIN_I_PD(5),
+	SH7372_PIN_IO_PU_PD(6),		SH7372_PIN_I_PD(7),
+	SH7372_PIN_IO_PD(8),		SH7372_PIN_O(9),
+	SH7372_PIN_O(10),		SH7372_PIN_O(11),
+	SH7372_PIN_IO_PU_PD(12),	SH7372_PIN_IO_PD(13),
+	SH7372_PIN_IO_PD(14),		SH7372_PIN_O(15),
+	SH7372_PIN_IO_PD(16),		SH7372_PIN_IO_PD(17),
+	SH7372_PIN_I_PD(18),		SH7372_PIN_IO(19),
+	SH7372_PIN_IO(20),		SH7372_PIN_IO(21),
+	SH7372_PIN_IO(22),		SH7372_PIN_IO(23),
+	SH7372_PIN_IO(24),		SH7372_PIN_IO(25),
+	SH7372_PIN_IO(26),		SH7372_PIN_IO(27),
+	SH7372_PIN_IO(28),		SH7372_PIN_IO(29),
+	SH7372_PIN_IO(30),		SH7372_PIN_IO(31),
+	SH7372_PIN_IO(32),		SH7372_PIN_IO(33),
+	SH7372_PIN_IO(34),		SH7372_PIN_IO(35),
+	SH7372_PIN_IO(36),		SH7372_PIN_IO(37),
+	SH7372_PIN_IO(38),		SH7372_PIN_IO(39),
+	SH7372_PIN_IO(40),		SH7372_PIN_IO(41),
+	SH7372_PIN_IO(42),		SH7372_PIN_IO(43),
+	SH7372_PIN_IO(44),		SH7372_PIN_IO(45),
+	SH7372_PIN_IO_PU(46),		SH7372_PIN_IO_PU(47),
+	SH7372_PIN_IO_PU(48),		SH7372_PIN_IO_PU(49),
+	SH7372_PIN_IO_PU(50),		SH7372_PIN_IO_PU(51),
+	SH7372_PIN_IO_PU(52),		SH7372_PIN_IO_PU(53),
+	SH7372_PIN_IO_PU(54),		SH7372_PIN_IO_PU(55),
+	SH7372_PIN_IO_PU(56),		SH7372_PIN_IO_PU(57),
+	SH7372_PIN_IO_PU(58),		SH7372_PIN_IO_PU(59),
+	SH7372_PIN_IO_PU(60),		SH7372_PIN_IO_PU(61),
+	SH7372_PIN_IO(62),		SH7372_PIN_O(63),
+	SH7372_PIN_O(64),		SH7372_PIN_IO_PU(65),
+	SH7372_PIN_O_PU_PD(66),		SH7372_PIN_IO_PU(67),
+	SH7372_PIN_O(68),		SH7372_PIN_IO(69),
+	SH7372_PIN_IO(70),		SH7372_PIN_IO(71),
+	SH7372_PIN_O(72),		SH7372_PIN_I_PU(73),
+	SH7372_PIN_I_PU_PD(74),		SH7372_PIN_IO_PU_PD(75),
+	SH7372_PIN_IO_PU_PD(76),	SH7372_PIN_IO_PU_PD(77),
+	SH7372_PIN_IO_PU_PD(78),	SH7372_PIN_IO_PU_PD(79),
+	SH7372_PIN_IO_PU_PD(80),	SH7372_PIN_IO_PU_PD(81),
+	SH7372_PIN_IO_PU_PD(82),	SH7372_PIN_IO_PU_PD(83),
+	SH7372_PIN_IO_PU_PD(84),	SH7372_PIN_IO_PU_PD(85),
+	SH7372_PIN_IO_PU_PD(86),	SH7372_PIN_IO_PU_PD(87),
+	SH7372_PIN_IO_PU_PD(88),	SH7372_PIN_IO_PU_PD(89),
+	SH7372_PIN_IO_PU_PD(90),	SH7372_PIN_IO_PU_PD(91),
+	SH7372_PIN_IO_PU_PD(92),	SH7372_PIN_IO_PU_PD(93),
+	SH7372_PIN_IO_PU_PD(94),	SH7372_PIN_IO_PU_PD(95),
+	SH7372_PIN_IO_PU(96),		SH7372_PIN_IO_PU_PD(97),
+	SH7372_PIN_IO_PU_PD(98),	SH7372_PIN_O_PU_PD(99),
+	SH7372_PIN_IO_PD(100),		SH7372_PIN_IO_PD(101),
+	SH7372_PIN_IO_PD(102),		SH7372_PIN_IO_PD(103),
+	SH7372_PIN_IO_PD(104),		SH7372_PIN_IO_PD(105),
+	SH7372_PIN_IO_PU(106),		SH7372_PIN_IO_PU(107),
+	SH7372_PIN_IO_PU(108),		SH7372_PIN_IO_PU(109),
+	SH7372_PIN_IO_PU(110),		SH7372_PIN_IO_PU(111),
+	SH7372_PIN_IO_PD(112),		SH7372_PIN_IO_PD(113),
+	SH7372_PIN_IO_PU(114),		SH7372_PIN_IO_PU(115),
+	SH7372_PIN_IO_PU(116),		SH7372_PIN_IO_PU(117),
+	SH7372_PIN_IO_PU(118),		SH7372_PIN_IO_PU(119),
+	SH7372_PIN_IO_PU(120),		SH7372_PIN_IO_PD(121),
+	SH7372_PIN_IO_PD(122),		SH7372_PIN_IO_PD(123),
+	SH7372_PIN_IO_PD(124),		SH7372_PIN_IO_PD(125),
+	SH7372_PIN_IO_PD(126),		SH7372_PIN_IO_PD(127),
+	SH7372_PIN_IO_PD(128),		SH7372_PIN_IO_PU_PD(129),
+	SH7372_PIN_IO_PU_PD(130),	SH7372_PIN_IO_PU_PD(131),
+	SH7372_PIN_IO_PU_PD(132),	SH7372_PIN_IO_PU_PD(133),
+	SH7372_PIN_IO_PU_PD(134),	SH7372_PIN_IO_PU_PD(135),
+	SH7372_PIN_IO_PD(136),		SH7372_PIN_IO_PD(137),
+	SH7372_PIN_IO_PD(138),		SH7372_PIN_IO_PD(139),
+	SH7372_PIN_IO_PD(140),		SH7372_PIN_IO_PD(141),
+	SH7372_PIN_IO_PD(142),		SH7372_PIN_IO_PU_PD(143),
+	SH7372_PIN_IO_PD(144),		SH7372_PIN_IO_PD(145),
+	SH7372_PIN_IO_PD(146),		SH7372_PIN_IO_PD(147),
+	SH7372_PIN_IO_PD(148),		SH7372_PIN_IO_PD(149),
+	SH7372_PIN_IO_PD(150),		SH7372_PIN_IO_PD(151),
+	SH7372_PIN_IO_PU_PD(152),	SH7372_PIN_I_PD(153),
+	SH7372_PIN_IO_PU_PD(154),	SH7372_PIN_I_PD(155),
+	SH7372_PIN_IO_PD(156),		SH7372_PIN_IO_PD(157),
+	SH7372_PIN_I_PD(158),		SH7372_PIN_IO_PD(159),
+	SH7372_PIN_O(160),		SH7372_PIN_IO_PD(161),
+	SH7372_PIN_IO_PD(162),		SH7372_PIN_IO_PD(163),
+	SH7372_PIN_I_PD(164),		SH7372_PIN_IO_PD(165),
+	SH7372_PIN_I_PD(166),		SH7372_PIN_I_PD(167),
+	SH7372_PIN_I_PD(168),		SH7372_PIN_I_PD(169),
+	SH7372_PIN_I_PD(170),		SH7372_PIN_O(171),
+	SH7372_PIN_IO_PU_PD(172),	SH7372_PIN_IO_PU_PD(173),
+	SH7372_PIN_IO_PU_PD(174),	SH7372_PIN_IO_PU_PD(175),
+	SH7372_PIN_IO_PU_PD(176),	SH7372_PIN_IO_PU_PD(177),
+	SH7372_PIN_IO_PU_PD(178),	SH7372_PIN_O(179),
+	SH7372_PIN_IO_PU_PD(180),	SH7372_PIN_IO_PU_PD(181),
+	SH7372_PIN_IO_PU_PD(182),	SH7372_PIN_IO_PU_PD(183),
+	SH7372_PIN_IO_PU_PD(184),	SH7372_PIN_O(185),
+	SH7372_PIN_IO_PU_PD(186),	SH7372_PIN_IO_PU_PD(187),
+	SH7372_PIN_IO_PU_PD(188),	SH7372_PIN_IO_PU_PD(189),
+	SH7372_PIN_IO_PU_PD(190),
 };
 
 /* - BSC -------------------------------------------------------------------- */
@@ -2136,6 +2137,17 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(usb1),
 };
 
+#undef PORTCR
+#define PORTCR(nr, reg)							\
+	{								\
+		PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {		\
+			_PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT),     \
+				PORT##nr##_FN0, PORT##nr##_FN1,		\
+				PORT##nr##_FN2, PORT##nr##_FN3,		\
+				PORT##nr##_FN4, PORT##nr##_FN5,		\
+				PORT##nr##_FN6, PORT##nr##_FN7 }	\
+	}
+
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 	PORTCR(0,	0xE6051000), /* PORT0CR */
 	PORTCR(1,	0xE6051001), /* PORT1CR */
@@ -2568,11 +2580,80 @@ static const struct pinmux_irq pinmux_irqs[] = {
 	PINMUX_IRQ(EXT_IRQ16H(31), 138, 184),
 };
 
+#define PORTnCR_PULMD_OFF	(0 << 6)
+#define PORTnCR_PULMD_DOWN	(2 << 6)
+#define PORTnCR_PULMD_UP	(3 << 6)
+#define PORTnCR_PULMD_MASK	(3 << 6)
+
+struct sh7372_portcr_group {
+	unsigned int end_pin;
+	unsigned int offset;
+};
+
+static const struct sh7372_portcr_group sh7372_portcr_offsets[] = {
+	{ 45,  0x1000 }, { 75,  0x2000 }, { 99,  0x0000 }, { 120, 0x3000 },
+	{ 151, 0x0000 }, { 155, 0x3000 }, { 166, 0x0000 }, { 190, 0x2000 },
+};
+
+static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
+{
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(sh7372_portcr_offsets); ++i) {
+		const struct sh7372_portcr_group *group +			&sh7372_portcr_offsets[i];
+
+		if (i <= group->end_pin)
+			return pfc->window->virt + group->offset + pin;
+	}
+
+	return NULL;
+}
+
+static unsigned int sh7372_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
+{
+	void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
+	u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
+
+	switch (value) {
+	case PORTnCR_PULMD_UP:
+		return PIN_CONFIG_BIAS_PULL_UP;
+	case PORTnCR_PULMD_DOWN:
+		return PIN_CONFIG_BIAS_PULL_DOWN;
+	case PORTnCR_PULMD_OFF:
+	default:
+		return PIN_CONFIG_BIAS_DISABLE;
+	}
+}
+
+static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+				   unsigned int bias)
+{
+	void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
+	u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
+
+	switch (bias) {
+	case PIN_CONFIG_BIAS_PULL_UP:
+		value |= PORTnCR_PULMD_UP;
+		break;
+	case PIN_CONFIG_BIAS_PULL_DOWN:
+		value |= PORTnCR_PULMD_DOWN;
+		break;
+	}
+
+	iowrite8(value, addr);
+}
+
+static const struct sh_pfc_soc_operations sh7372_pinmux_ops = {
+	.get_bias = sh7372_pinmux_get_bias,
+	.set_bias = sh7372_pinmux_set_bias,
+};
+
 const struct sh_pfc_soc_info sh7372_pinmux_info = {
 	.name = "sh7372_pfc",
+	.ops = &sh7372_pinmux_ops,
+
 	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-	.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
-	.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
 	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
-- 
1.8.2.1

[PATCH 059/130] sh-pfc: r8a7740: Add SCIF pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 346 +++++++++++++++++++++++++++++++++++
 1 file changed, 346 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 4753f54..58b0284 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -1999,6 +1999,28 @@ static const unsigned int mmc0_ctrl_1_pins[] = {
 static const unsigned int mmc0_ctrl_1_mux[] = {
 	MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
 };
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+	/* RXD, TXD */
+	197, 198,
+};
+static const unsigned int scifa0_data_mux[] = {
+	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+	/* SCK */
+	188,
+};
+static const unsigned int scifa0_clk_mux[] = {
+	SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+	/* RTS, CTS */
+	194, 193,
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+	SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
+};
 /* - SCIFA1 ----------------------------------------------------------------- */
 static const unsigned int scifa1_data_pins[] = {
 	/* RXD, TXD */
@@ -2007,6 +2029,230 @@ static const unsigned int scifa1_data_pins[] = {
 static const unsigned int scifa1_data_mux[] = {
 	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
 };
+static const unsigned int scifa1_clk_pins[] = {
+	/* SCK */
+	185,
+};
+static const unsigned int scifa1_clk_mux[] = {
+	SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+	/* RTS, CTS */
+	23, 21,
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+	SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_pins[] = {
+	/* RXD, TXD */
+	200, 201,
+};
+static const unsigned int scifa2_data_mux[] = {
+	SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
+};
+static const unsigned int scifa2_clk_0_pins[] = {
+	/* SCK */
+	22,
+};
+static const unsigned int scifa2_clk_0_mux[] = {
+	SCIFA2_SCK_PORT22_MARK,
+};
+static const unsigned int scifa2_clk_1_pins[] = {
+	/* SCK */
+	199,
+};
+static const unsigned int scifa2_clk_1_mux[] = {
+	SCIFA2_SCK_PORT199_MARK,
+};
+static const unsigned int scifa2_ctrl_pins[] = {
+	/* RTS, CTS */
+	96, 95,
+};
+static const unsigned int scifa2_ctrl_mux[] = {
+	SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
+};
+/* - SCIFA3 ----------------------------------------------------------------- */
+static const unsigned int scifa3_data_0_pins[] = {
+	/* RXD, TXD */
+	174, 175,
+};
+static const unsigned int scifa3_data_0_mux[] = {
+	SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
+};
+static const unsigned int scifa3_clk_0_pins[] = {
+	/* SCK */
+	116,
+};
+static const unsigned int scifa3_clk_0_mux[] = {
+	SCIFA3_SCK_PORT116_MARK,
+};
+static const unsigned int scifa3_ctrl_0_pins[] = {
+	/* RTS, CTS */
+	105, 117,
+};
+static const unsigned int scifa3_ctrl_0_mux[] = {
+	SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
+};
+static const unsigned int scifa3_data_1_pins[] = {
+	/* RXD, TXD */
+	159, 160,
+};
+static const unsigned int scifa3_data_1_mux[] = {
+	SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
+};
+static const unsigned int scifa3_clk_1_pins[] = {
+	/* SCK */
+	158,
+};
+static const unsigned int scifa3_clk_1_mux[] = {
+	SCIFA3_SCK_PORT158_MARK,
+};
+static const unsigned int scifa3_ctrl_1_pins[] = {
+	/* RTS, CTS */
+	161, 162,
+};
+static const unsigned int scifa3_ctrl_1_mux[] = {
+	SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
+};
+/* - SCIFA4 ----------------------------------------------------------------- */
+static const unsigned int scifa4_data_0_pins[] = {
+	/* RXD, TXD */
+	12, 13,
+};
+static const unsigned int scifa4_data_0_mux[] = {
+	SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
+};
+static const unsigned int scifa4_data_1_pins[] = {
+	/* RXD, TXD */
+	204, 203,
+};
+static const unsigned int scifa4_data_1_mux[] = {
+	SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
+};
+static const unsigned int scifa4_data_2_pins[] = {
+	/* RXD, TXD */
+	94, 93,
+};
+static const unsigned int scifa4_data_2_mux[] = {
+	SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
+};
+static const unsigned int scifa4_clk_0_pins[] = {
+	/* SCK */
+	21,
+};
+static const unsigned int scifa4_clk_0_mux[] = {
+	SCIFA4_SCK_PORT21_MARK,
+};
+static const unsigned int scifa4_clk_1_pins[] = {
+	/* SCK */
+	205,
+};
+static const unsigned int scifa4_clk_1_mux[] = {
+	SCIFA4_SCK_PORT205_MARK,
+};
+/* - SCIFA5 ----------------------------------------------------------------- */
+static const unsigned int scifa5_data_0_pins[] = {
+	/* RXD, TXD */
+	10, 20,
+};
+static const unsigned int scifa5_data_0_mux[] = {
+	SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
+};
+static const unsigned int scifa5_data_1_pins[] = {
+	/* RXD, TXD */
+	207, 208,
+};
+static const unsigned int scifa5_data_1_mux[] = {
+	SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
+};
+static const unsigned int scifa5_data_2_pins[] = {
+	/* RXD, TXD */
+	92, 91,
+};
+static const unsigned int scifa5_data_2_mux[] = {
+	SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
+};
+static const unsigned int scifa5_clk_0_pins[] = {
+	/* SCK */
+	23,
+};
+static const unsigned int scifa5_clk_0_mux[] = {
+	SCIFA5_SCK_PORT23_MARK,
+};
+static const unsigned int scifa5_clk_1_pins[] = {
+	/* SCK */
+	206,
+};
+static const unsigned int scifa5_clk_1_mux[] = {
+	SCIFA5_SCK_PORT206_MARK,
+};
+/* - SCIFA6 ----------------------------------------------------------------- */
+static const unsigned int scifa6_data_pins[] = {
+	/* RXD, TXD */
+	25, 26,
+};
+static const unsigned int scifa6_data_mux[] = {
+	SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
+};
+static const unsigned int scifa6_clk_pins[] = {
+	/* SCK */
+	24,
+};
+static const unsigned int scifa6_clk_mux[] = {
+	SCIFA6_SCK_MARK,
+};
+/* - SCIFA7 ----------------------------------------------------------------- */
+static const unsigned int scifa7_data_pins[] = {
+	/* RXD, TXD */
+	0, 1,
+};
+static const unsigned int scifa7_data_mux[] = {
+	SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
+};
+/* - SCIFB ------------------------------------------------------------------ */
+static const unsigned int scifb_data_0_pins[] = {
+	/* RXD, TXD */
+	191, 192,
+};
+static const unsigned int scifb_data_0_mux[] = {
+	SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
+};
+static const unsigned int scifb_clk_0_pins[] = {
+	/* SCK */
+	190,
+};
+static const unsigned int scifb_clk_0_mux[] = {
+	SCIFB_SCK_PORT190_MARK,
+};
+static const unsigned int scifb_ctrl_0_pins[] = {
+	/* RTS, CTS */
+	186, 187,
+};
+static const unsigned int scifb_ctrl_0_mux[] = {
+	SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
+};
+static const unsigned int scifb_data_1_pins[] = {
+	/* RXD, TXD */
+	3, 4,
+};
+static const unsigned int scifb_data_1_mux[] = {
+	SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
+};
+static const unsigned int scifb_clk_1_pins[] = {
+	/* SCK */
+	2,
+};
+static const unsigned int scifb_clk_1_mux[] = {
+	SCIFB_SCK_PORT2_MARK,
+};
+static const unsigned int scifb_ctrl_1_pins[] = {
+	/* RTS, CTS */
+	172, 173,
+};
+static const unsigned int scifb_ctrl_1_mux[] = {
+	SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
+};
 /* - SDHI0 ------------------------------------------------------------------ */
 static const unsigned int sdhi0_data1_pins[] = {
 	/* D0 */
@@ -2212,7 +2458,41 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(mmc0_data4_1),
 	SH_PFC_PIN_GROUP(mmc0_data8_1),
 	SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+	SH_PFC_PIN_GROUP(scifa0_data),
+	SH_PFC_PIN_GROUP(scifa0_clk),
+	SH_PFC_PIN_GROUP(scifa0_ctrl),
 	SH_PFC_PIN_GROUP(scifa1_data),
+	SH_PFC_PIN_GROUP(scifa1_clk),
+	SH_PFC_PIN_GROUP(scifa1_ctrl),
+	SH_PFC_PIN_GROUP(scifa2_data),
+	SH_PFC_PIN_GROUP(scifa2_clk_0),
+	SH_PFC_PIN_GROUP(scifa2_clk_1),
+	SH_PFC_PIN_GROUP(scifa2_ctrl),
+	SH_PFC_PIN_GROUP(scifa3_data_0),
+	SH_PFC_PIN_GROUP(scifa3_clk_0),
+	SH_PFC_PIN_GROUP(scifa3_ctrl_0),
+	SH_PFC_PIN_GROUP(scifa3_data_1),
+	SH_PFC_PIN_GROUP(scifa3_clk_1),
+	SH_PFC_PIN_GROUP(scifa3_ctrl_1),
+	SH_PFC_PIN_GROUP(scifa4_data_0),
+	SH_PFC_PIN_GROUP(scifa4_data_1),
+	SH_PFC_PIN_GROUP(scifa4_data_2),
+	SH_PFC_PIN_GROUP(scifa4_clk_0),
+	SH_PFC_PIN_GROUP(scifa4_clk_1),
+	SH_PFC_PIN_GROUP(scifa5_data_0),
+	SH_PFC_PIN_GROUP(scifa5_data_1),
+	SH_PFC_PIN_GROUP(scifa5_data_2),
+	SH_PFC_PIN_GROUP(scifa5_clk_0),
+	SH_PFC_PIN_GROUP(scifa5_clk_1),
+	SH_PFC_PIN_GROUP(scifa6_data),
+	SH_PFC_PIN_GROUP(scifa6_clk),
+	SH_PFC_PIN_GROUP(scifa7_data),
+	SH_PFC_PIN_GROUP(scifb_data_0),
+	SH_PFC_PIN_GROUP(scifb_clk_0),
+	SH_PFC_PIN_GROUP(scifb_ctrl_0),
+	SH_PFC_PIN_GROUP(scifb_data_1),
+	SH_PFC_PIN_GROUP(scifb_clk_1),
+	SH_PFC_PIN_GROUP(scifb_ctrl_1),
 	SH_PFC_PIN_GROUP(sdhi0_data1),
 	SH_PFC_PIN_GROUP(sdhi0_data4),
 	SH_PFC_PIN_GROUP(sdhi0_ctrl),
@@ -2325,8 +2605,66 @@ static const char * const mmc0_groups[] = {
 	"mmc0_ctrl_1",
 };
 
+static const char * const scifa0_groups[] = {
+	"scifa0_data",
+	"scifa0_clk",
+	"scifa0_ctrl",
+};
+
 static const char * const scifa1_groups[] = {
 	"scifa1_data",
+	"scifa1_clk",
+	"scifa1_ctrl",
+};
+
+static const char * const scifa2_groups[] = {
+	"scifa2_data",
+	"scifa2_clk_0",
+	"scifa2_clk_1",
+	"scifa2_ctrl",
+};
+
+static const char * const scifa3_groups[] = {
+	"scifa3_data_0",
+	"scifa3_clk_0",
+	"scifa3_ctrl_0",
+	"scifa3_data_1",
+	"scifa3_clk_1",
+	"scifa3_ctrl_1",
+};
+
+static const char * const scifa4_groups[] = {
+	"scifa4_data_0",
+	"scifa4_data_1",
+	"scifa4_data_2",
+	"scifa4_clk_0",
+	"scifa4_clk_1",
+};
+
+static const char * const scifa5_groups[] = {
+	"scifa5_data_0",
+	"scifa5_data_1",
+	"scifa5_data_2",
+	"scifa5_clk_0",
+	"scifa5_clk_1",
+};
+
+static const char * const scifa6_groups[] = {
+	"scifa6_data",
+	"scifa6_clk",
+};
+
+static const char * const scifa7_groups[] = {
+	"scifa7_data",
+};
+
+static const char * const scifb_groups[] = {
+	"scifb_data_0",
+	"scifb_clk_0",
+	"scifb_ctrl_0",
+	"scifb_data_1",
+	"scifb_clk_1",
+	"scifb_ctrl_1",
 };
 
 static const char * const sdhi0_groups[] = {
@@ -2359,7 +2697,15 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(lcd0),
 	SH_PFC_FUNCTION(lcd1),
 	SH_PFC_FUNCTION(mmc0),
+	SH_PFC_FUNCTION(scifa0),
 	SH_PFC_FUNCTION(scifa1),
+	SH_PFC_FUNCTION(scifa2),
+	SH_PFC_FUNCTION(scifa3),
+	SH_PFC_FUNCTION(scifa4),
+	SH_PFC_FUNCTION(scifa5),
+	SH_PFC_FUNCTION(scifa6),
+	SH_PFC_FUNCTION(scifa7),
+	SH_PFC_FUNCTION(scifb),
 	SH_PFC_FUNCTION(sdhi0),
 	SH_PFC_FUNCTION(sdhi1),
 	SH_PFC_FUNCTION(sdhi2),
-- 
1.8.2.1

[PATCH 060/130] sh-pfc: r8a7740: Declare missing INTC function

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

When adding the INTC pin groups the INTC function hasn't been added to
the functions list. Fix it.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 58b0284..da00bc4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -2694,6 +2694,7 @@ static const char * const sdhi2_groups[] = {
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(intc),
 	SH_PFC_FUNCTION(lcd0),
 	SH_PFC_FUNCTION(lcd1),
 	SH_PFC_FUNCTION(mmc0),
-- 
1.8.2.1

[PATCH 061/130] sh-pfc: r8a7740: Add BSC pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 155 +++++++++++++++++++++++++++++++++++
 1 file changed, 155 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index da00bc4..f17a39a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -1674,6 +1674,127 @@ static struct sh_pfc_pin pinmux_pins[] = {
 	GPIO_PORT_ALL(),
 };
 
+/* - BSC -------------------------------------------------------------------- */
+static const unsigned int bsc_data8_pins[] = {
+	/* D[0:7] */
+	157, 156, 155, 154, 153, 152, 151, 150,
+};
+static const unsigned int bsc_data8_mux[] = {
+	D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+	D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+};
+static const unsigned int bsc_data16_pins[] = {
+	/* D[0:15] */
+	157, 156, 155, 154, 153, 152, 151, 150,
+	149, 148, 147, 146, 145, 144, 143, 142,
+};
+static const unsigned int bsc_data16_mux[] = {
+	D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+	D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+	D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+	D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+};
+static const unsigned int bsc_data32_pins[] = {
+	/* D[0:31] */
+	157, 156, 155, 154, 153, 152, 151, 150,
+	149, 148, 147, 146, 145, 144, 143, 142,
+	171, 170, 169, 168, 167, 166, 173, 172,
+	165, 164, 163, 162, 161, 160, 159, 158,
+};
+static const unsigned int bsc_data32_mux[] = {
+	D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+	D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+	D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+	D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+	D16_MARK, D17_MARK, D18_MARK, D19_MARK,
+	D20_MARK, D21_MARK, D22_MARK, D23_MARK,
+	D24_MARK, D25_MARK, D26_MARK, D27_MARK,
+	D28_MARK, D29_MARK, D30_MARK, D31_MARK,
+};
+static const unsigned int bsc_cs0_pins[] = {
+	/* CS */
+	109,
+};
+static const unsigned int bsc_cs0_mux[] = {
+	CS0_MARK,
+};
+static const unsigned int bsc_cs2_pins[] = {
+	/* CS */
+	110,
+};
+static const unsigned int bsc_cs2_mux[] = {
+	CS2_MARK,
+};
+static const unsigned int bsc_cs4_pins[] = {
+	/* CS */
+	111,
+};
+static const unsigned int bsc_cs4_mux[] = {
+	CS4_MARK,
+};
+static const unsigned int bsc_cs5a_0_pins[] = {
+	/* CS */
+	105,
+};
+static const unsigned int bsc_cs5a_0_mux[] = {
+	CS5A_PORT105_MARK,
+};
+static const unsigned int bsc_cs5a_1_pins[] = {
+	/* CS */
+	19,
+};
+static const unsigned int bsc_cs5a_1_mux[] = {
+	CS5A_PORT19_MARK,
+};
+static const unsigned int bsc_cs5b_pins[] = {
+	/* CS */
+	103,
+};
+static const unsigned int bsc_cs5b_mux[] = {
+	CS5B_MARK,
+};
+static const unsigned int bsc_cs6a_pins[] = {
+	/* CS */
+	104,
+};
+static const unsigned int bsc_cs6a_mux[] = {
+	CS6A_MARK,
+};
+static const unsigned int bsc_rd_we8_pins[] = {
+	/* RD, WE[0] */
+	115, 113,
+};
+static const unsigned int bsc_rd_we8_mux[] = {
+	RD_FSC_MARK, WE0_FWE_MARK,
+};
+static const unsigned int bsc_rd_we16_pins[] = {
+	/* RD, WE[0:1] */
+	115, 113, 112,
+};
+static const unsigned int bsc_rd_we16_mux[] = {
+	RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
+};
+static const unsigned int bsc_rd_we32_pins[] = {
+	/* RD, WE[0:3] */
+	115, 113, 112, 108, 107,
+};
+static const unsigned int bsc_rd_we32_mux[] = {
+	RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
+};
+static const unsigned int bsc_bs_pins[] = {
+	/* BS */
+	175,
+};
+static const unsigned int bsc_bs_mux[] = {
+	BS_MARK,
+};
+static const unsigned int bsc_rdwr_pins[] = {
+	/* RDWR */
+	114,
+};
+static const unsigned int bsc_rdwr_mux[] = {
+	RDWR_MARK,
+};
 /* - INTC ------------------------------------------------------------------- */
 IRQC_PINS_MUX(0, 0, 2);
 IRQC_PINS_MUX(0, 1, 13);
@@ -2377,6 +2498,21 @@ static const unsigned int sdhi2_wp_1_mux[] = {
 };
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SH_PFC_PIN_GROUP(bsc_data8),
+	SH_PFC_PIN_GROUP(bsc_data16),
+	SH_PFC_PIN_GROUP(bsc_data32),
+	SH_PFC_PIN_GROUP(bsc_cs0),
+	SH_PFC_PIN_GROUP(bsc_cs2),
+	SH_PFC_PIN_GROUP(bsc_cs4),
+	SH_PFC_PIN_GROUP(bsc_cs5a_0),
+	SH_PFC_PIN_GROUP(bsc_cs5a_1),
+	SH_PFC_PIN_GROUP(bsc_cs5b),
+	SH_PFC_PIN_GROUP(bsc_cs6a),
+	SH_PFC_PIN_GROUP(bsc_rd_we8),
+	SH_PFC_PIN_GROUP(bsc_rd_we16),
+	SH_PFC_PIN_GROUP(bsc_rd_we32),
+	SH_PFC_PIN_GROUP(bsc_bs),
+	SH_PFC_PIN_GROUP(bsc_rdwr),
 	SH_PFC_PIN_GROUP(intc_irq0_0),
 	SH_PFC_PIN_GROUP(intc_irq0_1),
 	SH_PFC_PIN_GROUP(intc_irq1),
@@ -2512,6 +2648,24 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(sdhi2_wp_1),
 };
 
+static const char * const bsc_groups[] = {
+	"bsc_data8",
+	"bsc_data16",
+	"bsc_data32",
+	"bsc_cs0",
+	"bsc_cs2",
+	"bsc_cs4",
+	"bsc_cs5a_0",
+	"bsc_cs5a_1",
+	"bsc_cs5b",
+	"bsc_cs6a",
+	"bsc_rd_we8",
+	"bsc_rd_we16",
+	"bsc_rd_we32",
+	"bsc_bs",
+	"bsc_rdwr",
+};
+
 static const char * const intc_groups[] = {
 	"intc_irq0_0",
 	"intc_irq0_1",
@@ -2694,6 +2848,7 @@ static const char * const sdhi2_groups[] = {
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(bsc),
 	SH_PFC_FUNCTION(intc),
 	SH_PFC_FUNCTION(lcd0),
 	SH_PFC_FUNCTION(lcd1),
-- 
1.8.2.1

[PATCH 062/130] sh-pfc: r8a7740: Add GETHER pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 82 ++++++++++++++++++++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index f17a39a..1b98990 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -1795,6 +1795,72 @@ static const unsigned int bsc_rdwr_pins[] = {
 static const unsigned int bsc_rdwr_mux[] = {
 	RDWR_MARK,
 };
+/* - GETHER ----------------------------------------------------------------- */
+static const unsigned int gether_rmii_pins[] = {
+	/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
+	195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
+};
+static const unsigned int gether_rmii_mux[] = {
+	RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
+	RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
+	RMII_MDC_MARK, RMII_MDIO_MARK,
+};
+static const unsigned int gether_mii_pins[] = {
+	/* RXD[0:3], RX_CLK, RX_DV, RX_ER
+	 * TXD[0:3], TX_CLK, TX_EN, TX_ER
+	 * CRS, COL, MDC, MDIO,
+	 */
+	185, 186, 187, 188, 174, 161, 204,
+	171, 170, 169, 168, 184, 183, 203,
+	205, 163, 206, 207,
+};
+static const unsigned int gether_mii_mux[] = {
+	ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
+	ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
+	ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
+	ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
+	ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
+};
+static const unsigned int gether_gmii_pins[] = {
+	/* RXD[0:7], RX_CLK, RX_DV, RX_ER
+	 * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
+	 * CRS, COL, MDC, MDIO, REF125CK_MARK,
+	 */
+	185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
+	171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
+	205, 163, 206, 207,
+};
+static const unsigned int gether_gmii_mux[] = {
+	ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
+	ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
+	ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
+	ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
+	ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
+	ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
+	ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
+	RMII_REF125CK_MARK,
+};
+static const unsigned int gether_int_pins[] = {
+	/* PHY_INT */
+	164,
+};
+static const unsigned int gether_int_mux[] = {
+	ET_PHY_INT_MARK,
+};
+static const unsigned int gether_link_pins[] = {
+	/* LINK */
+	177,
+};
+static const unsigned int gether_link_mux[] = {
+	ET_LINK_MARK,
+};
+static const unsigned int gether_wol_pins[] = {
+	/* WOL */
+	175,
+};
+static const unsigned int gether_wol_mux[] = {
+	ET_WOL_MARK,
+};
 /* - INTC ------------------------------------------------------------------- */
 IRQC_PINS_MUX(0, 0, 2);
 IRQC_PINS_MUX(0, 1, 13);
@@ -2513,6 +2579,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(bsc_rd_we32),
 	SH_PFC_PIN_GROUP(bsc_bs),
 	SH_PFC_PIN_GROUP(bsc_rdwr),
+	SH_PFC_PIN_GROUP(gether_rmii),
+	SH_PFC_PIN_GROUP(gether_mii),
+	SH_PFC_PIN_GROUP(gether_gmii),
+	SH_PFC_PIN_GROUP(gether_int),
+	SH_PFC_PIN_GROUP(gether_link),
+	SH_PFC_PIN_GROUP(gether_wol),
 	SH_PFC_PIN_GROUP(intc_irq0_0),
 	SH_PFC_PIN_GROUP(intc_irq0_1),
 	SH_PFC_PIN_GROUP(intc_irq1),
@@ -2666,6 +2738,15 @@ static const char * const bsc_groups[] = {
 	"bsc_rdwr",
 };
 
+static const char * const gether_groups[] = {
+	"gether_rmii",
+	"gether_mii",
+	"gether_gmii",
+	"gether_int",
+	"gether_link",
+	"gether_wol",
+};
+
 static const char * const intc_groups[] = {
 	"intc_irq0_0",
 	"intc_irq0_1",
@@ -2849,6 +2930,7 @@ static const char * const sdhi2_groups[] = {
 
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(bsc),
+	SH_PFC_FUNCTION(gether),
 	SH_PFC_FUNCTION(intc),
 	SH_PFC_FUNCTION(lcd0),
 	SH_PFC_FUNCTION(lcd1),
-- 
1.8.2.1

[PATCH 063/130] sh-pfc: r8a7740: Add CEU pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 124 +++++++++++++++++++++++++++++++++++
 1 file changed, 124 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 1b98990..71d7c1f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -1795,6 +1795,98 @@ static const unsigned int bsc_rdwr_pins[] = {
 static const unsigned int bsc_rdwr_mux[] = {
 	RDWR_MARK,
 };
+/* - CEU0 ------------------------------------------------------------------- */
+static const unsigned int ceu0_data_0_7_pins[] = {
+	/* D[0:7] */
+	34, 33, 32, 31, 30, 29, 28, 27,
+};
+static const unsigned int ceu0_data_0_7_mux[] = {
+	VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
+	VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
+};
+static const unsigned int ceu0_data_8_15_0_pins[] = {
+	/* D[8:15] */
+	182, 181, 180, 179, 178, 26, 25, 24,
+};
+static const unsigned int ceu0_data_8_15_0_mux[] = {
+	VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
+	VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
+	VIO0_D15_PORT24_MARK,
+};
+static const unsigned int ceu0_data_8_15_1_pins[] = {
+	/* D[8:15] */
+	182, 181, 180, 179, 178, 22, 95, 96,
+};
+static const unsigned int ceu0_data_8_15_1_mux[] = {
+	VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
+	VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
+	VIO0_D15_PORT96_MARK,
+};
+static const unsigned int ceu0_clk_0_pins[] = {
+	/* CKO */
+	36,
+};
+static const unsigned int ceu0_clk_0_mux[] = {
+	VIO_CKO_MARK,
+};
+static const unsigned int ceu0_clk_1_pins[] = {
+	/* CKO */
+	14,
+};
+static const unsigned int ceu0_clk_1_mux[] = {
+	VIO_CKO1_MARK,
+};
+static const unsigned int ceu0_clk_2_pins[] = {
+	/* CKO */
+	15,
+};
+static const unsigned int ceu0_clk_2_mux[] = {
+	VIO_CKO2_MARK,
+};
+static const unsigned int ceu0_sync_pins[] = {
+	/* CLK, VD, HD */
+	35, 39, 37,
+};
+static const unsigned int ceu0_sync_mux[] = {
+	VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
+};
+static const unsigned int ceu0_field_pins[] = {
+	/* FIELD */
+	38,
+};
+static const unsigned int ceu0_field_mux[] = {
+	VIO0_FIELD_MARK,
+};
+/* - CEU1 ------------------------------------------------------------------- */
+static const unsigned int ceu1_data_pins[] = {
+	/* D[0:7] */
+	182, 181, 180, 179, 178, 26, 25, 24,
+};
+static const unsigned int ceu1_data_mux[] = {
+	VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
+	VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
+};
+static const unsigned int ceu1_clk_pins[] = {
+	/* CKO */
+	23,
+};
+static const unsigned int ceu1_clk_mux[] = {
+	VIO_CKO_1_MARK,
+};
+static const unsigned int ceu1_sync_pins[] = {
+	/* CLK, VD, HD */
+	197, 198, 160,
+};
+static const unsigned int ceu1_sync_mux[] = {
+	VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
+};
+static const unsigned int ceu1_field_pins[] = {
+	/* FIELD */
+	21,
+};
+static const unsigned int ceu1_field_mux[] = {
+	VIO1_FIELD_MARK,
+};
 /* - GETHER ----------------------------------------------------------------- */
 static const unsigned int gether_rmii_pins[] = {
 	/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
@@ -2579,6 +2671,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(bsc_rd_we32),
 	SH_PFC_PIN_GROUP(bsc_bs),
 	SH_PFC_PIN_GROUP(bsc_rdwr),
+	SH_PFC_PIN_GROUP(ceu0_data_0_7),
+	SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
+	SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
+	SH_PFC_PIN_GROUP(ceu0_clk_0),
+	SH_PFC_PIN_GROUP(ceu0_clk_1),
+	SH_PFC_PIN_GROUP(ceu0_clk_2),
+	SH_PFC_PIN_GROUP(ceu0_sync),
+	SH_PFC_PIN_GROUP(ceu0_field),
+	SH_PFC_PIN_GROUP(ceu1_data),
+	SH_PFC_PIN_GROUP(ceu1_clk),
+	SH_PFC_PIN_GROUP(ceu1_sync),
+	SH_PFC_PIN_GROUP(ceu1_field),
 	SH_PFC_PIN_GROUP(gether_rmii),
 	SH_PFC_PIN_GROUP(gether_mii),
 	SH_PFC_PIN_GROUP(gether_gmii),
@@ -2738,6 +2842,24 @@ static const char * const bsc_groups[] = {
 	"bsc_rdwr",
 };
 
+static const char * const ceu0_groups[] = {
+	"ceu0_data_0_7",
+	"ceu0_data_8_15_0",
+	"ceu0_data_8_15_1",
+	"ceu0_clk_0",
+	"ceu0_clk_1",
+	"ceu0_clk_2",
+	"ceu0_sync",
+	"ceu0_field",
+};
+
+static const char * const ceu1_groups[] = {
+	"ceu1_data",
+	"ceu1_clk",
+	"ceu1_sync",
+	"ceu1_field",
+};
+
 static const char * const gether_groups[] = {
 	"gether_rmii",
 	"gether_mii",
@@ -2930,6 +3052,8 @@ static const char * const sdhi2_groups[] = {
 
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(bsc),
+	SH_PFC_FUNCTION(ceu0),
+	SH_PFC_FUNCTION(ceu1),
 	SH_PFC_FUNCTION(gether),
 	SH_PFC_FUNCTION(intc),
 	SH_PFC_FUNCTION(lcd0),
-- 
1.8.2.1

[PATCH 064/130] sh-pfc: r8a7740: Add FSI pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 118 +++++++++++++++++++++++++++++++++++
 1 file changed, 118 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 71d7c1f..49da76a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -1887,6 +1887,92 @@ static const unsigned int ceu1_field_pins[] = {
 static const unsigned int ceu1_field_mux[] = {
 	VIO1_FIELD_MARK,
 };
+/* - FSIA ------------------------------------------------------------------- */
+static const unsigned int fsia_mclk_in_pins[] = {
+	/* CK */
+	11,
+};
+static const unsigned int fsia_mclk_in_mux[] = {
+	FSIACK_MARK,
+};
+static const unsigned int fsia_mclk_out_pins[] = {
+	/* OMC */
+	10,
+};
+static const unsigned int fsia_mclk_out_mux[] = {
+	FSIAOMC_MARK,
+};
+static const unsigned int fsia_sclk_in_pins[] = {
+	/* ILR, IBT */
+	12, 13,
+};
+static const unsigned int fsia_sclk_in_mux[] = {
+	FSIAILR_MARK, FSIAIBT_MARK,
+};
+static const unsigned int fsia_sclk_out_pins[] = {
+	/* OLR, OBT */
+	7, 8,
+};
+static const unsigned int fsia_sclk_out_mux[] = {
+	FSIAOLR_MARK, FSIAOBT_MARK,
+};
+static const unsigned int fsia_data_in_0_pins[] = {
+	/* ISLD */
+	0,
+};
+static const unsigned int fsia_data_in_0_mux[] = {
+	FSIAISLD_PORT0_MARK,
+};
+static const unsigned int fsia_data_in_1_pins[] = {
+	/* ISLD */
+	5,
+};
+static const unsigned int fsia_data_in_1_mux[] = {
+	FSIAISLD_PORT5_MARK,
+};
+static const unsigned int fsia_data_out_0_pins[] = {
+	/* OSLD */
+	9,
+};
+static const unsigned int fsia_data_out_0_mux[] = {
+	FSIAOSLD_MARK,
+};
+static const unsigned int fsia_data_out_1_pins[] = {
+	/* OSLD */
+	0,
+};
+static const unsigned int fsia_data_out_1_mux[] = {
+	FSIAOSLD1_MARK,
+};
+static const unsigned int fsia_data_out_2_pins[] = {
+	/* OSLD */
+	1,
+};
+static const unsigned int fsia_data_out_2_mux[] = {
+	FSIAOSLD2_MARK,
+};
+static const unsigned int fsia_spdif_0_pins[] = {
+	/* SPDIF */
+	9,
+};
+static const unsigned int fsia_spdif_0_mux[] = {
+	FSIASPDIF_PORT9_MARK,
+};
+static const unsigned int fsia_spdif_1_pins[] = {
+	/* SPDIF */
+	18,
+};
+static const unsigned int fsia_spdif_1_mux[] = {
+	FSIASPDIF_PORT18_MARK,
+};
+/* - FSIB ------------------------------------------------------------------- */
+static const unsigned int fsib_mclk_in_pins[] = {
+	/* CK */
+	11,
+};
+static const unsigned int fsib_mclk_in_mux[] = {
+	FSIBCK_MARK,
+};
 /* - GETHER ----------------------------------------------------------------- */
 static const unsigned int gether_rmii_pins[] = {
 	/* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
@@ -2683,6 +2769,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(ceu1_clk),
 	SH_PFC_PIN_GROUP(ceu1_sync),
 	SH_PFC_PIN_GROUP(ceu1_field),
+	SH_PFC_PIN_GROUP(fsia_mclk_in),
+	SH_PFC_PIN_GROUP(fsia_mclk_out),
+	SH_PFC_PIN_GROUP(fsia_sclk_in),
+	SH_PFC_PIN_GROUP(fsia_sclk_out),
+	SH_PFC_PIN_GROUP(fsia_data_in_0),
+	SH_PFC_PIN_GROUP(fsia_data_in_1),
+	SH_PFC_PIN_GROUP(fsia_data_out_0),
+	SH_PFC_PIN_GROUP(fsia_data_out_1),
+	SH_PFC_PIN_GROUP(fsia_data_out_2),
+	SH_PFC_PIN_GROUP(fsia_spdif_0),
+	SH_PFC_PIN_GROUP(fsia_spdif_1),
+	SH_PFC_PIN_GROUP(fsib_mclk_in),
 	SH_PFC_PIN_GROUP(gether_rmii),
 	SH_PFC_PIN_GROUP(gether_mii),
 	SH_PFC_PIN_GROUP(gether_gmii),
@@ -2860,6 +2958,24 @@ static const char * const ceu1_groups[] = {
 	"ceu1_field",
 };
 
+static const char * const fsia_groups[] = {
+	"fsia_mclk_in",
+	"fsia_mclk_out",
+	"fsia_sclk_in",
+	"fsia_sclk_out",
+	"fsia_data_in_0",
+	"fsia_data_in_1",
+	"fsia_data_out_0",
+	"fsia_data_out_1",
+	"fsia_data_out_2",
+	"fsia_spdif_0",
+	"fsia_spdif_1",
+};
+
+static const char * const fsib_groups[] = {
+	"fsib_mclk_in",
+};
+
 static const char * const gether_groups[] = {
 	"gether_rmii",
 	"gether_mii",
@@ -3054,6 +3170,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(bsc),
 	SH_PFC_FUNCTION(ceu0),
 	SH_PFC_FUNCTION(ceu1),
+	SH_PFC_FUNCTION(fsia),
+	SH_PFC_FUNCTION(fsib),
 	SH_PFC_FUNCTION(gether),
 	SH_PFC_FUNCTION(intc),
 	SH_PFC_FUNCTION(lcd0),
-- 
1.8.2.1

[PATCH 065/130] sh-pfc: r8a7740: Add HDMI pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 49da76a..5a77d39 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -2039,6 +2039,14 @@ static const unsigned int gether_wol_pins[] = {
 static const unsigned int gether_wol_mux[] = {
 	ET_WOL_MARK,
 };
+/* - HDMI ------------------------------------------------------------------- */
+static const unsigned int hdmi_pins[] = {
+	/* HPD, CEC */
+	210, 211,
+};
+static const unsigned int hdmi_mux[] = {
+	HDMI_HPD_MARK, HDMI_CEC_MARK,
+};
 /* - INTC ------------------------------------------------------------------- */
 IRQC_PINS_MUX(0, 0, 2);
 IRQC_PINS_MUX(0, 1, 13);
@@ -2787,6 +2795,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(gether_int),
 	SH_PFC_PIN_GROUP(gether_link),
 	SH_PFC_PIN_GROUP(gether_wol),
+	SH_PFC_PIN_GROUP(hdmi),
 	SH_PFC_PIN_GROUP(intc_irq0_0),
 	SH_PFC_PIN_GROUP(intc_irq0_1),
 	SH_PFC_PIN_GROUP(intc_irq1),
@@ -2985,6 +2994,10 @@ static const char * const gether_groups[] = {
 	"gether_wol",
 };
 
+static const char * const hdmi_groups[] = {
+	"hdmi",
+};
+
 static const char * const intc_groups[] = {
 	"intc_irq0_0",
 	"intc_irq0_1",
@@ -3173,6 +3186,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(fsia),
 	SH_PFC_FUNCTION(fsib),
 	SH_PFC_FUNCTION(gether),
+	SH_PFC_FUNCTION(hdmi),
 	SH_PFC_FUNCTION(intc),
 	SH_PFC_FUNCTION(lcd0),
 	SH_PFC_FUNCTION(lcd1),
-- 
1.8.2.1

[PATCH 066/130] sh-pfc: r8a7740: Hardcode the LCDC0 output

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The r8a7740 has two LCDC units and two sets of LCDC output signals. By
default LCDC0 is routed to the LCD0 signals, and LCDC1 to the LCD1
signals. However, LCDC1 can be routed to the LCD0 signals by setting bit
MSEL6 in MSEL3CR (the LCD0 signals are further pinmuxed the usual way).

This could be configured by duplicating the LCD0 pin groups for LCDC1.
However, this would unnecessarily complicate the LCD pin groups, as no
r8a7740 board supported in mainline use such a configuration. Hardcode
the MSEL3CR MSEL6 bit to 0 for now.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 14 +-------------
 1 file changed, 1 insertion(+), 13 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 5a77d39..9afc7b0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -277,8 +277,6 @@ enum {
 	SCIFB_CTS_PORT173_MARK,
 
 	/* LCD0 */
-	LCDC0_SELECT_MARK,
-
 	LCD0_D0_MARK,	LCD0_D1_MARK,	LCD0_D2_MARK,	LCD0_D3_MARK,
 	LCD0_D4_MARK,	LCD0_D5_MARK,	LCD0_D6_MARK,	LCD0_D7_MARK,
 	LCD0_D8_MARK,	LCD0_D9_MARK,	LCD0_D10_MARK,	LCD0_D11_MARK,
@@ -301,8 +299,6 @@ enum {
 	LCD0_LCLK_PORT102_MARK,
 
 	/* LCD1 */
-	LCDC1_SELECT_MARK,
-
 	LCD1_D0_MARK,	LCD1_D1_MARK,	LCD1_D2_MARK,	LCD1_D3_MARK,
 	LCD1_D4_MARK,	LCD1_D5_MARK,	LCD1_D6_MARK,	LCD1_D7_MARK,
 	LCD1_D8_MARK,	LCD1_D9_MARK,	LCD1_D10_MARK,	LCD1_D11_MARK,
@@ -1002,7 +998,7 @@ static const pinmux_enum_t pinmux_data[] = {
 	PINMUX_DATA(IRQ27_PORT57_MARK,		PORT57_FN0,	MSEL1CR_27_1),
 
 	/* Port58 */
-	PINMUX_DATA(LCD0_D0_MARK,		PORT58_FN1),
+	PINMUX_DATA(LCD0_D0_MARK,		PORT58_FN1,	MSEL3CR_6_0),
 	PINMUX_DATA(KEYOUT7_MARK,		PORT58_FN3),
 	PINMUX_DATA(KEYIN0_PORT58_MARK,		PORT58_FN4,	MSEL4CR_18_1),
 	PINMUX_DATA(DV_D0_MARK,			PORT58_FN6),
@@ -1649,10 +1645,6 @@ static const pinmux_enum_t pinmux_data[] = {
 	PINMUX_DATA(IRQ16_PORT211_MARK,		PORT211_FN0,	MSEL1CR_16_1),
 	PINMUX_DATA(HDMI_CEC_MARK,		PORT211_FN1),
 
-	/* LCDC select */
-	PINMUX_DATA(LCDC0_SELECT_MARK,				MSEL3CR_6_0),
-	PINMUX_DATA(LCDC1_SELECT_MARK,				MSEL3CR_6_1),
-
 	/* SDENC */
 	PINMUX_DATA(SDENC_CPG_MARK,				MSEL4CR_19_0),
 	PINMUX_DATA(SDENC_DV_CLKI_MARK,				MSEL4CR_19_1),
@@ -3578,10 +3570,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	/* IRREM */
 	GPIO_FN(IROUT),
 
-	/* LCDC */
-	GPIO_FN(LCDC0_SELECT),
-	GPIO_FN(LCDC1_SELECT),
-
 	/* SDENC */
 	GPIO_FN(SDENC_CPG),
 	GPIO_FN(SDENC_DV_CLKI),
-- 
1.8.2.1

[PATCH 067/130] ARM: shmobile: armadillo800eva: Register pinctrl mapping for INTC

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based INTC pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-armadillo800eva.c | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index b85b288..8d8b362 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -1065,6 +1065,12 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
 				  "sdhi0_ctrl", "sdhi0"),
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
 				  "sdhi0_wp", "sdhi0"),
+	/* ST1232 */
+	PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-r8a7740",
+				  "intc_irq10", "intc"),
+	/* USBHS */
+	PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7740",
+				  "intc_irq7_1", "intc"),
 };
 
 static void __init eva_clock_init(void)
@@ -1130,7 +1136,7 @@ static void __init eva_init(void)
 	gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
 
 	/* Touchscreen */
-	gpio_request(GPIO_FN_IRQ10,	NULL); /* TP_INT */
+	gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
 
 	/* GETHER */
 	gpio_request(GPIO_FN_ET_CRS,		NULL);
@@ -1163,13 +1169,11 @@ static void __init eva_init(void)
 	} else {
 		/* USB Func */
 		/*
-		 * A1 chip has 2 IRQ7 pin and it was controled by MSEL register.
-		 * OTOH, usbhs interrupt needs its value (HI/LOW) to decide
-		 * USB connection/disconnection (usbhsf_get_vbus()).
-		 * This means we needs to select GPIO_FN_IRQ7_PORT209 first,
-		 * and select GPIO 209 here
+		 * The USBHS interrupt handlers needs to read the IRQ pin value
+		 * (HI/LOW) to diffentiate USB connection and disconnection
+		 * events (usbhsf_get_vbus()). We thus need to select both the
+		 * intc_irq7_1 pin group and GPIO 209 here.
 		 */
-		gpio_request(GPIO_FN_IRQ7_PORT209, NULL);
 		gpio_request_one(209, GPIOF_IN, NULL);
 
 		platform_device_register(&usbhsf_device);
-- 
1.8.2.1

[PATCH 068/130] ARM: shmobile: armadillo800eva: Register pinctrl mapping for GETHER

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based GETHER pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-armadillo800eva.c | 25 +++++--------------------
 1 file changed, 5 insertions(+), 20 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 8d8b362..328f650 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -1046,6 +1046,11 @@ static struct platform_device *eva_devices[] __initdata = {
 };
 
 static const struct pinctrl_map eva_pinctrl_map[] = {
+	/* GETHER */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
+				  "gether_mii", "gether"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
+				  "gether_int", "gether"),
 	/* LCD0 */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
 				  "lcd0_data24_0", "lcd0"),
@@ -1139,26 +1144,6 @@ static void __init eva_init(void)
 	gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
 
 	/* GETHER */
-	gpio_request(GPIO_FN_ET_CRS,		NULL);
-	gpio_request(GPIO_FN_ET_MDC,		NULL);
-	gpio_request(GPIO_FN_ET_MDIO,		NULL);
-	gpio_request(GPIO_FN_ET_TX_ER,		NULL);
-	gpio_request(GPIO_FN_ET_RX_ER,		NULL);
-	gpio_request(GPIO_FN_ET_ERXD0,		NULL);
-	gpio_request(GPIO_FN_ET_ERXD1,		NULL);
-	gpio_request(GPIO_FN_ET_ERXD2,		NULL);
-	gpio_request(GPIO_FN_ET_ERXD3,		NULL);
-	gpio_request(GPIO_FN_ET_TX_CLK,		NULL);
-	gpio_request(GPIO_FN_ET_TX_EN,		NULL);
-	gpio_request(GPIO_FN_ET_ETXD0,		NULL);
-	gpio_request(GPIO_FN_ET_ETXD1,		NULL);
-	gpio_request(GPIO_FN_ET_ETXD2,		NULL);
-	gpio_request(GPIO_FN_ET_ETXD3,		NULL);
-	gpio_request(GPIO_FN_ET_PHY_INT,	NULL);
-	gpio_request(GPIO_FN_ET_COL,		NULL);
-	gpio_request(GPIO_FN_ET_RX_DV,		NULL);
-	gpio_request(GPIO_FN_ET_RX_CLK,		NULL);
-
 	gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
 
 	/* USB */
-- 
1.8.2.1

[PATCH 069/130] ARM: shmobile: armadillo800eva: Register pinctrl mapping for CEU0

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based CEU0 pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-armadillo800eva.c | 24 +++++++++---------------
 1 file changed, 9 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 328f650..4327f7e 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -1046,6 +1046,15 @@ static struct platform_device *eva_devices[] __initdata = {
 };
 
 static const struct pinctrl_map eva_pinctrl_map[] = {
+	/* CEU0 */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+				  "ceu0_data_0_7", "ceu0"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+				  "ceu0_clk_0", "ceu0"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+				  "ceu0_sync", "ceu0"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+				  "ceu0_field", "ceu0"),
 	/* GETHER */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
 				  "gether_mii", "gether"),
@@ -1165,21 +1174,6 @@ static void __init eva_init(void)
 		usb = &usbhsf_device;
 	}
 
-	/* CEU0 */
-	gpio_request(GPIO_FN_VIO0_D7,		NULL);
-	gpio_request(GPIO_FN_VIO0_D6,		NULL);
-	gpio_request(GPIO_FN_VIO0_D5,		NULL);
-	gpio_request(GPIO_FN_VIO0_D4,		NULL);
-	gpio_request(GPIO_FN_VIO0_D3,		NULL);
-	gpio_request(GPIO_FN_VIO0_D2,		NULL);
-	gpio_request(GPIO_FN_VIO0_D1,		NULL);
-	gpio_request(GPIO_FN_VIO0_D0,		NULL);
-	gpio_request(GPIO_FN_VIO0_CLK,		NULL);
-	gpio_request(GPIO_FN_VIO0_HD,		NULL);
-	gpio_request(GPIO_FN_VIO0_VD,		NULL);
-	gpio_request(GPIO_FN_VIO0_FIELD,	NULL);
-	gpio_request(GPIO_FN_VIO_CKO,		NULL);
-
 	/* CON1/CON15 Camera */
 	gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL);  /* STANDBY */
 	gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
-- 
1.8.2.1

[PATCH 070/130] ARM: shmobile: armadillo800eva: Register pinctrl mapping for FSI

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based FSI pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-armadillo800eva.c | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 4327f7e..4e1f8f3 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -1055,6 +1055,18 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
 				  "ceu0_sync", "ceu0"),
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
 				  "ceu0_field", "ceu0"),
+	/* FSIA */
+	PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+				  "fsia_sclk_in", "fsia"),
+	PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+				  "fsia_mclk_out", "fsia"),
+	PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+				  "fsia_data_in_1", "fsia"),
+	PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+				  "fsia_data_out_0", "fsia"),
+	/* FSIB */
+	PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-r8a7740",
+				  "fsib_mclk_in", "fsib"),
 	/* GETHER */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
 				  "gether_mii", "gether"),
@@ -1181,20 +1193,11 @@ static void __init eva_init(void)
 	gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL);  /* CAM_PON */
 
 	/* FSI-WM8978 */
-	gpio_request(GPIO_FN_FSIAIBT,		NULL);
-	gpio_request(GPIO_FN_FSIAILR,		NULL);
-	gpio_request(GPIO_FN_FSIAOMC,		NULL);
-	gpio_request(GPIO_FN_FSIAOSLD,		NULL);
-	gpio_request(GPIO_FN_FSIAISLD_PORT5,	NULL);
-
 	gpio_request(7, NULL);
 	gpio_request(8, NULL);
 	gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */
 	gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */
 
-	/* FSI-HDMI */
-	gpio_request(GPIO_FN_FSIBCK,		NULL);
-
 	/* HDMI */
 	gpio_request(GPIO_FN_HDMI_HPD,		NULL);
 	gpio_request(GPIO_FN_HDMI_CEC,		NULL);
-- 
1.8.2.1

[PATCH 071/130] ARM: shmobile: armadillo800eva: Register pinctrl mapping for HDMI

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based HDMI pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-armadillo800eva.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 4e1f8f3..dad4966 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -1072,6 +1072,9 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
 				  "gether_mii", "gether"),
 	PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
 				  "gether_int", "gether"),
+	/* HDMI */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-r8a7740",
+				  "hdmi", "hdmi"),
 	/* LCD0 */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
 				  "lcd0_data24_0", "lcd0"),
@@ -1198,10 +1201,6 @@ static void __init eva_init(void)
 	gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */
 	gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */
 
-	/* HDMI */
-	gpio_request(GPIO_FN_HDMI_HPD,		NULL);
-	gpio_request(GPIO_FN_HDMI_CEC,		NULL);
-
 	/*
 	 * CAUTION
 	 *
-- 
1.8.2.1

[PATCH 072/130] ARM: shmobile: armadillo800eva: Don't configure LCDC routing manually

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

LCDC routing is configured automatically in the PFC driver, don't
configure it manually in board code.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-armadillo800eva.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index dad4966..8ec6961 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -1159,8 +1159,6 @@ static void __init eva_init(void)
 	gpio_request(GPIO_FN_SCIFA1_TXD, NULL);
 
 	/* LCDC0 */
-	gpio_request(GPIO_FN_LCDC0_SELECT,	NULL);
-
 	gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
 	gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
 
-- 
1.8.2.1

[PATCH 073/130] ARM: shmobile: armadillo800eva: Replace GPIO_PORTx with GPIO port numbers

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The PFC GPIO API implementation moved to using port numbers. Replace all
GPIO_PORTx enum usage with the corresponding port number. The GPIO_PORTx
enum values are identical to the port number on this platform.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-armadillo800eva.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 8ec6961..aafa99b 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -584,7 +584,7 @@ static struct regulator_init_data vcc_sdhi0_init_data = {
 static struct fixed_voltage_config vcc_sdhi0_info = {
 	.supply_name = "SDHI0 Vcc",
 	.microvolts = 3300000,
-	.gpio = GPIO_PORT75,
+	.gpio = 75,
 	.enable_high = 1,
 	.init_data = &vcc_sdhi0_init_data,
 };
@@ -615,7 +615,7 @@ static struct regulator_init_data vccq_sdhi0_init_data = {
 };
 
 static struct gpio vccq_sdhi0_gpios[] = {
-	{GPIO_PORT17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" },
+	{17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" },
 };
 
 static struct gpio_regulator_state vccq_sdhi0_states[] = {
@@ -626,7 +626,7 @@ static struct gpio_regulator_state vccq_sdhi0_states[] = {
 static struct gpio_regulator_config vccq_sdhi0_info = {
 	.supply_name = "vqmmc",
 
-	.enable_gpio = GPIO_PORT74,
+	.enable_gpio = 74,
 	.enable_high = 1,
 	.enabled_at_boot = 0,
 
@@ -664,7 +664,7 @@ static struct regulator_init_data vcc_sdhi1_init_data = {
 static struct fixed_voltage_config vcc_sdhi1_info = {
 	.supply_name = "SDHI1 Vcc",
 	.microvolts = 3300000,
-	.gpio = GPIO_PORT16,
+	.gpio = 16,
 	.enable_high = 1,
 	.init_data = &vcc_sdhi1_init_data,
 };
@@ -693,7 +693,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
 	.tmio_caps	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
 			  MMC_CAP_POWER_OFF_CARD,
 	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
-	.cd_gpio	= GPIO_PORT167,
+	.cd_gpio	= 167,
 };
 
 static struct resource sdhi0_resources[] = {
@@ -736,7 +736,7 @@ static struct sh_mobile_sdhi_info sdhi1_info = {
 			  MMC_CAP_POWER_OFF_CARD,
 	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
 	/* Port72 cannot generate IRQs, will be used in polling mode. */
-	.cd_gpio	= GPIO_PORT72,
+	.cd_gpio	= 72,
 };
 
 static struct resource sdhi1_resources[] = {
-- 
1.8.2.1

[PATCH 074/130] ARM: shmobile: bonito: Remove empty core devices array

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The core devices array is empty, passing it to platform_add_devices() is
a no-op. Remove it.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-bonito.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index 70d992c..b111c13 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -331,12 +331,6 @@ static struct platform_device smsc_device = {
 };
 
 /*
- * core board devices
- */
-static struct platform_device *bonito_core_devices[] __initdata = {
-};
-
-/*
  * base board devices
  */
 static struct platform_device *bonito_base_devices[] __initdata = {
@@ -397,9 +391,6 @@ static void __init bonito_init(void)
 
 	r8a7740_add_standard_devices();
 
-	platform_add_devices(bonito_core_devices,
-			     ARRAY_SIZE(bonito_core_devices));
-
 	/*
 	 * base board settings
 	 */
-- 
1.8.2.1

[PATCH 075/130] ARM: shmobile: bonito: Register pinctrl mapping for SCIF

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based SCIF pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-bonito.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index b111c13..b6620662 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -369,6 +369,12 @@ static void __init bonito_map_io(void)
 #define VCCQ1CR		IOMEM(0xE6058140)
 #define VCCQ1LCDCR	IOMEM(0xE6058186)
 
+static const struct pinctrl_map scifa5_pinctrl_map[] = {
+	/* SCIFA5 */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.5", "pfc-r8a7740",
+				  "scifa5_data_2", "scifa5"),
+};
+
 static void __init bonito_init(void)
 {
 	u16 val;
@@ -423,8 +429,8 @@ static void __init bonito_init(void)
 		if (BIT_OFF(bsw2, 1) &&	/* S38.3 = ON */
 		    BIT_OFF(bsw3, 9) &&	/* S39.6 = ON */
 		    BIT_OFF(bsw4, 4)) {	/* S43.1 = ON */
-			gpio_request(GPIO_FN_SCIFA5_TXD_PORT91,	NULL);
-			gpio_request(GPIO_FN_SCIFA5_RXD_PORT92,	NULL);
+			pinctrl_register_mappings(scifa5_pinctrl_map,
+						  ARRAY_SIZE(scifa5_pinctrl_map));
 		}
 
 		/*
-- 
1.8.2.1

[PATCH 076/130] ARM: shmobile: bonito: Register pinctrl mapping for INTC

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based INTC pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-bonito.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index b6620662..5076f4d 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -369,6 +369,17 @@ static void __init bonito_map_io(void)
 #define VCCQ1CR		IOMEM(0xE6058140)
 #define VCCQ1LCDCR	IOMEM(0xE6058186)
 
+/*
+ * HACK: The FPGA mappings should be associated with the FPGA device, but we
+ * don't have one at the moment. Associate them with the PFC device to make
+ * sure they will be applied.
+ */
+static const struct pinctrl_map fpga_pinctrl_map[] = {
+	/* FPGA */
+	PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
+				  "intc_irq10", "intc"),
+};
+
 static const struct pinctrl_map scifa5_pinctrl_map[] = {
 	/* SCIFA5 */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.5", "pfc-r8a7740",
@@ -381,6 +392,8 @@ static void __init bonito_init(void)
 
 	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 
+	pinctrl_register_mappings(fpga_pinctrl_map,
+				  ARRAY_SIZE(fpga_pinctrl_map));
 	r8a7740_pinmux_init();
 	bonito_fpga_init();
 
@@ -412,7 +425,6 @@ static void __init bonito_init(void)
 		gpio_request(GPIO_FN_CS5B,		NULL);
 		gpio_request(GPIO_FN_CS6A,		NULL);
 		gpio_request(GPIO_FN_CS5A_PORT105,	NULL);
-		gpio_request(GPIO_FN_IRQ10,		NULL);
 
 		val = bonito_fpga_read(BVERR);
 		pr_info("bonito version: cpu %02x, base %02x\n",
-- 
1.8.2.1

[PATCH 077/130] ARM: shmobile: bonito: Register pinctrl mapping for BSC

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace the GPIO-based BSC pinmux configuration by a pinctrl mapping.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-bonito.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index 5076f4d..2781c7f 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -377,6 +377,12 @@ static void __init bonito_map_io(void)
 static const struct pinctrl_map fpga_pinctrl_map[] = {
 	/* FPGA */
 	PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
+				  "bsc_cs5a_0", "bsc"),
+	PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
+				  "bsc_cs5b", "bsc"),
+	PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
+				  "bsc_cs6a", "bsc"),
+	PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
 				  "intc_irq10", "intc"),
 };
 
@@ -419,13 +425,6 @@ static void __init bonito_init(void)
 		u16 bsw3;
 		u16 bsw4;
 
-		/*
-		 * FPGA
-		 */
-		gpio_request(GPIO_FN_CS5B,		NULL);
-		gpio_request(GPIO_FN_CS6A,		NULL);
-		gpio_request(GPIO_FN_CS5A_PORT105,	NULL);
-
 		val = bonito_fpga_read(BVERR);
 		pr_info("bonito version: cpu %02x, base %02x\n",
 			((val >> 8) & 0xFF),
-- 
1.8.2.1

[PATCH 078/130] ARM: shmobile: bonito: Don't configure LCDC routing manually

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

LCDC routing is configured automatically in the PFC driver, don't
configure it manually in board code.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-bonito.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index 2781c7f..b373e9c 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -451,7 +451,6 @@ static void __init bonito_init(void)
 		    BIT_ON(bsw2, 2)) {	/* S38.2 = OFF */
 			pinctrl_register_mappings(lcdc0_pinctrl_map,
 						  ARRAY_SIZE(lcdc0_pinctrl_map));
-			gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
 
 			gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
 					 NULL); /* LCDDON */
-- 
1.8.2.1

[PATCH 079/130] sh-pfc: r8a7740: Remove SCIF function GPIOS

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

All r8a7740 platforms now use the pinctrl API to control the SCIF pins,
the corresponding function GPIOS are unused. Remove them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 72 ------------------------------------
 1 file changed, 72 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 9afc7b0..3b53193 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -3261,78 +3261,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(FMSOIBT),	GPIO_FN(FMSOOLR),	GPIO_FN(FMSOOBT),
 	GPIO_FN(FMSOSLD),	GPIO_FN(FMSOCK),
 
-	/* SCIFA0 */
-	GPIO_FN(SCIFA0_SCK),	GPIO_FN(SCIFA0_CTS),	GPIO_FN(SCIFA0_RTS),
-	GPIO_FN(SCIFA0_RXD),	GPIO_FN(SCIFA0_TXD),
-
-	/* SCIFA1 */
-	GPIO_FN(SCIFA1_CTS),	GPIO_FN(SCIFA1_SCK),
-	GPIO_FN(SCIFA1_RXD),	GPIO_FN(SCIFA1_TXD),	GPIO_FN(SCIFA1_RTS),
-
-	/* SCIFA2 */
-	GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */
-	GPIO_FN(SCIFA2_SCK_PORT199),
-	GPIO_FN(SCIFA2_RXD),	GPIO_FN(SCIFA2_TXD),
-	GPIO_FN(SCIFA2_CTS),	GPIO_FN(SCIFA2_RTS),
-
-	/* SCIFA3 */
-	GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */
-	GPIO_FN(SCIFA3_SCK_PORT116),
-	GPIO_FN(SCIFA3_CTS_PORT117),
-	GPIO_FN(SCIFA3_RXD_PORT174),
-	GPIO_FN(SCIFA3_TXD_PORT175),
-
-	GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */
-	GPIO_FN(SCIFA3_SCK_PORT158),
-	GPIO_FN(SCIFA3_CTS_PORT162),
-	GPIO_FN(SCIFA3_RXD_PORT159),
-	GPIO_FN(SCIFA3_TXD_PORT160),
-
-	/* SCIFA4 */
-	GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */
-	GPIO_FN(SCIFA4_TXD_PORT13),
-
-	GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */
-	GPIO_FN(SCIFA4_TXD_PORT203),
-
-	GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */
-	GPIO_FN(SCIFA4_TXD_PORT93),
-
-	GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */
-	GPIO_FN(SCIFA4_SCK_PORT205),
-
-	/* SCIFA5 */
-	GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */
-	GPIO_FN(SCIFA5_RXD_PORT10),
-
-	GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */
-	GPIO_FN(SCIFA5_TXD_PORT208),
-
-	GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */
-	GPIO_FN(SCIFA5_RXD_PORT92),
-
-	GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */
-	GPIO_FN(SCIFA5_SCK_PORT206),
-
-	/* SCIFA6 */
-	GPIO_FN(SCIFA6_SCK),	GPIO_FN(SCIFA6_RXD),	GPIO_FN(SCIFA6_TXD),
-
-	/* SCIFA7 */
-	GPIO_FN(SCIFA7_TXD),	GPIO_FN(SCIFA7_RXD),
-
-	/* SCIFAB */
-	GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */
-	GPIO_FN(SCIFB_RXD_PORT191),
-	GPIO_FN(SCIFB_TXD_PORT192),
-	GPIO_FN(SCIFB_RTS_PORT186),
-	GPIO_FN(SCIFB_CTS_PORT187),
-
-	GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */
-	GPIO_FN(SCIFB_RXD_PORT3),
-	GPIO_FN(SCIFB_TXD_PORT4),
-	GPIO_FN(SCIFB_RTS_PORT172),
-	GPIO_FN(SCIFB_CTS_PORT173),
-
 	/* RSPI */
 	GPIO_FN(RSPI_SSL0_A),	GPIO_FN(RSPI_SSL1_A),	GPIO_FN(RSPI_SSL2_A),
 	GPIO_FN(RSPI_SSL3_A),	GPIO_FN(RSPI_CK_A),	GPIO_FN(RSPI_MOSI_A),
-- 
1.8.2.1

[PATCH 080/130] sh-pfc: r8a7740: Remove INTC function GPIOS

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

All r8a7740 platforms now use the pinctrl API to control the INTC pins,
the corresponding function GPIOS are unused. Remove them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 34 ----------------------------------
 1 file changed, 34 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 3b53193..0429c7d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -3200,40 +3200,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
 #define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
 
 static const struct pinmux_func pinmux_func_gpios[] = {
-	/* IRQ */
-	GPIO_FN(IRQ0_PORT2),	GPIO_FN(IRQ0_PORT13),
-	GPIO_FN(IRQ1),
-	GPIO_FN(IRQ2_PORT11),	GPIO_FN(IRQ2_PORT12),
-	GPIO_FN(IRQ3_PORT10),	GPIO_FN(IRQ3_PORT14),
-	GPIO_FN(IRQ4_PORT15),	GPIO_FN(IRQ4_PORT172),
-	GPIO_FN(IRQ5_PORT0),	GPIO_FN(IRQ5_PORT1),
-	GPIO_FN(IRQ6_PORT121),	GPIO_FN(IRQ6_PORT173),
-	GPIO_FN(IRQ7_PORT120),	GPIO_FN(IRQ7_PORT209),
-	GPIO_FN(IRQ8),
-	GPIO_FN(IRQ9_PORT118),	GPIO_FN(IRQ9_PORT210),
-	GPIO_FN(IRQ10),
-	GPIO_FN(IRQ11),
-	GPIO_FN(IRQ12_PORT42),	GPIO_FN(IRQ12_PORT97),
-	GPIO_FN(IRQ13_PORT64),	GPIO_FN(IRQ13_PORT98),
-	GPIO_FN(IRQ14_PORT63),	GPIO_FN(IRQ14_PORT99),
-	GPIO_FN(IRQ15_PORT62),	GPIO_FN(IRQ15_PORT100),
-	GPIO_FN(IRQ16_PORT68),	GPIO_FN(IRQ16_PORT211),
-	GPIO_FN(IRQ17),
-	GPIO_FN(IRQ18),
-	GPIO_FN(IRQ19),
-	GPIO_FN(IRQ20),
-	GPIO_FN(IRQ21),
-	GPIO_FN(IRQ22),
-	GPIO_FN(IRQ23),
-	GPIO_FN(IRQ24),
-	GPIO_FN(IRQ25),
-	GPIO_FN(IRQ26_PORT58),	GPIO_FN(IRQ26_PORT81),
-	GPIO_FN(IRQ27_PORT57),	GPIO_FN(IRQ27_PORT168),
-	GPIO_FN(IRQ28_PORT56),	GPIO_FN(IRQ28_PORT169),
-	GPIO_FN(IRQ29_PORT50),	GPIO_FN(IRQ29_PORT170),
-	GPIO_FN(IRQ30_PORT49),	GPIO_FN(IRQ30_PORT171),
-	GPIO_FN(IRQ31_PORT41),	GPIO_FN(IRQ31_PORT167),
-
 	/* Function */
 
 	/* DBGT */
-- 
1.8.2.1

[PATCH 081/130] sh-pfc: r8a7740: Remove BSC function GPIOS

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

All r8a7740 platforms now use the pinctrl API to control the BSC pins,
the corresponding function GPIOS are unused. Remove them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 26 ++------------------------
 1 file changed, 2 insertions(+), 24 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 0429c7d..c78eda8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -3377,11 +3377,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(BBIF2_TSCK2_PORT89),
 	GPIO_FN(BBIF2_TSYNC2_PORT184),
 
-	/* BSC / FLCTL / PCMCIA */
-	GPIO_FN(CS0),	GPIO_FN(CS2),	GPIO_FN(CS4),
-	GPIO_FN(CS5B),	GPIO_FN(CS6A),
-	GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */
-	GPIO_FN(CS5A_PORT19),
+	/* FLCTL / PCMCIA */
 	GPIO_FN(IOIS16), /* ? */
 
 	GPIO_FN(A0),	GPIO_FN(A1),	GPIO_FN(A2),	GPIO_FN(A3),
@@ -3393,25 +3389,7 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(A22),	GPIO_FN(A23),	GPIO_FN(A24),	GPIO_FN(A25),
 	GPIO_FN(A26),
 
-	GPIO_FN(D0_NAF0),	GPIO_FN(D1_NAF1),	/* share with FLCTL */
-	GPIO_FN(D2_NAF2),	GPIO_FN(D3_NAF3),	/* share with FLCTL */
-	GPIO_FN(D4_NAF4),	GPIO_FN(D5_NAF5),	/* share with FLCTL */
-	GPIO_FN(D6_NAF6),	GPIO_FN(D7_NAF7),	/* share with FLCTL */
-	GPIO_FN(D8_NAF8),	GPIO_FN(D9_NAF9),	/* share with FLCTL */
-	GPIO_FN(D10_NAF10),	GPIO_FN(D11_NAF11),	/* share with FLCTL */
-	GPIO_FN(D12_NAF12),	GPIO_FN(D13_NAF13),	/* share with FLCTL */
-	GPIO_FN(D14_NAF14),	GPIO_FN(D15_NAF15),	/* share with FLCTL */
-	GPIO_FN(D16),	GPIO_FN(D17),	GPIO_FN(D18),	GPIO_FN(D19),
-	GPIO_FN(D20),	GPIO_FN(D21),	GPIO_FN(D22),	GPIO_FN(D23),
-	GPIO_FN(D24),	GPIO_FN(D25),	GPIO_FN(D26),	GPIO_FN(D27),
-	GPIO_FN(D28),	GPIO_FN(D29),	GPIO_FN(D30),	GPIO_FN(D31),
-
-	GPIO_FN(WE0_FWE),	/* share with FLCTL */
-	GPIO_FN(WE1),
-	GPIO_FN(WE2_ICIORD),	/* share with PCMCIA */
-	GPIO_FN(WE3_ICIOWR),	/* share with PCMCIA */
-	GPIO_FN(CKO),	GPIO_FN(BS),	GPIO_FN(RDWR),
-	GPIO_FN(RD_FSC),	/* share with FLCTL */
+	GPIO_FN(CKO),
 	GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
 	GPIO_FN(WAIT_PORT90),
 
-- 
1.8.2.1

[PATCH 082/130] sh-pfc: r8a7740: Remove GETHER function GPIOS

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

All r8a7740 platforms now use the pinctrl API to control the GETHER
pins, the corresponding function GPIOS are unused. Remove them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 20 --------------------
 1 file changed, 20 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index c78eda8..58fbe6b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -3410,26 +3410,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(IDE_INT),	GPIO_FN(IDE_RST),	GPIO_FN(IDE_DIRECTION),
 	GPIO_FN(IDE_EXBUF_ENB),	GPIO_FN(IDE_IODACK),	GPIO_FN(IDE_IODREQ),
 
-	/* RMII */
-	GPIO_FN(RMII_CRS_DV),	GPIO_FN(RMII_RX_ER),	GPIO_FN(RMII_RXD0),
-	GPIO_FN(RMII_RXD1),	GPIO_FN(RMII_TX_EN),	GPIO_FN(RMII_TXD0),
-	GPIO_FN(RMII_MDC),	GPIO_FN(RMII_TXD1),	GPIO_FN(RMII_MDIO),
-	GPIO_FN(RMII_REF50CK),	GPIO_FN(RMII_REF125CK),	/* for GMII */
-
-	/* GEther */
-	GPIO_FN(ET_TX_CLK),	GPIO_FN(ET_TX_EN),	GPIO_FN(ET_ETXD0),
-	GPIO_FN(ET_ETXD1),	GPIO_FN(ET_ETXD2),	GPIO_FN(ET_ETXD3),
-	GPIO_FN(ET_ETXD4),	GPIO_FN(ET_ETXD5), /* for GEther */
-	GPIO_FN(ET_ETXD6),	GPIO_FN(ET_ETXD7), /* for GEther */
-	GPIO_FN(ET_COL),	GPIO_FN(ET_TX_ER),	GPIO_FN(ET_RX_CLK),
-	GPIO_FN(ET_RX_DV),	GPIO_FN(ET_ERXD0),	GPIO_FN(ET_ERXD1),
-	GPIO_FN(ET_ERXD2),	GPIO_FN(ET_ERXD3),
-	GPIO_FN(ET_ERXD4),	GPIO_FN(ET_ERXD5), /* for GEther */
-	GPIO_FN(ET_ERXD6),	GPIO_FN(ET_ERXD7), /* for GEther */
-	GPIO_FN(ET_RX_ER),	GPIO_FN(ET_CRS),	GPIO_FN(ET_MDC),
-	GPIO_FN(ET_MDIO),	GPIO_FN(ET_LINK),	GPIO_FN(ET_PHY_INT),
-	GPIO_FN(ET_WOL),	GPIO_FN(ET_GTX_CLK),
-
 	/* DMA0 */
 	GPIO_FN(DREQ0),	GPIO_FN(DACK0),
 
-- 
1.8.2.1

[PATCH 083/130] sh-pfc: r8a7740: Remove CEU function GPIOS

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

All r8a7740 platforms now use the pinctrl API to control the CEU pins,
the corresponding function GPIOS are unused. Remove them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 28 ----------------------------
 1 file changed, 28 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 58fbe6b..7ab4ff2 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -3232,34 +3232,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(RSPI_SSL3_A),	GPIO_FN(RSPI_CK_A),	GPIO_FN(RSPI_MOSI_A),
 	GPIO_FN(RSPI_MISO_A),
 
-	/* VIO CKO */
-	GPIO_FN(VIO_CKO1),
-	GPIO_FN(VIO_CKO2),
-	GPIO_FN(VIO_CKO_1),
-	GPIO_FN(VIO_CKO),
-
-	/* VIO0 */
-	GPIO_FN(VIO0_D0),	GPIO_FN(VIO0_D1),	GPIO_FN(VIO0_D2),
-	GPIO_FN(VIO0_D3),	GPIO_FN(VIO0_D4),	GPIO_FN(VIO0_D5),
-	GPIO_FN(VIO0_D6),	GPIO_FN(VIO0_D7),	GPIO_FN(VIO0_D8),
-	GPIO_FN(VIO0_D9),	GPIO_FN(VIO0_D10),	GPIO_FN(VIO0_D11),
-	GPIO_FN(VIO0_D12),	GPIO_FN(VIO0_VD),	GPIO_FN(VIO0_HD),
-	GPIO_FN(VIO0_CLK),	GPIO_FN(VIO0_FIELD),
-
-	GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
-	GPIO_FN(VIO0_D14_PORT25),
-	GPIO_FN(VIO0_D15_PORT24),
-
-	GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
-	GPIO_FN(VIO0_D14_PORT95),
-	GPIO_FN(VIO0_D15_PORT96),
-
-	/* VIO1 */
-	GPIO_FN(VIO1_D0),	GPIO_FN(VIO1_D1),	GPIO_FN(VIO1_D2),
-	GPIO_FN(VIO1_D3),	GPIO_FN(VIO1_D4),	GPIO_FN(VIO1_D5),
-	GPIO_FN(VIO1_D6),	GPIO_FN(VIO1_D7),	GPIO_FN(VIO1_VD),
-	GPIO_FN(VIO1_HD),	GPIO_FN(VIO1_CLK),	GPIO_FN(VIO1_FIELD),
-
 	/* TPU0 */
 	GPIO_FN(TPU0TO0),	GPIO_FN(TPU0TO1),	GPIO_FN(TPU0TO3),
 	GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
-- 
1.8.2.1

[PATCH 084/130] sh-pfc: r8a7740: Remove FSI function GPIOS

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

All r8a7740 platforms now use the pinctrl API to control the FSI pins,
the corresponding function GPIOS are unused. Remove them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 7ab4ff2..a93fd84 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -3207,18 +3207,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(DBGMD10),	GPIO_FN(DBGMD11),	GPIO_FN(DBGMD20),
 	GPIO_FN(DBGMD21),
 
-	/* FSI-A */
-	GPIO_FN(FSIAISLD_PORT0),	/* FSIAISLD Port 0/5 */
-	GPIO_FN(FSIAISLD_PORT5),
-	GPIO_FN(FSIASPDIF_PORT9),	/* FSIASPDIF Port 9/18 */
-	GPIO_FN(FSIASPDIF_PORT18),
-	GPIO_FN(FSIAOSLD1),	GPIO_FN(FSIAOSLD2),	GPIO_FN(FSIAOLR),
-	GPIO_FN(FSIAOBT),	GPIO_FN(FSIAOSLD),	GPIO_FN(FSIAOMC),
-	GPIO_FN(FSIACK),	GPIO_FN(FSIAILR),	GPIO_FN(FSIAIBT),
-
-	/* FSI-B */
-	GPIO_FN(FSIBCK),
-
 	/* FMSI */
 	GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
 	GPIO_FN(FMSISLD_PORT6),
-- 
1.8.2.1

[PATCH 085/130] sh-pfc: r8a7740: Remove HDMI function GPIOS

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

All r8a7740 platforms now use the pinctrl API to control the HDMI pins,
the corresponding function GPIOS are unused. Remove them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index a93fd84..fb7a3e8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -3386,10 +3386,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
 	GPIO_FN(SDENC_CPG),
 	GPIO_FN(SDENC_DV_CLKI),
 
-	/* HDMI */
-	GPIO_FN(HDMI_HPD),
-	GPIO_FN(HDMI_CEC),
-
 	/* SYSC */
 	GPIO_FN(RESETP_PULLUP),
 	GPIO_FN(RESETP_PLAIN),
-- 
1.8.2.1

[PATCH 086/130] ARM: shmobile: armadillo800eva: Convert SCIFA1 to pinctrl

[Simon Horman]

From: Bastian Hecht <hechtb@gmail.com>

We use the new pinctrl framework now.

Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-armadillo800eva.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index aafa99b..44a6215 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -1087,6 +1087,9 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
 				  "mmc0_data8_1", "mmc0"),
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
 				  "mmc0_ctrl_1", "mmc0"),
+	/* SCIFA1 */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740",
+				  "scifa1_data", "scifa1"),
 	/* SDHI0 */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
 				  "sdhi0_data4", "sdhi0"),
@@ -1154,10 +1157,6 @@ static void __init eva_init(void)
 	r8a7740_pinmux_init();
 	r8a7740_meram_workaround();
 
-	/* SCIFA1 */
-	gpio_request(GPIO_FN_SCIFA1_RXD, NULL);
-	gpio_request(GPIO_FN_SCIFA1_TXD, NULL);
-
 	/* LCDC0 */
 	gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
 	gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
-- 
1.8.2.1

[PATCH 087/130] ARM: shmobile: r8a7740: Remove SCIF function GPIOs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a7740.h | 74 ---------------------------
 1 file changed, 74 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index abdc4d4..bb207d8 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -165,80 +165,6 @@ enum {
 	GPIO_FN_FMSOOBT,	GPIO_FN_FMSOSLD,
 	GPIO_FN_FMSOCK,
 
-	/* SCIFA0 */
-	GPIO_FN_SCIFA0_SCK,	GPIO_FN_SCIFA0_CTS,
-	GPIO_FN_SCIFA0_RTS,	GPIO_FN_SCIFA0_RXD,
-	GPIO_FN_SCIFA0_TXD,
-
-	/* SCIFA1 */
-	GPIO_FN_SCIFA1_CTS,	GPIO_FN_SCIFA1_SCK,
-	GPIO_FN_SCIFA1_RXD,	GPIO_FN_SCIFA1_TXD,
-	GPIO_FN_SCIFA1_RTS,
-
-	/* SCIFA2 */
-	GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
-	GPIO_FN_SCIFA2_SCK_PORT199,
-	GPIO_FN_SCIFA2_RXD,	GPIO_FN_SCIFA2_TXD,
-	GPIO_FN_SCIFA2_CTS,	GPIO_FN_SCIFA2_RTS,
-
-	/* SCIFA3 */
-	GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
-	GPIO_FN_SCIFA3_SCK_PORT116,
-	GPIO_FN_SCIFA3_CTS_PORT117,
-	GPIO_FN_SCIFA3_RXD_PORT174,
-	GPIO_FN_SCIFA3_TXD_PORT175,
-
-	GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
-	GPIO_FN_SCIFA3_SCK_PORT158,
-	GPIO_FN_SCIFA3_CTS_PORT162,
-	GPIO_FN_SCIFA3_RXD_PORT159,
-	GPIO_FN_SCIFA3_TXD_PORT160,
-
-	/* SCIFA4 */
-	GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
-	GPIO_FN_SCIFA4_TXD_PORT13,
-
-	GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
-	GPIO_FN_SCIFA4_TXD_PORT203,
-
-	GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
-	GPIO_FN_SCIFA4_TXD_PORT93,
-
-	GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
-	GPIO_FN_SCIFA4_SCK_PORT205,
-
-	/* SCIFA5 */
-	GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
-	GPIO_FN_SCIFA5_RXD_PORT10,
-
-	GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
-	GPIO_FN_SCIFA5_TXD_PORT208,
-
-	GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
-	GPIO_FN_SCIFA5_RXD_PORT92,
-
-	GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
-	GPIO_FN_SCIFA5_SCK_PORT206,
-
-	/* SCIFA6 */
-	GPIO_FN_SCIFA6_SCK,	GPIO_FN_SCIFA6_RXD,	GPIO_FN_SCIFA6_TXD,
-
-	/* SCIFA7 */
-	GPIO_FN_SCIFA7_TXD,	GPIO_FN_SCIFA7_RXD,
-
-	/* SCIFAB */
-	GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
-	GPIO_FN_SCIFB_RXD_PORT191,
-	GPIO_FN_SCIFB_TXD_PORT192,
-	GPIO_FN_SCIFB_RTS_PORT186,
-	GPIO_FN_SCIFB_CTS_PORT187,
-
-	GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
-	GPIO_FN_SCIFB_RXD_PORT3,
-	GPIO_FN_SCIFB_TXD_PORT4,
-	GPIO_FN_SCIFB_RTS_PORT172,
-	GPIO_FN_SCIFB_CTS_PORT173,
-
 	/* LCD0 */
 	GPIO_FN_LCDC0_SELECT,
 
-- 
1.8.2.1

[PATCH 088/130] ARM: shmobile: r8a7740: Remove INTC function GPIOs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a7740.h | 34 ---------------------------
 1 file changed, 34 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index bb207d8..dea430e 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -100,40 +100,6 @@ enum {
 
 	GPIO_PORT210, GPIO_PORT211,
 
-	/* IRQ */
-	GPIO_FN_IRQ0_PORT2,	GPIO_FN_IRQ0_PORT13,
-	GPIO_FN_IRQ1,
-	GPIO_FN_IRQ2_PORT11,	GPIO_FN_IRQ2_PORT12,
-	GPIO_FN_IRQ3_PORT10,	GPIO_FN_IRQ3_PORT14,
-	GPIO_FN_IRQ4_PORT15,	GPIO_FN_IRQ4_PORT172,
-	GPIO_FN_IRQ5_PORT0,	GPIO_FN_IRQ5_PORT1,
-	GPIO_FN_IRQ6_PORT121,	GPIO_FN_IRQ6_PORT173,
-	GPIO_FN_IRQ7_PORT120,	GPIO_FN_IRQ7_PORT209,
-	GPIO_FN_IRQ8,
-	GPIO_FN_IRQ9_PORT118,	GPIO_FN_IRQ9_PORT210,
-	GPIO_FN_IRQ10,
-	GPIO_FN_IRQ11,
-	GPIO_FN_IRQ12_PORT42,	GPIO_FN_IRQ12_PORT97,
-	GPIO_FN_IRQ13_PORT64,	GPIO_FN_IRQ13_PORT98,
-	GPIO_FN_IRQ14_PORT63,	GPIO_FN_IRQ14_PORT99,
-	GPIO_FN_IRQ15_PORT62,	GPIO_FN_IRQ15_PORT100,
-	GPIO_FN_IRQ16_PORT68,	GPIO_FN_IRQ16_PORT211,
-	GPIO_FN_IRQ17,
-	GPIO_FN_IRQ18,
-	GPIO_FN_IRQ19,
-	GPIO_FN_IRQ20,
-	GPIO_FN_IRQ21,
-	GPIO_FN_IRQ22,
-	GPIO_FN_IRQ23,
-	GPIO_FN_IRQ24,
-	GPIO_FN_IRQ25,
-	GPIO_FN_IRQ26_PORT58,	GPIO_FN_IRQ26_PORT81,
-	GPIO_FN_IRQ27_PORT57,	GPIO_FN_IRQ27_PORT168,
-	GPIO_FN_IRQ28_PORT56,	GPIO_FN_IRQ28_PORT169,
-	GPIO_FN_IRQ29_PORT50,	GPIO_FN_IRQ29_PORT170,
-	GPIO_FN_IRQ30_PORT49,	GPIO_FN_IRQ30_PORT171,
-	GPIO_FN_IRQ31_PORT41,	GPIO_FN_IRQ31_PORT167,
-
 	/* Function */
 
 	/* DBGT */
-- 
1.8.2.1

[PATCH 089/130] ARM: shmobile: r8a7740: Remove BSC function GPIOs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a7740.h | 27 ++-------------------------
 1 file changed, 2 insertions(+), 25 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index dea430e..61cff39 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -297,11 +297,7 @@ enum {
 	GPIO_FN_BBIF2_TSCK2_PORT89,
 	GPIO_FN_BBIF2_TSYNC2_PORT184,
 
-	/* BSC / FLCTL / PCMCIA */
-	GPIO_FN_CS0,	GPIO_FN_CS2,	GPIO_FN_CS4,
-	GPIO_FN_CS5B,	GPIO_FN_CS6A,
-	GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
-	GPIO_FN_CS5A_PORT19,
+	/* FLCTL / PCMCIA */
 	GPIO_FN_IOIS16, /* ? */
 
 	GPIO_FN_A0,	GPIO_FN_A1,	GPIO_FN_A2,	GPIO_FN_A3,
@@ -314,26 +310,7 @@ enum {
 	GPIO_FN_A22,	GPIO_FN_A23,	GPIO_FN_A24,	GPIO_FN_A25,
 	GPIO_FN_A26,
 
-	GPIO_FN_D0_NAF0,	GPIO_FN_D1_NAF1,	/* share with FLCTL */
-	GPIO_FN_D2_NAF2,	GPIO_FN_D3_NAF3,	/* share with FLCTL */
-	GPIO_FN_D4_NAF4,	GPIO_FN_D5_NAF5,	/* share with FLCTL */
-	GPIO_FN_D6_NAF6,	GPIO_FN_D7_NAF7,	/* share with FLCTL */
-	GPIO_FN_D8_NAF8,	GPIO_FN_D9_NAF9,	/* share with FLCTL */
-	GPIO_FN_D10_NAF10,	GPIO_FN_D11_NAF11,	/* share with FLCTL */
-	GPIO_FN_D12_NAF12,	GPIO_FN_D13_NAF13,	/* share with FLCTL */
-	GPIO_FN_D14_NAF14,	GPIO_FN_D15_NAF15,	/* share with FLCTL */
-
-	GPIO_FN_D16,	GPIO_FN_D17,	GPIO_FN_D18,	GPIO_FN_D19,
-	GPIO_FN_D20,	GPIO_FN_D21,	GPIO_FN_D22,	GPIO_FN_D23,
-	GPIO_FN_D24,	GPIO_FN_D25,	GPIO_FN_D26,	GPIO_FN_D27,
-	GPIO_FN_D28,	GPIO_FN_D29,	GPIO_FN_D30,	GPIO_FN_D31,
-
-	GPIO_FN_WE0_FWE,	/* share with FLCTL */
-	GPIO_FN_WE1,
-	GPIO_FN_WE2_ICIORD,	/* share with PCMCIA */
-	GPIO_FN_WE3_ICIOWR,	/* share with PCMCIA */
-	GPIO_FN_CKO,	GPIO_FN_BS,	GPIO_FN_RDWR,
-	GPIO_FN_RD_FSC,		/* share with FLCTL */
+	GPIO_FN_CKO,
 	GPIO_FN_WAIT_PORT177,	/* WAIT Port 90/177 */
 	GPIO_FN_WAIT_PORT90,
 
-- 
1.8.2.1

[PATCH 090/130] ARM: shmobile: r8a7740: Remove GETHER function GPIOs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a7740.h | 23 -----------------------
 1 file changed, 23 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 61cff39..0db82aa 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -331,29 +331,6 @@ enum {
 	GPIO_FN_IDE_INT,	GPIO_FN_IDE_RST,	GPIO_FN_IDE_DIRECTION,
 	GPIO_FN_IDE_EXBUF_ENB,	GPIO_FN_IDE_IODACK,	GPIO_FN_IDE_IODREQ,
 
-	/* RMII */
-	GPIO_FN_RMII_CRS_DV,	GPIO_FN_RMII_RX_ER,	GPIO_FN_RMII_RXD0,
-	GPIO_FN_RMII_RXD1,	GPIO_FN_RMII_TX_EN,	GPIO_FN_RMII_TXD0,
-	GPIO_FN_RMII_MDC,	GPIO_FN_RMII_TXD1,	GPIO_FN_RMII_MDIO,
-	GPIO_FN_RMII_REF50CK,	/* for RMII */
-	GPIO_FN_RMII_REF125CK,	/* for GMII */
-
-	/* GEther */
-	GPIO_FN_ET_TX_CLK,	GPIO_FN_ET_TX_EN,	GPIO_FN_ET_ETXD0,
-	GPIO_FN_ET_ETXD1,	GPIO_FN_ET_ETXD2,	GPIO_FN_ET_ETXD3,
-	GPIO_FN_ET_ETXD4,	GPIO_FN_ET_ETXD5, /* for GEther */
-	GPIO_FN_ET_ETXD6,	GPIO_FN_ET_ETXD7, /* for GEther */
-	GPIO_FN_ET_COL,		GPIO_FN_ET_TX_ER,
-	GPIO_FN_ET_RX_CLK,	GPIO_FN_ET_RX_DV,
-	GPIO_FN_ET_ERXD0,	GPIO_FN_ET_ERXD1,
-	GPIO_FN_ET_ERXD2,	GPIO_FN_ET_ERXD3,
-	GPIO_FN_ET_ERXD4,	GPIO_FN_ET_ERXD5, /* for GEther */
-	GPIO_FN_ET_ERXD6,	GPIO_FN_ET_ERXD7, /* for GEther */
-	GPIO_FN_ET_RX_ER,	GPIO_FN_ET_CRS,
-	GPIO_FN_ET_MDC,		GPIO_FN_ET_MDIO,
-	GPIO_FN_ET_LINK,	GPIO_FN_ET_PHY_INT,
-	GPIO_FN_ET_WOL,		GPIO_FN_ET_GTX_CLK,
-
 	/* DMA0 */
 	GPIO_FN_DREQ0,		GPIO_FN_DACK0,
 
-- 
1.8.2.1

[PATCH 091/130] ARM: shmobile: r8a7740: Remove CEU function GPIOs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a7740.h | 28 ---------------------------
 1 file changed, 28 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 0db82aa..08b7da0 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -143,34 +143,6 @@ enum {
 	GPIO_FN_RSPI_MOSI_A,	GPIO_FN_RSPI_MISO_A,
 	GPIO_FN_RSPI_CK_A,
 
-	/* VIO CKO */
-	GPIO_FN_VIO_CKO1,
-	GPIO_FN_VIO_CKO2,
-	GPIO_FN_VIO_CKO_1,
-	GPIO_FN_VIO_CKO,
-
-	/* VIO0 */
-	GPIO_FN_VIO0_D0,	GPIO_FN_VIO0_D1,	GPIO_FN_VIO0_D2,
-	GPIO_FN_VIO0_D3,	GPIO_FN_VIO0_D4,	GPIO_FN_VIO0_D5,
-	GPIO_FN_VIO0_D6,	GPIO_FN_VIO0_D7,	GPIO_FN_VIO0_D8,
-	GPIO_FN_VIO0_D9,	GPIO_FN_VIO0_D10,	GPIO_FN_VIO0_D11,
-	GPIO_FN_VIO0_D12,	GPIO_FN_VIO0_VD,	GPIO_FN_VIO0_HD,
-	GPIO_FN_VIO0_CLK,	GPIO_FN_VIO0_FIELD,
-
-	GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
-	GPIO_FN_VIO0_D14_PORT25,
-	GPIO_FN_VIO0_D15_PORT24,
-
-	GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
-	GPIO_FN_VIO0_D14_PORT95,
-	GPIO_FN_VIO0_D15_PORT96,
-
-	/* VIO1 */
-	GPIO_FN_VIO1_D0,	GPIO_FN_VIO1_D1,	GPIO_FN_VIO1_D2,
-	GPIO_FN_VIO1_D3,	GPIO_FN_VIO1_D4,	GPIO_FN_VIO1_D5,
-	GPIO_FN_VIO1_D6,	GPIO_FN_VIO1_D7,	GPIO_FN_VIO1_VD,
-	GPIO_FN_VIO1_HD,	GPIO_FN_VIO1_CLK,	GPIO_FN_VIO1_FIELD,
-
 	/* TPU0 */
 	GPIO_FN_TPU0TO0,	GPIO_FN_TPU0TO1,
 	GPIO_FN_TPU0TO3,
-- 
1.8.2.1

[PATCH 092/130] ARM: shmobile: r8a7740: Remove FSI function GPIOs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a7740.h | 14 --------------
 1 file changed, 14 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 08b7da0..001302f 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -107,20 +107,6 @@ enum {
 	GPIO_FN_DBGMD10,	GPIO_FN_DBGMD11,	GPIO_FN_DBGMD20,
 	GPIO_FN_DBGMD21,
 
-	/* FSI-A */
-	GPIO_FN_FSIAISLD_PORT0,		/* FSIAISLD Port 0/5 */
-	GPIO_FN_FSIAISLD_PORT5,
-	GPIO_FN_FSIASPDIF_PORT9,	/* FSIASPDIF Port 9/18 */
-	GPIO_FN_FSIASPDIF_PORT18,
-	GPIO_FN_FSIAOSLD1,	GPIO_FN_FSIAOSLD2,
-	GPIO_FN_FSIAOLR,	GPIO_FN_FSIAOBT,
-	GPIO_FN_FSIAOSLD,	GPIO_FN_FSIAOMC,
-	GPIO_FN_FSIACK,		GPIO_FN_FSIAILR,
-	GPIO_FN_FSIAIBT,
-
-	/* FSI-B */
-	GPIO_FN_FSIBCK,
-
 	/* FMSI */
 	GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
 	GPIO_FN_FMSISLD_PORT6,
-- 
1.8.2.1

[PATCH 093/130] ARM: shmobile: r8a7740: Remove HDMI function GPIOs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Those GPIOs have been deprecated by the pinctrl API. They are unused and
unneeded, remove them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a7740.h | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 001302f..55f3d1a 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -300,10 +300,6 @@ enum {
 	GPIO_FN_RESETP_PULLUP,
 	GPIO_FN_RESETP_PLAIN,
 
-	/* HDMI */
-	GPIO_FN_HDMI_HPD,
-	GPIO_FN_HDMI_CEC,
-
 	/* SDENC */
 	GPIO_FN_SDENC_CPG,
 	GPIO_FN_SDENC_DV_CLKI,
-- 
1.8.2.1

[PATCH 094/130] sh-pfc: r8a7740: Remove function GPIOs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

No r8a7740 platform use the function GPIOs API. Remove it.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 205 -----------------------------------
 1 file changed, 205 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index fb7a3e8..9f44fd6 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -3197,208 +3197,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(sdhi2),
 };
 
-#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	/* Function */
-
-	/* DBGT */
-	GPIO_FN(DBGMDT2),	GPIO_FN(DBGMDT1),	GPIO_FN(DBGMDT0),
-	GPIO_FN(DBGMD10),	GPIO_FN(DBGMD11),	GPIO_FN(DBGMD20),
-	GPIO_FN(DBGMD21),
-
-	/* FMSI */
-	GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
-	GPIO_FN(FMSISLD_PORT6),
-	GPIO_FN(FMSIILR),	GPIO_FN(FMSIIBT),	GPIO_FN(FMSIOLR),
-	GPIO_FN(FMSIOBT),	GPIO_FN(FMSICK),	GPIO_FN(FMSOILR),
-	GPIO_FN(FMSOIBT),	GPIO_FN(FMSOOLR),	GPIO_FN(FMSOOBT),
-	GPIO_FN(FMSOSLD),	GPIO_FN(FMSOCK),
-
-	/* RSPI */
-	GPIO_FN(RSPI_SSL0_A),	GPIO_FN(RSPI_SSL1_A),	GPIO_FN(RSPI_SSL2_A),
-	GPIO_FN(RSPI_SSL3_A),	GPIO_FN(RSPI_CK_A),	GPIO_FN(RSPI_MOSI_A),
-	GPIO_FN(RSPI_MISO_A),
-
-	/* TPU0 */
-	GPIO_FN(TPU0TO0),	GPIO_FN(TPU0TO1),	GPIO_FN(TPU0TO3),
-	GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
-	GPIO_FN(TPU0TO2_PORT202),
-
-	/* SSP1 0 */
-	GPIO_FN(STP0_IPD0),	GPIO_FN(STP0_IPD1),	GPIO_FN(STP0_IPD2),
-	GPIO_FN(STP0_IPD3),	GPIO_FN(STP0_IPD4),	GPIO_FN(STP0_IPD5),
-	GPIO_FN(STP0_IPD6),	GPIO_FN(STP0_IPD7),	GPIO_FN(STP0_IPEN),
-	GPIO_FN(STP0_IPCLK),	GPIO_FN(STP0_IPSYNC),
-
-	/* SSP1 1 */
-	GPIO_FN(STP1_IPD1),	GPIO_FN(STP1_IPD2),	GPIO_FN(STP1_IPD3),
-	GPIO_FN(STP1_IPD4),	GPIO_FN(STP1_IPD5),	GPIO_FN(STP1_IPD6),
-	GPIO_FN(STP1_IPD7),	GPIO_FN(STP1_IPCLK),	GPIO_FN(STP1_IPSYNC),
-
-	GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
-	GPIO_FN(STP1_IPEN_PORT187),
-
-	GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
-	GPIO_FN(STP1_IPEN_PORT193),
-
-	/* SIM */
-	GPIO_FN(SIM_RST),	GPIO_FN(SIM_CLK),
-	GPIO_FN(SIM_D_PORT22), /* SIM_D  Port 22/199 */
-	GPIO_FN(SIM_D_PORT199),
-
-	/* MSIOF2 */
-	GPIO_FN(MSIOF2_TXD),	GPIO_FN(MSIOF2_RXD),	GPIO_FN(MSIOF2_TSCK),
-	GPIO_FN(MSIOF2_SS2),	GPIO_FN(MSIOF2_TSYNC),	GPIO_FN(MSIOF2_SS1),
-	GPIO_FN(MSIOF2_MCK1),	GPIO_FN(MSIOF2_MCK0),	GPIO_FN(MSIOF2_RSYNC),
-	GPIO_FN(MSIOF2_RSCK),
-
-	/* KEYSC */
-	GPIO_FN(KEYIN4),	GPIO_FN(KEYIN5),
-	GPIO_FN(KEYIN6),	GPIO_FN(KEYIN7),
-	GPIO_FN(KEYOUT0),	GPIO_FN(KEYOUT1),	GPIO_FN(KEYOUT2),
-	GPIO_FN(KEYOUT3),	GPIO_FN(KEYOUT4),	GPIO_FN(KEYOUT5),
-	GPIO_FN(KEYOUT6),	GPIO_FN(KEYOUT7),
-
-	GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
-	GPIO_FN(KEYIN1_PORT44),
-	GPIO_FN(KEYIN2_PORT45),
-	GPIO_FN(KEYIN3_PORT46),
-
-	GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
-	GPIO_FN(KEYIN1_PORT57),
-	GPIO_FN(KEYIN2_PORT56),
-	GPIO_FN(KEYIN3_PORT55),
-
-	/* VOU */
-	GPIO_FN(DV_D0),		GPIO_FN(DV_D1),		GPIO_FN(DV_D2),
-	GPIO_FN(DV_D3),		GPIO_FN(DV_D4),		GPIO_FN(DV_D5),
-	GPIO_FN(DV_D6),		GPIO_FN(DV_D7),		GPIO_FN(DV_D8),
-	GPIO_FN(DV_D9),		GPIO_FN(DV_D10),	GPIO_FN(DV_D11),
-	GPIO_FN(DV_D12),	GPIO_FN(DV_D13),	GPIO_FN(DV_D14),
-	GPIO_FN(DV_D15),	GPIO_FN(DV_CLK),
-	GPIO_FN(DV_VSYNC),	GPIO_FN(DV_HSYNC),
-
-	/* MEMC */
-	GPIO_FN(MEMC_AD0),	GPIO_FN(MEMC_AD1),	GPIO_FN(MEMC_AD2),
-	GPIO_FN(MEMC_AD3),	GPIO_FN(MEMC_AD4),	GPIO_FN(MEMC_AD5),
-	GPIO_FN(MEMC_AD6),	GPIO_FN(MEMC_AD7),	GPIO_FN(MEMC_AD8),
-	GPIO_FN(MEMC_AD9),	GPIO_FN(MEMC_AD10),	GPIO_FN(MEMC_AD11),
-	GPIO_FN(MEMC_AD12),	GPIO_FN(MEMC_AD13),	GPIO_FN(MEMC_AD14),
-	GPIO_FN(MEMC_AD15),	GPIO_FN(MEMC_CS0),	GPIO_FN(MEMC_INT),
-	GPIO_FN(MEMC_NWE),	GPIO_FN(MEMC_NOE),	GPIO_FN(MEMC_CS1),
-	GPIO_FN(MEMC_A1),	GPIO_FN(MEMC_ADV),	GPIO_FN(MEMC_DREQ0),
-	GPIO_FN(MEMC_WAIT),	GPIO_FN(MEMC_DREQ1),	GPIO_FN(MEMC_BUSCLK),
-	GPIO_FN(MEMC_A0),
-
-	/* MSIOF0 */
-	GPIO_FN(MSIOF0_SS1),	GPIO_FN(MSIOF0_SS2),	GPIO_FN(MSIOF0_RXD),
-	GPIO_FN(MSIOF0_TXD),	GPIO_FN(MSIOF0_MCK0),	GPIO_FN(MSIOF0_MCK1),
-	GPIO_FN(MSIOF0_RSYNC),	GPIO_FN(MSIOF0_RSCK),	GPIO_FN(MSIOF0_TSCK),
-	GPIO_FN(MSIOF0_TSYNC),
-
-	/* MSIOF1 */
-	GPIO_FN(MSIOF1_RSCK),	GPIO_FN(MSIOF1_RSYNC),
-	GPIO_FN(MSIOF1_MCK0),	GPIO_FN(MSIOF1_MCK1),
-
-	GPIO_FN(MSIOF1_SS2_PORT116),	GPIO_FN(MSIOF1_SS1_PORT117),
-	GPIO_FN(MSIOF1_RXD_PORT118),	GPIO_FN(MSIOF1_TXD_PORT119),
-	GPIO_FN(MSIOF1_TSYNC_PORT120),
-	GPIO_FN(MSIOF1_TSCK_PORT121),	/* MSEL4CR_10_0 */
-
-	GPIO_FN(MSIOF1_SS1_PORT67),	GPIO_FN(MSIOF1_TSCK_PORT72),
-	GPIO_FN(MSIOF1_TSYNC_PORT73),	GPIO_FN(MSIOF1_TXD_PORT74),
-	GPIO_FN(MSIOF1_RXD_PORT75),
-	GPIO_FN(MSIOF1_SS2_PORT202),	/* MSEL4CR_10_1 */
-
-	/* GPIO */
-	GPIO_FN(GPO0),	GPIO_FN(GPI0),
-	GPIO_FN(GPO1),	GPIO_FN(GPI1),
-
-	/* USB0 */
-	GPIO_FN(USB0_OCI),	GPIO_FN(USB0_PPON),	GPIO_FN(VBUS),
-
-	/* USB1 */
-	GPIO_FN(USB1_OCI),	GPIO_FN(USB1_PPON),
-
-	/* BBIF1 */
-	GPIO_FN(BBIF1_RXD),	GPIO_FN(BBIF1_TXD),	GPIO_FN(BBIF1_TSYNC),
-	GPIO_FN(BBIF1_TSCK),	GPIO_FN(BBIF1_RSCK),	GPIO_FN(BBIF1_RSYNC),
-	GPIO_FN(BBIF1_FLOW),	GPIO_FN(BBIF1_RX_FLOW_N),
-
-	/* BBIF2 */
-	GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
-	GPIO_FN(BBIF2_RXD2_PORT60),
-	GPIO_FN(BBIF2_TSYNC2_PORT6),
-	GPIO_FN(BBIF2_TSCK2_PORT59),
-
-	GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
-	GPIO_FN(BBIF2_TXD2_PORT183),
-	GPIO_FN(BBIF2_TSCK2_PORT89),
-	GPIO_FN(BBIF2_TSYNC2_PORT184),
-
-	/* FLCTL / PCMCIA */
-	GPIO_FN(IOIS16), /* ? */
-
-	GPIO_FN(A0),	GPIO_FN(A1),	GPIO_FN(A2),	GPIO_FN(A3),
-	GPIO_FN(A4_FOE),	GPIO_FN(A5_FCDE),	/* share with FLCTL */
-	GPIO_FN(A6),	GPIO_FN(A7),	GPIO_FN(A8),	GPIO_FN(A9),
-	GPIO_FN(A10),	GPIO_FN(A11),	GPIO_FN(A12),	GPIO_FN(A13),
-	GPIO_FN(A14),	GPIO_FN(A15),	GPIO_FN(A16),	GPIO_FN(A17),
-	GPIO_FN(A18),	GPIO_FN(A19),	GPIO_FN(A20),	GPIO_FN(A21),
-	GPIO_FN(A22),	GPIO_FN(A23),	GPIO_FN(A24),	GPIO_FN(A25),
-	GPIO_FN(A26),
-
-	GPIO_FN(CKO),
-	GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
-	GPIO_FN(WAIT_PORT90),
-
-	GPIO_FN(FCE0),	GPIO_FN(FCE1),	GPIO_FN(FRB), /* FLCTL */
-
-	/* IRDA */
-	GPIO_FN(IRDA_FIRSEL),	GPIO_FN(IRDA_IN),	GPIO_FN(IRDA_OUT),
-
-	/* ATAPI */
-	GPIO_FN(IDE_D0),	GPIO_FN(IDE_D1),	GPIO_FN(IDE_D2),
-	GPIO_FN(IDE_D3),	GPIO_FN(IDE_D4),	GPIO_FN(IDE_D5),
-	GPIO_FN(IDE_D6),	GPIO_FN(IDE_D7),	GPIO_FN(IDE_D8),
-	GPIO_FN(IDE_D9),	GPIO_FN(IDE_D10),	GPIO_FN(IDE_D11),
-	GPIO_FN(IDE_D12),	GPIO_FN(IDE_D13),	GPIO_FN(IDE_D14),
-	GPIO_FN(IDE_D15),	GPIO_FN(IDE_A0),	GPIO_FN(IDE_A1),
-	GPIO_FN(IDE_A2),	GPIO_FN(IDE_CS0),	GPIO_FN(IDE_CS1),
-	GPIO_FN(IDE_IOWR),	GPIO_FN(IDE_IORD),	GPIO_FN(IDE_IORDY),
-	GPIO_FN(IDE_INT),	GPIO_FN(IDE_RST),	GPIO_FN(IDE_DIRECTION),
-	GPIO_FN(IDE_EXBUF_ENB),	GPIO_FN(IDE_IODACK),	GPIO_FN(IDE_IODREQ),
-
-	/* DMA0 */
-	GPIO_FN(DREQ0),	GPIO_FN(DACK0),
-
-	/* DMA1 */
-	GPIO_FN(DREQ1),	GPIO_FN(DACK1),
-
-	/* SYSC */
-	GPIO_FN(RESETOUTS),
-
-	/* IRREM */
-	GPIO_FN(IROUT),
-
-	/* SDENC */
-	GPIO_FN(SDENC_CPG),
-	GPIO_FN(SDENC_DV_CLKI),
-
-	/* SYSC */
-	GPIO_FN(RESETP_PULLUP),
-	GPIO_FN(RESETP_PLAIN),
-
-	/* DEBUG */
-	GPIO_FN(EDEBGREQ_PULLDOWN),
-	GPIO_FN(EDEBGREQ_PULLUP),
-
-	GPIO_FN(TRACEAUD_FROM_VIO),
-	GPIO_FN(TRACEAUD_FROM_LCDC0),
-	GPIO_FN(TRACEAUD_FROM_MEMC),
-};
-
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 	PORTCR(0,	0xe6050000), /* PORT0CR */
 	PORTCR(1,	0xe6050001), /* PORT1CR */
@@ -3872,9 +3670,6 @@ const struct sh_pfc_soc_info r8a7740_pinmux_info = {
 	.functions	= pinmux_functions,
 	.nr_functions	= ARRAY_SIZE(pinmux_functions),
 
-	.func_gpios	= pinmux_func_gpios,
-	.nr_func_gpios	= ARRAY_SIZE(pinmux_func_gpios),
-
 	.cfg_regs	= pinmux_config_regs,
 	.data_regs	= pinmux_data_regs,
 
-- 
1.8.2.1

[PATCH 095/130] sh-pfc: r8a7740: Replace GPIO_PORTx enum with GPIO port numbers

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The PFC GPIO API implementation moved to using port numbers. Replace all
GPIO_PORTx enum usage with the corresponding port number. The GPIO_PORTx
enum values are identical to the port number on this platform.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 71 ++++++++++++++++++++----------------
 1 file changed, 39 insertions(+), 32 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 9f44fd6..6af8fae 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -30,6 +30,13 @@
 	PORT_10(fn, pfx##20, sfx),					\
 	PORT_1(fn, pfx##210, sfx),	PORT_1(fn, pfx##211, sfx)
 
+#undef _GPIO_PORT
+#define _GPIO_PORT(gpio, sfx)						\
+	[gpio] = {							\
+		.name = __stringify(PORT##gpio),			\
+		.enum_id = PORT##gpio##_DATA,				\
+	}
+
 #define IRQC_PIN_MUX(irq, pin)						\
 static const unsigned int intc_irq##irq##_pins[] = {			\
 	pin,								\
@@ -3616,38 +3623,38 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
 };
 
 static const struct pinmux_irq pinmux_irqs[] = {
-	PINMUX_IRQ(irq_pin(0), GPIO_PORT2,   GPIO_PORT13),	/* IRQ0A */
-	PINMUX_IRQ(irq_pin(1), GPIO_PORT20),		/* IRQ1A */
-	PINMUX_IRQ(irq_pin(2), GPIO_PORT11,  GPIO_PORT12),	/* IRQ2A */
-	PINMUX_IRQ(irq_pin(3), GPIO_PORT10,  GPIO_PORT14),	/* IRQ3A */
-	PINMUX_IRQ(irq_pin(4), GPIO_PORT15,  GPIO_PORT172),/* IRQ4A */
-	PINMUX_IRQ(irq_pin(5), GPIO_PORT0,   GPIO_PORT1),	/* IRQ5A */
-	PINMUX_IRQ(irq_pin(6), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */
-	PINMUX_IRQ(irq_pin(7), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */
-	PINMUX_IRQ(irq_pin(8), GPIO_PORT119),		/* IRQ8A */
-	PINMUX_IRQ(irq_pin(9), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */
-	PINMUX_IRQ(irq_pin(10), GPIO_PORT19),		/* IRQ10A */
-	PINMUX_IRQ(irq_pin(11), GPIO_PORT104),		/* IRQ11A */
-	PINMUX_IRQ(irq_pin(12), GPIO_PORT42,  GPIO_PORT97),	/* IRQ12A */
-	PINMUX_IRQ(irq_pin(13), GPIO_PORT64,  GPIO_PORT98),	/* IRQ13A */
-	PINMUX_IRQ(irq_pin(14), GPIO_PORT63,  GPIO_PORT99),	/* IRQ14A */
-	PINMUX_IRQ(irq_pin(15), GPIO_PORT62,  GPIO_PORT100),/* IRQ15A */
-	PINMUX_IRQ(irq_pin(16), GPIO_PORT68,  GPIO_PORT211),/* IRQ16A */
-	PINMUX_IRQ(irq_pin(17), GPIO_PORT69),		/* IRQ17A */
-	PINMUX_IRQ(irq_pin(18), GPIO_PORT70),		/* IRQ18A */
-	PINMUX_IRQ(irq_pin(19), GPIO_PORT71),		/* IRQ19A */
-	PINMUX_IRQ(irq_pin(20), GPIO_PORT67),		/* IRQ20A */
-	PINMUX_IRQ(irq_pin(21), GPIO_PORT202),		/* IRQ21A */
-	PINMUX_IRQ(irq_pin(22), GPIO_PORT95),		/* IRQ22A */
-	PINMUX_IRQ(irq_pin(23), GPIO_PORT96),		/* IRQ23A */
-	PINMUX_IRQ(irq_pin(24), GPIO_PORT180),		/* IRQ24A */
-	PINMUX_IRQ(irq_pin(25), GPIO_PORT38),		/* IRQ25A */
-	PINMUX_IRQ(irq_pin(26), GPIO_PORT58,  GPIO_PORT81),	/* IRQ26A */
-	PINMUX_IRQ(irq_pin(27), GPIO_PORT57,  GPIO_PORT168),/* IRQ27A */
-	PINMUX_IRQ(irq_pin(28), GPIO_PORT56,  GPIO_PORT169),/* IRQ28A */
-	PINMUX_IRQ(irq_pin(29), GPIO_PORT50,  GPIO_PORT170),/* IRQ29A */
-	PINMUX_IRQ(irq_pin(30), GPIO_PORT49,  GPIO_PORT171),/* IRQ30A */
-	PINMUX_IRQ(irq_pin(31), GPIO_PORT41,  GPIO_PORT167),/* IRQ31A */
+	PINMUX_IRQ(irq_pin(0), 2,   13),	/* IRQ0A */
+	PINMUX_IRQ(irq_pin(1), 20),		/* IRQ1A */
+	PINMUX_IRQ(irq_pin(2), 11,  12),	/* IRQ2A */
+	PINMUX_IRQ(irq_pin(3), 10,  14),	/* IRQ3A */
+	PINMUX_IRQ(irq_pin(4), 15,  172),	/* IRQ4A */
+	PINMUX_IRQ(irq_pin(5), 0,   1),		/* IRQ5A */
+	PINMUX_IRQ(irq_pin(6), 121, 173),	/* IRQ6A */
+	PINMUX_IRQ(irq_pin(7), 120, 209),	/* IRQ7A */
+	PINMUX_IRQ(irq_pin(8), 119),		/* IRQ8A */
+	PINMUX_IRQ(irq_pin(9), 118, 210),	/* IRQ9A */
+	PINMUX_IRQ(irq_pin(10), 19),		/* IRQ10A */
+	PINMUX_IRQ(irq_pin(11), 104),		/* IRQ11A */
+	PINMUX_IRQ(irq_pin(12), 42,  97),	/* IRQ12A */
+	PINMUX_IRQ(irq_pin(13), 64,  98),	/* IRQ13A */
+	PINMUX_IRQ(irq_pin(14), 63,  99),	/* IRQ14A */
+	PINMUX_IRQ(irq_pin(15), 62,  100),	/* IRQ15A */
+	PINMUX_IRQ(irq_pin(16), 68,  211),	/* IRQ16A */
+	PINMUX_IRQ(irq_pin(17), 69),		/* IRQ17A */
+	PINMUX_IRQ(irq_pin(18), 70),		/* IRQ18A */
+	PINMUX_IRQ(irq_pin(19), 71),		/* IRQ19A */
+	PINMUX_IRQ(irq_pin(20), 67),		/* IRQ20A */
+	PINMUX_IRQ(irq_pin(21), 202),		/* IRQ21A */
+	PINMUX_IRQ(irq_pin(22), 95),		/* IRQ22A */
+	PINMUX_IRQ(irq_pin(23), 96),		/* IRQ23A */
+	PINMUX_IRQ(irq_pin(24), 180),		/* IRQ24A */
+	PINMUX_IRQ(irq_pin(25), 38),		/* IRQ25A */
+	PINMUX_IRQ(irq_pin(26), 58,  81),	/* IRQ26A */
+	PINMUX_IRQ(irq_pin(27), 57,  168),	/* IRQ27A */
+	PINMUX_IRQ(irq_pin(28), 56,  169),	/* IRQ28A */
+	PINMUX_IRQ(irq_pin(29), 50,  170),	/* IRQ29A */
+	PINMUX_IRQ(irq_pin(30), 49,  171),	/* IRQ30A */
+	PINMUX_IRQ(irq_pin(31), 41,  167),	/* IRQ31A */
 };
 
 const struct sh_pfc_soc_info r8a7740_pinmux_info = {
-- 
1.8.2.1

[PATCH 096/130] ARM: shmobile: r8a7740: Remove all GPIOs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Function GPIOs are not used anymore, and all code use the GPIO numbers
directly. Remove the GPIOs enumeration.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a7740.h | 288 --------------------------
 1 file changed, 288 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 55f3d1a..9c9a66c 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -28,294 +28,6 @@
 #define MD_CK1	(1 << 1)
 #define MD_CK0	(1 << 0)
 
-/*
- * Pin Function Controller:
- *	GPIO_FN_xx - GPIO used to select pin function
- *	GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
- */
-enum {
-	/* PORT */
-	GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
-	GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
-
-	GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
-	GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
-
-	GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
-	GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
-
-	GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
-	GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
-
-	GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
-	GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
-
-	GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
-	GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
-
-	GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
-	GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
-
-	GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
-	GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
-
-	GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
-	GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
-
-	GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
-	GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
-
-	GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
-	GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
-
-	GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
-	GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
-
-	GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
-	GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
-
-	GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
-	GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
-
-	GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
-	GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
-
-	GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
-	GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
-
-	GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
-	GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
-
-	GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
-	GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
-
-	GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
-	GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
-
-	GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
-	GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
-
-	GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
-	GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
-
-	GPIO_PORT210, GPIO_PORT211,
-
-	/* Function */
-
-	/* DBGT */
-	GPIO_FN_DBGMDT2,	GPIO_FN_DBGMDT1,	GPIO_FN_DBGMDT0,
-	GPIO_FN_DBGMD10,	GPIO_FN_DBGMD11,	GPIO_FN_DBGMD20,
-	GPIO_FN_DBGMD21,
-
-	/* FMSI */
-	GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
-	GPIO_FN_FMSISLD_PORT6,
-	GPIO_FN_FMSIILR,	GPIO_FN_FMSIIBT,
-	GPIO_FN_FMSIOLR,	GPIO_FN_FMSIOBT,
-	GPIO_FN_FMSICK,		GPIO_FN_FMSOILR,
-	GPIO_FN_FMSOIBT,	GPIO_FN_FMSOOLR,
-	GPIO_FN_FMSOOBT,	GPIO_FN_FMSOSLD,
-	GPIO_FN_FMSOCK,
-
-	/* LCD0 */
-	GPIO_FN_LCDC0_SELECT,
-
-	/* LCD1 */
-	GPIO_FN_LCDC1_SELECT,
-
-	/* RSPI */
-	GPIO_FN_RSPI_SSL0_A,	GPIO_FN_RSPI_SSL1_A,
-	GPIO_FN_RSPI_SSL2_A,	GPIO_FN_RSPI_SSL3_A,
-	GPIO_FN_RSPI_MOSI_A,	GPIO_FN_RSPI_MISO_A,
-	GPIO_FN_RSPI_CK_A,
-
-	/* TPU0 */
-	GPIO_FN_TPU0TO0,	GPIO_FN_TPU0TO1,
-	GPIO_FN_TPU0TO3,
-	GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
-	GPIO_FN_TPU0TO2_PORT202,
-
-	/* SSP1 0 */
-	GPIO_FN_STP0_IPD0,	GPIO_FN_STP0_IPD1,	GPIO_FN_STP0_IPD2,
-	GPIO_FN_STP0_IPD3,	GPIO_FN_STP0_IPD4,	GPIO_FN_STP0_IPD5,
-	GPIO_FN_STP0_IPD6,	GPIO_FN_STP0_IPD7,	GPIO_FN_STP0_IPEN,
-	GPIO_FN_STP0_IPCLK,	GPIO_FN_STP0_IPSYNC,
-
-	/* SSP1 1 */
-	GPIO_FN_STP1_IPD1,	GPIO_FN_STP1_IPD2,	GPIO_FN_STP1_IPD3,
-	GPIO_FN_STP1_IPD4,	GPIO_FN_STP1_IPD5,	GPIO_FN_STP1_IPD6,
-	GPIO_FN_STP1_IPD7,	GPIO_FN_STP1_IPCLK,	GPIO_FN_STP1_IPSYNC,
-
-	GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
-	GPIO_FN_STP1_IPEN_PORT187,
-
-	GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
-	GPIO_FN_STP1_IPEN_PORT193,
-
-	/* SIM */
-	GPIO_FN_SIM_RST,	GPIO_FN_SIM_CLK,
-	GPIO_FN_SIM_D_PORT22, /* SIM_D  Port 22/199 */
-	GPIO_FN_SIM_D_PORT199,
-
-	/* MSIOF2 */
-	GPIO_FN_MSIOF2_TXD,	GPIO_FN_MSIOF2_RXD,	GPIO_FN_MSIOF2_TSCK,
-	GPIO_FN_MSIOF2_SS2,	GPIO_FN_MSIOF2_TSYNC,	GPIO_FN_MSIOF2_SS1,
-	GPIO_FN_MSIOF2_MCK1,	GPIO_FN_MSIOF2_MCK0,	GPIO_FN_MSIOF2_RSYNC,
-	GPIO_FN_MSIOF2_RSCK,
-
-	/* KEYSC */
-	GPIO_FN_KEYIN4,		GPIO_FN_KEYIN5,
-	GPIO_FN_KEYIN6,		GPIO_FN_KEYIN7,
-	GPIO_FN_KEYOUT0,	GPIO_FN_KEYOUT1,	GPIO_FN_KEYOUT2,
-	GPIO_FN_KEYOUT3,	GPIO_FN_KEYOUT4,	GPIO_FN_KEYOUT5,
-	GPIO_FN_KEYOUT6,	GPIO_FN_KEYOUT7,
-
-	GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
-	GPIO_FN_KEYIN1_PORT44,
-	GPIO_FN_KEYIN2_PORT45,
-	GPIO_FN_KEYIN3_PORT46,
-
-	GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
-	GPIO_FN_KEYIN1_PORT57,
-	GPIO_FN_KEYIN2_PORT56,
-	GPIO_FN_KEYIN3_PORT55,
-
-	/* VOU */
-	GPIO_FN_DV_D0,	GPIO_FN_DV_D1,	GPIO_FN_DV_D2,	GPIO_FN_DV_D3,
-	GPIO_FN_DV_D4,	GPIO_FN_DV_D5,	GPIO_FN_DV_D6,	GPIO_FN_DV_D7,
-	GPIO_FN_DV_D8,	GPIO_FN_DV_D9,	GPIO_FN_DV_D10,	GPIO_FN_DV_D11,
-	GPIO_FN_DV_D12,	GPIO_FN_DV_D13,	GPIO_FN_DV_D14,	GPIO_FN_DV_D15,
-	GPIO_FN_DV_CLK,
-	GPIO_FN_DV_VSYNC,
-	GPIO_FN_DV_HSYNC,
-
-	/* MEMC */
-	GPIO_FN_MEMC_AD0,	GPIO_FN_MEMC_AD1,	GPIO_FN_MEMC_AD2,
-	GPIO_FN_MEMC_AD3,	GPIO_FN_MEMC_AD4,	GPIO_FN_MEMC_AD5,
-	GPIO_FN_MEMC_AD6,	GPIO_FN_MEMC_AD7,	GPIO_FN_MEMC_AD8,
-	GPIO_FN_MEMC_AD9,	GPIO_FN_MEMC_AD10,	GPIO_FN_MEMC_AD11,
-	GPIO_FN_MEMC_AD12,	GPIO_FN_MEMC_AD13,	GPIO_FN_MEMC_AD14,
-	GPIO_FN_MEMC_AD15,	GPIO_FN_MEMC_CS0,	GPIO_FN_MEMC_INT,
-	GPIO_FN_MEMC_NWE,	GPIO_FN_MEMC_NOE,
-
-	GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
-	GPIO_FN_MEMC_ADV,
-	GPIO_FN_MEMC_WAIT,
-	GPIO_FN_MEMC_BUSCLK,
-
-	GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
-	GPIO_FN_MEMC_DREQ0,
-	GPIO_FN_MEMC_DREQ1,
-	GPIO_FN_MEMC_A0,
-
-	/* MSIOF0 */
-	GPIO_FN_MSIOF0_SS1,	GPIO_FN_MSIOF0_SS2,
-	GPIO_FN_MSIOF0_RXD,	GPIO_FN_MSIOF0_TXD,
-	GPIO_FN_MSIOF0_MCK0,	GPIO_FN_MSIOF0_MCK1,
-	GPIO_FN_MSIOF0_RSYNC,	GPIO_FN_MSIOF0_RSCK,
-	GPIO_FN_MSIOF0_TSCK,	GPIO_FN_MSIOF0_TSYNC,
-
-	/* MSIOF1 */
-	GPIO_FN_MSIOF1_RSCK,	GPIO_FN_MSIOF1_RSYNC,
-	GPIO_FN_MSIOF1_MCK0,	GPIO_FN_MSIOF1_MCK1,
-
-	GPIO_FN_MSIOF1_SS2_PORT116,	GPIO_FN_MSIOF1_SS1_PORT117,
-	GPIO_FN_MSIOF1_RXD_PORT118,	GPIO_FN_MSIOF1_TXD_PORT119,
-	GPIO_FN_MSIOF1_TSYNC_PORT120,
-	GPIO_FN_MSIOF1_TSCK_PORT121,	/* MSEL4CR_10_0 */
-
-	GPIO_FN_MSIOF1_SS1_PORT67,	GPIO_FN_MSIOF1_TSCK_PORT72,
-	GPIO_FN_MSIOF1_TSYNC_PORT73,	GPIO_FN_MSIOF1_TXD_PORT74,
-	GPIO_FN_MSIOF1_RXD_PORT75,
-	GPIO_FN_MSIOF1_SS2_PORT202,	/* MSEL4CR_10_1 */
-
-	/* GPIO */
-	GPIO_FN_GPO0,	GPIO_FN_GPI0,
-	GPIO_FN_GPO1,	GPIO_FN_GPI1,
-
-	/* USB0 */
-	GPIO_FN_USB0_OCI,	GPIO_FN_USB0_PPON,	GPIO_FN_VBUS,
-
-	/* USB1 */
-	GPIO_FN_USB1_OCI,	GPIO_FN_USB1_PPON,
-
-	/* BBIF1 */
-	GPIO_FN_BBIF1_RXD,	GPIO_FN_BBIF1_TXD,	GPIO_FN_BBIF1_TSYNC,
-	GPIO_FN_BBIF1_TSCK,	GPIO_FN_BBIF1_RSCK,	GPIO_FN_BBIF1_RSYNC,
-	GPIO_FN_BBIF1_FLOW,	GPIO_FN_BBIF1_RX_FLOW_N,
-
-	/* BBIF2 */
-	GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
-	GPIO_FN_BBIF2_RXD2_PORT60,
-	GPIO_FN_BBIF2_TSYNC2_PORT6,
-	GPIO_FN_BBIF2_TSCK2_PORT59,
-
-	GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
-	GPIO_FN_BBIF2_TXD2_PORT183,
-	GPIO_FN_BBIF2_TSCK2_PORT89,
-	GPIO_FN_BBIF2_TSYNC2_PORT184,
-
-	/* FLCTL / PCMCIA */
-	GPIO_FN_IOIS16, /* ? */
-
-	GPIO_FN_A0,	GPIO_FN_A1,	GPIO_FN_A2,	GPIO_FN_A3,
-	GPIO_FN_A4_FOE,		/* share with FLCTL */
-	GPIO_FN_A5_FCDE,	/* share with FLCTL */
-	GPIO_FN_A6,	GPIO_FN_A7,	GPIO_FN_A8,	GPIO_FN_A9,
-	GPIO_FN_A10,	GPIO_FN_A11,	GPIO_FN_A12,	GPIO_FN_A13,
-	GPIO_FN_A14,	GPIO_FN_A15,	GPIO_FN_A16,	GPIO_FN_A17,
-	GPIO_FN_A18,	GPIO_FN_A19,	GPIO_FN_A20,	GPIO_FN_A21,
-	GPIO_FN_A22,	GPIO_FN_A23,	GPIO_FN_A24,	GPIO_FN_A25,
-	GPIO_FN_A26,
-
-	GPIO_FN_CKO,
-	GPIO_FN_WAIT_PORT177,	/* WAIT Port 90/177 */
-	GPIO_FN_WAIT_PORT90,
-
-	GPIO_FN_FCE0,	GPIO_FN_FCE1,	GPIO_FN_FRB, /* FLCTL */
-
-	/* IRDA */
-	GPIO_FN_IRDA_FIRSEL,	GPIO_FN_IRDA_IN,	GPIO_FN_IRDA_OUT,
-
-	/* ATAPI */
-	GPIO_FN_IDE_D0,		GPIO_FN_IDE_D1,		GPIO_FN_IDE_D2,
-	GPIO_FN_IDE_D3,		GPIO_FN_IDE_D4,		GPIO_FN_IDE_D5,
-	GPIO_FN_IDE_D6,		GPIO_FN_IDE_D7,		GPIO_FN_IDE_D8,
-	GPIO_FN_IDE_D9,		GPIO_FN_IDE_D10,	GPIO_FN_IDE_D11,
-	GPIO_FN_IDE_D12,	GPIO_FN_IDE_D13,	GPIO_FN_IDE_D14,
-	GPIO_FN_IDE_D15,	GPIO_FN_IDE_A0,		GPIO_FN_IDE_A1,
-	GPIO_FN_IDE_A2,		GPIO_FN_IDE_CS0,	GPIO_FN_IDE_CS1,
-	GPIO_FN_IDE_IOWR,	GPIO_FN_IDE_IORD,	GPIO_FN_IDE_IORDY,
-	GPIO_FN_IDE_INT,	GPIO_FN_IDE_RST,	GPIO_FN_IDE_DIRECTION,
-	GPIO_FN_IDE_EXBUF_ENB,	GPIO_FN_IDE_IODACK,	GPIO_FN_IDE_IODREQ,
-
-	/* DMA0 */
-	GPIO_FN_DREQ0,		GPIO_FN_DACK0,
-
-	/* DMA1 */
-	GPIO_FN_DREQ1,		GPIO_FN_DACK1,
-
-	/* SYSC */
-	GPIO_FN_RESETOUTS,
-	GPIO_FN_RESETP_PULLUP,
-	GPIO_FN_RESETP_PLAIN,
-
-	/* SDENC */
-	GPIO_FN_SDENC_CPG,
-	GPIO_FN_SDENC_DV_CLKI,
-
-	/* IRREM */
-	GPIO_FN_IROUT,
-
-	/* DEBUG */
-	GPIO_FN_EDEBGREQ_PULLDOWN,
-	GPIO_FN_EDEBGREQ_PULLUP,
-
-	GPIO_FN_TRACEAUD_FROM_VIO,
-	GPIO_FN_TRACEAUD_FROM_LCDC0,
-	GPIO_FN_TRACEAUD_FROM_MEMC,
-};
-
 /* DMA slave IDs */
 enum {
 	SHDMA_SLAVE_INVALID,
-- 
1.8.2.1

[PATCH 097/130] sh-pfc: r8a7740: Add bias (pull-up/down) pinconf support

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 365 +++++++++++++++++++++--------------
 1 file changed, 220 insertions(+), 145 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 6af8fae..e5ef587 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -18,10 +18,14 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
+#include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
 #include <mach/r8a7740.h>
 #include <mach/irqs.h>
 
+#include "core.h"
 #include "sh_pfc.h"
 
 #define CPU_ALL_PORT(fn, pfx, sfx)					\
@@ -66,16 +70,6 @@ enum {
 	PORT_ALL(IN),
 	PINMUX_INPUT_END,
 
-	/* PORT0_IN_PU -> PORT211_IN_PU */
-	PINMUX_INPUT_PULLUP_BEGIN,
-	PORT_ALL(IN_PU),
-	PINMUX_INPUT_PULLUP_END,
-
-	/* PORT0_IN_PD -> PORT211_IN_PD */
-	PINMUX_INPUT_PULLDOWN_BEGIN,
-	PORT_ALL(IN_PD),
-	PINMUX_INPUT_PULLDOWN_END,
-
 	/* PORT0_OUT -> PORT211_OUT */
 	PINMUX_OUTPUT_BEGIN,
 	PORT_ALL(OUT),
@@ -596,137 +590,11 @@ enum {
 	PINMUX_MARK_END,
 };
 
+#define _PORT_DATA(pfx, sfx)	PORT_DATA_IO(pfx)
+#define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_PORT_DATA, , unused)
+
 static const pinmux_enum_t pinmux_data[] = {
-	/* specify valid pin states for each pin in GPIO mode */
-
-	/* I/O and Pull U/D */
-	PORT_DATA_IO_PD(0),		PORT_DATA_IO_PD(1),
-	PORT_DATA_IO_PD(2),		PORT_DATA_IO_PD(3),
-	PORT_DATA_IO_PD(4),		PORT_DATA_IO_PD(5),
-	PORT_DATA_IO_PD(6),		PORT_DATA_IO(7),
-	PORT_DATA_IO(8),		PORT_DATA_IO(9),
-
-	PORT_DATA_IO_PD(10),		PORT_DATA_IO_PD(11),
-	PORT_DATA_IO_PD(12),		PORT_DATA_IO_PU_PD(13),
-	PORT_DATA_IO_PD(14),		PORT_DATA_IO_PD(15),
-	PORT_DATA_IO_PD(16),		PORT_DATA_IO_PD(17),
-	PORT_DATA_IO(18),		PORT_DATA_IO_PU(19),
-
-	PORT_DATA_IO_PU_PD(20),		PORT_DATA_IO_PD(21),
-	PORT_DATA_IO_PU_PD(22),		PORT_DATA_IO(23),
-	PORT_DATA_IO_PU(24),		PORT_DATA_IO_PU(25),
-	PORT_DATA_IO_PU(26),		PORT_DATA_IO_PU(27),
-	PORT_DATA_IO_PU(28),		PORT_DATA_IO_PU(29),
-
-	PORT_DATA_IO_PU(30),		PORT_DATA_IO_PD(31),
-	PORT_DATA_IO_PD(32),		PORT_DATA_IO_PD(33),
-	PORT_DATA_IO_PD(34),		PORT_DATA_IO_PU(35),
-	PORT_DATA_IO_PU(36),		PORT_DATA_IO_PD(37),
-	PORT_DATA_IO_PU(38),		PORT_DATA_IO_PD(39),
-
-	PORT_DATA_IO_PU_PD(40),		PORT_DATA_IO_PD(41),
-	PORT_DATA_IO_PD(42),		PORT_DATA_IO_PU_PD(43),
-	PORT_DATA_IO_PU_PD(44),		PORT_DATA_IO_PU_PD(45),
-	PORT_DATA_IO_PU_PD(46),		PORT_DATA_IO_PU_PD(47),
-	PORT_DATA_IO_PU_PD(48),		PORT_DATA_IO_PU_PD(49),
-
-	PORT_DATA_IO_PU_PD(50),		PORT_DATA_IO_PD(51),
-	PORT_DATA_IO_PD(52),		PORT_DATA_IO_PD(53),
-	PORT_DATA_IO_PD(54),		PORT_DATA_IO_PU_PD(55),
-	PORT_DATA_IO_PU_PD(56),		PORT_DATA_IO_PU_PD(57),
-	PORT_DATA_IO_PU_PD(58),		PORT_DATA_IO_PU_PD(59),
-
-	PORT_DATA_IO_PU_PD(60),		PORT_DATA_IO_PD(61),
-	PORT_DATA_IO_PD(62),		PORT_DATA_IO_PD(63),
-	PORT_DATA_IO_PD(64),		PORT_DATA_IO_PD(65),
-	PORT_DATA_IO_PU_PD(66),		PORT_DATA_IO_PU_PD(67),
-	PORT_DATA_IO_PU_PD(68),		PORT_DATA_IO_PU_PD(69),
-
-	PORT_DATA_IO_PU_PD(70),		PORT_DATA_IO_PU_PD(71),
-	PORT_DATA_IO_PU_PD(72),		PORT_DATA_IO_PU_PD(73),
-	PORT_DATA_IO_PU_PD(74),		PORT_DATA_IO_PU_PD(75),
-	PORT_DATA_IO_PU_PD(76),		PORT_DATA_IO_PU_PD(77),
-	PORT_DATA_IO_PU_PD(78),		PORT_DATA_IO_PU_PD(79),
-
-	PORT_DATA_IO_PU_PD(80),		PORT_DATA_IO_PU_PD(81),
-	PORT_DATA_IO(82),		PORT_DATA_IO_PU_PD(83),
-	PORT_DATA_IO(84),		PORT_DATA_IO_PD(85),
-	PORT_DATA_IO_PD(86),		PORT_DATA_IO_PD(87),
-	PORT_DATA_IO_PD(88),		PORT_DATA_IO_PD(89),
-
-	PORT_DATA_IO_PD(90),		PORT_DATA_IO_PU_PD(91),
-	PORT_DATA_IO_PU_PD(92),		PORT_DATA_IO_PU_PD(93),
-	PORT_DATA_IO_PU_PD(94),		PORT_DATA_IO_PU_PD(95),
-	PORT_DATA_IO_PU_PD(96),		PORT_DATA_IO_PU_PD(97),
-	PORT_DATA_IO_PU_PD(98),		PORT_DATA_IO_PU_PD(99),
-
-	PORT_DATA_IO_PU_PD(100),	PORT_DATA_IO(101),
-	PORT_DATA_IO_PU(102),		PORT_DATA_IO_PU_PD(103),
-	PORT_DATA_IO_PU(104),		PORT_DATA_IO_PU(105),
-	PORT_DATA_IO_PU_PD(106),	PORT_DATA_IO(107),
-	PORT_DATA_IO(108),		PORT_DATA_IO(109),
-
-	PORT_DATA_IO(110),		PORT_DATA_IO(111),
-	PORT_DATA_IO(112),		PORT_DATA_IO(113),
-	PORT_DATA_IO_PU_PD(114),	PORT_DATA_IO(115),
-	PORT_DATA_IO_PD(116),		PORT_DATA_IO_PD(117),
-	PORT_DATA_IO_PD(118),		PORT_DATA_IO_PD(119),
-
-	PORT_DATA_IO_PD(120),		PORT_DATA_IO_PD(121),
-	PORT_DATA_IO_PD(122),		PORT_DATA_IO_PD(123),
-	PORT_DATA_IO_PD(124),		PORT_DATA_IO(125),
-	PORT_DATA_IO(126),		PORT_DATA_IO(127),
-	PORT_DATA_IO(128),		PORT_DATA_IO(129),
-
-	PORT_DATA_IO(130),		PORT_DATA_IO(131),
-	PORT_DATA_IO(132),		PORT_DATA_IO(133),
-	PORT_DATA_IO(134),		PORT_DATA_IO(135),
-	PORT_DATA_IO(136),		PORT_DATA_IO(137),
-	PORT_DATA_IO(138),		PORT_DATA_IO(139),
-
-	PORT_DATA_IO(140),		PORT_DATA_IO(141),
-	PORT_DATA_IO_PU(142),		PORT_DATA_IO_PU(143),
-	PORT_DATA_IO_PU(144),		PORT_DATA_IO_PU(145),
-	PORT_DATA_IO_PU(146),		PORT_DATA_IO_PU(147),
-	PORT_DATA_IO_PU(148),		PORT_DATA_IO_PU(149),
-
-	PORT_DATA_IO_PU(150),		PORT_DATA_IO_PU(151),
-	PORT_DATA_IO_PU(152),		PORT_DATA_IO_PU(153),
-	PORT_DATA_IO_PU(154),		PORT_DATA_IO_PU(155),
-	PORT_DATA_IO_PU(156),		PORT_DATA_IO_PU(157),
-	PORT_DATA_IO_PD(158),		PORT_DATA_IO_PD(159),
-
-	PORT_DATA_IO_PU_PD(160),	PORT_DATA_IO_PD(161),
-	PORT_DATA_IO_PD(162),		PORT_DATA_IO_PD(163),
-	PORT_DATA_IO_PD(164),		PORT_DATA_IO_PD(165),
-	PORT_DATA_IO_PU(166),		PORT_DATA_IO_PU(167),
-	PORT_DATA_IO_PU(168),		PORT_DATA_IO_PU(169),
-
-	PORT_DATA_IO_PU(170),		PORT_DATA_IO_PU(171),
-	PORT_DATA_IO_PD(172),		PORT_DATA_IO_PD(173),
-	PORT_DATA_IO_PD(174),		PORT_DATA_IO_PD(175),
-	PORT_DATA_IO_PU(176),		PORT_DATA_IO_PU_PD(177),
-	PORT_DATA_IO_PU(178),		PORT_DATA_IO_PD(179),
-
-	PORT_DATA_IO_PD(180),		PORT_DATA_IO_PU(181),
-	PORT_DATA_IO_PU(182),		PORT_DATA_IO(183),
-	PORT_DATA_IO_PD(184),		PORT_DATA_IO_PD(185),
-	PORT_DATA_IO_PD(186),		PORT_DATA_IO_PD(187),
-	PORT_DATA_IO_PD(188),		PORT_DATA_IO_PD(189),
-
-	PORT_DATA_IO_PD(190),		PORT_DATA_IO_PD(191),
-	PORT_DATA_IO_PD(192),		PORT_DATA_IO_PU_PD(193),
-	PORT_DATA_IO_PU_PD(194),	PORT_DATA_IO_PD(195),
-	PORT_DATA_IO_PU_PD(196),	PORT_DATA_IO_PD(197),
-	PORT_DATA_IO_PU_PD(198),	PORT_DATA_IO_PU_PD(199),
-
-	PORT_DATA_IO_PU_PD(200),	PORT_DATA_IO_PU(201),
-	PORT_DATA_IO_PU_PD(202),	PORT_DATA_IO(203),
-	PORT_DATA_IO_PU_PD(204),	PORT_DATA_IO_PU_PD(205),
-	PORT_DATA_IO_PU_PD(206),	PORT_DATA_IO_PU_PD(207),
-	PORT_DATA_IO_PU_PD(208),	PORT_DATA_IO_PD(209),
-
-	PORT_DATA_IO_PD(210),		PORT_DATA_IO_PD(211),
+	PINMUX_DATA_GP_ALL(),
 
 	/* Port0 */
 	PINMUX_DATA(DBGMDT2_MARK,		PORT0_FN1),
@@ -1669,8 +1537,138 @@ static const pinmux_enum_t pinmux_data[] = {
 	PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK,			MSEL5CR_30_1,	MSEL5CR_29_0),
 };
 
+#define R8A7740_PIN(pin, cfgs)						\
+	{								\
+		.name = __stringify(PORT##pin),				\
+		.enum_id = PORT##pin##_DATA,				\
+		.configs = cfgs,					\
+	}
+
+#define __I		(SH_PFC_PIN_CFG_INPUT)
+#define __O		(SH_PFC_PIN_CFG_OUTPUT)
+#define __IO		(SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
+#define __PD		(SH_PFC_PIN_CFG_PULL_DOWN)
+#define __PU		(SH_PFC_PIN_CFG_PULL_UP)
+#define __PUD		(SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
+
+#define R8A7740_PIN_I_PD(pin)		R8A7740_PIN(pin, __I | __PD)
+#define R8A7740_PIN_I_PU(pin)		R8A7740_PIN(pin, __I | __PU)
+#define R8A7740_PIN_I_PU_PD(pin)		R8A7740_PIN(pin, __I | __PUD)
+#define R8A7740_PIN_IO(pin)		R8A7740_PIN(pin, __IO)
+#define R8A7740_PIN_IO_PD(pin)		R8A7740_PIN(pin, __IO | __PD)
+#define R8A7740_PIN_IO_PU(pin)		R8A7740_PIN(pin, __IO | __PU)
+#define R8A7740_PIN_IO_PU_PD(pin)	R8A7740_PIN(pin, __IO | __PUD)
+#define R8A7740_PIN_O(pin)		R8A7740_PIN(pin, __O)
+#define R8A7740_PIN_O_PU_PD(pin)		R8A7740_PIN(pin, __O | __PUD)
+
 static struct sh_pfc_pin pinmux_pins[] = {
-	GPIO_PORT_ALL(),
+	/* Table 56-1 (I/O and Pull U/D) */
+	R8A7740_PIN_IO_PD(0),		R8A7740_PIN_IO_PD(1),
+	R8A7740_PIN_IO_PD(2),		R8A7740_PIN_IO_PD(3),
+	R8A7740_PIN_IO_PD(4),		R8A7740_PIN_IO_PD(5),
+	R8A7740_PIN_IO_PD(6),		R8A7740_PIN_IO(7),
+	R8A7740_PIN_IO(8),		R8A7740_PIN_IO(9),
+	R8A7740_PIN_IO_PD(10),		R8A7740_PIN_IO_PD(11),
+	R8A7740_PIN_IO_PD(12),		R8A7740_PIN_IO_PU_PD(13),
+	R8A7740_PIN_IO_PD(14),		R8A7740_PIN_IO_PD(15),
+	R8A7740_PIN_IO_PD(16),		R8A7740_PIN_IO_PD(17),
+	R8A7740_PIN_IO(18),		R8A7740_PIN_IO_PU(19),
+	R8A7740_PIN_IO_PU_PD(20),	R8A7740_PIN_IO_PD(21),
+	R8A7740_PIN_IO_PU_PD(22),	R8A7740_PIN_IO(23),
+	R8A7740_PIN_IO_PU(24),		R8A7740_PIN_IO_PU(25),
+	R8A7740_PIN_IO_PU(26),		R8A7740_PIN_IO_PU(27),
+	R8A7740_PIN_IO_PU(28),		R8A7740_PIN_IO_PU(29),
+	R8A7740_PIN_IO_PU(30),		R8A7740_PIN_IO_PD(31),
+	R8A7740_PIN_IO_PD(32),		R8A7740_PIN_IO_PD(33),
+	R8A7740_PIN_IO_PD(34),		R8A7740_PIN_IO_PU(35),
+	R8A7740_PIN_IO_PU(36),		R8A7740_PIN_IO_PD(37),
+	R8A7740_PIN_IO_PU(38),		R8A7740_PIN_IO_PD(39),
+	R8A7740_PIN_IO_PU_PD(40),	R8A7740_PIN_IO_PD(41),
+	R8A7740_PIN_IO_PD(42),		R8A7740_PIN_IO_PU_PD(43),
+	R8A7740_PIN_IO_PU_PD(44),	R8A7740_PIN_IO_PU_PD(45),
+	R8A7740_PIN_IO_PU_PD(46),	R8A7740_PIN_IO_PU_PD(47),
+	R8A7740_PIN_IO_PU_PD(48),	R8A7740_PIN_IO_PU_PD(49),
+	R8A7740_PIN_IO_PU_PD(50),	R8A7740_PIN_IO_PD(51),
+	R8A7740_PIN_IO_PD(52),		R8A7740_PIN_IO_PD(53),
+	R8A7740_PIN_IO_PD(54),		R8A7740_PIN_IO_PU_PD(55),
+	R8A7740_PIN_IO_PU_PD(56),	R8A7740_PIN_IO_PU_PD(57),
+	R8A7740_PIN_IO_PU_PD(58),	R8A7740_PIN_IO_PU_PD(59),
+	R8A7740_PIN_IO_PU_PD(60),	R8A7740_PIN_IO_PD(61),
+	R8A7740_PIN_IO_PD(62),		R8A7740_PIN_IO_PD(63),
+	R8A7740_PIN_IO_PD(64),		R8A7740_PIN_IO_PD(65),
+	R8A7740_PIN_IO_PU_PD(66),	R8A7740_PIN_IO_PU_PD(67),
+	R8A7740_PIN_IO_PU_PD(68),	R8A7740_PIN_IO_PU_PD(69),
+	R8A7740_PIN_IO_PU_PD(70),	R8A7740_PIN_IO_PU_PD(71),
+	R8A7740_PIN_IO_PU_PD(72),	R8A7740_PIN_IO_PU_PD(73),
+	R8A7740_PIN_IO_PU_PD(74),	R8A7740_PIN_IO_PU_PD(75),
+	R8A7740_PIN_IO_PU_PD(76),	R8A7740_PIN_IO_PU_PD(77),
+	R8A7740_PIN_IO_PU_PD(78),	R8A7740_PIN_IO_PU_PD(79),
+	R8A7740_PIN_IO_PU_PD(80),	R8A7740_PIN_IO_PU_PD(81),
+	R8A7740_PIN_IO(82),		R8A7740_PIN_IO_PU_PD(83),
+	R8A7740_PIN_IO(84),		R8A7740_PIN_IO_PD(85),
+	R8A7740_PIN_IO_PD(86),		R8A7740_PIN_IO_PD(87),
+	R8A7740_PIN_IO_PD(88),		R8A7740_PIN_IO_PD(89),
+	R8A7740_PIN_IO_PD(90),		R8A7740_PIN_IO_PU_PD(91),
+	R8A7740_PIN_IO_PU_PD(92),	R8A7740_PIN_IO_PU_PD(93),
+	R8A7740_PIN_IO_PU_PD(94),	R8A7740_PIN_IO_PU_PD(95),
+	R8A7740_PIN_IO_PU_PD(96),	R8A7740_PIN_IO_PU_PD(97),
+	R8A7740_PIN_IO_PU_PD(98),	R8A7740_PIN_IO_PU_PD(99),
+	R8A7740_PIN_IO_PU_PD(100),	R8A7740_PIN_IO(101),
+	R8A7740_PIN_IO_PU(102),		R8A7740_PIN_IO_PU_PD(103),
+	R8A7740_PIN_IO_PU(104),		R8A7740_PIN_IO_PU(105),
+	R8A7740_PIN_IO_PU_PD(106),	R8A7740_PIN_IO(107),
+	R8A7740_PIN_IO(108),		R8A7740_PIN_IO(109),
+	R8A7740_PIN_IO(110),		R8A7740_PIN_IO(111),
+	R8A7740_PIN_IO(112),		R8A7740_PIN_IO(113),
+	R8A7740_PIN_IO_PU_PD(114),	R8A7740_PIN_IO(115),
+	R8A7740_PIN_IO_PD(116),		R8A7740_PIN_IO_PD(117),
+	R8A7740_PIN_IO_PD(118),		R8A7740_PIN_IO_PD(119),
+	R8A7740_PIN_IO_PD(120),		R8A7740_PIN_IO_PD(121),
+	R8A7740_PIN_IO_PD(122),		R8A7740_PIN_IO_PD(123),
+	R8A7740_PIN_IO_PD(124),		R8A7740_PIN_IO(125),
+	R8A7740_PIN_IO(126),		R8A7740_PIN_IO(127),
+	R8A7740_PIN_IO(128),		R8A7740_PIN_IO(129),
+	R8A7740_PIN_IO(130),		R8A7740_PIN_IO(131),
+	R8A7740_PIN_IO(132),		R8A7740_PIN_IO(133),
+	R8A7740_PIN_IO(134),		R8A7740_PIN_IO(135),
+	R8A7740_PIN_IO(136),		R8A7740_PIN_IO(137),
+	R8A7740_PIN_IO(138),		R8A7740_PIN_IO(139),
+	R8A7740_PIN_IO(140),		R8A7740_PIN_IO(141),
+	R8A7740_PIN_IO_PU(142),		R8A7740_PIN_IO_PU(143),
+	R8A7740_PIN_IO_PU(144),		R8A7740_PIN_IO_PU(145),
+	R8A7740_PIN_IO_PU(146),		R8A7740_PIN_IO_PU(147),
+	R8A7740_PIN_IO_PU(148),		R8A7740_PIN_IO_PU(149),
+	R8A7740_PIN_IO_PU(150),		R8A7740_PIN_IO_PU(151),
+	R8A7740_PIN_IO_PU(152),		R8A7740_PIN_IO_PU(153),
+	R8A7740_PIN_IO_PU(154),		R8A7740_PIN_IO_PU(155),
+	R8A7740_PIN_IO_PU(156),		R8A7740_PIN_IO_PU(157),
+	R8A7740_PIN_IO_PD(158),		R8A7740_PIN_IO_PD(159),
+	R8A7740_PIN_IO_PU_PD(160),	R8A7740_PIN_IO_PD(161),
+	R8A7740_PIN_IO_PD(162),		R8A7740_PIN_IO_PD(163),
+	R8A7740_PIN_IO_PD(164),		R8A7740_PIN_IO_PD(165),
+	R8A7740_PIN_IO_PU(166),		R8A7740_PIN_IO_PU(167),
+	R8A7740_PIN_IO_PU(168),		R8A7740_PIN_IO_PU(169),
+	R8A7740_PIN_IO_PU(170),		R8A7740_PIN_IO_PU(171),
+	R8A7740_PIN_IO_PD(172),		R8A7740_PIN_IO_PD(173),
+	R8A7740_PIN_IO_PD(174),		R8A7740_PIN_IO_PD(175),
+	R8A7740_PIN_IO_PU(176),		R8A7740_PIN_IO_PU_PD(177),
+	R8A7740_PIN_IO_PU(178),		R8A7740_PIN_IO_PD(179),
+	R8A7740_PIN_IO_PD(180),		R8A7740_PIN_IO_PU(181),
+	R8A7740_PIN_IO_PU(182),		R8A7740_PIN_IO(183),
+	R8A7740_PIN_IO_PD(184),		R8A7740_PIN_IO_PD(185),
+	R8A7740_PIN_IO_PD(186),		R8A7740_PIN_IO_PD(187),
+	R8A7740_PIN_IO_PD(188),		R8A7740_PIN_IO_PD(189),
+	R8A7740_PIN_IO_PD(190),		R8A7740_PIN_IO_PD(191),
+	R8A7740_PIN_IO_PD(192),		R8A7740_PIN_IO_PU_PD(193),
+	R8A7740_PIN_IO_PU_PD(194),	R8A7740_PIN_IO_PD(195),
+	R8A7740_PIN_IO_PU_PD(196),	R8A7740_PIN_IO_PD(197),
+	R8A7740_PIN_IO_PU_PD(198),	R8A7740_PIN_IO_PU_PD(199),
+	R8A7740_PIN_IO_PU_PD(200),	R8A7740_PIN_IO_PU(201),
+	R8A7740_PIN_IO_PU_PD(202),	R8A7740_PIN_IO(203),
+	R8A7740_PIN_IO_PU_PD(204),	R8A7740_PIN_IO_PU_PD(205),
+	R8A7740_PIN_IO_PU_PD(206),	R8A7740_PIN_IO_PU_PD(207),
+	R8A7740_PIN_IO_PU_PD(208),	R8A7740_PIN_IO_PD(209),
+	R8A7740_PIN_IO_PD(210),		R8A7740_PIN_IO_PD(211),
 };
 
 /* - BSC -------------------------------------------------------------------- */
@@ -3204,6 +3202,17 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(sdhi2),
 };
 
+#undef PORTCR
+#define PORTCR(nr, reg)							\
+	{								\
+		PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {		\
+			_PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT),	\
+				PORT##nr##_FN0, PORT##nr##_FN1,		\
+				PORT##nr##_FN2, PORT##nr##_FN3,		\
+				PORT##nr##_FN4, PORT##nr##_FN5,		\
+				PORT##nr##_FN6, PORT##nr##_FN7 }	\
+	}
+
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 	PORTCR(0,	0xe6050000), /* PORT0CR */
 	PORTCR(1,	0xe6050001), /* PORT1CR */
@@ -3657,14 +3666,80 @@ static const struct pinmux_irq pinmux_irqs[] = {
 	PINMUX_IRQ(irq_pin(31), 41,  167),	/* IRQ31A */
 };
 
+#define PORTnCR_PULMD_OFF	(0 << 6)
+#define PORTnCR_PULMD_DOWN	(2 << 6)
+#define PORTnCR_PULMD_UP	(3 << 6)
+#define PORTnCR_PULMD_MASK	(3 << 6)
+
+struct r8a7740_portcr_group {
+	unsigned int end_pin;
+	unsigned int offset;
+};
+
+static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
+	{ 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
+};
+
+static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
+{
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
+		const struct r8a7740_portcr_group *group +			&r8a7740_portcr_offsets[i];
+
+		if (i <= group->end_pin)
+			return pfc->window->virt + group->offset + pin;
+	}
+
+	return NULL;
+}
+
+static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
+{
+	void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
+	u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
+
+	switch (value) {
+	case PORTnCR_PULMD_UP:
+		return PIN_CONFIG_BIAS_PULL_UP;
+	case PORTnCR_PULMD_DOWN:
+		return PIN_CONFIG_BIAS_PULL_DOWN;
+	case PORTnCR_PULMD_OFF:
+	default:
+		return PIN_CONFIG_BIAS_DISABLE;
+	}
+}
+
+static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+				   unsigned int bias)
+{
+	void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
+	u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
+
+	switch (bias) {
+	case PIN_CONFIG_BIAS_PULL_UP:
+		value |= PORTnCR_PULMD_UP;
+		break;
+	case PIN_CONFIG_BIAS_PULL_DOWN:
+		value |= PORTnCR_PULMD_DOWN;
+		break;
+	}
+
+	iowrite8(value, addr);
+}
+
+static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = {
+	.get_bias = r8a7740_pinmux_get_bias,
+	.set_bias = r8a7740_pinmux_set_bias,
+};
+
 const struct sh_pfc_soc_info r8a7740_pinmux_info = {
 	.name		= "r8a7740_pfc",
+	.ops		= &r8a7740_pinmux_ops,
+
 	.input		= { PINMUX_INPUT_BEGIN,
 			    PINMUX_INPUT_END },
-	.input_pu	= { PINMUX_INPUT_PULLUP_BEGIN,
-			    PINMUX_INPUT_PULLUP_END },
-	.input_pd	= { PINMUX_INPUT_PULLDOWN_BEGIN,
-			    PINMUX_INPUT_PULLDOWN_END },
 	.output		= { PINMUX_OUTPUT_BEGIN,
 			    PINMUX_OUTPUT_END },
 	.function	= { PINMUX_FUNCTION_BEGIN,
-- 
1.8.2.1

[PATCH 098/130] sh-pfc: r8a7778: Fix outdated GPIO_FN comments

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Function GPIOs have been removed, remove comments that refer to them.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index b1925cc..72f7a3c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -376,19 +376,19 @@ enum {
 	AVS1_MARK,
 	AVS2_MARK,
 
-	VI0_R0_C_MARK,  /* see GPIO_FN_VI0_R0_A */
-	VI0_R1_C_MARK,  /* see GPIO_FN_VI0_R1_A */
-	VI0_R2_C_MARK,  /* see GPIO_FN_VI0_R2_A */
-	/* VI0_R3_C_MARK,  see GPIO_FN_VI0_R3_A */
-	VI0_R4_C_MARK,  /* see GPIO_FN_VI0_R4_A */
-	VI0_R5_C_MARK,  /* see GPIO_FN_VI0_R5_A */
-
-	VI0_R0_D_MARK,  /* see GPIO_FN_VI0_R0_B */
-	VI0_R1_D_MARK,  /* see GPIO_FN_VI0_R1_B */
-	VI0_R2_D_MARK,  /* see GPIO_FN_VI0_R2_B */
-	VI0_R3_D_MARK,  /* see GPIO_FN_VI0_R3_B */
-	VI0_R4_D_MARK,  /* see GPIO_FN_VI0_R4_B */
-	VI0_R5_D_MARK,  /* see GPIO_FN_VI0_R5_B */
+	VI0_R0_C_MARK,		/* see sel_vi0 */
+	VI0_R1_C_MARK,		/* see sel_vi0 */
+	VI0_R2_C_MARK,		/* see sel_vi0 */
+	/* VI0_R3_C_MARK, */
+	VI0_R4_C_MARK,		/* see sel_vi0 */
+	VI0_R5_C_MARK,		/* see sel_vi0 */
+
+	VI0_R0_D_MARK,		/* see sel_vi0 */
+	VI0_R1_D_MARK,		/* see sel_vi0 */
+	VI0_R2_D_MARK,		/* see sel_vi0 */
+	VI0_R3_D_MARK,		/* see sel_vi0 */
+	VI0_R4_D_MARK,		/* see sel_vi0 */
+	VI0_R5_D_MARK,		/* see sel_vi0 */
 
 	/* IPSR0 */
 	PRESETOUT_MARK,	PWM1_MARK,	AUDATA0_MARK,
-- 
1.8.2.1

[PATCH 099/130] sh-pfc: r8a7778: tidyup SDHI naming suffixes and sort it alphabetically

[Simon Horman]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

SDHI 1/2 are the target

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 164 +++++++++++++++++------------------
 1 file changed, 80 insertions(+), 84 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index 72f7a3c..15295a5 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -1450,60 +1450,56 @@ SDHI_PFC_PINS(sdhi0_wp,		RCAR_GP_PIN(3, 18));
 SDHI_PFC_WPPN(sdhi0_wp,		SD0_WP);
 
 /* - SDHI1 ------------------------------------------------------------------ */
-SDHI_PFC_PINS(sdhi1_a_cd,	RCAR_GP_PIN(0, 30));
-SDHI_PFC_CDPN(sdhi1_a_cd,	SD1_CD_A);
-SDHI_PFC_PINS(sdhi1_a_ctrl,	RCAR_GP_PIN(1, 5),	RCAR_GP_PIN(1, 6));
-SDHI_PFC_CTRL(sdhi1_a_ctrl,	SD1_CLK_A,		SD1_CMD_A);
-SDHI_PFC_PINS(sdhi1_a_data1,	RCAR_GP_PIN(1, 7));
-SDHI_PFC_DAT1(sdhi1_a_data1,	SD1_DAT0_A);
-SDHI_PFC_PINS(sdhi1_a_data4,	RCAR_GP_PIN(1, 7),	RCAR_GP_PIN(1, 8),
+SDHI_PFC_PINS(sdhi1_cd_a,	RCAR_GP_PIN(0, 30));
+SDHI_PFC_CDPN(sdhi1_cd_a,	SD1_CD_A);
+SDHI_PFC_PINS(sdhi1_cd_b,	RCAR_GP_PIN(2, 24));
+SDHI_PFC_CDPN(sdhi1_cd_b,	SD1_CD_B);
+SDHI_PFC_PINS(sdhi1_ctrl_a,	RCAR_GP_PIN(1, 5),	RCAR_GP_PIN(1, 6));
+SDHI_PFC_CTRL(sdhi1_ctrl_a,	SD1_CLK_A,		SD1_CMD_A);
+SDHI_PFC_PINS(sdhi1_ctrl_b,	RCAR_GP_PIN(1, 17),	RCAR_GP_PIN(1, 16));
+SDHI_PFC_CTRL(sdhi1_ctrl_b,	SD1_CLK_B,		SD1_CMD_B);
+SDHI_PFC_PINS(sdhi1_data1_a,	RCAR_GP_PIN(1, 7));
+SDHI_PFC_DAT1(sdhi1_data1_a,	SD1_DAT0_A);
+SDHI_PFC_PINS(sdhi1_data1_b,	RCAR_GP_PIN(1, 18));
+SDHI_PFC_DAT1(sdhi1_data1_b,	SD1_DAT0_B);
+SDHI_PFC_PINS(sdhi1_data4_a,	RCAR_GP_PIN(1, 7),	RCAR_GP_PIN(1, 8),
 				RCAR_GP_PIN(0, 5),	RCAR_GP_PIN(0, 6));
-SDHI_PFC_DAT4(sdhi1_a_data4,	SD1_DAT0_A,		SD1_DAT1_A,
+SDHI_PFC_DAT4(sdhi1_data4_a,	SD1_DAT0_A,		SD1_DAT1_A,
 				SD1_DAT2_A,		SD1_DAT3_A);
-SDHI_PFC_PINS(sdhi1_a_wp,	RCAR_GP_PIN(0, 31));
-SDHI_PFC_WPPN(sdhi1_a_wp,	SD1_WP_A);
-
-SDHI_PFC_PINS(sdhi1_b_cd,	RCAR_GP_PIN(2, 24));
-SDHI_PFC_CDPN(sdhi1_b_cd,	SD1_CD_B);
-SDHI_PFC_PINS(sdhi1_b_ctrl,	RCAR_GP_PIN(1, 17),	RCAR_GP_PIN(1, 16));
-SDHI_PFC_CTRL(sdhi1_b_ctrl,	SD1_CLK_B,		SD1_CMD_B);
-SDHI_PFC_PINS(sdhi1_b_data1,	RCAR_GP_PIN(1, 18));
-SDHI_PFC_DAT1(sdhi1_b_data1,	SD1_DAT0_B);
-SDHI_PFC_PINS(sdhi1_b_data4,	RCAR_GP_PIN(1, 18),	RCAR_GP_PIN(1, 19),
+SDHI_PFC_PINS(sdhi1_data4_b,	RCAR_GP_PIN(1, 18),	RCAR_GP_PIN(1, 19),
 				RCAR_GP_PIN(1, 20),	RCAR_GP_PIN(1, 21));
-SDHI_PFC_DAT4(sdhi1_b_data4,	SD1_DAT0_B,		SD1_DAT1_B,
+SDHI_PFC_DAT4(sdhi1_data4_b,	SD1_DAT0_B,		SD1_DAT1_B,
 				SD1_DAT2_B,		SD1_DAT3_B);
-SDHI_PFC_PINS(sdhi1_b_wp,	RCAR_GP_PIN(2, 25));
-SDHI_PFC_WPPN(sdhi1_b_wp,	SD1_WP_B);
-
+SDHI_PFC_PINS(sdhi1_wp_a,	RCAR_GP_PIN(0, 31));
+SDHI_PFC_WPPN(sdhi1_wp_a,	SD1_WP_A);
+SDHI_PFC_PINS(sdhi1_wp_b,	RCAR_GP_PIN(2, 25));
+SDHI_PFC_WPPN(sdhi1_wp_b,	SD1_WP_B);
 
 /* - SDH2 ------------------------------------------------------------------- */
-SDHI_PFC_PINS(sdhi2_a_cd,	RCAR_GP_PIN(4, 23));
-SDHI_PFC_CDPN(sdhi2_a_cd,	SD2_CD_A);
-SDHI_PFC_PINS(sdhi2_a_ctrl,	RCAR_GP_PIN(4, 17),	RCAR_GP_PIN(4, 18));
-SDHI_PFC_CTRL(sdhi2_a_ctrl,	SD2_CLK_A,		SD2_CMD_A);
-SDHI_PFC_PINS(sdhi2_a_data1,	RCAR_GP_PIN(4, 19));
-SDHI_PFC_DAT1(sdhi2_a_data1,	SD2_DAT0_A);
-SDHI_PFC_PINS(sdhi2_a_data4,	RCAR_GP_PIN(4, 19),	RCAR_GP_PIN(4, 20),
+SDHI_PFC_PINS(sdhi2_cd_a,	RCAR_GP_PIN(4, 23));
+SDHI_PFC_CDPN(sdhi2_cd_a,	SD2_CD_A);
+SDHI_PFC_PINS(sdhi2_cd_b,	RCAR_GP_PIN(3, 27));
+SDHI_PFC_CDPN(sdhi2_cd_b,	SD2_CD_B);
+SDHI_PFC_PINS(sdhi2_ctrl_a,	RCAR_GP_PIN(4, 17),	RCAR_GP_PIN(4, 18));
+SDHI_PFC_CTRL(sdhi2_ctrl_a,	SD2_CLK_A,		SD2_CMD_A);
+SDHI_PFC_PINS(sdhi2_ctrl_b,	RCAR_GP_PIN(4, 5),	RCAR_GP_PIN(4, 6));
+SDHI_PFC_CTRL(sdhi2_ctrl_b,	SD2_CLK_B,		SD2_CMD_B);
+SDHI_PFC_PINS(sdhi2_data1_a,	RCAR_GP_PIN(4, 19));
+SDHI_PFC_DAT1(sdhi2_data1_a,	SD2_DAT0_A);
+SDHI_PFC_PINS(sdhi2_data1_b,	RCAR_GP_PIN(4, 7));
+SDHI_PFC_DAT1(sdhi2_data1_b,	SD2_DAT0_B);
+SDHI_PFC_PINS(sdhi2_data4_a,	RCAR_GP_PIN(4, 19),	RCAR_GP_PIN(4, 20),
 				RCAR_GP_PIN(4, 21),	RCAR_GP_PIN(4, 22));
-SDHI_PFC_DAT4(sdhi2_a_data4,	SD2_DAT0_A,		SD2_DAT1_A,
+SDHI_PFC_DAT4(sdhi2_data4_a,	SD2_DAT0_A,		SD2_DAT1_A,
 				SD2_DAT2_A,		SD2_DAT3_A);
-SDHI_PFC_PINS(sdhi2_a_wp,	RCAR_GP_PIN(4, 24));
-SDHI_PFC_WPPN(sdhi2_a_wp,	SD2_WP_A);
-
-SDHI_PFC_PINS(sdhi2_b_cd,	RCAR_GP_PIN(3, 27));
-SDHI_PFC_CDPN(sdhi2_b_cd,	SD2_CD_B);
-SDHI_PFC_PINS(sdhi2_b_ctrl,	RCAR_GP_PIN(4, 5),	RCAR_GP_PIN(4, 6));
-SDHI_PFC_CTRL(sdhi2_b_ctrl,	SD2_CLK_B,		SD2_CMD_B);
-SDHI_PFC_PINS(sdhi2_b_data1,	RCAR_GP_PIN(4, 7));
-SDHI_PFC_DAT1(sdhi2_b_data1,	SD2_DAT0_B);
-SDHI_PFC_PINS(sdhi2_b_data4,	RCAR_GP_PIN(4, 7),	RCAR_GP_PIN(4, 8),
+SDHI_PFC_PINS(sdhi2_data4_b,	RCAR_GP_PIN(4, 7),	RCAR_GP_PIN(4, 8),
 				RCAR_GP_PIN(3, 25),	RCAR_GP_PIN(3, 26));
-SDHI_PFC_DAT4(sdhi2_b_data4,	SD2_DAT0_B,		SD2_DAT1_B,
+SDHI_PFC_DAT4(sdhi2_data4_b,	SD2_DAT0_B,		SD2_DAT1_B,
 				SD2_DAT2_B,		SD2_DAT3_B);
-SDHI_PFC_PINS(sdhi2_b_wp,	RCAR_GP_PIN(3, 28));
-SDHI_PFC_WPPN(sdhi2_b_wp,	SD2_WP_B);
-
+SDHI_PFC_PINS(sdhi2_wp_a,	RCAR_GP_PIN(4, 24));
+SDHI_PFC_WPPN(sdhi2_wp_a,	SD2_WP_A);
+SDHI_PFC_PINS(sdhi2_wp_b,	RCAR_GP_PIN(3, 28));
+SDHI_PFC_WPPN(sdhi2_wp_b,	SD2_WP_B);
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(hscif0_data_a),
@@ -1554,26 +1550,26 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(sdhi0_data1),
 	SH_PFC_PIN_GROUP(sdhi0_data4),
 	SH_PFC_PIN_GROUP(sdhi0_wp),
-	SH_PFC_PIN_GROUP(sdhi1_a_cd),
-	SH_PFC_PIN_GROUP(sdhi1_a_ctrl),
-	SH_PFC_PIN_GROUP(sdhi1_a_data1),
-	SH_PFC_PIN_GROUP(sdhi1_a_data4),
-	SH_PFC_PIN_GROUP(sdhi1_a_wp),
-	SH_PFC_PIN_GROUP(sdhi1_b_cd),
-	SH_PFC_PIN_GROUP(sdhi1_b_ctrl),
-	SH_PFC_PIN_GROUP(sdhi1_b_data1),
-	SH_PFC_PIN_GROUP(sdhi1_b_data4),
-	SH_PFC_PIN_GROUP(sdhi1_b_wp),
-	SH_PFC_PIN_GROUP(sdhi2_a_cd),
-	SH_PFC_PIN_GROUP(sdhi2_a_ctrl),
-	SH_PFC_PIN_GROUP(sdhi2_a_data1),
-	SH_PFC_PIN_GROUP(sdhi2_a_data4),
-	SH_PFC_PIN_GROUP(sdhi2_a_wp),
-	SH_PFC_PIN_GROUP(sdhi2_b_cd),
-	SH_PFC_PIN_GROUP(sdhi2_b_ctrl),
-	SH_PFC_PIN_GROUP(sdhi2_b_data1),
-	SH_PFC_PIN_GROUP(sdhi2_b_data4),
-	SH_PFC_PIN_GROUP(sdhi2_b_wp),
+	SH_PFC_PIN_GROUP(sdhi1_cd_a),
+	SH_PFC_PIN_GROUP(sdhi1_cd_b),
+	SH_PFC_PIN_GROUP(sdhi1_ctrl_a),
+	SH_PFC_PIN_GROUP(sdhi1_ctrl_b),
+	SH_PFC_PIN_GROUP(sdhi1_data1_a),
+	SH_PFC_PIN_GROUP(sdhi1_data1_b),
+	SH_PFC_PIN_GROUP(sdhi1_data4_a),
+	SH_PFC_PIN_GROUP(sdhi1_data4_b),
+	SH_PFC_PIN_GROUP(sdhi1_wp_a),
+	SH_PFC_PIN_GROUP(sdhi1_wp_b),
+	SH_PFC_PIN_GROUP(sdhi2_cd_a),
+	SH_PFC_PIN_GROUP(sdhi2_cd_b),
+	SH_PFC_PIN_GROUP(sdhi2_ctrl_a),
+	SH_PFC_PIN_GROUP(sdhi2_ctrl_b),
+	SH_PFC_PIN_GROUP(sdhi2_data1_a),
+	SH_PFC_PIN_GROUP(sdhi2_data1_b),
+	SH_PFC_PIN_GROUP(sdhi2_data4_a),
+	SH_PFC_PIN_GROUP(sdhi2_data4_b),
+	SH_PFC_PIN_GROUP(sdhi2_wp_a),
+	SH_PFC_PIN_GROUP(sdhi2_wp_b),
 };
 
 static const char * const hscif0_groups[] = {
@@ -1656,29 +1652,29 @@ static const char * const sdhi0_groups[] = {
 };
 
 static const char * const sdhi1_groups[] = {
-	"sdhi1_a_cd",
-	"sdhi1_a_ctrl",
-	"sdhi1_a_data1",
-	"sdhi1_a_data4",
-	"sdhi1_a_wp",
-	"sdhi1_b_cd",
-	"sdhi1_b_ctrl",
-	"sdhi1_b_data1",
-	"sdhi1_b_data4",
-	"sdhi1_b_wp",
+	"sdhi1_cd_a",
+	"sdhi1_cd_b",
+	"sdhi1_ctrl_a",
+	"sdhi1_ctrl_b",
+	"sdhi1_data1_a",
+	"sdhi1_data1_b",
+	"sdhi1_data4_a",
+	"sdhi1_data4_b",
+	"sdhi1_wp_a",
+	"sdhi1_wp_b",
 };
 
 static const char * const sdhi2_groups[] = {
-	"sdhi2_a_cd",
-	"sdhi2_a_ctrl",
-	"sdhi2_a_data1",
-	"sdhi2_a_data4",
-	"sdhi2_a_wp",
-	"sdhi2_b_cd",
-	"sdhi2_b_ctrl",
-	"sdhi2_b_data1",
-	"sdhi2_b_data4",
-	"sdhi2_b_wp",
+	"sdhi2_cd_a",
+	"sdhi2_cd_b",
+	"sdhi2_ctrl_a",
+	"sdhi2_ctrl_b",
+	"sdhi2_data1_a",
+	"sdhi2_data1_b",
+	"sdhi2_data4_a",
+	"sdhi2_data4_b",
+	"sdhi2_wp_a",
+	"sdhi2_wp_b",
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
-- 
1.8.2.1

[PATCH 100/130] ARM: shmobile: r8a7778: add GPIO support

[Simon Horman]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

This patch was tested on Bock-W board

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/setup-r8a7778.c | 36 +++++++++++++++++++++++++++++++++-
 1 file changed, 35 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 0ca5701..1f36ecc 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -24,6 +24,7 @@
 #include <linux/irqchip/arm-gic.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
 #include <linux/platform_device.h>
 #include <linux/irqchip.h>
@@ -94,17 +95,50 @@ static struct resource ether_resources[] = {
 		&sh_tmu##idx##_platform_data,		\
 		sizeof(sh_tmu##idx##_platform_data))
 
-/* PFC */
+/* PFC/GPIO */
 static struct resource pfc_resources[] = {
 	DEFINE_RES_MEM(0xfffc0000, 0x118),
 };
 
+#define R8A7778_GPIO(idx)						\
+static struct resource r8a7778_gpio##idx##_resources[] = {		\
+	DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30),		\
+	DEFINE_RES_IRQ(gic_iid(0x87)),					\
+};									\
+									\
+static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data = {	\
+	.gpio_base	= 32 * (idx),					\
+	.irq_base	= GPIO_IRQ_BASE(idx),				\
+	.number_of_pins	= 32,						\
+	.pctl_name	= "pfc-r8a7778",				\
+}
+
+R8A7778_GPIO(0);
+R8A7778_GPIO(1);
+R8A7778_GPIO(2);
+R8A7778_GPIO(3);
+R8A7778_GPIO(4);
+
+#define r8a7778_register_gpio(idx)				\
+	platform_device_register_resndata(			\
+		&platform_bus, "gpio_rcar", idx,		\
+		r8a7778_gpio##idx##_resources,			\
+		ARRAY_SIZE(r8a7778_gpio##idx##_resources),	\
+		&r8a7778_gpio##idx##_platform_data,		\
+		sizeof(r8a7778_gpio##idx##_platform_data))
+
 void __init r8a7778_pinmux_init(void)
 {
 	platform_device_register_simple(
 		"pfc-r8a7778", -1,
 		pfc_resources,
 		ARRAY_SIZE(pfc_resources));
+
+	r8a7778_register_gpio(0);
+	r8a7778_register_gpio(1);
+	r8a7778_register_gpio(2);
+	r8a7778_register_gpio(3);
+	r8a7778_register_gpio(4);
 }
 
 void __init r8a7778_add_standard_devices(void)
-- 
1.8.2.1

[PATCH 101/130] ARM: shmobile: r8a7790: Register GPIO devices

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Move GPIOs handling from the PFC device to separate GPIO devices.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/setup-r8a7790.c | 35 +++++++++++++++++++++++++++++++++-
 1 file changed, 34 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 49de2d5..eeef5f6 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -23,6 +23,7 @@
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/serial_sci.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/irq-renesas-irqc.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
@@ -31,13 +32,45 @@
 
 static const struct resource pfc_resources[] = {
 	DEFINE_RES_MEM(0xe6060000, 0x250),
-	DEFINE_RES_MEM(0xe6050000, 0x5050),
 };
 
+#define R8A7790_GPIO(idx)						\
+static struct resource r8a7790_gpio##idx##_resources[] = {		\
+	DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50),		\
+	DEFINE_RES_IRQ(gic_spi(4 + (idx))),				\
+};									\
+									\
+static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data = {	\
+	.gpio_base	= 32 * (idx),					\
+	.irq_base	= 0,						\
+	.number_of_pins	= 32,						\
+	.pctl_name	= "pfc-r8a7790",				\
+};									\
+
+R8A7790_GPIO(0);
+R8A7790_GPIO(1);
+R8A7790_GPIO(2);
+R8A7790_GPIO(3);
+R8A7790_GPIO(4);
+R8A7790_GPIO(5);
+
+#define r8a7790_register_gpio(idx)					\
+	platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
+		r8a7790_gpio##idx##_resources,				\
+		ARRAY_SIZE(r8a7790_gpio##idx##_resources),		\
+		&r8a7790_gpio##idx##_platform_data,			\
+		sizeof(r8a7790_gpio##idx##_platform_data))
+
 void __init r8a7790_pinmux_init(void)
 {
 	platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
 					ARRAY_SIZE(pfc_resources));
+	r8a7790_register_gpio(0);
+	r8a7790_register_gpio(1);
+	r8a7790_register_gpio(2);
+	r8a7790_register_gpio(3);
+	r8a7790_register_gpio(4);
+	r8a7790_register_gpio(5);
 }
 
 #define SCIF_COMMON(scif_type, baseaddr, irq)			\
-- 
1.8.2.1

[PATCH 102/130] ARM: shmobile: r8a7790: Remove all GPIOs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Function GPIOs are not used anymore, and all code use the GPIO numbers
directly. Remove the GPIOs enumeration.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/include/mach/r8a7790.h | 383 --------------------------
 1 file changed, 383 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
index e01ac4e..2e919e6 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
@@ -1,389 +1,6 @@
 #ifndef __ASM_R8A7790_H__
 #define __ASM_R8A7790_H__
 
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
- */
-enum {
-	GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
-	GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
-	GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
-	GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
-	GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
-	GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
-	GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
-	GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
-
-	GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
-	GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
-	GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
-	GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
-	GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
-	GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
-	GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
-	GPIO_GP_1_28, GPIO_GP_1_29,
-
-	GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
-	GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
-	GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
-	GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
-	GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
-	GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
-	GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
-	GPIO_GP_2_28, GPIO_GP_2_29,
-
-	GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
-	GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
-	GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
-	GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
-	GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
-	GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
-	GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
-	GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
-
-	GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
-	GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
-	GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
-	GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
-	GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
-	GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
-	GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
-	GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
-
-	GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
-	GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
-	GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
-	GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
-	GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
-	GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
-	GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
-	GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
-
-	GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC_VBUS,
-	GPIO_FN_USB2_PWEN, GPIO_FN_USB2_OVC, GPIO_FN_AVS1, GPIO_FN_AVS2,
-	GPIO_FN_DU_DOTCLKIN0, GPIO_FN_DU_DOTCLKIN2,
-
-	/* IPSR0 */
-	GPIO_FN_D1, GPIO_FN_MSIOF3_SYNC_B, GPIO_FN_VI3_DATA1, GPIO_FN_VI0_G5,
-	GPIO_FN_VI0_G5_B, GPIO_FN_D2, GPIO_FN_MSIOF3_RXD_B, GPIO_FN_VI3_DATA2,
-	GPIO_FN_VI0_G6, GPIO_FN_VI0_G6_B, GPIO_FN_D3, GPIO_FN_MSIOF3_TXD_B,
-	GPIO_FN_VI3_DATA3, GPIO_FN_VI0_G7, GPIO_FN_VI0_G7_B, GPIO_FN_D4,
-	GPIO_FN_SCIFB1_RXD_F, GPIO_FN_SCIFB0_RXD_C, GPIO_FN_VI3_DATA4,
-	GPIO_FN_VI0_R0, GPIO_FN_VI0_R0_B, GPIO_FN_RX0_B, GPIO_FN_D5,
-	GPIO_FN_SCIFB1_TXD_F, GPIO_FN_SCIFB0_TXD_C, GPIO_FN_VI3_DATA5,
-	GPIO_FN_VI0_R1, GPIO_FN_VI0_R1_B, GPIO_FN_TX0_B, GPIO_FN_D6,
-	GPIO_FN_SCL2_C, GPIO_FN_VI3_DATA6, GPIO_FN_VI0_R2, GPIO_FN_VI0_R2_B,
-	GPIO_FN_SCL2_CIS_C, GPIO_FN_D7, GPIO_FN_AD_DI_B, GPIO_FN_SDA2_C,
-	GPIO_FN_VI3_DATA7, GPIO_FN_VI0_R3, GPIO_FN_VI0_R3_B, GPIO_FN_SDA2_CIS_C,
-	GPIO_FN_D8, GPIO_FN_SCIFA1_SCK_C, GPIO_FN_AVB_TXD0, GPIO_FN_MII_TXD0,
-	GPIO_FN_VI0_G0, GPIO_FN_VI0_G0_B, GPIO_FN_VI2_DATA0_VI2_B0,
-
-	/* IPSR1 */
-	GPIO_FN_D9, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_AVB_TXD1, GPIO_FN_MII_TXD1,
-	GPIO_FN_VI0_G1, GPIO_FN_VI0_G1_B, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_D10,
-	GPIO_FN_SCIFA1_TXD_C, GPIO_FN_AVB_TXD2, GPIO_FN_MII_TXD2,
-	GPIO_FN_VI0_G2, GPIO_FN_VI0_G2_B, GPIO_FN_VI2_DATA2_VI2_B2, GPIO_FN_D11,
-	GPIO_FN_SCIFA1_CTS_N_C, GPIO_FN_AVB_TXD3, GPIO_FN_MII_TXD3,
-	GPIO_FN_VI0_G3, GPIO_FN_VI0_G3_B, GPIO_FN_VI2_DATA3_VI2_B3,
-	GPIO_FN_D12, GPIO_FN_SCIFA1_RTS_N_C, GPIO_FN_AVB_TXD4,
-	GPIO_FN_VI0_HSYNC_N, GPIO_FN_VI0_HSYNC_N_B, GPIO_FN_VI2_DATA4_VI2_B4,
-	GPIO_FN_D13, GPIO_FN_AVB_TXD5, GPIO_FN_VI0_VSYNC_N,
-	GPIO_FN_VI0_VSYNC_N_B, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_D14,
-	GPIO_FN_SCIFB1_RXD_C, GPIO_FN_AVB_TXD6, GPIO_FN_RX1_B,
-	GPIO_FN_VI0_CLKENB, GPIO_FN_VI0_CLKENB_B, GPIO_FN_VI2_DATA6_VI2_B6,
-	GPIO_FN_D15, GPIO_FN_SCIFB1_TXD_C, GPIO_FN_AVB_TXD7, GPIO_FN_TX1_B,
-	GPIO_FN_VI0_FIELD, GPIO_FN_VI0_FIELD_B, GPIO_FN_VI2_DATA7_VI2_B7,
-	GPIO_FN_A0, GPIO_FN_PWM3, GPIO_FN_A1, GPIO_FN_PWM4,
-
-	/* IPSR2 */
-	GPIO_FN_A2, GPIO_FN_PWM5, GPIO_FN_MSIOF1_SS1_B, GPIO_FN_A3,
-	GPIO_FN_PWM6, GPIO_FN_MSIOF1_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF1_TXD_B,
-	GPIO_FN_TPU0TO0, GPIO_FN_A5, GPIO_FN_SCIFA1_TXD_B, GPIO_FN_TPU0TO1,
-	GPIO_FN_A6, GPIO_FN_SCIFA1_RTS_N_B, GPIO_FN_TPU0TO2, GPIO_FN_A7,
-	GPIO_FN_SCIFA1_SCK_B, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_TPU0TO3,
-	GPIO_FN_A8, GPIO_FN_SCIFA1_RXD_B, GPIO_FN_SSI_SCK5_B, GPIO_FN_VI0_R4,
-	GPIO_FN_VI0_R4_B, GPIO_FN_SCIFB2_RXD_C, GPIO_FN_VI2_DATA0_VI2_B0_B,
-	GPIO_FN_A9, GPIO_FN_SCIFA1_CTS_N_B, GPIO_FN_SSI_WS5_B, GPIO_FN_VI0_R5,
-	GPIO_FN_VI0_R5_B, GPIO_FN_SCIFB2_TXD_C, GPIO_FN_VI2_DATA1_VI2_B1_B,
-	GPIO_FN_A10, GPIO_FN_SSI_SDATA5_B, GPIO_FN_MSIOF2_SYNC, GPIO_FN_VI0_R6,
-	GPIO_FN_VI0_R6_B, GPIO_FN_VI2_DATA2_VI2_B2_B,
-
-	/* IPSR3 */
-	GPIO_FN_A11, GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_MSIOF2_SCK, GPIO_FN_VI1_R0,
-	GPIO_FN_VI1_R0_B, GPIO_FN_VI2_G0, GPIO_FN_VI2_DATA3_VI2_B3_B,
-	GPIO_FN_A12, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_MSIOF2_TXD, GPIO_FN_VI1_R1,
-	GPIO_FN_VI1_R1_B, GPIO_FN_VI2_G1, GPIO_FN_VI2_DATA4_VI2_B4_B,
-	GPIO_FN_A13, GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_EX_WAIT2,
-	GPIO_FN_MSIOF2_RXD, GPIO_FN_VI1_R2, GPIO_FN_VI1_R2_B, GPIO_FN_VI2_G2,
-	GPIO_FN_VI2_DATA5_VI2_B5_B, GPIO_FN_A14, GPIO_FN_SCIFB2_TXD_B,
-	GPIO_FN_ATACS11_N, GPIO_FN_MSIOF2_SS1, GPIO_FN_A15,
-	GPIO_FN_SCIFB2_SCK_B, GPIO_FN_ATARD1_N, GPIO_FN_MSIOF2_SS2, GPIO_FN_A16,
-	GPIO_FN_ATAWR1_N, GPIO_FN_A17, GPIO_FN_AD_DO_B, GPIO_FN_ATADIR1_N,
-	GPIO_FN_A18, GPIO_FN_AD_CLK_B, GPIO_FN_ATAG1_N, GPIO_FN_A19,
-	GPIO_FN_AD_NCS_N_B, GPIO_FN_ATACS01_N, GPIO_FN_EX_WAIT0_B, GPIO_FN_A20,
-	GPIO_FN_SPCLK, GPIO_FN_VI1_R3, GPIO_FN_VI1_R3_B, GPIO_FN_VI2_G4,
-
-	/* IPSR4 */
-	GPIO_FN_A21, GPIO_FN_MOSI_IO0, GPIO_FN_VI1_R4, GPIO_FN_VI1_R4_B,
-	GPIO_FN_VI2_G5, GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_VI1_R5,
-	GPIO_FN_VI1_R5_B, GPIO_FN_VI2_G6, GPIO_FN_A23, GPIO_FN_IO2,
-	GPIO_FN_VI1_G7, GPIO_FN_VI1_G7_B, GPIO_FN_VI2_G7, GPIO_FN_A24,
-	GPIO_FN_IO3, GPIO_FN_VI1_R7, GPIO_FN_VI1_R7_B, GPIO_FN_VI2_CLKENB,
-	GPIO_FN_VI2_CLKENB_B, GPIO_FN_A25, GPIO_FN_SSL, GPIO_FN_VI1_G6,
-	GPIO_FN_VI1_G6_B, GPIO_FN_VI2_FIELD, GPIO_FN_VI2_FIELD_B, GPIO_FN_CS0_N,
-	GPIO_FN_VI1_R6, GPIO_FN_VI1_R6_B, GPIO_FN_VI2_G3, GPIO_FN_MSIOF0_SS2_B,
-	GPIO_FN_CS1_N_A26, GPIO_FN_SPEEDIN, GPIO_FN_VI0_R7, GPIO_FN_VI0_R7_B,
-	GPIO_FN_VI2_CLK, GPIO_FN_VI2_CLK_B, GPIO_FN_EX_CS0_N, GPIO_FN_HRX1_B,
-	GPIO_FN_VI1_G5, GPIO_FN_VI1_G5_B, GPIO_FN_VI2_R0, GPIO_FN_HTX0_B,
-	GPIO_FN_MSIOF0_SS1_B, GPIO_FN_EX_CS1_N, GPIO_FN_GPS_CLK,
-	GPIO_FN_HCTS1_N_B, GPIO_FN_VI1_FIELD, GPIO_FN_VI1_FIELD_B,
-	GPIO_FN_VI2_R1, GPIO_FN_EX_CS2_N, GPIO_FN_GPS_SIGN, GPIO_FN_HRTS1_N_B,
-	GPIO_FN_VI3_CLKENB, GPIO_FN_VI1_G0, GPIO_FN_VI1_G0_B, GPIO_FN_VI2_R2,
-
-	/* IPSR5 */
-	GPIO_FN_EX_CS3_N, GPIO_FN_GPS_MAG, GPIO_FN_VI3_FIELD, GPIO_FN_VI1_G1,
-	GPIO_FN_VI1_G1_B, GPIO_FN_VI2_R3, GPIO_FN_EX_CS4_N,
-	GPIO_FN_MSIOF1_SCK_B, GPIO_FN_VI3_HSYNC_N,
-	GPIO_FN_VI2_HSYNC_N, GPIO_FN_SCL1, GPIO_FN_VI2_HSYNC_N_B,
-	GPIO_FN_INTC_EN0_N, GPIO_FN_SCL1_CIS, GPIO_FN_EX_CS5_N, GPIO_FN_CAN0_RX,
-	GPIO_FN_MSIOF1_RXD_B, GPIO_FN_VI3_VSYNC_N, GPIO_FN_VI1_G2,
-	GPIO_FN_VI1_G2_B, GPIO_FN_VI2_R4, GPIO_FN_SDA1, GPIO_FN_INTC_EN1_N,
-	GPIO_FN_SDA1_CIS, GPIO_FN_BS_N, GPIO_FN_IETX, GPIO_FN_HTX1_B,
-	GPIO_FN_CAN1_TX, GPIO_FN_DRACK0, GPIO_FN_IETX_C, GPIO_FN_RD_N,
-	GPIO_FN_CAN0_TX, GPIO_FN_SCIFA0_SCK_B, GPIO_FN_RD_WR_N, GPIO_FN_VI1_G3,
-	GPIO_FN_VI1_G3_B, GPIO_FN_VI2_R5, GPIO_FN_SCIFA0_RXD_B,
-	GPIO_FN_INTC_IRQ4_N, GPIO_FN_WE0_N, GPIO_FN_IECLK, GPIO_FN_CAN_CLK,
-	GPIO_FN_VI2_VSYNC_N, GPIO_FN_SCIFA0_TXD_B, GPIO_FN_VI2_VSYNC_N_B,
-	GPIO_FN_WE1_N, GPIO_FN_IERX, GPIO_FN_CAN1_RX, GPIO_FN_VI1_G4,
-	GPIO_FN_VI1_G4_B, GPIO_FN_VI2_R6, GPIO_FN_SCIFA0_CTS_N_B,
-	GPIO_FN_IERX_C, GPIO_FN_EX_WAIT0, GPIO_FN_IRQ3, GPIO_FN_INTC_IRQ3_N,
-	GPIO_FN_VI3_CLK, GPIO_FN_SCIFA0_RTS_N_B, GPIO_FN_HRX0_B,
-	GPIO_FN_MSIOF0_SCK_B, GPIO_FN_DREQ0_N, GPIO_FN_VI1_HSYNC_N,
-	GPIO_FN_VI1_HSYNC_N_B, GPIO_FN_VI2_R7, GPIO_FN_SSI_SCK78_C,
-	GPIO_FN_SSI_WS78_B,
-
-	/* IPSR6 */
-	GPIO_FN_DACK0, GPIO_FN_IRQ0, GPIO_FN_INTC_IRQ0_N, GPIO_FN_SSI_SCK6_B,
-	GPIO_FN_VI1_VSYNC_N, GPIO_FN_VI1_VSYNC_N_B, GPIO_FN_SSI_WS78_C,
-	GPIO_FN_DREQ1_N, GPIO_FN_VI1_CLKENB, GPIO_FN_VI1_CLKENB_B,
-	GPIO_FN_SSI_SDATA7_C, GPIO_FN_SSI_SCK78_B, GPIO_FN_DACK1, GPIO_FN_IRQ1,
-	GPIO_FN_INTC_IRQ1_N, GPIO_FN_SSI_WS6_B, GPIO_FN_SSI_SDATA8_C,
-	GPIO_FN_DREQ2_N, GPIO_FN_HSCK1_B, GPIO_FN_HCTS0_N_B,
-	GPIO_FN_MSIOF0_TXD_B, GPIO_FN_DACK2, GPIO_FN_IRQ2, GPIO_FN_INTC_IRQ2_N,
-	GPIO_FN_SSI_SDATA6_B, GPIO_FN_HRTS0_N_B, GPIO_FN_MSIOF0_RXD_B,
-	GPIO_FN_ETH_CRS_DV, GPIO_FN_RMII_CRS_DV, GPIO_FN_STP_ISCLK_0_B,
-	GPIO_FN_TS_SDEN0_D, GPIO_FN_GLO_Q0_C, GPIO_FN_SCL2_E,
-	GPIO_FN_SCL2_CIS_E, GPIO_FN_ETH_RX_ER, GPIO_FN_RMII_RX_ER,
-	GPIO_FN_STP_ISD_0_B, GPIO_FN_TS_SPSYNC0_D, GPIO_FN_GLO_Q1_C,
-	GPIO_FN_SDA2_E, GPIO_FN_SDA2_CIS_E, GPIO_FN_ETH_RXD0, GPIO_FN_RMII_RXD0,
-	GPIO_FN_STP_ISEN_0_B, GPIO_FN_TS_SDAT0_D, GPIO_FN_GLO_I0_C,
-	GPIO_FN_SCIFB1_SCK_G, GPIO_FN_SCK1_E, GPIO_FN_ETH_RXD1,
-	GPIO_FN_RMII_RXD1, GPIO_FN_HRX0_E, GPIO_FN_STP_ISSYNC_0_B,
-	GPIO_FN_TS_SCK0_D, GPIO_FN_GLO_I1_C, GPIO_FN_SCIFB1_RXD_G,
-	GPIO_FN_RX1_E, GPIO_FN_ETH_LINK, GPIO_FN_RMII_LINK, GPIO_FN_HTX0_E,
-	GPIO_FN_STP_IVCXO27_0_B, GPIO_FN_SCIFB1_TXD_G, GPIO_FN_TX1_E,
-	GPIO_FN_ETH_REF_CLK, GPIO_FN_RMII_REF_CLK, GPIO_FN_HCTS0_N_E,
-	GPIO_FN_STP_IVCXO27_1_B, GPIO_FN_HRX0_F,
-
-	/* IPSR7 */
-	GPIO_FN_ETH_MDIO, GPIO_FN_RMII_MDIO, GPIO_FN_HRTS0_N_E,
-	GPIO_FN_SIM0_D_C, GPIO_FN_HCTS0_N_F, GPIO_FN_ETH_TXD1,
-	GPIO_FN_RMII_TXD1, GPIO_FN_HTX0_F, GPIO_FN_BPFCLK_G, GPIO_FN_RDS_CLK_F,
-	GPIO_FN_ETH_TX_EN, GPIO_FN_RMII_TX_EN, GPIO_FN_SIM0_CLK_C,
-	GPIO_FN_HRTS0_N_F, GPIO_FN_ETH_MAGIC, GPIO_FN_RMII_MAGIC,
-	GPIO_FN_SIM0_RST_C, GPIO_FN_ETH_TXD0, GPIO_FN_RMII_TXD0,
-	GPIO_FN_STP_ISCLK_1_B, GPIO_FN_TS_SDEN1_C, GPIO_FN_GLO_SCLK_C,
-	GPIO_FN_ETH_MDC, GPIO_FN_RMII_MDC, GPIO_FN_STP_ISD_1_B,
-	GPIO_FN_TS_SPSYNC1_C, GPIO_FN_GLO_SDATA_C, GPIO_FN_PWM0,
-	GPIO_FN_SCIFA2_SCK_C, GPIO_FN_STP_ISEN_1_B, GPIO_FN_TS_SDAT1_C,
-	GPIO_FN_GLO_SS_C, GPIO_FN_PWM1, GPIO_FN_SCIFA2_TXD_C,
-	GPIO_FN_STP_ISSYNC_1_B, GPIO_FN_TS_SCK1_C, GPIO_FN_GLO_RFON_C,
-	GPIO_FN_PCMOE_N, GPIO_FN_PWM2, GPIO_FN_PWMFSW0, GPIO_FN_SCIFA2_RXD_C,
-	GPIO_FN_PCMWE_N, GPIO_FN_IECLK_C, GPIO_FN_DU1_DOTCLKIN,
-	GPIO_FN_AUDIO_CLKC, GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_VI0_CLK,
-	GPIO_FN_ATACS00_N, GPIO_FN_AVB_RXD1, GPIO_FN_MII_RXD1,
-	GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_ATACS10_N, GPIO_FN_AVB_RXD2,
-	GPIO_FN_MII_RXD2,
-
-	/* IPSR8 */
-	GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_ATARD0_N, GPIO_FN_AVB_RXD3,
-	GPIO_FN_MII_RXD3, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_ATAWR0_N,
-	GPIO_FN_AVB_RXD4, GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_ATADIR0_N,
-	GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_ATAG0_N,
-	GPIO_FN_AVB_RXD6, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_EX_WAIT1,
-	GPIO_FN_AVB_RXD7, GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RX_ER,
-	GPIO_FN_MII_RX_ER, GPIO_FN_VI0_DATA7_VI0_B7, GPIO_FN_AVB_RX_CLK,
-	GPIO_FN_MII_RX_CLK, GPIO_FN_VI1_CLK, GPIO_FN_AVB_RX_DV,
-	GPIO_FN_MII_RX_DV, GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SCIFA1_SCK_D,
-	GPIO_FN_AVB_CRS, GPIO_FN_MII_CRS, GPIO_FN_VI1_DATA1_VI1_B1,
-	GPIO_FN_SCIFA1_RXD_D, GPIO_FN_AVB_MDC, GPIO_FN_MII_MDC,
-	GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SCIFA1_TXD_D, GPIO_FN_AVB_MDIO,
-	GPIO_FN_MII_MDIO, GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SCIFA1_CTS_N_D,
-	GPIO_FN_AVB_GTX_CLK, GPIO_FN_VI1_DATA4_VI1_B4, GPIO_FN_SCIFA1_RTS_N_D,
-	GPIO_FN_AVB_MAGIC, GPIO_FN_MII_MAGIC, GPIO_FN_VI1_DATA5_VI1_B5,
-	GPIO_FN_AVB_PHY_INT, GPIO_FN_VI1_DATA6_VI1_B6, GPIO_FN_AVB_GTXREFCLK,
-	GPIO_FN_SD0_CLK, GPIO_FN_VI1_DATA0_VI1_B0_B, GPIO_FN_SD0_CMD,
-	GPIO_FN_SCIFB1_SCK_B, GPIO_FN_VI1_DATA1_VI1_B1_B,
-
-	/* IPSR9 */
-	GPIO_FN_SD0_DAT0, GPIO_FN_SCIFB1_RXD_B, GPIO_FN_VI1_DATA2_VI1_B2_B,
-	GPIO_FN_SD0_DAT1, GPIO_FN_SCIFB1_TXD_B, GPIO_FN_VI1_DATA3_VI1_B3_B,
-	GPIO_FN_SD0_DAT2, GPIO_FN_SCIFB1_CTS_N_B, GPIO_FN_VI1_DATA4_VI1_B4_B,
-	GPIO_FN_SD0_DAT3, GPIO_FN_SCIFB1_RTS_N_B, GPIO_FN_VI1_DATA5_VI1_B5_B,
-	GPIO_FN_SD0_CD, GPIO_FN_MMC0_D6, GPIO_FN_TS_SDEN0_B, GPIO_FN_USB0_EXTP,
-	GPIO_FN_GLO_SCLK, GPIO_FN_VI1_DATA6_VI1_B6_B, GPIO_FN_SCL1_B,
-	GPIO_FN_SCL1_CIS_B, GPIO_FN_VI2_DATA6_VI2_B6_B, GPIO_FN_SD0_WP,
-	GPIO_FN_MMC0_D7, GPIO_FN_TS_SPSYNC0_B, GPIO_FN_USB0_IDIN,
-	GPIO_FN_GLO_SDATA, GPIO_FN_VI1_DATA7_VI1_B7_B, GPIO_FN_SDA1_B,
-	GPIO_FN_SDA1_CIS_B, GPIO_FN_VI2_DATA7_VI2_B7_B, GPIO_FN_SD1_CLK,
-	GPIO_FN_AVB_TX_EN, GPIO_FN_MII_TX_EN, GPIO_FN_SD1_CMD,
-	GPIO_FN_AVB_TX_ER, GPIO_FN_MII_TX_ER, GPIO_FN_SCIFB0_SCK_B,
-	GPIO_FN_SD1_DAT0, GPIO_FN_AVB_TX_CLK, GPIO_FN_MII_TX_CLK,
-	GPIO_FN_SCIFB0_RXD_B, GPIO_FN_SD1_DAT1, GPIO_FN_AVB_LINK,
-	GPIO_FN_MII_LINK, GPIO_FN_SCIFB0_TXD_B, GPIO_FN_SD1_DAT2,
-	GPIO_FN_AVB_COL, GPIO_FN_MII_COL, GPIO_FN_SCIFB0_CTS_N_B,
-	GPIO_FN_SD1_DAT3, GPIO_FN_AVB_RXD0, GPIO_FN_MII_RXD0,
-	GPIO_FN_SCIFB0_RTS_N_B, GPIO_FN_SD1_CD, GPIO_FN_MMC1_D6,
-	GPIO_FN_TS_SDEN1, GPIO_FN_USB1_EXTP, GPIO_FN_GLO_SS, GPIO_FN_VI0_CLK_B,
-	GPIO_FN_SCL2_D, GPIO_FN_SCL2_CIS_D, GPIO_FN_SIM0_CLK_B,
-	GPIO_FN_VI3_CLK_B,
-
-	/* IPSR10 */
-	GPIO_FN_SD1_WP, GPIO_FN_MMC1_D7, GPIO_FN_TS_SPSYNC1, GPIO_FN_USB1_IDIN,
-	GPIO_FN_GLO_RFON, GPIO_FN_VI1_CLK_B, GPIO_FN_SDA2_D, GPIO_FN_SDA2_CIS_D,
-	GPIO_FN_SIM0_D_B, GPIO_FN_SD2_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_SIM0_CLK,
-	GPIO_FN_VI0_DATA0_VI0_B0_B, GPIO_FN_TS_SDEN0_C, GPIO_FN_GLO_SCLK_B,
-	GPIO_FN_VI3_DATA0_B, GPIO_FN_SD2_CMD, GPIO_FN_MMC0_CMD, GPIO_FN_SIM0_D,
-	GPIO_FN_VI0_DATA1_VI0_B1_B, GPIO_FN_SCIFB1_SCK_E, GPIO_FN_SCK1_D,
-	GPIO_FN_TS_SPSYNC0_C, GPIO_FN_GLO_SDATA_B, GPIO_FN_VI3_DATA1_B,
-	GPIO_FN_SD2_DAT0, GPIO_FN_MMC0_D0, GPIO_FN_FMCLK_B,
-	GPIO_FN_VI0_DATA2_VI0_B2_B, GPIO_FN_SCIFB1_RXD_E, GPIO_FN_RX1_D,
-	GPIO_FN_TS_SDAT0_C, GPIO_FN_GLO_SS_B, GPIO_FN_VI3_DATA2_B,
-	GPIO_FN_SD2_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FMIN_B, GPIO_FN_RDS_DATA,
-	GPIO_FN_VI0_DATA3_VI0_B3_B, GPIO_FN_SCIFB1_TXD_E, GPIO_FN_TX1_D,
-	GPIO_FN_TS_SCK0_C, GPIO_FN_GLO_RFON_B, GPIO_FN_VI3_DATA3_B,
-	GPIO_FN_SD2_DAT2, GPIO_FN_MMC0_D2, GPIO_FN_BPFCLK_B, GPIO_FN_RDS_CLK,
-	GPIO_FN_VI0_DATA4_VI0_B4_B, GPIO_FN_HRX0_D, GPIO_FN_TS_SDEN1_B,
-	GPIO_FN_GLO_Q0_B, GPIO_FN_VI3_DATA4_B, GPIO_FN_SD2_DAT3,
-	GPIO_FN_MMC0_D3, GPIO_FN_SIM0_RST, GPIO_FN_VI0_DATA5_VI0_B5_B,
-	GPIO_FN_HTX0_D, GPIO_FN_TS_SPSYNC1_B, GPIO_FN_GLO_Q1_B,
-	GPIO_FN_VI3_DATA5_B, GPIO_FN_SD2_CD, GPIO_FN_MMC0_D4,
-	GPIO_FN_TS_SDAT0_B, GPIO_FN_USB2_EXTP, GPIO_FN_GLO_I0,
-	GPIO_FN_VI0_DATA6_VI0_B6_B, GPIO_FN_HCTS0_N_D, GPIO_FN_TS_SDAT1_B,
-	GPIO_FN_GLO_I0_B, GPIO_FN_VI3_DATA6_B,
-
-	/* IPSR11 */
-	GPIO_FN_SD2_WP, GPIO_FN_MMC0_D5, GPIO_FN_TS_SCK0_B, GPIO_FN_USB2_IDIN,
-	GPIO_FN_GLO_I1, GPIO_FN_VI0_DATA7_VI0_B7_B, GPIO_FN_HRTS0_N_D,
-	GPIO_FN_TS_SCK1_B, GPIO_FN_GLO_I1_B, GPIO_FN_VI3_DATA7_B,
-	GPIO_FN_SD3_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_SD3_CMD, GPIO_FN_MMC1_CMD,
-	GPIO_FN_MTS_N, GPIO_FN_SD3_DAT0, GPIO_FN_MMC1_D0, GPIO_FN_STM_N,
-	GPIO_FN_SD3_DAT1, GPIO_FN_MMC1_D1, GPIO_FN_MDATA, GPIO_FN_SD3_DAT2,
-	GPIO_FN_MMC1_D2, GPIO_FN_SDATA, GPIO_FN_SD3_DAT3, GPIO_FN_MMC1_D3,
-	GPIO_FN_SCKZ, GPIO_FN_SD3_CD, GPIO_FN_MMC1_D4, GPIO_FN_TS_SDAT1,
-	GPIO_FN_VSP, GPIO_FN_GLO_Q0, GPIO_FN_SIM0_RST_B, GPIO_FN_SD3_WP,
-	GPIO_FN_MMC1_D5, GPIO_FN_TS_SCK1, GPIO_FN_GLO_Q1, GPIO_FN_FMIN_C,
-	GPIO_FN_RDS_DATA_B, GPIO_FN_FMIN_E, GPIO_FN_RDS_DATA_D, GPIO_FN_FMIN_F,
-	GPIO_FN_RDS_DATA_E, GPIO_FN_MLB_CLK, GPIO_FN_SCL2_B, GPIO_FN_SCL2_CIS_B,
-	GPIO_FN_MLB_SIG, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_RX1_C, GPIO_FN_SDA2_B,
-	GPIO_FN_SDA2_CIS_B, GPIO_FN_MLB_DAT, GPIO_FN_SPV_EVEN,
-	GPIO_FN_SCIFB1_TXD_D, GPIO_FN_TX1_C, GPIO_FN_BPFCLK_C,
-	GPIO_FN_RDS_CLK_B, GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_CLK_B,
-	GPIO_FN_MOUT0,
-
-	/* IPSR12 */
-	GPIO_FN_SSI_WS0129, GPIO_FN_CAN0_TX_B, GPIO_FN_MOUT1,
-	GPIO_FN_SSI_SDATA0, GPIO_FN_CAN0_RX_B, GPIO_FN_MOUT2,
-	GPIO_FN_SSI_SDATA1, GPIO_FN_CAN1_TX_B, GPIO_FN_MOUT5,
-	GPIO_FN_SSI_SDATA2, GPIO_FN_CAN1_RX_B, GPIO_FN_SSI_SCK1, GPIO_FN_MOUT6,
-	GPIO_FN_SSI_SCK34, GPIO_FN_STP_OPWM_0, GPIO_FN_SCIFB0_SCK,
-	GPIO_FN_MSIOF1_SCK, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_SSI_WS34,
-	GPIO_FN_STP_IVCXO27_0, GPIO_FN_SCIFB0_RXD, GPIO_FN_MSIOF1_SYNC,
-	GPIO_FN_CAN_STEP0, GPIO_FN_SSI_SDATA3, GPIO_FN_STP_ISCLK_0,
-	GPIO_FN_SCIFB0_TXD, GPIO_FN_MSIOF1_SS1, GPIO_FN_CAN_TXCLK,
-	GPIO_FN_SSI_SCK4, GPIO_FN_STP_ISD_0, GPIO_FN_SCIFB0_CTS_N,
-	GPIO_FN_MSIOF1_SS2, GPIO_FN_SSI_SCK5_C, GPIO_FN_CAN_DEBUGOUT0,
-	GPIO_FN_SSI_WS4, GPIO_FN_STP_ISEN_0, GPIO_FN_SCIFB0_RTS_N,
-	GPIO_FN_MSIOF1_TXD, GPIO_FN_SSI_WS5_C, GPIO_FN_CAN_DEBUGOUT1,
-	GPIO_FN_SSI_SDATA4, GPIO_FN_STP_ISSYNC_0, GPIO_FN_MSIOF1_RXD,
-	GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_SSI_SCK5, GPIO_FN_SCIFB1_SCK,
-	GPIO_FN_IERX_B, GPIO_FN_DU2_EXHSYNC_DU2_HSYNC, GPIO_FN_QSTH_QHS,
-	GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_SSI_WS5, GPIO_FN_SCIFB1_RXD,
-	GPIO_FN_IECLK_B, GPIO_FN_DU2_EXVSYNC_DU2_VSYNC, GPIO_FN_QSTB_QHE,
-	GPIO_FN_CAN_DEBUGOUT4,
-
-	/* IPSR13 */
-	GPIO_FN_SSI_SDATA5, GPIO_FN_SCIFB1_TXD, GPIO_FN_IETX_B, GPIO_FN_DU2_DR2,
-	GPIO_FN_LCDOUT2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK6,
-	GPIO_FN_SCIFB1_CTS_N, GPIO_FN_BPFCLK_D, GPIO_FN_RDS_CLK_C,
-	GPIO_FN_DU2_DR3, GPIO_FN_LCDOUT3, GPIO_FN_CAN_DEBUGOUT6,
-	GPIO_FN_BPFCLK_F, GPIO_FN_RDS_CLK_E, GPIO_FN_SSI_WS6,
-	GPIO_FN_SCIFB1_RTS_N, GPIO_FN_CAN0_TX_D, GPIO_FN_DU2_DR4,
-	GPIO_FN_LCDOUT4, GPIO_FN_CAN_DEBUGOUT7, GPIO_FN_SSI_SDATA6,
-	GPIO_FN_FMIN_D, GPIO_FN_RDS_DATA_C, GPIO_FN_DU2_DR5, GPIO_FN_LCDOUT5,
-	GPIO_FN_CAN_DEBUGOUT8, GPIO_FN_SSI_SCK78, GPIO_FN_STP_IVCXO27_1,
-	GPIO_FN_SCK1, GPIO_FN_SCIFA1_SCK, GPIO_FN_DU2_DR6, GPIO_FN_LCDOUT6,
-	GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_WS78, GPIO_FN_STP_ISCLK_1,
-	GPIO_FN_SCIFB2_SCK, GPIO_FN_SCIFA2_CTS_N, GPIO_FN_DU2_DR7,
-	GPIO_FN_LCDOUT7, GPIO_FN_CAN_DEBUGOUT10, GPIO_FN_SSI_SDATA7,
-	GPIO_FN_STP_ISD_1, GPIO_FN_SCIFB2_RXD, GPIO_FN_SCIFA2_RTS_N,
-	GPIO_FN_TCLK2, GPIO_FN_QSTVA_QVS, GPIO_FN_CAN_DEBUGOUT11,
-	GPIO_FN_BPFCLK_E, GPIO_FN_RDS_CLK_D, GPIO_FN_SSI_SDATA7_B,
-	GPIO_FN_FMIN_G, GPIO_FN_RDS_DATA_F, GPIO_FN_SSI_SDATA8,
-	GPIO_FN_STP_ISEN_1, GPIO_FN_SCIFB2_TXD, GPIO_FN_CAN0_TX_C,
-	GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SDATA8_B, GPIO_FN_SSI_SDATA9,
-	GPIO_FN_STP_ISSYNC_1, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_SSI_WS1,
-	GPIO_FN_SSI_SDATA5_C, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_AUDIO_CLKA,
-	GPIO_FN_SCIFB2_RTS_N, GPIO_FN_CAN_DEBUGOUT14,
-
-	/* IPSR14 */
-	GPIO_FN_AUDIO_CLKB, GPIO_FN_SCIF_CLK, GPIO_FN_CAN0_RX_D,
-	GPIO_FN_DVC_MUTE, GPIO_FN_CAN0_RX_C, GPIO_FN_CAN_DEBUGOUT15,
-	GPIO_FN_REMOCON, GPIO_FN_SCIFA0_SCK, GPIO_FN_HSCK1, GPIO_FN_SCK0,
-	GPIO_FN_MSIOF3_SS2, GPIO_FN_DU2_DG2, GPIO_FN_LCDOUT10, GPIO_FN_SDA1_C,
-	GPIO_FN_SDA1_CIS_C, GPIO_FN_SCIFA0_RXD, GPIO_FN_HRX1, GPIO_FN_RX0,
-	GPIO_FN_DU2_DR0, GPIO_FN_LCDOUT0, GPIO_FN_SCIFA0_TXD, GPIO_FN_HTX1,
-	GPIO_FN_TX0, GPIO_FN_DU2_DR1, GPIO_FN_LCDOUT1, GPIO_FN_SCIFA0_CTS_N,
-	GPIO_FN_HCTS1_N, GPIO_FN_CTS0_N, GPIO_FN_MSIOF3_SYNC, GPIO_FN_DU2_DG3,
-	GPIO_FN_LCDOUT11, GPIO_FN_PWM0_B, GPIO_FN_SCL1_C, GPIO_FN_SCL1_CIS_C,
-	GPIO_FN_SCIFA0_RTS_N, GPIO_FN_HRTS1_N, GPIO_FN_RTS0_N_TANS,
-	GPIO_FN_MSIOF3_SS1, GPIO_FN_DU2_DG0, GPIO_FN_LCDOUT8, GPIO_FN_PWM1_B,
-	GPIO_FN_SCIFA1_RXD, GPIO_FN_AD_DI, GPIO_FN_RX1,
-	GPIO_FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
-	GPIO_FN_SCIFA1_TXD, GPIO_FN_AD_DO, GPIO_FN_TX1, GPIO_FN_DU2_DG1,
-	GPIO_FN_LCDOUT9, GPIO_FN_SCIFA1_CTS_N, GPIO_FN_AD_CLK,
-	GPIO_FN_CTS1_N, GPIO_FN_MSIOF3_RXD, GPIO_FN_DU0_DOTCLKOUT, GPIO_FN_QCLK,
-	GPIO_FN_SCIFA1_RTS_N, GPIO_FN_AD_NCS_N, GPIO_FN_RTS1_N_TANS,
-	GPIO_FN_MSIOF3_TXD, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_QSTVB_QVE,
-	GPIO_FN_HRTS0_N_C,
-
-	/* IPSR15 */
-	GPIO_FN_SCIFA2_SCK, GPIO_FN_FMCLK, GPIO_FN_MSIOF3_SCK, GPIO_FN_DU2_DG7,
-	GPIO_FN_LCDOUT15, GPIO_FN_SCIF_CLK_B, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN,
-	GPIO_FN_DU2_DB0, GPIO_FN_LCDOUT16, GPIO_FN_SCL2, GPIO_FN_SCL2_CIS,
-	GPIO_FN_SCIFA2_TXD, GPIO_FN_BPFCLK, GPIO_FN_DU2_DB1, GPIO_FN_LCDOUT17,
-	GPIO_FN_SDA2, GPIO_FN_SDA2_CIS, GPIO_FN_HSCK0, GPIO_FN_TS_SDEN0,
-	GPIO_FN_DU2_DG4, GPIO_FN_LCDOUT12, GPIO_FN_HCTS0_N_C, GPIO_FN_HRX0,
-	GPIO_FN_DU2_DB2, GPIO_FN_LCDOUT18, GPIO_FN_HTX0, GPIO_FN_DU2_DB3,
-	GPIO_FN_LCDOUT19, GPIO_FN_HCTS0_N, GPIO_FN_SSI_SCK9, GPIO_FN_DU2_DB4,
-	GPIO_FN_LCDOUT20, GPIO_FN_HRTS0_N, GPIO_FN_SSI_WS9, GPIO_FN_DU2_DB5,
-	GPIO_FN_LCDOUT21, GPIO_FN_MSIOF0_SCK, GPIO_FN_TS_SDAT0, GPIO_FN_ADICLK,
-	GPIO_FN_DU2_DB6, GPIO_FN_LCDOUT22, GPIO_FN_MSIOF0_SYNC, GPIO_FN_TS_SCK0,
-	GPIO_FN_SSI_SCK2, GPIO_FN_ADIDATA, GPIO_FN_DU2_DB7, GPIO_FN_LCDOUT23,
-	GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF0_SS1, GPIO_FN_ADICHS0,
-	GPIO_FN_DU2_DG5, GPIO_FN_LCDOUT13, GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICHS1,
-	GPIO_FN_DU2_DG6, GPIO_FN_LCDOUT14,
-
-	/* IPSR16 */
-	GPIO_FN_MSIOF0_SS2, GPIO_FN_AUDIO_CLKOUT, GPIO_FN_ADICHS2,
-	GPIO_FN_DU2_DISP, GPIO_FN_QPOLA, GPIO_FN_HTX0_C, GPIO_FN_SCIFA2_TXD_B,
-	GPIO_FN_MSIOF0_RXD, GPIO_FN_TS_SPSYNC0, GPIO_FN_SSI_WS2,
-	GPIO_FN_ADICS_SAMP, GPIO_FN_DU2_CDE, GPIO_FN_QPOLB, GPIO_FN_HRX0_C,
-	GPIO_FN_USB1_PWEN, GPIO_FN_AUDIO_CLKOUT_D, GPIO_FN_USB1_OVC,
-	GPIO_FN_TCLK1_B,
-};
-
 void r8a7790_add_standard_devices(void);
 void r8a7790_clock_init(void);
 void r8a7790_pinmux_init(void);
-- 
1.8.2.1

[PATCH 103/130] ARM: shmobile: r8a7779 pinmux platform device cleanup

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

Use DEFINE_RES_MEM() to save a couple of lines of code.

Signed-off-by: Magnus Damm <damm@opensource.se>
[lp: Don't declare r8a7779_pfc_resources as const]
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/setup-r8a7779.c | 17 +++--------------
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index b0b3948..dbb13f2 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -65,11 +65,7 @@ void __init r8a7779_map_io(void)
 }
 
 static struct resource r8a7779_pfc_resources[] = {
-	[0] = {
-		.start	= 0xfffc0000,
-		.end	= 0xfffc023b,
-		.flags	= IORESOURCE_MEM,
-	},
+	DEFINE_RES_MEM(0xfffc0000, 0x023c),
 };
 
 static struct platform_device r8a7779_pfc_device = {
@@ -81,15 +77,8 @@ static struct platform_device r8a7779_pfc_device = {
 
 #define R8A7779_GPIO(idx, npins) \
 static struct resource r8a7779_gpio##idx##_resources[] = {		\
-	[0] = {								\
-		.start	= 0xffc40000 + 0x1000 * (idx),			\
-		.end	= 0xffc4002b + 0x1000 * (idx),			\
-		.flags	= IORESOURCE_MEM,				\
-	},								\
-	[1] = {								\
-		.start	= gic_iid(0xad + (idx)),			\
-		.flags	= IORESOURCE_IRQ,				\
-	}								\
+	DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c),		\
+	DEFINE_RES_IRQ(gic_iid(0xad + (idx))),				\
 };									\
 									\
 static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = {	\
-- 
1.8.2.1

[PATCH 104/130] sh-pfc: Add support for SoC-specific initialization

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Add two optional init and exit SoC operations and call them from the
core at probe and remove time.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/core.c   | 16 +++++++++++++++-
 drivers/pinctrl/sh-pfc/core.h   |  1 +
 drivers/pinctrl/sh-pfc/sh_pfc.h |  2 ++
 3 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 4540ce3..3b2fd43 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -372,6 +372,12 @@ static int sh_pfc_probe(struct platform_device *pdev)
 
 	spin_lock_init(&pfc->lock);
 
+	if (info->ops && info->ops->init) {
+		ret = info->ops->init(pfc);
+		if (ret < 0)
+			return ret;
+	}
+
 	pinctrl_provide_dummies();
 
 	/*
@@ -379,7 +385,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
 	 */
 	ret = sh_pfc_register_pinctrl(pfc);
 	if (unlikely(ret != 0))
-		return ret;
+		goto error;
 
 #ifdef CONFIG_GPIO_SH_PFC
 	/*
@@ -401,6 +407,11 @@ static int sh_pfc_probe(struct platform_device *pdev)
 	dev_info(pfc->dev, "%s support registered\n", info->name);
 
 	return 0;
+
+error:
+	if (info->ops && info->ops->exit)
+		info->ops->exit(pfc);
+	return ret;
 }
 
 static int sh_pfc_remove(struct platform_device *pdev)
@@ -412,6 +423,9 @@ static int sh_pfc_remove(struct platform_device *pdev)
 #endif
 	sh_pfc_unregister_pinctrl(pfc);
 
+	if (pfc->info->ops && pfc->info->ops->exit)
+		pfc->info->ops->exit(pfc);
+
 	platform_set_drvdata(pdev, NULL);
 
 	return 0;
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index e847afb..f02ba1d 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -28,6 +28,7 @@ struct sh_pfc_pinctrl;
 struct sh_pfc {
 	struct device *dev;
 	const struct sh_pfc_soc_info *info;
+	void *soc_data;
 	spinlock_t lock;
 
 	unsigned int num_windows;
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index b170761..830ae1f 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -129,6 +129,8 @@ struct pinmux_range {
 struct sh_pfc;
 
 struct sh_pfc_soc_operations {
+	int (*init)(struct sh_pfc *pfc);
+	void (*exit)(struct sh_pfc *pfc);
 	unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
 	void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
 			 unsigned int bias);
-- 
1.8.2.1

[PATCH 105/130] sh-pfc: sh73a0: Add VCCQ MC0 regulator

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The sh73a0 has an internal power gate on the VCCQ power supply for the
SDHI0 device that is controlled (for some strange reason) by a bit in a
PFC register. This feature should be exposed as a regulator.

As the same register is also used for pin control purposes there is no
way to achieve atomic read/write sequences with a separate regulator
driver. We thus need to implement the regulator here.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/Kconfig      |   1 +
 drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 134 ++++++++++++++++++++++++++++++++++++
 2 files changed, 135 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 32161c4..636a882 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -72,6 +72,7 @@ config PINCTRL_PFC_SH73A0
 	def_bool y
 	depends on ARCH_SH73A0
 	select PINCTRL_SH_PFC
+	select REGULATOR
 
 config PINCTRL_PFC_SH7720
 	def_bool y
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 587f777..b783724 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -20,7 +20,11 @@
  */
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/pinctrl/pinconf-generic.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/slab.h>
 
 #include <mach/sh73a0.h>
 #include <mach/irqs.h>
@@ -3888,6 +3892,92 @@ static const struct pinmux_irq pinmux_irqs[] = {
 	PINMUX_IRQ(EXT_IRQ16L(9), 308),
 };
 
+/* -----------------------------------------------------------------------------
+ * VCCQ MC0 regulator
+ */
+
+static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
+{
+	struct sh_pfc *pfc = reg->reg_data;
+	void __iomem *addr = pfc->window[1].virt + 4;
+	unsigned long flags;
+	u32 value;
+
+	spin_lock_irqsave(&pfc->lock, flags);
+
+	value = ioread32(addr);
+
+	if (enable)
+		value |= BIT(28);
+	else
+		value &= ~BIT(28);
+
+	iowrite32(value, addr);
+
+	spin_unlock_irqrestore(&pfc->lock, flags);
+}
+
+static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg)
+{
+	sh73a0_vccq_mc0_endisable(reg, true);
+	return 0;
+}
+
+static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
+{
+	sh73a0_vccq_mc0_endisable(reg, false);
+	return 0;
+}
+
+static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
+{
+	struct sh_pfc *pfc = reg->reg_data;
+	void __iomem *addr = pfc->window[1].virt + 4;
+	unsigned long flags;
+	u32 value;
+
+	spin_lock_irqsave(&pfc->lock, flags);
+	value = ioread32(addr);
+	spin_unlock_irqrestore(&pfc->lock, flags);
+
+	return !!(value & BIT(28));
+}
+
+static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg)
+{
+	return 3300000;
+}
+
+static struct regulator_ops sh73a0_vccq_mc0_ops = {
+	.enable = sh73a0_vccq_mc0_enable,
+	.disable = sh73a0_vccq_mc0_disable,
+	.is_enabled = sh73a0_vccq_mc0_is_enabled,
+	.get_voltage = sh73a0_vccq_mc0_get_voltage,
+};
+
+static const struct regulator_desc sh73a0_vccq_mc0_desc = {
+	.owner = THIS_MODULE,
+	.name = "vccq_mc0",
+	.type = REGULATOR_VOLTAGE,
+	.ops = &sh73a0_vccq_mc0_ops,
+};
+
+static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = {
+	REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
+
+static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {
+	.constraints = {
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers),
+	.consumer_supplies = sh73a0_vccq_mc0_consumers,
+};
+
+/* -----------------------------------------------------------------------------
+ * Pin bias
+ */
+
 #define PORTnCR_PULMD_OFF	(0 << 6)
 #define PORTnCR_PULMD_DOWN	(2 << 6)
 #define PORTnCR_PULMD_UP	(3 << 6)
@@ -3934,7 +4024,51 @@ static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
 	iowrite8(value, addr);
 }
 
+/* -----------------------------------------------------------------------------
+ * SoC information
+ */
+
+struct sh73a0_pinmux_data {
+	struct regulator_dev *vccq_mc0;
+};
+
+static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
+{
+	struct sh73a0_pinmux_data *data;
+	struct regulator_config cfg = { };
+	int ret;
+
+	data = devm_kzalloc(pfc->dev, sizeof(*data), GFP_KERNEL);
+	if (data = NULL)
+		return -ENOMEM;
+
+	cfg.dev = pfc->dev;
+	cfg.init_data = &sh73a0_vccq_mc0_init_data;
+	cfg.driver_data = pfc;
+
+	data->vccq_mc0 = regulator_register(&sh73a0_vccq_mc0_desc, &cfg);
+	if (IS_ERR(data->vccq_mc0)) {
+		ret = PTR_ERR(data->vccq_mc0);
+		dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
+			ret);
+		return ret;
+	}
+
+	pfc->soc_data = data;
+
+	return 0;
+}
+
+static void sh73a0_pinmux_soc_exit(struct sh_pfc *pfc)
+{
+	struct sh73a0_pinmux_data *data = pfc->soc_data;
+
+	regulator_unregister(data->vccq_mc0);
+}
+
 static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
+	.init = sh73a0_pinmux_soc_init,
+	.exit = sh73a0_pinmux_soc_exit,
 	.get_bias = sh73a0_pinmux_get_bias,
 	.set_bias = sh73a0_pinmux_set_bias,
 };
-- 
1.8.2.1

[PATCH 106/130] ARM: shmobile: kzm9g: Remove the VCCQ MC0 function GPIO

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The VCCQ MC0 power gate is now controlled by a regulator registered by
the PFC driver. Remove the corresponding function GPIO.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-kzm9g.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index e6b775a..fc4ca9b 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -788,9 +788,6 @@ static void __init kzm_init(void)
 	/* Touchscreen */
 	gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
 
-	/* enable SD */
-	gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON,	NULL);
-
 #ifdef CONFIG_CACHE_L2X0
 	/* Early BRESP enable, Shared attribute override enable, 64K*8way */
 	l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
-- 
1.8.2.1

[PATCH 107/130] ARM: shmobile: kzm9g-reference: Remove the VCCQ MC0 function GPIO

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The VCCQ MC0 power gate is now controlled by a regulator registered by
the PFC driver. Remove the corresponding function GPIO.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-kzm9g-reference.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index aefa50d..44055fe 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -79,7 +79,6 @@ static void __init kzm_init(void)
 	sh73a0_pinmux_init();
 
 	/* enable SD */
-	gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON,	NULL);
 	gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
 
 	gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
-- 
1.8.2.1

[PATCH 108/130] sh-pfc: r8a7778: add USB pin groups

[Simon Horman]

From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Add USB0/1 PENC/USB_OVC pin groups to R8A7778 PFC driver.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index 15295a5..1f692e5 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -1501,6 +1501,18 @@ SDHI_PFC_WPPN(sdhi2_wp_a,	SD2_WP_A);
 SDHI_PFC_PINS(sdhi2_wp_b,	RCAR_GP_PIN(3, 28));
 SDHI_PFC_WPPN(sdhi2_wp_b,	SD2_WP_B);
 
+/* - USB0 ------------------------------------------------------------------- */
+SH_PFC_PINS(usb0,		RCAR_GP_PIN(0, 1));
+SH_PFC_MUX1(usb0,		PENC0);
+SH_PFC_PINS(usb0_ovc,		RCAR_GP_PIN(0, 3));
+SH_PFC_MUX1(usb0_ovc,		USB_OVC0);
+
+/* - USB1 ------------------------------------------------------------------- */
+SH_PFC_PINS(usb1,		RCAR_GP_PIN(0, 2));
+SH_PFC_MUX1(usb1,		PENC1);
+SH_PFC_PINS(usb1_ovc,		RCAR_GP_PIN(0, 4));
+SH_PFC_MUX1(usb1_ovc,		USB_OVC1);
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(hscif0_data_a),
 	SH_PFC_PIN_GROUP(hscif0_data_b),
@@ -1570,6 +1582,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(sdhi2_data4_b),
 	SH_PFC_PIN_GROUP(sdhi2_wp_a),
 	SH_PFC_PIN_GROUP(sdhi2_wp_b),
+	SH_PFC_PIN_GROUP(usb0),
+	SH_PFC_PIN_GROUP(usb0_ovc),
+	SH_PFC_PIN_GROUP(usb1),
+	SH_PFC_PIN_GROUP(usb1_ovc),
 };
 
 static const char * const hscif0_groups[] = {
@@ -1677,6 +1693,16 @@ static const char * const sdhi2_groups[] = {
 	"sdhi2_wp_b",
 };
 
+static const char * const usb0_groups[] = {
+	"usb0",
+	"usb0_ovc",
+};
+
+static const char * const usb1_groups[] = {
+	"usb1",
+	"usb1_ovc",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(hscif0),
 	SH_PFC_FUNCTION(hscif1),
@@ -1690,6 +1716,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(sdhi0),
 	SH_PFC_FUNCTION(sdhi1),
 	SH_PFC_FUNCTION(sdhi2),
+	SH_PFC_FUNCTION(usb0),
+	SH_PFC_FUNCTION(usb1),
 };
 
 static struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
1.8.2.1

[PATCH 109/130] sh-pfc: sh73a0: Add TPU pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 213 ++++++++++++++++++++++++++++++++++++
 1 file changed, 213 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index b783724..78f7ae8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -2542,6 +2542,157 @@ static const unsigned int sdhi2_ctrl_pins[] = {
 static const unsigned int sdhi2_ctrl_mux[] = {
 	SDHICMD2_MARK, SDHICLK2_MARK,
 };
+/* - TPU0 ------------------------------------------------------------------- */
+static const unsigned int tpu0_to0_pins[] = {
+	/* TO */
+	55,
+};
+static const unsigned int tpu0_to0_mux[] = {
+	TPU0TO0_MARK,
+};
+static const unsigned int tpu0_to1_pins[] = {
+	/* TO */
+	59,
+};
+static const unsigned int tpu0_to1_mux[] = {
+	TPU0TO1_MARK,
+};
+static const unsigned int tpu0_to2_pins[] = {
+	/* TO */
+	140,
+};
+static const unsigned int tpu0_to2_mux[] = {
+	TPU0TO2_MARK,
+};
+static const unsigned int tpu0_to3_pins[] = {
+	/* TO */
+	141,
+};
+static const unsigned int tpu0_to3_mux[] = {
+	TPU0TO3_MARK,
+};
+/* - TPU1 ------------------------------------------------------------------- */
+static const unsigned int tpu1_to0_pins[] = {
+	/* TO */
+	246,
+};
+static const unsigned int tpu1_to0_mux[] = {
+	TPU1TO0_MARK,
+};
+static const unsigned int tpu1_to1_0_pins[] = {
+	/* TO */
+	28,
+};
+static const unsigned int tpu1_to1_0_mux[] = {
+	PORT28_TPU1TO1_MARK,
+};
+static const unsigned int tpu1_to1_1_pins[] = {
+	/* TO */
+	29,
+};
+static const unsigned int tpu1_to1_1_mux[] = {
+	PORT29_TPU1TO1_MARK,
+};
+static const unsigned int tpu1_to2_pins[] = {
+	/* TO */
+	153,
+};
+static const unsigned int tpu1_to2_mux[] = {
+	TPU1TO2_MARK,
+};
+static const unsigned int tpu1_to3_pins[] = {
+	/* TO */
+	145,
+};
+static const unsigned int tpu1_to3_mux[] = {
+	TPU1TO3_MARK,
+};
+/* - TPU2 ------------------------------------------------------------------- */
+static const unsigned int tpu2_to0_pins[] = {
+	/* TO */
+	248,
+};
+static const unsigned int tpu2_to0_mux[] = {
+	TPU2TO0_MARK,
+};
+static const unsigned int tpu2_to1_pins[] = {
+	/* TO */
+	197,
+};
+static const unsigned int tpu2_to1_mux[] = {
+	TPU2TO1_MARK,
+};
+static const unsigned int tpu2_to2_pins[] = {
+	/* TO */
+	50,
+};
+static const unsigned int tpu2_to2_mux[] = {
+	TPU2TO2_MARK,
+};
+static const unsigned int tpu2_to3_pins[] = {
+	/* TO */
+	51,
+};
+static const unsigned int tpu2_to3_mux[] = {
+	TPU2TO3_MARK,
+};
+/* - TPU3 ------------------------------------------------------------------- */
+static const unsigned int tpu3_to0_pins[] = {
+	/* TO */
+	163,
+};
+static const unsigned int tpu3_to0_mux[] = {
+	TPU3TO0_MARK,
+};
+static const unsigned int tpu3_to1_pins[] = {
+	/* TO */
+	247,
+};
+static const unsigned int tpu3_to1_mux[] = {
+	TPU3TO1_MARK,
+};
+static const unsigned int tpu3_to2_pins[] = {
+	/* TO */
+	54,
+};
+static const unsigned int tpu3_to2_mux[] = {
+	TPU3TO2_MARK,
+};
+static const unsigned int tpu3_to3_pins[] = {
+	/* TO */
+	53,
+};
+static const unsigned int tpu3_to3_mux[] = {
+	TPU3TO3_MARK,
+};
+/* - TPU4 ------------------------------------------------------------------- */
+static const unsigned int tpu4_to0_pins[] = {
+	/* TO */
+	241,
+};
+static const unsigned int tpu4_to0_mux[] = {
+	TPU4TO0_MARK,
+};
+static const unsigned int tpu4_to1_pins[] = {
+	/* TO */
+	199,
+};
+static const unsigned int tpu4_to1_mux[] = {
+	TPU4TO1_MARK,
+};
+static const unsigned int tpu4_to2_pins[] = {
+	/* TO */
+	58,
+};
+static const unsigned int tpu4_to2_mux[] = {
+	TPU4TO2_MARK,
+};
+static const unsigned int tpu4_to3_pins[] = {
+	/* TO */
+};
+static const unsigned int tpu4_to3_mux[] = {
+	TPU4TO3_MARK,
+};
 /* - USB -------------------------------------------------------------------- */
 static const unsigned int usb_vbus_pins[] = {
 	/* VBUS */
@@ -2693,6 +2844,27 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(sdhi2_data1),
 	SH_PFC_PIN_GROUP(sdhi2_data4),
 	SH_PFC_PIN_GROUP(sdhi2_ctrl),
+	SH_PFC_PIN_GROUP(tpu0_to0),
+	SH_PFC_PIN_GROUP(tpu0_to1),
+	SH_PFC_PIN_GROUP(tpu0_to2),
+	SH_PFC_PIN_GROUP(tpu0_to3),
+	SH_PFC_PIN_GROUP(tpu1_to0),
+	SH_PFC_PIN_GROUP(tpu1_to1_0),
+	SH_PFC_PIN_GROUP(tpu1_to1_1),
+	SH_PFC_PIN_GROUP(tpu1_to2),
+	SH_PFC_PIN_GROUP(tpu1_to3),
+	SH_PFC_PIN_GROUP(tpu2_to0),
+	SH_PFC_PIN_GROUP(tpu2_to1),
+	SH_PFC_PIN_GROUP(tpu2_to2),
+	SH_PFC_PIN_GROUP(tpu2_to3),
+	SH_PFC_PIN_GROUP(tpu3_to0),
+	SH_PFC_PIN_GROUP(tpu3_to1),
+	SH_PFC_PIN_GROUP(tpu3_to2),
+	SH_PFC_PIN_GROUP(tpu3_to3),
+	SH_PFC_PIN_GROUP(tpu4_to0),
+	SH_PFC_PIN_GROUP(tpu4_to1),
+	SH_PFC_PIN_GROUP(tpu4_to2),
+	SH_PFC_PIN_GROUP(tpu4_to3),
 	SH_PFC_PIN_GROUP(usb_vbus),
 };
 
@@ -2912,6 +3084,42 @@ static const char * const usb_groups[] = {
 	"usb_vbus",
 };
 
+static const char * const tpu0_groups[] = {
+	"tpu0_to0",
+	"tpu0_to1",
+	"tpu0_to2",
+	"tpu0_to3",
+};
+
+static const char * const tpu1_groups[] = {
+	"tpu1_to0",
+	"tpu1_to1_0",
+	"tpu1_to1_1",
+	"tpu1_to2",
+	"tpu1_to3",
+};
+
+static const char * const tpu2_groups[] = {
+	"tpu2_to0",
+	"tpu2_to1",
+	"tpu2_to2",
+	"tpu2_to3",
+};
+
+static const char * const tpu3_groups[] = {
+	"tpu3_to0",
+	"tpu3_to1",
+	"tpu3_to2",
+	"tpu3_to3",
+};
+
+static const char * const tpu4_groups[] = {
+	"tpu4_to0",
+	"tpu4_to1",
+	"tpu4_to2",
+	"tpu4_to3",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(bsc),
 	SH_PFC_FUNCTION(fsia),
@@ -2937,6 +3145,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(sdhi0),
 	SH_PFC_FUNCTION(sdhi1),
 	SH_PFC_FUNCTION(sdhi2),
+	SH_PFC_FUNCTION(tpu0),
+	SH_PFC_FUNCTION(tpu1),
+	SH_PFC_FUNCTION(tpu2),
+	SH_PFC_FUNCTION(tpu3),
+	SH_PFC_FUNCTION(tpu4),
 	SH_PFC_FUNCTION(usb),
 };
 
-- 
1.8.2.1

[PATCH 110/130] sh-pfc: r8a7740: Add TPU pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7740.c | 50 ++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index e5ef587..f6ea47c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -2745,6 +2745,42 @@ static const unsigned int sdhi2_wp_1_pins[] = {
 static const unsigned int sdhi2_wp_1_mux[] = {
 	SDHI2_WP_PORT25_MARK,
 };
+/* - TPU0 ------------------------------------------------------------------- */
+static const unsigned int tpu0_to0_pins[] = {
+	/* TO */
+	23,
+};
+static const unsigned int tpu0_to0_mux[] = {
+	TPU0TO0_MARK,
+};
+static const unsigned int tpu0_to1_pins[] = {
+	/* TO */
+	21,
+};
+static const unsigned int tpu0_to1_mux[] = {
+	TPU0TO1_MARK,
+};
+static const unsigned int tpu0_to2_0_pins[] = {
+	/* TO */
+	66,
+};
+static const unsigned int tpu0_to2_0_mux[] = {
+	TPU0TO2_PORT66_MARK,
+};
+static const unsigned int tpu0_to2_1_pins[] = {
+	/* TO */
+	202,
+};
+static const unsigned int tpu0_to2_1_mux[] = {
+	TPU0TO2_PORT202_MARK,
+};
+static const unsigned int tpu0_to3_pins[] = {
+	/* TO */
+	180,
+};
+static const unsigned int tpu0_to3_mux[] = {
+	TPU0TO3_MARK,
+};
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(bsc_data8),
@@ -2926,6 +2962,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(sdhi2_wp_0),
 	SH_PFC_PIN_GROUP(sdhi2_cd_1),
 	SH_PFC_PIN_GROUP(sdhi2_wp_1),
+	SH_PFC_PIN_GROUP(tpu0_to0),
+	SH_PFC_PIN_GROUP(tpu0_to1),
+	SH_PFC_PIN_GROUP(tpu0_to2_0),
+	SH_PFC_PIN_GROUP(tpu0_to2_1),
+	SH_PFC_PIN_GROUP(tpu0_to3),
 };
 
 static const char * const bsc_groups[] = {
@@ -3176,6 +3217,14 @@ static const char * const sdhi2_groups[] = {
 	"sdhi2_wp_1",
 };
 
+static const char * const tpu0_groups[] = {
+	"tpu0_to0",
+	"tpu0_to1",
+	"tpu0_to2_0",
+	"tpu0_to2_1",
+	"tpu0_to3",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(bsc),
 	SH_PFC_FUNCTION(ceu0),
@@ -3200,6 +3249,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(sdhi0),
 	SH_PFC_FUNCTION(sdhi1),
 	SH_PFC_FUNCTION(sdhi2),
+	SH_PFC_FUNCTION(tpu0),
 };
 
 #undef PORTCR
-- 
1.8.2.1

[PATCH 111/130] sh-pfc: r8a7790: Add TPU pin groups and functions

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 41 ++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 1656915..5be2999 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -2342,6 +2342,35 @@ static const unsigned int scifb2_data_c_pins[] = {
 static const unsigned int scifb2_data_c_mux[] = {
 	SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
 };
+/* - TPU0 ------------------------------------------------------------------- */
+static const unsigned int tpu0_to0_pins[] = {
+	/* TO */
+	RCAR_GP_PIN(0, 20),
+};
+static const unsigned int tpu0_to0_mux[] = {
+	TPU0TO0_MARK,
+};
+static const unsigned int tpu0_to1_pins[] = {
+	/* TO */
+	RCAR_GP_PIN(0, 21),
+};
+static const unsigned int tpu0_to1_mux[] = {
+	TPU0TO1_MARK,
+};
+static const unsigned int tpu0_to2_pins[] = {
+	/* TO */
+	RCAR_GP_PIN(0, 22),
+};
+static const unsigned int tpu0_to2_mux[] = {
+	TPU0TO2_MARK,
+};
+static const unsigned int tpu0_to3_pins[] = {
+	/* TO */
+	RCAR_GP_PIN(0, 23),
+};
+static const unsigned int tpu0_to3_mux[] = {
+	TPU0TO3_MARK,
+};
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(eth_link),
@@ -2416,6 +2445,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(scifb2_clk_b),
 	SH_PFC_PIN_GROUP(scifb2_ctrl_b),
 	SH_PFC_PIN_GROUP(scifb2_data_c),
+	SH_PFC_PIN_GROUP(tpu0_to0),
+	SH_PFC_PIN_GROUP(tpu0_to1),
+	SH_PFC_PIN_GROUP(tpu0_to2),
+	SH_PFC_PIN_GROUP(tpu0_to3),
 };
 
 static const char * const eth_groups[] = {
@@ -2520,6 +2553,13 @@ static const char * const scifb2_groups[] = {
 	"scifb2_data_c",
 };
 
+static const char * const tpu0_groups[] = {
+	"tpu0_to0",
+	"tpu0_to1",
+	"tpu0_to2",
+	"tpu0_to3",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(eth),
 	SH_PFC_FUNCTION(intc),
@@ -2531,6 +2571,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(scifb0),
 	SH_PFC_FUNCTION(scifb1),
 	SH_PFC_FUNCTION(scifb2),
+	SH_PFC_FUNCTION(tpu0),
 };
 
 static struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
1.8.2.1

[PATCH 112/130] sh-pfc: sh73a0: Remove function GPIOs

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

No sh73a0 platform use the function GPIOs API. Remove it.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-sh73a0.c | 395 ------------------------------------
 1 file changed, 395 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 78f7ae8..7956df5 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -26,7 +26,6 @@
 #include <linux/regulator/machine.h>
 #include <linux/slab.h>
 
-#include <mach/sh73a0.h>
 #include <mach/irqs.h>
 
 #include "core.h"
@@ -3153,397 +3152,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(usb),
 };
 
-#define PINMUX_FN_BASE	GPIO_FN_GPI0
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-	/* Table 25-1 (Functions 0-7) */
-	GPIO_FN(GPI0),
-	GPIO_FN(GPI1),
-	GPIO_FN(GPI2),
-	GPIO_FN(GPI3),
-	GPIO_FN(GPI4),
-	GPIO_FN(GPI5),
-	GPIO_FN(GPI6),
-	GPIO_FN(GPI7),
-	GPIO_FN(GPO7), \
-	GPIO_FN(MFG0_OUT2),
-	GPIO_FN(GPO6), \
-	GPIO_FN(MFG1_OUT2),
-	GPIO_FN(GPO5), \
-	GPIO_FN(PORT16_VIO_CKOR),
-	GPIO_FN(PORT19_VIO_CKO2),
-	GPIO_FN(GPO0),
-	GPIO_FN(GPO1),
-	GPIO_FN(GPO2), \
-	GPIO_FN(STATUS0),
-	GPIO_FN(GPO3), \
-	GPIO_FN(STATUS1),
-	GPIO_FN(GPO4), \
-	GPIO_FN(STATUS2),
-	GPIO_FN(VINT),
-	GPIO_FN(TCKON),
-	GPIO_FN(XDVFS1), \
-	GPIO_FN(MFG0_OUT1), \
-	GPIO_FN(PORT27_IROUT),
-	GPIO_FN(XDVFS2), \
-	GPIO_FN(PORT28_TPU1TO1),
-	GPIO_FN(SIM_RST), \
-	GPIO_FN(PORT29_TPU1TO1),
-	GPIO_FN(SIM_CLK), \
-	GPIO_FN(PORT30_VIO_CKOR),
-	GPIO_FN(SIM_D), \
-	GPIO_FN(PORT31_IROUT),
-	GPIO_FN(XWUP),
-	GPIO_FN(VACK),
-	GPIO_FN(XTAL1L),
-	GPIO_FN(PORT49_IROUT), \
-	GPIO_FN(BBIF2_TSYNC2), \
-	GPIO_FN(TPU2TO2), \
-
-	GPIO_FN(BBIF2_TSCK2), \
-	GPIO_FN(TPU2TO3), \
-	GPIO_FN(BBIF2_TXD2),
-	GPIO_FN(TPU3TO3), \
-	GPIO_FN(TPU3TO2), \
-	GPIO_FN(TPU0TO0),
-	GPIO_FN(A0), \
-	GPIO_FN(BS_),
-	GPIO_FN(A12), \
-	GPIO_FN(TPU4TO2),
-	GPIO_FN(A13), \
-	GPIO_FN(TPU0TO1),
-	GPIO_FN(A14), \
-	GPIO_FN(A15), \
-	GPIO_FN(A16), \
-	GPIO_FN(MSIOF0_SS1),
-	GPIO_FN(A17), \
-	GPIO_FN(MSIOF0_TSYNC),
-	GPIO_FN(A18), \
-	GPIO_FN(MSIOF0_TSCK),
-	GPIO_FN(A19), \
-	GPIO_FN(MSIOF0_TXD),
-	GPIO_FN(A20), \
-	GPIO_FN(MSIOF0_RSCK),
-	GPIO_FN(A21), \
-	GPIO_FN(MSIOF0_RSYNC),
-	GPIO_FN(A22), \
-	GPIO_FN(MSIOF0_MCK0),
-	GPIO_FN(A23), \
-	GPIO_FN(MSIOF0_MCK1),
-	GPIO_FN(A24), \
-	GPIO_FN(MSIOF0_RXD),
-	GPIO_FN(A25), \
-	GPIO_FN(MSIOF0_SS2),
-	GPIO_FN(A26), \
-	GPIO_FN(FCE1_),
-	GPIO_FN(DACK0),
-	GPIO_FN(FCE0_), \
-	GPIO_FN(WAIT_), \
-	GPIO_FN(DREQ0),
-	GPIO_FN(FRB),
-	GPIO_FN(CKO),
-	GPIO_FN(NBRSTOUT_),
-	GPIO_FN(NBRST_),
-	GPIO_FN(BBIF2_TXD),
-	GPIO_FN(BBIF2_RXD),
-	GPIO_FN(BBIF2_SYNC),
-	GPIO_FN(BBIF2_SCK),
-	GPIO_FN(MFG3_IN2),
-	GPIO_FN(MFG3_IN1),
-	GPIO_FN(BBIF1_SS2), \
-	GPIO_FN(MFG3_OUT1),
-	GPIO_FN(HSI_RX_DATA), \
-	GPIO_FN(BBIF1_RXD),
-	GPIO_FN(HSI_TX_WAKE), \
-	GPIO_FN(BBIF1_TSCK),
-	GPIO_FN(HSI_TX_DATA), \
-	GPIO_FN(BBIF1_TSYNC),
-	GPIO_FN(HSI_TX_READY), \
-	GPIO_FN(BBIF1_TXD),
-	GPIO_FN(HSI_RX_READY), \
-	GPIO_FN(BBIF1_RSCK), \
-	GPIO_FN(HSI_RX_WAKE), \
-	GPIO_FN(BBIF1_RSYNC), \
-	GPIO_FN(HSI_RX_FLAG), \
-	GPIO_FN(BBIF1_SS1), \
-	GPIO_FN(BBIF1_FLOW),
-	GPIO_FN(HSI_TX_FLAG),
-	GPIO_FN(VIO_VD), \
-	GPIO_FN(VIO2_VD), \
-
-	GPIO_FN(VIO_HD), \
-	GPIO_FN(VIO2_HD), \
-	GPIO_FN(VIO_D0), \
-	GPIO_FN(PORT130_MSIOF2_RXD), \
-	GPIO_FN(VIO_D1), \
-	GPIO_FN(PORT131_MSIOF2_SS1), \
-	GPIO_FN(VIO_D2), \
-	GPIO_FN(PORT132_MSIOF2_SS2), \
-	GPIO_FN(VIO_D3), \
-	GPIO_FN(MSIOF2_TSYNC), \
-	GPIO_FN(VIO_D4), \
-	GPIO_FN(MSIOF2_TXD), \
-	GPIO_FN(VIO_D5), \
-	GPIO_FN(MSIOF2_TSCK), \
-	GPIO_FN(VIO_D6), \
-	GPIO_FN(VIO_D7), \
-	GPIO_FN(VIO_D8), \
-	GPIO_FN(VIO2_D0), \
-	GPIO_FN(VIO_D9), \
-	GPIO_FN(VIO2_D1), \
-	GPIO_FN(VIO_D10), \
-	GPIO_FN(TPU0TO2), \
-	GPIO_FN(VIO2_D2), \
-	GPIO_FN(VIO_D11), \
-	GPIO_FN(TPU0TO3), \
-	GPIO_FN(VIO2_D3), \
-	GPIO_FN(VIO_D12), \
-	GPIO_FN(VIO2_D4), \
-	GPIO_FN(VIO_D13), \
-	GPIO_FN(VIO2_D5), \
-	GPIO_FN(VIO_D14), \
-	GPIO_FN(VIO2_D6), \
-	GPIO_FN(VIO_D15), \
-	GPIO_FN(TPU1TO3), \
-	GPIO_FN(VIO2_D7), \
-	GPIO_FN(VIO_CLK), \
-	GPIO_FN(VIO2_CLK), \
-	GPIO_FN(VIO_FIELD), \
-	GPIO_FN(VIO2_FIELD), \
-	GPIO_FN(VIO_CKO),
-	GPIO_FN(A27), \
-	GPIO_FN(MFG0_IN1), \
-	GPIO_FN(MFG0_IN2),
-	GPIO_FN(TS_SPSYNC3), \
-	GPIO_FN(MSIOF2_RSCK),
-	GPIO_FN(TS_SDAT3), \
-	GPIO_FN(MSIOF2_RSYNC),
-	GPIO_FN(TPU1TO2), \
-	GPIO_FN(TS_SDEN3), \
-	GPIO_FN(PORT153_MSIOF2_SS1),
-	GPIO_FN(MSIOF2_MCK0),
-	GPIO_FN(MSIOF2_MCK1),
-	GPIO_FN(PORT156_MSIOF2_SS2),
-	GPIO_FN(PORT157_MSIOF2_RXD),
-	GPIO_FN(DINT_), \
-	GPIO_FN(TS_SCK3),
-	GPIO_FN(NMI),
-	GPIO_FN(TPU3TO0),
-	GPIO_FN(BBIF2_TSYNC1),
-	GPIO_FN(BBIF2_TSCK1),
-	GPIO_FN(BBIF2_TXD1),
-	GPIO_FN(MFG2_OUT2), \
-	GPIO_FN(TPU2TO1),
-	GPIO_FN(TPU4TO1), \
-	GPIO_FN(MFG4_OUT2),
-	GPIO_FN(D16),
-	GPIO_FN(D17),
-	GPIO_FN(D18),
-	GPIO_FN(D19),
-	GPIO_FN(D20),
-	GPIO_FN(D21),
-	GPIO_FN(D22),
-	GPIO_FN(PORT207_MSIOF0L_SS1), \
-	GPIO_FN(D23),
-	GPIO_FN(PORT208_MSIOF0L_SS2), \
-	GPIO_FN(D24),
-	GPIO_FN(D25),
-	GPIO_FN(DREQ2), \
-	GPIO_FN(PORT210_MSIOF0L_SS1), \
-	GPIO_FN(D26),
-	GPIO_FN(PORT211_MSIOF0L_SS2), \
-	GPIO_FN(D27),
-	GPIO_FN(TS_SPSYNC1), \
-	GPIO_FN(MSIOF0L_MCK0), \
-	GPIO_FN(D28),
-	GPIO_FN(TS_SDAT1), \
-	GPIO_FN(MSIOF0L_MCK1), \
-	GPIO_FN(D29),
-	GPIO_FN(TS_SDEN1), \
-	GPIO_FN(MSIOF0L_RSCK), \
-	GPIO_FN(D30),
-	GPIO_FN(TS_SCK1), \
-	GPIO_FN(MSIOF0L_RSYNC), \
-	GPIO_FN(D31),
-	GPIO_FN(DACK2), \
-	GPIO_FN(MSIOF0L_TSYNC), \
-	GPIO_FN(VIO2_FIELD3), \
-	GPIO_FN(DACK3), \
-	GPIO_FN(PORT218_VIO_CKOR),
-	GPIO_FN(DREQ3), \
-	GPIO_FN(MSIOF0L_TSCK), \
-	GPIO_FN(VIO2_CLK3), \
-	GPIO_FN(DREQ1), \
-	GPIO_FN(PWEN), \
-	GPIO_FN(MSIOF0L_RXD), \
-	GPIO_FN(VIO2_HD3), \
-	GPIO_FN(DACK1), \
-	GPIO_FN(OVCN), \
-	GPIO_FN(MSIOF0L_TXD), \
-	GPIO_FN(VIO2_VD3), \
-
-	GPIO_FN(OVCN2),
-	GPIO_FN(EXTLP), \
-	GPIO_FN(PORT226_VIO_CKO2),
-	GPIO_FN(IDIN),
-	GPIO_FN(MFG1_IN1),
-	GPIO_FN(MSIOF1_TXD), \
-	GPIO_FN(MSIOF1_TSYNC), \
-	GPIO_FN(MSIOF1_TSCK), \
-	GPIO_FN(MSIOF1_RXD), \
-	GPIO_FN(MSIOF1_RSCK), \
-	GPIO_FN(VIO2_CLK2), \
-	GPIO_FN(MSIOF1_RSYNC), \
-	GPIO_FN(MFG1_IN2), \
-	GPIO_FN(VIO2_VD2), \
-	GPIO_FN(MSIOF1_MCK0), \
-	GPIO_FN(MSIOF1_MCK1), \
-	GPIO_FN(MSIOF1_SS1), \
-	GPIO_FN(VIO2_FIELD2), \
-	GPIO_FN(MSIOF1_SS2), \
-	GPIO_FN(VIO2_HD2), \
-	GPIO_FN(PORT241_IROUT), \
-	GPIO_FN(MFG4_OUT1), \
-	GPIO_FN(TPU4TO0),
-	GPIO_FN(MFG4_IN2),
-	GPIO_FN(PORT243_VIO_CKO2),
-	GPIO_FN(MFG2_IN1), \
-	GPIO_FN(MSIOF2R_RXD),
-	GPIO_FN(MFG2_IN2), \
-	GPIO_FN(MSIOF2R_TXD),
-	GPIO_FN(MFG1_OUT1), \
-	GPIO_FN(TPU1TO0),
-	GPIO_FN(MFG3_OUT2), \
-	GPIO_FN(TPU3TO1),
-	GPIO_FN(MFG2_OUT1), \
-	GPIO_FN(TPU2TO0), \
-	GPIO_FN(MSIOF2R_TSCK),
-	GPIO_FN(PORT249_IROUT), \
-	GPIO_FN(MFG4_IN1), \
-	GPIO_FN(MSIOF2R_TSYNC),
-	GPIO_FN(SDHICLK0),
-	GPIO_FN(SDHICD0),
-	GPIO_FN(SDHID0_0),
-	GPIO_FN(SDHID0_1),
-	GPIO_FN(SDHID0_2),
-	GPIO_FN(SDHID0_3),
-	GPIO_FN(SDHICMD0),
-	GPIO_FN(SDHIWP0),
-	GPIO_FN(SDHICLK1),
-	GPIO_FN(SDHID1_0), \
-	GPIO_FN(TS_SPSYNC2),
-	GPIO_FN(SDHID1_1), \
-	GPIO_FN(TS_SDAT2),
-	GPIO_FN(SDHID1_2), \
-	GPIO_FN(TS_SDEN2),
-	GPIO_FN(SDHID1_3), \
-	GPIO_FN(TS_SCK2),
-	GPIO_FN(SDHICMD1),
-	GPIO_FN(SDHICLK2),
-	GPIO_FN(SDHID2_0), \
-	GPIO_FN(TS_SPSYNC4),
-	GPIO_FN(SDHID2_1), \
-	GPIO_FN(TS_SDAT4),
-	GPIO_FN(SDHID2_2), \
-	GPIO_FN(TS_SDEN4),
-	GPIO_FN(SDHID2_3), \
-	GPIO_FN(TS_SCK4),
-	GPIO_FN(SDHICMD2),
-	GPIO_FN(MMCCLK0),
-	GPIO_FN(MMCD0_0),
-	GPIO_FN(MMCD0_1),
-	GPIO_FN(MMCD0_2),
-	GPIO_FN(MMCD0_3),
-	GPIO_FN(MMCD0_4), \
-	GPIO_FN(TS_SPSYNC5),
-	GPIO_FN(MMCD0_5), \
-	GPIO_FN(TS_SDAT5),
-	GPIO_FN(MMCD0_6), \
-	GPIO_FN(TS_SDEN5),
-	GPIO_FN(MMCD0_7), \
-	GPIO_FN(TS_SCK5),
-	GPIO_FN(MMCCMD0),
-	GPIO_FN(RESETOUTS_), \
-	GPIO_FN(EXTAL2OUT),
-	GPIO_FN(MCP_WAIT__MCP_FRB),
-	GPIO_FN(MCP_CKO), \
-	GPIO_FN(MMCCLK1),
-	GPIO_FN(MCP_D15_MCP_NAF15),
-	GPIO_FN(MCP_D14_MCP_NAF14),
-	GPIO_FN(MCP_D13_MCP_NAF13),
-	GPIO_FN(MCP_D12_MCP_NAF12),
-	GPIO_FN(MCP_D11_MCP_NAF11),
-	GPIO_FN(MCP_D10_MCP_NAF10),
-	GPIO_FN(MCP_D9_MCP_NAF9),
-	GPIO_FN(MCP_D8_MCP_NAF8), \
-	GPIO_FN(MMCCMD1),
-	GPIO_FN(MCP_D7_MCP_NAF7), \
-	GPIO_FN(MMCD1_7),
-
-	GPIO_FN(MCP_D6_MCP_NAF6), \
-	GPIO_FN(MMCD1_6),
-	GPIO_FN(MCP_D5_MCP_NAF5), \
-	GPIO_FN(MMCD1_5),
-	GPIO_FN(MCP_D4_MCP_NAF4), \
-	GPIO_FN(MMCD1_4),
-	GPIO_FN(MCP_D3_MCP_NAF3), \
-	GPIO_FN(MMCD1_3),
-	GPIO_FN(MCP_D2_MCP_NAF2), \
-	GPIO_FN(MMCD1_2),
-	GPIO_FN(MCP_D1_MCP_NAF1), \
-	GPIO_FN(MMCD1_1),
-	GPIO_FN(MCP_D0_MCP_NAF0), \
-	GPIO_FN(MMCD1_0),
-	GPIO_FN(MCP_NBRSTOUT_),
-	GPIO_FN(MCP_WE0__MCP_FWE), \
-	GPIO_FN(MCP_RDWR_MCP_FWE),
-
-	/* MSEL2 special cases */
-	GPIO_FN(TSIF2_TS_XX1),
-	GPIO_FN(TSIF2_TS_XX2),
-	GPIO_FN(TSIF2_TS_XX3),
-	GPIO_FN(TSIF2_TS_XX4),
-	GPIO_FN(TSIF2_TS_XX5),
-	GPIO_FN(TSIF1_TS_XX1),
-	GPIO_FN(TSIF1_TS_XX2),
-	GPIO_FN(TSIF1_TS_XX3),
-	GPIO_FN(TSIF1_TS_XX4),
-	GPIO_FN(TSIF1_TS_XX5),
-	GPIO_FN(TSIF0_TS_XX1),
-	GPIO_FN(TSIF0_TS_XX2),
-	GPIO_FN(TSIF0_TS_XX3),
-	GPIO_FN(TSIF0_TS_XX4),
-	GPIO_FN(TSIF0_TS_XX5),
-	GPIO_FN(MST1_TS_XX1),
-	GPIO_FN(MST1_TS_XX2),
-	GPIO_FN(MST1_TS_XX3),
-	GPIO_FN(MST1_TS_XX4),
-	GPIO_FN(MST1_TS_XX5),
-	GPIO_FN(MST0_TS_XX1),
-	GPIO_FN(MST0_TS_XX2),
-	GPIO_FN(MST0_TS_XX3),
-	GPIO_FN(MST0_TS_XX4),
-	GPIO_FN(MST0_TS_XX5),
-
-	/* MSEL3 special cases */
-	GPIO_FN(SDHI0_VCCQ_MC0_ON),
-	GPIO_FN(SDHI0_VCCQ_MC0_OFF),
-	GPIO_FN(DEBUG_MON_VIO),
-	GPIO_FN(DEBUG_MON_LCDD),
-	GPIO_FN(LCDC_LCDC0),
-	GPIO_FN(LCDC_LCDC1),
-
-	/* MSEL4 special cases */
-	GPIO_FN(IRQ9_MEM_INT),
-	GPIO_FN(IRQ9_MCP_INT),
-	GPIO_FN(A11),
-	GPIO_FN(TPU4TO3),
-	GPIO_FN(RESETA_N_PU_ON),
-	GPIO_FN(RESETA_N_PU_OFF),
-	GPIO_FN(EDBGREQ_PD),
-	GPIO_FN(EDBGREQ_PU),
-};
-
 #undef PORTCR
 #define PORTCR(nr, reg)							\
 	{								\
@@ -4303,9 +3911,6 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = {
 	.functions = pinmux_functions,
 	.nr_functions = ARRAY_SIZE(pinmux_functions),
 
-	.func_gpios = pinmux_func_gpios,
-	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
 	.cfg_regs = pinmux_config_regs,
 	.data_regs = pinmux_data_regs,
 
-- 
1.8.2.1

[PATCH 113/130] sh-pfc: r8a7778: add VIN pin groups

[Simon Horman]

From: Vladimir Barinov <vladimir.barinov@cogentembedded.com>

Add VIN DATA[0:8]/CLK/HSYNC/VSYNC pin groups to R8A7778 PFC driver.
While at it, add SH_PFC_MUX8() macro for 8-bit data busses.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
[Sergei: updated the copyrights, added SH_PFC_MUX8() macro for 8-bit data bus,
made use of SH_PFC_*() macros to define the pin groups.]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 60 ++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index 1f692e5..e518c33 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2013  Renesas Solutions Corp.
  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ * Copyright (C) 2013  Cogent Embedded, Inc.
  *
  * based on
  * Copyright (C) 2011  Renesas Solutions Corp.
@@ -1316,6 +1317,11 @@ static struct sh_pfc_pin pinmux_pins[] = {
 #define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4)			\
 	static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
 						     arg3##_MARK, arg4##_MARK }
+#define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \
+	static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
+						     arg3##_MARK, arg4##_MARK, \
+						     arg5##_MARK, arg6##_MARK, \
+						     arg7##_MARK, arg8##_MARK, }
 
 /* - SCIF macro ------------------------------------------------------------- */
 #define SCIF_PFC_PIN(name, args...)	SH_PFC_PINS(name, args)
@@ -1513,6 +1519,40 @@ SH_PFC_MUX1(usb1,		PENC1);
 SH_PFC_PINS(usb1_ovc,		RCAR_GP_PIN(0, 4));
 SH_PFC_MUX1(usb1_ovc,		USB_OVC1);
 
+/* - VIN macros ------------------------------------------------------------- */
+#define VIN_PFC_PINS(name, args...)		SH_PFC_PINS(name, args)
+#define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)	\
+	SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
+#define VIN_PFC_CLK(name, clk)			SH_PFC_MUX1(name, clk)
+#define VIN_PFC_SYNC(name, hsync, vsync)	SH_PFC_MUX2(name, hsync, vsync)
+
+/* - VIN0 ------------------------------------------------------------------- */
+VIN_PFC_PINS(vin0_data8,	RCAR_GP_PIN(3, 29),	RCAR_GP_PIN(3, 30),
+				RCAR_GP_PIN(3, 31),	RCAR_GP_PIN(4, 0),
+				RCAR_GP_PIN(4, 1),	RCAR_GP_PIN(4, 2),
+				RCAR_GP_PIN(4, 3),	RCAR_GP_PIN(4, 4));
+VIN_PFC_DAT8(vin0_data8,	VI0_DATA0_VI0_B0,	VI0_DATA1_VI0_B1,
+				VI0_DATA2_VI0_B2,	VI0_DATA3_VI0_B3,
+				VI0_DATA4_VI0_B4,	VI0_DATA5_VI0_B5,
+				VI0_DATA6_VI0_G0,	VI0_DATA7_VI0_G1);
+VIN_PFC_PINS(vin0_clk,		RCAR_GP_PIN(3, 24));
+VIN_PFC_CLK(vin0_clk,		VI0_CLK);
+VIN_PFC_PINS(vin0_sync,		RCAR_GP_PIN(3, 27),	RCAR_GP_PIN(3, 28));
+VIN_PFC_SYNC(vin0_sync,		VI0_HSYNC,		VI0_VSYNC);
+/* - VIN1 ------------------------------------------------------------------- */
+VIN_PFC_PINS(vin1_data8,	RCAR_GP_PIN(3, 25),	RCAR_GP_PIN(3, 26),
+				RCAR_GP_PIN(3, 27),	RCAR_GP_PIN(3, 28),
+				RCAR_GP_PIN(4, 5),	RCAR_GP_PIN(4, 6),
+				RCAR_GP_PIN(4, 7),	RCAR_GP_PIN(4, 8));
+VIN_PFC_DAT8(vin1_data8,	VI1_DATA0,		VI1_DATA1,
+				VI1_DATA2,		VI1_DATA3,
+				VI1_DATA4,		VI1_DATA5,
+				VI1_DATA6,		VI1_DATA7);
+VIN_PFC_PINS(vin1_clk,		RCAR_GP_PIN(4, 9));
+VIN_PFC_CLK(vin1_clk,		VI1_CLK);
+VIN_PFC_PINS(vin1_sync,		RCAR_GP_PIN(3, 21),	RCAR_GP_PIN(3, 22));
+VIN_PFC_SYNC(vin1_sync,		VI1_HSYNC,		VI1_VSYNC);
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(hscif0_data_a),
 	SH_PFC_PIN_GROUP(hscif0_data_b),
@@ -1586,6 +1626,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(usb0_ovc),
 	SH_PFC_PIN_GROUP(usb1),
 	SH_PFC_PIN_GROUP(usb1_ovc),
+	SH_PFC_PIN_GROUP(vin0_data8),
+	SH_PFC_PIN_GROUP(vin0_clk),
+	SH_PFC_PIN_GROUP(vin0_sync),
+	SH_PFC_PIN_GROUP(vin1_data8),
+	SH_PFC_PIN_GROUP(vin1_clk),
+	SH_PFC_PIN_GROUP(vin1_sync),
 };
 
 static const char * const hscif0_groups[] = {
@@ -1703,6 +1749,18 @@ static const char * const usb1_groups[] = {
 	"usb1_ovc",
 };
 
+static const char * const vin0_groups[] = {
+	"vin0_data8",
+	"vin0_clk",
+	"vin0_sync",
+};
+
+static const char * const vin1_groups[] = {
+	"vin1_data8",
+	"vin1_clk",
+	"vin1_sync",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(hscif0),
 	SH_PFC_FUNCTION(hscif1),
@@ -1718,6 +1776,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(sdhi2),
 	SH_PFC_FUNCTION(usb0),
 	SH_PFC_FUNCTION(usb1),
+	SH_PFC_FUNCTION(vin0),
+	SH_PFC_FUNCTION(vin1),
 };
 
 static struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
1.8.2.1

[PATCH 114/130] sh-pfc: r8a7778: add Ether pin groups

[Simon Horman]

From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Add Ether RMII/LINK/MAGIC pin groups to R8A7778 PFC driver.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart<laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index e518c33..bc20083 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -1323,6 +1323,22 @@ static struct sh_pfc_pin pinmux_pins[] = {
 						     arg5##_MARK, arg6##_MARK, \
 						     arg7##_MARK, arg8##_MARK, }
 
+/* - Ether ------------------------------------------------------------------ */
+SH_PFC_PINS(ether_rmii,		RCAR_GP_PIN(4, 10),	RCAR_GP_PIN(4, 11),
+				RCAR_GP_PIN(4, 13),	RCAR_GP_PIN(4, 9),
+				RCAR_GP_PIN(4, 15),	RCAR_GP_PIN(4, 16),
+				RCAR_GP_PIN(4, 12),	RCAR_GP_PIN(4, 14),
+				RCAR_GP_PIN(4, 18),	RCAR_GP_PIN(4, 17));
+static const unsigned int ether_rmii_mux[] = {
+	ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REF_CLK_MARK,
+	ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
+	ETH_MDIO_MARK, ETH_MDC_MARK,
+};
+SH_PFC_PINS(ether_link,		RCAR_GP_PIN(4, 19));
+SH_PFC_MUX1(ether_link,		ETH_LINK);
+SH_PFC_PINS(ether_magic,	RCAR_GP_PIN(4, 20));
+SH_PFC_MUX1(ether_magic,	ETH_MAGIC);
+
 /* - SCIF macro ------------------------------------------------------------- */
 #define SCIF_PFC_PIN(name, args...)	SH_PFC_PINS(name, args)
 #define SCIF_PFC_DAT(name, tx, rx)	SH_PFC_MUX2(name, tx, rx)
@@ -1554,6 +1570,9 @@ VIN_PFC_PINS(vin1_sync,		RCAR_GP_PIN(3, 21),	RCAR_GP_PIN(3, 22));
 VIN_PFC_SYNC(vin1_sync,		VI1_HSYNC,		VI1_VSYNC);
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SH_PFC_PIN_GROUP(ether_rmii),
+	SH_PFC_PIN_GROUP(ether_link),
+	SH_PFC_PIN_GROUP(ether_magic),
 	SH_PFC_PIN_GROUP(hscif0_data_a),
 	SH_PFC_PIN_GROUP(hscif0_data_b),
 	SH_PFC_PIN_GROUP(hscif0_ctrl_a),
@@ -1634,6 +1653,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(vin1_sync),
 };
 
+static const char * const ether_groups[] = {
+	"ether_rmii",
+	"ether_link",
+	"ether_magic",
+};
+
 static const char * const hscif0_groups[] = {
 	"hscif0_data_a",
 	"hscif0_data_b",
@@ -1762,6 +1787,7 @@ static const char * const vin1_groups[] = {
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(ether),
 	SH_PFC_FUNCTION(hscif0),
 	SH_PFC_FUNCTION(hscif1),
 	SH_PFC_FUNCTION(scif_clk),
-- 
1.8.2.1

[PATCH 115/130] sh-pfc: r8a7779: add Ether pin groups

[Simon Horman]

From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Add Ether RMII/LINK/MAGIC pin groups to R8A7779 PFC driver.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart<laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 42 ++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 37ba571..96bdf48 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1640,6 +1640,38 @@ static const unsigned int du1_cde_pins[] = {
 static const unsigned int du1_cde_mux[] = {
 	DU1_CDE_MARK
 };
+/* - Ether ------------------------------------------------------------------ */
+static const unsigned int ether_rmii_pins[] = {
+	/*
+	 * ETH_TXD0, ETH_TXD1, ETH_TX_EN,  ETH_REFCLK,
+	 * ETH_RXD0, ETH_RXD1, ETH_CRS_DV, ETH_RX_ER,
+	 * ETH_MDIO, ETH_MDC
+	 */
+	RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 18),
+	RCAR_GP_PIN(2, 26),
+	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 17),
+	RCAR_GP_PIN(2, 19),
+	RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 28),
+};
+static const unsigned int ether_rmii_mux[] = {
+	ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REFCLK_MARK,
+	ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
+	ETH_MDIO_MARK, ETH_MDC_MARK,
+};
+static const unsigned int ether_link_pins[] = {
+	/* ETH_LINK */
+	RCAR_GP_PIN(2, 24),
+};
+static const unsigned int ether_link_mux[] = {
+	ETH_LINK_MARK,
+};
+static const unsigned int ether_magic_pins[] = {
+	/* ETH_MAGIC */
+	RCAR_GP_PIN(2, 25),
+};
+static const unsigned int ether_magic_mux[] = {
+	ETH_MAGIC_MARK,
+};
 /* - HSPI0 ------------------------------------------------------------------ */
 static const unsigned int hspi0_pins[] = {
 	/* CLK, CS, RX, TX */
@@ -2558,6 +2590,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(du1_sync_1),
 	SH_PFC_PIN_GROUP(du1_oddf),
 	SH_PFC_PIN_GROUP(du1_cde),
+	SH_PFC_PIN_GROUP(ether_rmii),
+	SH_PFC_PIN_GROUP(ether_link),
+	SH_PFC_PIN_GROUP(ether_magic),
 	SH_PFC_PIN_GROUP(hspi0),
 	SH_PFC_PIN_GROUP(hspi1),
 	SH_PFC_PIN_GROUP(hspi1_b),
@@ -2703,6 +2738,12 @@ static const char * const du1_groups[] = {
 	"du1_cde",
 };
 
+static const char * const ether_groups[] = {
+	"ether_rmii",
+	"ether_link",
+	"ether_magic",
+};
+
 static const char * const hspi0_groups[] = {
 	"hspi0",
 };
@@ -2898,6 +2939,7 @@ static const char * const vin3_groups[] = {
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(du0),
 	SH_PFC_FUNCTION(du1),
+	SH_PFC_FUNCTION(ether),
 	SH_PFC_FUNCTION(hspi0),
 	SH_PFC_FUNCTION(hspi1),
 	SH_PFC_FUNCTION(hspi2),
-- 
1.8.2.1

[PATCH 116/130] sh-pfc: r8a7778: fixup IRQ1A settings

[Simon Horman]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

IP2[31] func2 is IRQ1A, not IRQ3A

Reported-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index bc20083..6b2c6b5 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -2080,7 +2080,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
 			     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
 			     1, 1, 1, 1, 3, 2, 3, 3, 3, 3) {
 		/* IP2_31 [1] */
-		FN_MLB_CLK,	FN_IRQ3_A,
+		FN_MLB_CLK,	FN_IRQ1_A,
 		/* IP2_30 [1] */
 		FN_RD_WR_B,	FN_IRQ0,
 		/* IP2_29 [1] */
-- 
1.8.2.1

[PATCH 117/130] pinctrl: sh-pfc: fix r8a7790 Function Select register tables

[Simon Horman]

From: Guennadi Liakhovetski <g.liakhovetski@gmx.de>

Fix several errors in Peripheral Function Select register tables for
r8a7790, which prevent various function pins from being correctly
configured.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 5be2999..a2f83ae 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -3175,7 +3175,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
 		FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
 	},
 	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
-			     2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+			     2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
 		/* IP11_31_30 [2] */
 		FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
 		/* IP11_29_27 [3] */
@@ -3441,12 +3441,10 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
 		FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
 	},
 	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
-			     2, 1, 1, 1, 1, 2, 1, 2, 1,
-			     2, 1, 1, 1, 3, 3, 2, 3, 2, 2) {
-		/* RESEVED [2] */
+			     3, 1, 1, 1, 2, 1, 2, 1, 2,
+			     1, 1, 1, 3, 3, 2, 3, 2, 2) {
+		/* RESEVED [3] */
 		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESEVED [1] */
-		0, 0,
 		/* SEL_TMU1 [1] */
 		FN_SEL_TMU1_0, FN_SEL_TMU1_1,
 		/* SEL_HSCIF1 [1] */
@@ -3462,8 +3460,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
 		/* SEL_CAN1 [1] */
 		FN_SEL_CAN1_0, FN_SEL_CAN1_1,
 		/* RESEVED [2] */
-		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESEVED [1] */
+		0, 0, 0, 0,
+		/* RESEVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */
 		0, 0,
 		/* SEL_ADI [1] */
 		FN_SEL_ADI_0, FN_SEL_ADI_1,
-- 
1.8.2.1

[PATCH 118/130] pinctrl: sh-pfc: fix a typo in pfc-r8a7790

[Simon Horman]

From: Guennadi Liakhovetski <g.liakhovetski@gmx.de>

Fix multiple occurrences of the "RESEVED" typo.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index a2f83ae..9338422 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -3443,7 +3443,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
 	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
 			     3, 1, 1, 1, 2, 1, 2, 1, 2,
 			     1, 1, 1, 3, 3, 2, 3, 2, 2) {
-		/* RESEVED [3] */
+		/* RESERVED [3] */
 		0, 0, 0, 0, 0, 0, 0, 0,
 		/* SEL_TMU1 [1] */
 		FN_SEL_TMU1_0, FN_SEL_TMU1_1,
@@ -3459,9 +3459,9 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
 		FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
 		/* SEL_CAN1 [1] */
 		FN_SEL_CAN1_0, FN_SEL_CAN1_1,
-		/* RESEVED [2] */
+		/* RESERVED [2] */
 		0, 0, 0, 0,
-		/* RESEVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */
+		/* RESERVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */
 		0, 0,
 		/* SEL_ADI [1] */
 		FN_SEL_ADI_0, FN_SEL_ADI_1,
@@ -3490,22 +3490,22 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
 		FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
 		/* SEL_IIC0 [1] */
 		FN_SEL_IIC0_0, FN_SEL_IIC0_1,
-		/* RESEVED [2] */
+		/* RESERVED [2] */
 		0, 0, 0, 0,
-		/* RESEVED [4] */
+		/* RESERVED [4] */
 		0, 0, 0, 0, 0, 0, 0, 0,
 		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESEVED [4] */
+		/* RESERVED [4] */
 		0, 0, 0, 0, 0, 0, 0, 0,
 		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESEVED [2] */
+		/* RESERVED [2] */
 		0, 0, 0, 0,
 		/* SEL_IEB [2] */
 		FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
-		/* RESEVED [4] */
+		/* RESERVED [4] */
 		0, 0, 0, 0, 0, 0, 0, 0,
 		0, 0, 0, 0, 0, 0, 0, 0,
-		/* RESEVED [2] */
+		/* RESERVED [2] */
 		0, 0, 0, 0,
 		/* SEL_IIC2 [3] */
 		FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
-- 
1.8.2.1

[PATCH 119/130] sh-pfc: r8a7778: add I2C pin groups

[Simon Horman]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

Add I2C SDA/SCL pin groups to R8A7778 PFC driver.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 54 ++++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index 6b2c6b5..605f8ae 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -1371,6 +1371,32 @@ SCIF_PFC_CLK(hscif1_clk_a,	HSCK1_A);
 SCIF_PFC_PIN(hscif1_clk_b,	RCAR_GP_PIN(4, 2));
 SCIF_PFC_CLK(hscif1_clk_b,	HSCK1_B);
 
+/* - I2C macro ------------------------------------------------------------- */
+#define I2C_PFC_PIN(name, args...)	SH_PFC_PINS(name, args)
+#define I2C_PFC_MUX(name, sda, scl)	SH_PFC_MUX2(name, sda, scl)
+
+/* - I2C1 ------------------------------------------------------------------ */
+I2C_PFC_PIN(i2c1_a,	RCAR_GP_PIN(3, 8),	RCAR_GP_PIN(3, 9));
+I2C_PFC_MUX(i2c1_a,	SDA1_A,			SCL1_A);
+I2C_PFC_PIN(i2c1_b,	RCAR_GP_PIN(4, 17),	RCAR_GP_PIN(4, 18));
+I2C_PFC_MUX(i2c1_b,	SDA1_B,			SCL1_B);
+
+/* - I2C2 ------------------------------------------------------------------ */
+I2C_PFC_PIN(i2c2_a,	PIN_NUMBER(3, 20),	RCAR_GP_PIN(1, 3));
+I2C_PFC_MUX(i2c2_a,	SDA2_A,			SCL2_A);
+I2C_PFC_PIN(i2c2_b,	RCAR_GP_PIN(0, 3),	RCAR_GP_PIN(0, 4));
+I2C_PFC_MUX(i2c2_b,	SDA2_B,			SCL2_B);
+I2C_PFC_PIN(i2c2_c,	RCAR_GP_PIN(4, 15),	RCAR_GP_PIN(4, 16));
+I2C_PFC_MUX(i2c2_c,	SDA2_C,			SCL2_C);
+
+/* - I2C3 ------------------------------------------------------------------ */
+I2C_PFC_PIN(i2c3_a,	RCAR_GP_PIN(1, 14),	RCAR_GP_PIN(1, 15));
+I2C_PFC_MUX(i2c3_a,	SDA3_A,			SCL3_A);
+I2C_PFC_PIN(i2c3_b,	RCAR_GP_PIN(1, 16),	RCAR_GP_PIN(1, 19));
+I2C_PFC_MUX(i2c3_b,	SDA3_B,			SCL3_B);
+I2C_PFC_PIN(i2c3_c,	RCAR_GP_PIN(1, 22),	RCAR_GP_PIN(1, 23));
+I2C_PFC_MUX(i2c3_c,	SDA3_C,			SCL3_C);
+
 /* - SCIF CLOCK ------------------------------------------------------------- */
 SCIF_PFC_PIN(scif_clk,		RCAR_GP_PIN(1, 16));
 SCIF_PFC_CLK(scif_clk,		SCIF_CLK);
@@ -1584,6 +1610,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
 	SH_PFC_PIN_GROUP(hscif1_clk_a),
 	SH_PFC_PIN_GROUP(hscif1_clk_b),
+	SH_PFC_PIN_GROUP(i2c1_a),
+	SH_PFC_PIN_GROUP(i2c1_b),
+	SH_PFC_PIN_GROUP(i2c2_a),
+	SH_PFC_PIN_GROUP(i2c2_b),
+	SH_PFC_PIN_GROUP(i2c2_c),
+	SH_PFC_PIN_GROUP(i2c3_a),
+	SH_PFC_PIN_GROUP(i2c3_b),
+	SH_PFC_PIN_GROUP(i2c3_c),
 	SH_PFC_PIN_GROUP(scif_clk),
 	SH_PFC_PIN_GROUP(scif0_data_a),
 	SH_PFC_PIN_GROUP(scif0_data_b),
@@ -1676,6 +1710,23 @@ static const char * const hscif1_groups[] = {
 	"hscif1_clk_b",
 };
 
+static const char * const i2c1_groups[] = {
+	"i2c1_a",
+	"i2c1_b",
+};
+
+static const char * const i2c2_groups[] = {
+	"i2c2_a",
+	"i2c2_b",
+	"i2c2_c",
+};
+
+static const char * const i2c3_groups[] = {
+	"i2c3_a",
+	"i2c3_b",
+	"i2c3_c",
+};
+
 static const char * const scif_clk_groups[] = {
 	"scif_clk",
 };
@@ -1790,6 +1841,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(ether),
 	SH_PFC_FUNCTION(hscif0),
 	SH_PFC_FUNCTION(hscif1),
+	SH_PFC_FUNCTION(i2c1),
+	SH_PFC_FUNCTION(i2c2),
+	SH_PFC_FUNCTION(i2c3),
 	SH_PFC_FUNCTION(scif_clk),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
-- 
1.8.2.1

[PATCH 120/130] sh-pfc: r8a7778: add HSPI pin groups

[Simon Horman]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

Add HSPI CLK/CS/RX/TX pin groups to R8A7778 PFC driver.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 61 ++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index 605f8ae..bf5e3d8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -1371,6 +1371,43 @@ SCIF_PFC_CLK(hscif1_clk_a,	HSCK1_A);
 SCIF_PFC_PIN(hscif1_clk_b,	RCAR_GP_PIN(4, 2));
 SCIF_PFC_CLK(hscif1_clk_b,	HSCK1_B);
 
+/* - HSPI macro --------------------------------------------------------------*/
+#define HSPI_PFC_PIN(name, args...)		SH_PFC_PINS(name, args)
+#define HSPI_PFC_DAT(name, clk, cs, rx, tx)	SH_PFC_MUX4(name, clk, cs, rx, tx)
+
+/* - HSPI0 -------------------------------------------------------------------*/
+HSPI_PFC_PIN(hspi0_a,	RCAR_GP_PIN(3, 19),	RCAR_GP_PIN(3, 20),
+			RCAR_GP_PIN(3, 21),	RCAR_GP_PIN(3, 22));
+HSPI_PFC_DAT(hspi0_a,	HSPI_CLK0_A,		HSPI_CS0_A,
+			HSPI_RX0_A,		HSPI_TX0);
+
+HSPI_PFC_PIN(hspi0_b,	RCAR_GP_PIN(2, 25),	RCAR_GP_PIN(2, 26),
+			RCAR_GP_PIN(2, 24),	RCAR_GP_PIN(2, 27));
+HSPI_PFC_DAT(hspi0_b,	HSPI_CLK0_B,		HSPI_CS0_B,
+			HSPI_RX0_B,		HSPI_TX0_B);
+
+/* - HSPI1 -------------------------------------------------------------------*/
+HSPI_PFC_PIN(hspi1_a,	RCAR_GP_PIN(3, 26),	RCAR_GP_PIN(3, 27),
+			RCAR_GP_PIN(3, 25),	RCAR_GP_PIN(3, 28));
+HSPI_PFC_DAT(hspi1_a,	HSPI_CLK1_A,		HSPI_CS1_A,
+			HSPI_RX1_A,		HSPI_TX1_A);
+
+HSPI_PFC_PIN(hspi1_b,	RCAR_GP_PIN(0, 27),	RCAR_GP_PIN(0, 26),
+			PIN_NUMBER(20, 1),	PIN_NUMBER(25, 2));
+HSPI_PFC_DAT(hspi1_b,	HSPI_CLK1_B,		HSPI_CS1_B,
+			HSPI_RX1_B,		HSPI_TX1_B);
+
+/* - HSPI2 -------------------------------------------------------------------*/
+HSPI_PFC_PIN(hspi2_a,	RCAR_GP_PIN(2, 29),	RCAR_GP_PIN(3, 8),
+			RCAR_GP_PIN(2, 28),	RCAR_GP_PIN(2, 30));
+HSPI_PFC_DAT(hspi2_a,	HSPI_CLK2_A,		HSPI_CS2_A,
+			HSPI_RX2_A,		HSPI_TX2_A);
+
+HSPI_PFC_PIN(hspi2_b,	RCAR_GP_PIN(4, 21),	RCAR_GP_PIN(4, 22),
+			RCAR_GP_PIN(4, 23),	RCAR_GP_PIN(4, 24));
+HSPI_PFC_DAT(hspi2_b,	HSPI_CLK2_B,		HSPI_CS2_B,
+			HSPI_RX2_B,		HSPI_TX2_B);
+
 /* - I2C macro ------------------------------------------------------------- */
 #define I2C_PFC_PIN(name, args...)	SH_PFC_PINS(name, args)
 #define I2C_PFC_MUX(name, sda, scl)	SH_PFC_MUX2(name, sda, scl)
@@ -1610,6 +1647,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
 	SH_PFC_PIN_GROUP(hscif1_clk_a),
 	SH_PFC_PIN_GROUP(hscif1_clk_b),
+	SH_PFC_PIN_GROUP(hspi0_a),
+	SH_PFC_PIN_GROUP(hspi0_b),
+	SH_PFC_PIN_GROUP(hspi1_a),
+	SH_PFC_PIN_GROUP(hspi1_b),
+	SH_PFC_PIN_GROUP(hspi2_a),
+	SH_PFC_PIN_GROUP(hspi2_b),
 	SH_PFC_PIN_GROUP(i2c1_a),
 	SH_PFC_PIN_GROUP(i2c1_b),
 	SH_PFC_PIN_GROUP(i2c2_a),
@@ -1710,6 +1753,21 @@ static const char * const hscif1_groups[] = {
 	"hscif1_clk_b",
 };
 
+static const char * const hspi0_groups[] = {
+	"hspi0_a",
+	"hspi0_b",
+};
+
+static const char * const hspi1_groups[] = {
+	"hspi1_a",
+	"hspi1_b",
+};
+
+static const char * const hspi2_groups[] = {
+	"hspi2_a",
+	"hspi2_b",
+};
+
 static const char * const i2c1_groups[] = {
 	"i2c1_a",
 	"i2c1_b",
@@ -1841,6 +1899,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(ether),
 	SH_PFC_FUNCTION(hscif0),
 	SH_PFC_FUNCTION(hscif1),
+	SH_PFC_FUNCTION(hspi0),
+	SH_PFC_FUNCTION(hspi1),
+	SH_PFC_FUNCTION(hspi2),
 	SH_PFC_FUNCTION(i2c1),
 	SH_PFC_FUNCTION(i2c2),
 	SH_PFC_FUNCTION(i2c3),
-- 
1.8.2.1

[PATCH 121/130] sh-pfc: r8a7778: add MMCIF pin groups

[Simon Horman]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

Add MMCIF CLK/CMD/DATA groups to R8A7778 PFC driver.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7778.c | 38 ++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index bf5e3d8..1dcbabc 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -1434,6 +1434,32 @@ I2C_PFC_MUX(i2c3_b,	SDA3_B,			SCL3_B);
 I2C_PFC_PIN(i2c3_c,	RCAR_GP_PIN(1, 22),	RCAR_GP_PIN(1, 23));
 I2C_PFC_MUX(i2c3_c,	SDA3_C,			SCL3_C);
 
+/* - MMC macro -------------------------------------------------------------- */
+#define MMC_PFC_PINS(name, args...)		SH_PFC_PINS(name, args)
+#define MMC_PFC_CTRL(name, clk, cmd)		SH_PFC_MUX2(name, clk, cmd)
+#define MMC_PFC_DAT1(name, d0)			SH_PFC_MUX1(name, d0)
+#define MMC_PFC_DAT4(name, d0, d1, d2, d3)	SH_PFC_MUX4(name, d0, d1, d2, d3)
+#define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)	\
+			SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
+
+/* - MMC -------------------------------------------------------------------- */
+MMC_PFC_PINS(mmc_ctrl,		RCAR_GP_PIN(1, 5),	RCAR_GP_PIN(1, 6));
+MMC_PFC_CTRL(mmc_ctrl,		MMC_CLK,		MMC_CMD);
+MMC_PFC_PINS(mmc_data1,		RCAR_GP_PIN(1, 7));
+MMC_PFC_DAT1(mmc_data1,		MMC_D0);
+MMC_PFC_PINS(mmc_data4,		RCAR_GP_PIN(1, 7),	RCAR_GP_PIN(2, 8),
+				RCAR_GP_PIN(0, 5),	RCAR_GP_PIN(0, 6));
+MMC_PFC_DAT4(mmc_data4,		MMC_D0,			MMC_D1,
+				MMC_D2,			MMC_D3);
+MMC_PFC_PINS(mmc_data8,		RCAR_GP_PIN(1, 7),	RCAR_GP_PIN(2, 8),
+				RCAR_GP_PIN(0, 5),	RCAR_GP_PIN(0, 6),
+				RCAR_GP_PIN(1, 4),	RCAR_GP_PIN(1, 0),
+				RCAR_GP_PIN(0, 30),	RCAR_GP_PIN(0, 31));
+MMC_PFC_DAT8(mmc_data8,		MMC_D0,			MMC_D1,
+				MMC_D2,			MMC_D3,
+				MMC_D4,			MMC_D5,
+				MMC_D6,			MMC_D7);
+
 /* - SCIF CLOCK ------------------------------------------------------------- */
 SCIF_PFC_PIN(scif_clk,		RCAR_GP_PIN(1, 16));
 SCIF_PFC_CLK(scif_clk,		SCIF_CLK);
@@ -1661,6 +1687,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(i2c3_a),
 	SH_PFC_PIN_GROUP(i2c3_b),
 	SH_PFC_PIN_GROUP(i2c3_c),
+	SH_PFC_PIN_GROUP(mmc_ctrl),
+	SH_PFC_PIN_GROUP(mmc_data1),
+	SH_PFC_PIN_GROUP(mmc_data4),
+	SH_PFC_PIN_GROUP(mmc_data8),
 	SH_PFC_PIN_GROUP(scif_clk),
 	SH_PFC_PIN_GROUP(scif0_data_a),
 	SH_PFC_PIN_GROUP(scif0_data_b),
@@ -1785,6 +1815,13 @@ static const char * const i2c3_groups[] = {
 	"i2c3_c",
 };
 
+static const char * const mmc_groups[] = {
+	"mmc_ctrl",
+	"mmc_data1",
+	"mmc_data4",
+	"mmc_data8",
+};
+
 static const char * const scif_clk_groups[] = {
 	"scif_clk",
 };
@@ -1905,6 +1942,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(i2c1),
 	SH_PFC_FUNCTION(i2c2),
 	SH_PFC_FUNCTION(i2c3),
+	SH_PFC_FUNCTION(mmc),
 	SH_PFC_FUNCTION(scif_clk),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
-- 
1.8.2.1

[PATCH 122/130] pinctrl: r8a7790: add pinmux data for MMCIF and SDHI interfaces

[Simon Horman]

From: Guennadi Liakhovetski <g.liakhovetski@gmx.de>

This patch adds pinmux groups and functions for the two MMCIF and four
SDHI interfaces on r8a73a4 (APE6).

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 294 +++++++++++++++++++++++++++++++++++
 1 file changed, 294 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 9338422..85d77a4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -2372,6 +2372,220 @@ static const unsigned int tpu0_to3_mux[] = {
 	TPU0TO3_MARK,
 };
 
+/* - MMCIF ------------------------------------------------------------------ */
+static const unsigned int mmc0_data1_pins[] = {
+	/* D[0] */
+	RCAR_GP_PIN(3, 18),
+};
+static const unsigned int mmc0_data1_mux[] = {
+	MMC0_D0_MARK,
+};
+static const unsigned int mmc0_data4_pins[] = {
+	/* D[0:3] */
+	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+};
+static const unsigned int mmc0_data4_mux[] = {
+	MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
+};
+static const unsigned int mmc0_data8_pins[] = {
+	/* D[0:7] */
+	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
+	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+static const unsigned int mmc0_data8_mux[] = {
+	MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
+	MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
+};
+static const unsigned int mmc0_ctrl_pins[] = {
+	/* CLK, CMD */
+	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
+};
+static const unsigned int mmc0_ctrl_mux[] = {
+	MMC0_CLK_MARK, MMC0_CMD_MARK,
+};
+
+static const unsigned int mmc1_data1_pins[] = {
+	/* D[0] */
+	RCAR_GP_PIN(3, 26),
+};
+static const unsigned int mmc1_data1_mux[] = {
+	MMC1_D0_MARK,
+};
+static const unsigned int mmc1_data4_pins[] = {
+	/* D[0:3] */
+	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
+	RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
+};
+static const unsigned int mmc1_data4_mux[] = {
+	MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
+};
+static const unsigned int mmc1_data8_pins[] = {
+	/* D[0:7] */
+	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
+	RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
+	RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
+	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+};
+static const unsigned int mmc1_data8_mux[] = {
+	MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
+	MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
+};
+static const unsigned int mmc1_ctrl_pins[] = {
+	/* CLK, CMD */
+	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
+};
+static const unsigned int mmc1_ctrl_mux[] = {
+	MMC1_CLK_MARK, MMC1_CMD_MARK,
+};
+
+/* - SDHI ------------------------------------------------------------------- */
+static const unsigned int sdhi0_data1_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(3, 2),
+};
+static const unsigned int sdhi0_data1_mux[] = {
+	SD0_DAT0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+	/* D[0:3] */
+	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+};
+static const unsigned int sdhi0_data4_mux[] = {
+	SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+	/* CLK, CMD */
+	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+	SD0_CLK_MARK, SD0_CMD_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+	/* CD */
+	RCAR_GP_PIN(3, 6),
+};
+static const unsigned int sdhi0_cd_mux[] = {
+	SD0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+	/* WP */
+	RCAR_GP_PIN(3, 7),
+};
+static const unsigned int sdhi0_wp_mux[] = {
+	SD0_WP_MARK,
+};
+
+static const unsigned int sdhi1_data1_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(3, 10),
+};
+static const unsigned int sdhi1_data1_mux[] = {
+	SD1_DAT0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+	/* D[0:3] */
+	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+};
+static const unsigned int sdhi1_data4_mux[] = {
+	SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+	/* CLK, CMD */
+	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+	SD1_CLK_MARK, SD1_CMD_MARK,
+};
+static const unsigned int sdhi1_cd_pins[] = {
+	/* CD */
+	RCAR_GP_PIN(3, 14),
+};
+static const unsigned int sdhi1_cd_mux[] = {
+	SD1_CD_MARK,
+};
+static const unsigned int sdhi1_wp_pins[] = {
+	/* WP */
+	RCAR_GP_PIN(3, 15),
+};
+static const unsigned int sdhi1_wp_mux[] = {
+	SD1_WP_MARK,
+};
+
+static const unsigned int sdhi2_data1_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(3, 18),
+};
+static const unsigned int sdhi2_data1_mux[] = {
+	SD2_DAT0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+	/* D[0:3] */
+	RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+};
+static const unsigned int sdhi2_data4_mux[] = {
+	SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+	/* CLK, CMD */
+	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+	SD2_CLK_MARK, SD2_CMD_MARK,
+};
+static const unsigned int sdhi2_cd_pins[] = {
+	/* CD */
+	RCAR_GP_PIN(3, 22),
+};
+static const unsigned int sdhi2_cd_mux[] = {
+	SD2_CD_MARK,
+};
+static const unsigned int sdhi2_wp_pins[] = {
+	/* WP */
+	RCAR_GP_PIN(3, 23),
+};
+static const unsigned int sdhi2_wp_mux[] = {
+	SD2_WP_MARK,
+};
+
+static const unsigned int sdhi3_data1_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(3, 26),
+};
+static const unsigned int sdhi3_data1_mux[] = {
+	SD3_DAT0_MARK,
+};
+static const unsigned int sdhi3_data4_pins[] = {
+	/* D[0:3] */
+	RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
+};
+static const unsigned int sdhi3_data4_mux[] = {
+	SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
+};
+static const unsigned int sdhi3_ctrl_pins[] = {
+	/* CLK, CMD */
+	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
+};
+static const unsigned int sdhi3_ctrl_mux[] = {
+	SD3_CLK_MARK, SD3_CMD_MARK,
+};
+static const unsigned int sdhi3_cd_pins[] = {
+	/* CD */
+	RCAR_GP_PIN(3, 30),
+};
+static const unsigned int sdhi3_cd_mux[] = {
+	SD3_CD_MARK,
+};
+static const unsigned int sdhi3_wp_pins[] = {
+	/* WP */
+	RCAR_GP_PIN(3, 31),
+};
+static const unsigned int sdhi3_wp_mux[] = {
+	SD3_WP_MARK,
+};
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(eth_link),
 	SH_PFC_PIN_GROUP(eth_magic),
@@ -2449,6 +2663,34 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(tpu0_to1),
 	SH_PFC_PIN_GROUP(tpu0_to2),
 	SH_PFC_PIN_GROUP(tpu0_to3),
+	SH_PFC_PIN_GROUP(mmc0_data1),
+	SH_PFC_PIN_GROUP(mmc0_data4),
+	SH_PFC_PIN_GROUP(mmc0_data8),
+	SH_PFC_PIN_GROUP(mmc0_ctrl),
+	SH_PFC_PIN_GROUP(mmc1_data1),
+	SH_PFC_PIN_GROUP(mmc1_data4),
+	SH_PFC_PIN_GROUP(mmc1_data8),
+	SH_PFC_PIN_GROUP(mmc1_ctrl),
+	SH_PFC_PIN_GROUP(sdhi0_data1),
+	SH_PFC_PIN_GROUP(sdhi0_data4),
+	SH_PFC_PIN_GROUP(sdhi0_ctrl),
+	SH_PFC_PIN_GROUP(sdhi0_cd),
+	SH_PFC_PIN_GROUP(sdhi0_wp),
+	SH_PFC_PIN_GROUP(sdhi1_data1),
+	SH_PFC_PIN_GROUP(sdhi1_data4),
+	SH_PFC_PIN_GROUP(sdhi1_ctrl),
+	SH_PFC_PIN_GROUP(sdhi1_cd),
+	SH_PFC_PIN_GROUP(sdhi1_wp),
+	SH_PFC_PIN_GROUP(sdhi2_data1),
+	SH_PFC_PIN_GROUP(sdhi2_data4),
+	SH_PFC_PIN_GROUP(sdhi2_ctrl),
+	SH_PFC_PIN_GROUP(sdhi2_cd),
+	SH_PFC_PIN_GROUP(sdhi2_wp),
+	SH_PFC_PIN_GROUP(sdhi3_data1),
+	SH_PFC_PIN_GROUP(sdhi3_data4),
+	SH_PFC_PIN_GROUP(sdhi3_ctrl),
+	SH_PFC_PIN_GROUP(sdhi3_cd),
+	SH_PFC_PIN_GROUP(sdhi3_wp),
 };
 
 static const char * const eth_groups[] = {
@@ -2560,6 +2802,52 @@ static const char * const tpu0_groups[] = {
 	"tpu0_to3",
 };
 
+static const char * const mmc0_groups[] = {
+	"mmc0_data1",
+	"mmc0_data4",
+	"mmc0_data8",
+	"mmc0_ctrl",
+};
+
+static const char * const mmc1_groups[] = {
+	"mmc1_data1",
+	"mmc1_data4",
+	"mmc1_data8",
+	"mmc1_ctrl",
+};
+
+static const char * const sdhi0_groups[] = {
+	"sdhi0_data1",
+	"sdhi0_data4",
+	"sdhi0_ctrl",
+	"sdhi0_cd",
+	"sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+	"sdhi1_data1",
+	"sdhi1_data4",
+	"sdhi1_ctrl",
+	"sdhi1_cd",
+	"sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+	"sdhi2_data1",
+	"sdhi2_data4",
+	"sdhi2_ctrl",
+	"sdhi2_cd",
+	"sdhi2_wp",
+};
+
+static const char * const sdhi3_groups[] = {
+	"sdhi3_data1",
+	"sdhi3_data4",
+	"sdhi3_ctrl",
+	"sdhi3_cd",
+	"sdhi3_wp",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(eth),
 	SH_PFC_FUNCTION(intc),
@@ -2572,6 +2860,12 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(scifb1),
 	SH_PFC_FUNCTION(scifb2),
 	SH_PFC_FUNCTION(tpu0),
+	SH_PFC_FUNCTION(mmc0),
+	SH_PFC_FUNCTION(mmc1),
+	SH_PFC_FUNCTION(sdhi0),
+	SH_PFC_FUNCTION(sdhi1),
+	SH_PFC_FUNCTION(sdhi2),
+	SH_PFC_FUNCTION(sdhi3),
 };
 
 static struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
1.8.2.1

[PATCH 123/130] Revert "ARM: shmobile: Disallow PINCTRL without GPIOLIB"

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

GPIOLIB dependency handling was added to the PINCTRL core by

commit 2afe8229687ec24cbc07e78449a588bb8b68f858
Author: Haojian Zhuang <haojian.zhuang@linaro.org>
Date:   Thu Mar 28 07:34:19 2013 +0800

    pinctrl: core: add dependence of GPIOLIB

There is not need to handle that dependency at the SH Mobile level
anymore. Revert

commit 6722f6cb763203cab775297b6e9d00834af0d6d7
Author: Magnus Damm <damm@opensource.se>
Date:   Mon Mar 18 22:58:18 2013 +0900

    ARM: shmobile: Disallow PINCTRL without GPIOLIB

    Modify mach-shmobile to only select PINCTRL in case of
    ARCH_WANT_OPTIONAL_GPIOLIB is set.

    This fixes a build error triggered when adding a new SoC
    lacking GPIO software support (ARCH_WANT_OPTIONAL_GPIOLIB=n):

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 49d993c..dfb4fee 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -645,7 +645,7 @@ config ARCH_SHMOBILE
 	select MULTI_IRQ_HANDLER
 	select NEED_MACH_MEMORY_H
 	select NO_IOPORT
-	select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
+	select PINCTRL
 	select PM_GENERIC_DOMAINS if PM
 	select SPARSE_IRQ
 	help
-- 
1.8.2.1

[PATCH 124/130] pinctrl: sh-pfc: r8a7779: Fix missing MOD_SEL2 entry

[Simon Horman]

From: Phil Edworthy <phil.edworthy@renesas.com>

The list of functions selected by the MOD_SEL2 register was missing
an entry. This caused all entries after this to modify the MOD_SEL2
register incorrectly.

This bug showed up when selecting i2c2_c pins on the Renesas Hurricane board.

This bug has been present since pinmux support was added for the
r8a7779 SoC by 881023d28b465eb457067dc8bbca0f24d8b34279 ("sh-pfc: Add
r8a7779 pinmux support") in v3.8-rc4.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7779.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 96bdf48..8e22ca6 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -3768,7 +3768,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 	    /* SEL_SCIF [2] */
 	    FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
 	    /* SEL_CANCLK [2] */
-	    FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
+	    FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 0,
 	    /* SEL_CAN0 [1] */
 	    FN_SEL_CAN0_0, FN_SEL_CAN0_1,
 	    /* SEL_HSCIF1 [1] */
-- 
1.8.2.1

[PATCH 125/130] ARM: shmobile: r8a7790: Configure R-Car GPIO for IRQ_TYPE_EDGE_BOTH

[Simon Horman]

"gpio-rcar: Support IRQ_TYPE_EDGE_BOTH" adds support to the R-Car GPIO
driver for IRQ_TYPE_EDGE_BOTH. As hardware support for this feature is
not universal for all SoCs a flag, has_both_edge_trigger, has been
added to the platform data of the driver to allow this feature to be
enabled.

As the r8a7790 SoC hardware supports this feature enable it.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/setup-r8a7790.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index eeef5f6..b461d93 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -45,6 +45,7 @@ static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data = {	\
 	.irq_base	= 0,						\
 	.number_of_pins	= 32,						\
 	.pctl_name	= "pfc-r8a7790",				\
+	.has_both_edge_trigger = 1,					\
 };									\
 
 R8A7790_GPIO(0);
-- 
1.8.2.1

[PATCH 126/130] ARM: shmobile: r8a7740 pinmux platform device cleanup

[Simon Horman]

From: Magnus Damm <damm@opensource.se>

Use DEFINE_RES_MEM() and platform_device_register_simple()
to save a couple of lines of code.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/setup-r8a7740.c | 24 +++++-------------------
 1 file changed, 5 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 326a4ab..3a6b6fe 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -70,29 +70,15 @@ void __init r8a7740_map_io(void)
 }
 
 /* PFC */
-static struct resource r8a7740_pfc_resources[] = {
-	[0] = {
-		.start	= 0xe6050000,
-		.end	= 0xe6057fff,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= 0xe605800c,
-		.end	= 0xe605802b,
-		.flags	= IORESOURCE_MEM,
-	}
-};
-
-static struct platform_device r8a7740_pfc_device = {
-	.name		= "pfc-r8a7740",
-	.id		= -1,
-	.resource	= r8a7740_pfc_resources,
-	.num_resources	= ARRAY_SIZE(r8a7740_pfc_resources),
+static const struct resource pfc_resources[] = {
+	DEFINE_RES_MEM(0xe6050000, 0x8000),
+	DEFINE_RES_MEM(0xe605800c, 0x0020),
 };
 
 void __init r8a7740_pinmux_init(void)
 {
-	platform_device_register(&r8a7740_pfc_device);
+	platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
+					ARRAY_SIZE(pfc_resources));
 }
 
 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
-- 
1.8.2.1

[PATCH 127/130] ARM: shmobile: kzm9g: tidyup FSI pinctrl

[Simon Horman]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

sh73a0 needs "sh_fsi2", not "sh_fsi2.0"

Tested-by: Hiep Cao Minh <cm-hiep@jinso.co.jp>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-kzm9g.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index fc4ca9b..1fdf05c 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -663,13 +663,13 @@ static unsigned long pin_pullup_conf[] = {
 
 static const struct pinctrl_map kzm_pinctrl_map[] = {
 	/* FSIA (AK4648) */
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
 				  "fsia_mclk_in", "fsia"),
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
 				  "fsia_sclk_in", "fsia"),
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
 				  "fsia_data_in", "fsia"),
-	PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+	PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
 				  "fsia_data_out", "fsia"),
 	/* I2C3 */
 	PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
-- 
1.8.2.1

[PATCH 128/130] ARM: shmobile: bockw: add pinctrl support

[Simon Horman]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

SCIF0 support as 1st step

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-bockw.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index 38e5e50..dac4365 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -18,6 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
 #include <linux/smsc911x.h>
 #include <mach/common.h>
@@ -37,6 +38,14 @@ static struct resource smsc911x_resources[] = {
 	DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
 };
 
+static const struct pinctrl_map bockw_pinctrl_map[] = {
+	/* SCIF0 */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
+				  "scif0_data_a", "scif0"),
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
+				  "scif0_ctrl", "scif0"),
+};
+
 #define IRQ0MR	0x30
 static void __init bockw_init(void)
 {
@@ -46,6 +55,10 @@ static void __init bockw_init(void)
 	r8a7778_init_irq_extpin(1);
 	r8a7778_add_standard_devices();
 
+	pinctrl_register_mappings(bockw_pinctrl_map,
+				  ARRAY_SIZE(bockw_pinctrl_map));
+	r8a7778_pinmux_init();
+
 	fpga = ioremap_nocache(0x18200000, SZ_1M);
 	if (fpga) {
 		/*
-- 
1.8.2.1

[PATCH 129/130] ARM: shmobile: lager: Initialize pinmux

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Initialize r8a7790 pinmuxing and register mappings for the two debug
serial ports.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-lager.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index f587187..6114edd 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -21,15 +21,30 @@
 #include <linux/interrupt.h>
 #include <linux/irqchip.h>
 #include <linux/kernel.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
 #include <mach/common.h>
 #include <mach/r8a7790.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+static const struct pinctrl_map lager_pinctrl_map[] = {
+	/* SCIF0 (CN19: DEBUG SERIAL0) */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
+				  "scif0_data", "scif0"),
+	/* SCIF1 (CN20: DEBUG SERIAL1) */
+	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
+				  "scif1_data", "scif1"),
+};
+
 static void __init lager_add_standard_devices(void)
 {
 	r8a7790_clock_init();
+
+	pinctrl_register_mappings(lager_pinctrl_map,
+				  ARRAY_SIZE(lager_pinctrl_map));
+	r8a7790_pinmux_init();
+
 	r8a7790_add_standard_devices();
 }
 
-- 
1.8.2.1

[PATCH 130/130] ARM: shmobile: marzen: Use RCAR_GP_PIN macro

[Simon Horman]

From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Replace hardcoded pin numbers with the RCAR_GP_PIN macro to make the
code match the documentation.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/board-marzen.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 9105285..fac9e0f 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -28,6 +28,7 @@
 #include <linux/leds.h>
 #include <linux/dma-mapping.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
@@ -173,15 +174,15 @@ static struct platform_device usb_phy_device = {
 static struct gpio_led marzen_leds[] = {
 	{
 		.name		= "led2",
-		.gpio		= 157,
+		.gpio		= RCAR_GP_PIN(4, 29),
 		.default_state	= LEDS_GPIO_DEFSTATE_ON,
 	}, {
 		.name		= "led3",
-		.gpio		= 158,
+		.gpio		= RCAR_GP_PIN(4, 30),
 		.default_state	= LEDS_GPIO_DEFSTATE_ON,
 	}, {
 		.name		= "led4",
-		.gpio		= 159,
+		.gpio		= RCAR_GP_PIN(4, 31),
 		.default_state	= LEDS_GPIO_DEFSTATE_ON,
 	},
 };
-- 
1.8.2.1

Re: [GIT PULL 000/130] Renesas ARM based SoC pinmux and GPIO update for

[Olof Johansson]

On Wed, Jun 05, 2013 at 05:24:51PM +0900, Simon Horman wrote:
> Hi Olof, Hi Arnd,
> 
> Please note that this pull-request is based on renesas-fixes-for-v3.10
> in order to avoid a messy conflict.

Thanks for doing that. It's quite common that platform maintainers forget to
deal with conflicts due to fixes, which can sometimes be a bit annoying. :-)


> The following changes since commit 5600a8485603b240790005b9b58de4c4f6ada69d:
> 
>   ARM: shmobile: sh73a0: Update CMT clockevent rating to 80 (2013-06-04 14:37:53 +0900)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-pinmux-for-v3.11

Pulled into next/drivers. Thanks!


-Olof