[PATCH 2/5] ARM: shmobile: r8a7790: Add DU and LVDS clocks

[PATCH 2/5] ARM: shmobile: r8a7790: Add DU and LVDS clocks

[Laurent Pinchart]

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 arch/arm/mach-shmobile/clock-r8a7790.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index fc36d3d..d99b87b 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -182,7 +182,7 @@ static struct clk div6_clks[DIV6_NR] = {
 /* MSTP */
 enum {
 	MSTP813,
-	MSTP721, MSTP720,
+	MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
 	MSTP717, MSTP716,
 	MSTP522,
 	MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
@@ -193,6 +193,11 @@ enum {
 
 static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
+	[MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
+	[MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */
+	[MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
+	[MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */
+	[MSTP722] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 22, 0), /* DU2 */
 	[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
 	[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
 	[MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
@@ -251,6 +256,11 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_CON_ID("ssprs",		&div6_clks[DIV6_SSPRS]),
 
 	/* MSTP */
+	CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
+	CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
+	CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
+	CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
+	CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
 	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
 	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
 	CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
-- 
1.8.1.5

[PATCH 2/5] arm: shmobile: r8a7790: Add SATA clock

[Valentine Barshak]

This adds SATA 0/1 clock support. External 100MHz SATA 0/1
reference clock is supposed to be applied to the following pins:
  CICREFP0_SATA/CICREFP1_SATA;
  CICREFN0_SATA/CICREFN1_SATA.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
---
 arch/arm/mach-shmobile/clock-r8a7790.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 3e27200..c4b567b 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -73,6 +73,18 @@ static struct clk extal_clk = {
 	.mapping	= &cpg_mapping,
 };
 
+/* External SATA0 reference clock: 100MHz fixed */
+static struct clk sata0_clk = {
+	.rate		= 100000000,
+	.mapping	= &cpg_mapping,
+};
+
+/* External SATA1 reference clock: 100MHz fixed */
+static struct clk sata1_clk = {
+	.rate		= 100000000,
+	.mapping	= &cpg_mapping,
+};
+
 static struct sh_clk_ops followparent_clk_ops = {
 	.recalc	= followparent_recalc,
 };
@@ -140,6 +152,8 @@ static struct clk *main_clks[] = {
 	&ddr_clk,
 	&mp_clk,
 	&cp_clk,
+	&sata0_clk,
+	&sata1_clk,
 };
 
 /* SDHI (DIV4) clock */
@@ -187,6 +201,7 @@ enum {
 	MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
 	MSTP931, MSTP930, MSTP929, MSTP928,
 	MSTP917,
+	MSTP815, MSTP814,
 	MSTP813,
 	MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
 	MSTP717, MSTP716,
@@ -215,6 +230,8 @@ static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP929] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 29, 0), /* I2C2 */
 	[MSTP928] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 28, 0), /* I2C3 */
 	[MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */
+	[MSTP815] = SH_CLK_MSTP32(&sata0_clk, SMSTPCR8, 15, 0), /* SATA0 */
+	[MSTP814] = SH_CLK_MSTP32(&sata1_clk, SMSTPCR8, 14, 0),	/* SATA1 */
 	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
 	[MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
 	[MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */
@@ -321,6 +338,8 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),
 	CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]),
 	CLKDEV_DEV_ID("pci-rcar-gen2.2", &mstp_clks[MSTP703]),
+	CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),
+	CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),
 
 	/* ICK */
 	CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
-- 
1.8.3.1

Re: [PATCH 2/5] arm: shmobile: r8a7790: Add SATA clock

[Laurent Pinchart]

Hi Valentine,

Thank you for the patch.

On Wednesday 18 December 2013 16:44:17 Valentine Barshak wrote:
> This adds SATA 0/1 clock support. External 100MHz SATA 0/1
> reference clock is supposed to be applied to the following pins:
>   CICREFP0_SATA/CICREFP1_SATA;
>   CICREFN0_SATA/CICREFN1_SATA.
> 
> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
> ---
>  arch/arm/mach-shmobile/clock-r8a7790.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c
> b/arch/arm/mach-shmobile/clock-r8a7790.c index 3e27200..c4b567b 100644
> --- a/arch/arm/mach-shmobile/clock-r8a7790.c
> +++ b/arch/arm/mach-shmobile/clock-r8a7790.c
> @@ -73,6 +73,18 @@ static struct clk extal_clk = {
>  	.mapping	= &cpg_mapping,
>  };
> 
> +/* External SATA0 reference clock: 100MHz fixed */
> +static struct clk sata0_clk = {
> +	.rate		= 100000000,
> +	.mapping	= &cpg_mapping,
> +};
> +
> +/* External SATA1 reference clock: 100MHz fixed */
> +static struct clk sata1_clk = {
> +	.rate		= 100000000,
> +	.mapping	= &cpg_mapping,
> +};
> +
>  static struct sh_clk_ops followparent_clk_ops = {
>  	.recalc	= followparent_recalc,
>  };
> @@ -140,6 +152,8 @@ static struct clk *main_clks[] = {
>  	&ddr_clk,
>  	&mp_clk,
>  	&cp_clk,
> +	&sata0_clk,
> +	&sata1_clk,
>  };
> 
>  /* SDHI (DIV4) clock */
> @@ -187,6 +201,7 @@ enum {
>  	MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
>  	MSTP931, MSTP930, MSTP929, MSTP928,
>  	MSTP917,
> +	MSTP815, MSTP814,
>  	MSTP813,
>  	MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
>  	MSTP717, MSTP716,
> @@ -215,6 +230,8 @@ static struct clk mstp_clks[MSTP_NR] = {
>  	[MSTP929] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 29, 0), /* I2C2 */
>  	[MSTP928] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 28, 0), /* I2C3 */
>  	[MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */
> +	[MSTP815] = SH_CLK_MSTP32(&sata0_clk, SMSTPCR8, 15, 0), /* SATA0 */
> +	[MSTP814] = SH_CLK_MSTP32(&sata1_clk, SMSTPCR8, 14, 0),	/* SATA1 */

Are those two clocks really children of the external reference clocks ? I got 
the impression that the external reference clocks would be used by the PHY 
only and that the functional clocks for the SATA controllers would be children 
of an internal clock generated by the CPG. Morimoto-san, do you have any 
information about this ?

>  	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
>  	[MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
>  	[MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */
> @@ -321,6 +338,8 @@ static struct clk_lookup lookups[] = {
>  	CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),
>  	CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]),
>  	CLKDEV_DEV_ID("pci-rcar-gen2.2", &mstp_clks[MSTP703]),
> +	CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),
> +	CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),
> 
>  	/* ICK */
>  	CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
-- 
Regards,

Laurent Pinchart

Re: [PATCH 2/5] arm: shmobile: r8a7790: Add SATA clock

[Valentine]

On 12/18/2013 06:19 PM, Laurent Pinchart wrote:
> Hi Valentine,

Hi Laurent, Morimoto-san,

>
> Thank you for the patch.
>
> On Wednesday 18 December 2013 16:44:17 Valentine Barshak wrote:
>> This adds SATA 0/1 clock support. External 100MHz SATA 0/1
>> reference clock is supposed to be applied to the following pins:
>>    CICREFP0_SATA/CICREFP1_SATA;
>>    CICREFN0_SATA/CICREFN1_SATA.
>>
>> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
>> ---
>>   arch/arm/mach-shmobile/clock-r8a7790.c | 19 +++++++++++++++++++
>>   1 file changed, 19 insertions(+)
>>
>> diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c
>> b/arch/arm/mach-shmobile/clock-r8a7790.c index 3e27200..c4b567b 100644
>> --- a/arch/arm/mach-shmobile/clock-r8a7790.c
>> +++ b/arch/arm/mach-shmobile/clock-r8a7790.c
>> @@ -73,6 +73,18 @@ static struct clk extal_clk = {
>>   	.mapping	= &cpg_mapping,
>>   };
>>
>> +/* External SATA0 reference clock: 100MHz fixed */
>> +static struct clk sata0_clk = {
>> +	.rate		= 100000000,
>> +	.mapping	= &cpg_mapping,
>> +};
>> +
>> +/* External SATA1 reference clock: 100MHz fixed */
>> +static struct clk sata1_clk = {
>> +	.rate		= 100000000,
>> +	.mapping	= &cpg_mapping,
>> +};
>> +
>>   static struct sh_clk_ops followparent_clk_ops = {
>>   	.recalc	= followparent_recalc,
>>   };
>> @@ -140,6 +152,8 @@ static struct clk *main_clks[] = {
>>   	&ddr_clk,
>>   	&mp_clk,
>>   	&cp_clk,
>> +	&sata0_clk,
>> +	&sata1_clk,
>>   };
>>
>>   /* SDHI (DIV4) clock */
>> @@ -187,6 +201,7 @@ enum {
>>   	MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
>>   	MSTP931, MSTP930, MSTP929, MSTP928,
>>   	MSTP917,
>> +	MSTP815, MSTP814,
>>   	MSTP813,
>>   	MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
>>   	MSTP717, MSTP716,
>> @@ -215,6 +230,8 @@ static struct clk mstp_clks[MSTP_NR] = {
>>   	[MSTP929] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 29, 0), /* I2C2 */
>>   	[MSTP928] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 28, 0), /* I2C3 */
>>   	[MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */
>> +	[MSTP815] = SH_CLK_MSTP32(&sata0_clk, SMSTPCR8, 15, 0), /* SATA0 */
>> +	[MSTP814] = SH_CLK_MSTP32(&sata1_clk, SMSTPCR8, 14, 0),	/* SATA1 */
>
> Are those two clocks really children of the external reference clocks ? I got
> the impression that the external reference clocks would be used by the PHY
> only and that the functional clocks for the SATA controllers would be children
> of an internal clock generated by the CPG. Morimoto-san, do you have any
> information about this ?

If understand the h/w manual correctly, the external clock is connected directly to the SATA module:

"Pin Name: CICREFP0_SATA CICREFN0_SATA CICREFP1_SATA CICREFN1_SATA
Description: Reference clock input to the PLL circuit in the Serial-ATA module (differential input).
Apply a 100-MHz clock."

Morimoto-san, could you confirm, please?

>
>>   	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
>>   	[MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
>>   	[MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */
>> @@ -321,6 +338,8 @@ static struct clk_lookup lookups[] = {
>>   	CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),
>>   	CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]),
>>   	CLKDEV_DEV_ID("pci-rcar-gen2.2", &mstp_clks[MSTP703]),
>> +	CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),
>> +	CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),
>>
>>   	/* ICK */
>>   	CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),

Thanks,
Val.

Re: [PATCH 2/5] arm: shmobile: r8a7790: Add SATA clock

[Laurent Pinchart]

Hi Valentine,

On Thursday 19 December 2013 05:00:03 Valentine wrote:
> On 12/18/2013 06:19 PM, Laurent Pinchart wrote:
> > Hi Valentine,
> 
> Hi Laurent, Morimoto-san,
> 
> > Thank you for the patch.
> > 
> > On Wednesday 18 December 2013 16:44:17 Valentine Barshak wrote:
> >> This adds SATA 0/1 clock support. External 100MHz SATA 0/1
> >> 
> >> reference clock is supposed to be applied to the following pins:
> >>    CICREFP0_SATA/CICREFP1_SATA;
> >>    CICREFN0_SATA/CICREFN1_SATA.
> >> 
> >> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
> >> ---
> >> 
> >>   arch/arm/mach-shmobile/clock-r8a7790.c | 19 +++++++++++++++++++
> >>   1 file changed, 19 insertions(+)
> >> 
> >> diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c
> >> b/arch/arm/mach-shmobile/clock-r8a7790.c index 3e27200..c4b567b 100644
> >> --- a/arch/arm/mach-shmobile/clock-r8a7790.c
> >> +++ b/arch/arm/mach-shmobile/clock-r8a7790.c
> >> @@ -73,6 +73,18 @@ static struct clk extal_clk = {
> >>   	.mapping	= &cpg_mapping,
> >>   };
> >> 
> >> +/* External SATA0 reference clock: 100MHz fixed */
> >> +static struct clk sata0_clk = {
> >> +	.rate		= 100000000,
> >> +	.mapping	= &cpg_mapping,
> >> +};
> >> +
> >> +/* External SATA1 reference clock: 100MHz fixed */
> >> +static struct clk sata1_clk = {
> >> +	.rate		= 100000000,
> >> +	.mapping	= &cpg_mapping,
> >> +};
> >> +
> >>   static struct sh_clk_ops followparent_clk_ops = {
> >>   	.recalc	= followparent_recalc,
> >>   };
> >> @@ -140,6 +152,8 @@ static struct clk *main_clks[] = {
> >>   	&ddr_clk,
> >>   	&mp_clk,
> >>   	&cp_clk,
> >> +	&sata0_clk,
> >> +	&sata1_clk,
> >>   };
> >>   
> >>   /* SDHI (DIV4) clock */
> >> @@ -187,6 +201,7 @@ enum {
> >>   	MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
> >>   	MSTP931, MSTP930, MSTP929, MSTP928,
> >>   	MSTP917,
> >> +	MSTP815, MSTP814,
> >>   	MSTP813,
> >>   	MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
> >>   	MSTP717, MSTP716,
> >> @@ -215,6 +230,8 @@ static struct clk mstp_clks[MSTP_NR] = {
> >>   	[MSTP929] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 29, 0), /* I2C2 */
> >>   	[MSTP928] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 28, 0), /* I2C3 */
> >>   	[MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */
> >> +	[MSTP815] = SH_CLK_MSTP32(&sata0_clk, SMSTPCR8, 15, 0), /* SATA0 */
> >> +	[MSTP814] = SH_CLK_MSTP32(&sata1_clk, SMSTPCR8, 14, 0), /* SATA1 */
> > 
> > Are those two clocks really children of the external reference clocks ? I
> > got the impression that the external reference clocks would be used by
> > the PHY only and that the functional clocks for the SATA controllers
> > would be children of an internal clock generated by the CPG.
> > Morimoto-san, do you have any information about this ?
> 
> If understand the h/w manual correctly, the external clock is connected
> directly to the SATA module:
> 
> "Pin Name: CICREFP0_SATA CICREFN0_SATA CICREFP1_SATA CICREFN1_SATA
> Description: Reference clock input to the PLL circuit in the Serial-ATA
> module (differential input). Apply a 100-MHz clock."

That's my understanding as well, but I suspect that clock to be the PHY clock 
only, not the SATA module functional clock.

> Morimoto-san, could you confirm, please?
> 
> >>   	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
> >>   	[MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
> >>   	[MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */
> >> @@ -321,6 +338,8 @@ static struct clk_lookup lookups[] = {
> >>   	CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),
> >>   	CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]),
> >>   	CLKDEV_DEV_ID("pci-rcar-gen2.2", &mstp_clks[MSTP703]),
> >> +	CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),
> >> +	CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),
> >> 
> >>   	/* ICK */
> >>   	CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),

-- 
Regards,

Laurent Pinchart

Re: [PATCH 2/5] arm: shmobile: r8a7790: Add SATA clock

[Kuninori Morimoto]

Hi Valentine, Laurent
Cc Magnus

> > > On Wednesday 18 December 2013 16:44:17 Valentine Barshak wrote:
> > >> This adds SATA 0/1 clock support. External 100MHz SATA 0/1
> > >> 
> > >> reference clock is supposed to be applied to the following pins:
> > >>    CICREFP0_SATA/CICREFP1_SATA;
> > >>    CICREFN0_SATA/CICREFN1_SATA.
> > >> 
> > >> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
> > >> ---
(snip)
> > If understand the h/w manual correctly, the external clock is connected
> > directly to the SATA module:
> > 
> > "Pin Name: CICREFP0_SATA CICREFN0_SATA CICREFP1_SATA CICREFN1_SATA
> > Description: Reference clock input to the PLL circuit in the Serial-ATA
> > module (differential input). Apply a 100-MHz clock."
> 
> That's my understanding as well, but I suspect that clock to be the PHY clock 
> only, not the SATA module functional clock.

I have same opinion with Laurent.

But I'm not sure detail of module parent clock,
since R-Car series datasheet seems doesn't have module clock relationship map.
# SH-mobile series had "Clock Assignment to Modules" in datasheet.

I will ask this to HW people, but maybe p_clk is fine here.

If you need to control CICREFN1_SATAx clocks,
it should be defined as CLKDEV_ICK_ID() and use clk_xx() function

But, hmm...
Current some clock-r8a7790 MSTP clocks have strange parent...


Best regards
---
Kuninori Morimoto

Re: [PATCH 2/5] arm: shmobile: r8a7790: Add SATA clock

[Valentine]

On 12/19/2013 08:58 AM, Kuninori Morimoto wrote:
>
> Hi Valentine, Laurent
> Cc Magnus
>
>>>> On Wednesday 18 December 2013 16:44:17 Valentine Barshak wrote:
>>>>> This adds SATA 0/1 clock support. External 100MHz SATA 0/1
>>>>>
>>>>> reference clock is supposed to be applied to the following pins:
>>>>>     CICREFP0_SATA/CICREFP1_SATA;
>>>>>     CICREFN0_SATA/CICREFN1_SATA.
>>>>>
>>>>> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
>>>>> ---
> (snip)
>>> If understand the h/w manual correctly, the external clock is connected
>>> directly to the SATA module:
>>>
>>> "Pin Name: CICREFP0_SATA CICREFN0_SATA CICREFP1_SATA CICREFN1_SATA
>>> Description: Reference clock input to the PLL circuit in the Serial-ATA
>>> module (differential input). Apply a 100-MHz clock."
>>
>> That's my understanding as well, but I suspect that clock to be the PHY clock
>> only, not the SATA module functional clock.
>
> I have same opinion with Laurent.
>
> But I'm not sure detail of module parent clock,
> since R-Car series datasheet seems doesn't have module clock relationship map.
> # SH-mobile series had "Clock Assignment to Modules" in datasheet.
>
> I will ask this to HW people, but maybe p_clk is fine here.

Morimoto-san,
is there any news?

It says "PLL in the Serial-ATA module" not the "Serial-ATA phy", but without the clock map it's hard to say.

>
> If you need to control CICREFN1_SATAx clocks,
> it should be defined as CLKDEV_ICK_ID() and use clk_xx() function

If MSTP814/MSTP815 controls the internal SATA clocks, then I'm not sure how to control the external CICREF[PN][01]_SATA ones.

>
> But, hmm...
> Current some clock-r8a7790 MSTP clocks have strange parent...
>
>
> Best regards
> ---
> Kuninori Morimoto
>

Thanks,
Val.

Re: [PATCH 2/5] arm: shmobile: r8a7790: Add SATA clock

[Laurent Pinchart]

Hi Valentine,

On Tuesday 24 December 2013 01:24:14 Valentine wrote:
> On 12/19/2013 08:58 AM, Kuninori Morimoto wrote:
> > Hi Valentine, Laurent
> > Cc Magnus
> > 
> >>>> On Wednesday 18 December 2013 16:44:17 Valentine Barshak wrote:
> >>>>> This adds SATA 0/1 clock support. External 100MHz SATA 0/1
> >>>>> 
> >>>>> reference clock is supposed to be applied to the following pins:
> >>>>>     CICREFP0_SATA/CICREFP1_SATA;
> >>>>>     CICREFN0_SATA/CICREFN1_SATA.
> >>>>> 
> >>>>> Signed-off-by: Valentine Barshak
> >>>>> <valentine.barshak@cogentembedded.com>
> >>>>> ---
> > 
> > (snip)
> > 
> >>> If understand the h/w manual correctly, the external clock is connected
> >>> directly to the SATA module:
> >>> 
> >>> "Pin Name: CICREFP0_SATA CICREFN0_SATA CICREFP1_SATA CICREFN1_SATA
> >>> Description: Reference clock input to the PLL circuit in the Serial-ATA
> >>> module (differential input). Apply a 100-MHz clock."
> >> 
> >> That's my understanding as well, but I suspect that clock to be the PHY
> >> clock only, not the SATA module functional clock.
> > 
> > I have same opinion with Laurent.
> > 
> > But I'm not sure detail of module parent clock,
> > since R-Car series datasheet seems doesn't have module clock relationship
> > map. # SH-mobile series had "Clock Assignment to Modules" in datasheet.
> > 
> > I will ask this to HW people, but maybe p_clk is fine here.
> 
> Morimoto-san,
> is there any news?
> 
> It says "PLL in the Serial-ATA module" not the "Serial-ATA phy", but without
> the clock map it's hard to say.
>
> > If you need to control CICREFN1_SATAx clocks,
> > it should be defined as CLKDEV_ICK_ID() and use clk_xx() function
> 
> If MSTP814/MSTP815 controls the internal SATA clocks, then I'm not sure how
> to control the external CICREF[PN][01]_SATA ones.

If my guess is correct the CICREF[PN][01]_SATA clock doesn't need to be 
controlled.

> > But, hmm...
> > Current some clock-r8a7790 MSTP clocks have strange parent...

-- 
Regards,

Laurent Pinchart

Re: [PATCH 2/5] arm: shmobile: r8a7790: Add SATA clock

[Valentine]

On 12/26/2013 06:16 PM, Laurent Pinchart wrote:
> Hi Valentine,
>
> On Tuesday 24 December 2013 01:24:14 Valentine wrote:
>> On 12/19/2013 08:58 AM, Kuninori Morimoto wrote:
>>> Hi Valentine, Laurent
>>> Cc Magnus
>>>
>>>>>> On Wednesday 18 December 2013 16:44:17 Valentine Barshak wrote:
>>>>>>> This adds SATA 0/1 clock support. External 100MHz SATA 0/1
>>>>>>>
>>>>>>> reference clock is supposed to be applied to the following pins:
>>>>>>>      CICREFP0_SATA/CICREFP1_SATA;
>>>>>>>      CICREFN0_SATA/CICREFN1_SATA.
>>>>>>>
>>>>>>> Signed-off-by: Valentine Barshak
>>>>>>> <valentine.barshak@cogentembedded.com>
>>>>>>> ---
>>>
>>> (snip)
>>>
>>>>> If understand the h/w manual correctly, the external clock is connected
>>>>> directly to the SATA module:
>>>>>
>>>>> "Pin Name: CICREFP0_SATA CICREFN0_SATA CICREFP1_SATA CICREFN1_SATA
>>>>> Description: Reference clock input to the PLL circuit in the Serial-ATA
>>>>> module (differential input). Apply a 100-MHz clock."
>>>>
>>>> That's my understanding as well, but I suspect that clock to be the PHY
>>>> clock only, not the SATA module functional clock.
>>>
>>> I have same opinion with Laurent.
>>>
>>> But I'm not sure detail of module parent clock,
>>> since R-Car series datasheet seems doesn't have module clock relationship
>>> map. # SH-mobile series had "Clock Assignment to Modules" in datasheet.
>>>
>>> I will ask this to HW people, but maybe p_clk is fine here.
>>
>> Morimoto-san,
>> is there any news?
>>
>> It says "PLL in the Serial-ATA module" not the "Serial-ATA phy", but without
>> the clock map it's hard to say.
>>
>>> If you need to control CICREFN1_SATAx clocks,
>>> it should be defined as CLKDEV_ICK_ID() and use clk_xx() function
>>
>> If MSTP814/MSTP815 controls the internal SATA clocks, then I'm not sure how
>> to control the external CICREF[PN][01]_SATA ones.
>
> If my guess is correct the CICREF[PN][01]_SATA clock doesn't need to be
> controlled.

I agree. Still the question remains whether it's OK to use p_clk here.

>
>>> But, hmm...
>>> Current some clock-r8a7790 MSTP clocks have strange parent...
>

Thanks,
Val.

Re: [PATCH 2/5] arm: shmobile: r8a7790: Add SATA clock

[Kuninori Morimoto]

Hi Valentine

Happy new year, and sorry for my late response

> >>> I will ask this to HW people, but maybe p_clk is fine here.
> >>
> >> Morimoto-san,
> >> is there any news?
> >>
> >> It says "PLL in the Serial-ATA module" not the "Serial-ATA phy", but without
> >> the clock map it's hard to say.
> >>
> >>> If you need to control CICREFN1_SATAx clocks,
> >>> it should be defined as CLKDEV_ICK_ID() and use clk_xx() function
> >>
> >> If MSTP814/MSTP815 controls the internal SATA clocks, then I'm not sure how
> >> to control the external CICREF[PN][01]_SATA ones.
> >
> > If my guess is correct the CICREF[PN][01]_SATA clock doesn't need to be
> > controlled.
> 
> I agree. Still the question remains whether it's OK to use p_clk here.

According to HW guys, parent clock of SATA module is zs_clk.

Best regards
---
Kuninori Morimoto

Re: [PATCH 2/5] arm: shmobile: r8a7790: Add SATA clock

[Valentine]

On 01/06/2014 05:25 AM, Kuninori Morimoto wrote:
>
> Hi Valentine
>
> Happy new year, and sorry for my late response

Thanks! No problem, hope you had great holidays!

>
>>>>> I will ask this to HW people, but maybe p_clk is fine here.
>>>>
>>>> Morimoto-san,
>>>> is there any news?
>>>>
>>>> It says "PLL in the Serial-ATA module" not the "Serial-ATA phy", but without
>>>> the clock map it's hard to say.
>>>>
>>>>> If you need to control CICREFN1_SATAx clocks,
>>>>> it should be defined as CLKDEV_ICK_ID() and use clk_xx() function
>>>>
>>>> If MSTP814/MSTP815 controls the internal SATA clocks, then I'm not sure how
>>>> to control the external CICREF[PN][01]_SATA ones.
>>>
>>> If my guess is correct the CICREF[PN][01]_SATA clock doesn't need to be
>>> controlled.
>>
>> I agree. Still the question remains whether it's OK to use p_clk here.
>
> According to HW guys, parent clock of SATA module is zs_clk.

Thanks!
I'll resend with series with the clocks updated.

>
> Best regards
> ---
> Kuninori Morimoto
>

Thanks,
Val.

Re: [PATCH 2/5] arm: shmobile: r8a7790: Add SATA clock

[Kuninori Morimoto]

Hi Valentine

> > Happy new year, and sorry for my late response
> 
> Thanks! No problem, hope you had great holidays!

Thank you :)

> > According to HW guys, parent clock of SATA module is zs_clk.
> 
> Thanks!
> I'll resend with series with the clocks updated.

Thanks

Best regards
---
Kuninori Morimoto

[PATCH 2/5] ARM: shmobile: r8a7790: add dmac0 dmac1 nodes

[Ben Dooks]

---
 arch/arm/boot/dts/r8a7790.dtsi | 89 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 89 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 700e0a1..ae65270 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -8,6 +8,7 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/dma/shdma.h>
 #include <dt-bindings/clock/r8a7790-clock.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -79,6 +80,94 @@
 		};
 	};
 
+#define CHCR_RX_32BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_32BIT)
+#define CHCR_TX_32BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_32BIT)
+#define CHCR_RX_256BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_256BIT)
+#define CHCR_TX_256BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_256BIT)
+
+	dma0: dma-mux@0 {
+		compatible = "renesas,shdma-mux";
+		#dma-cells = <1>;
+		dma-channels = <20>;
+                dma-requests = <256>;
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+		renesas,slaves = <0xce CHCR_RX_32BIT  0xee102060>,
+				<0xcd CHCR_TX_32BIT  0xee100060>,
+				<0xca CHCR_RX_256BIT 0xee122060>,
+				<0xc9 CHCR_TX_256BIT 0xee120060>,
+				<0xc2 CHCR_RX_256BIT 0xee142030>,
+				<0xc1 CHCR_TX_256BIT 0xee140030>,
+				<0xd2 CHCR_RX_32BIT  0xee200034>,
+				<0xd1 CHCR_TX_32BIT  0xee200034>,
+				<0xe2 CHCR_RX_32BIT  0xee220034>,
+				<0xe1 CHCR_TX_32BIT  0xee220034>;
+
+		sysdma0: dmac@e6700000 {
+			compatible = "renesas,dma-r8a7790", "renesas,dma-arm";
+			clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
+			dma-channels = <15>;
+			status = "disabled";
+			reg = <0 0xe6700020 0 0xffc0>;
+			interrupt-parent = <&gic>;
+
+			interrupts =	<0 197 IRQ_TYPE_LEVEL_HIGH>, /* error */
+					<0 200 IRQ_TYPE_LEVEL_HIGH>, /* ch0 */
+					<0 201 IRQ_TYPE_LEVEL_HIGH>,
+					<0 202 IRQ_TYPE_LEVEL_HIGH>,
+					<0 203 IRQ_TYPE_LEVEL_HIGH>,
+					<0 204 IRQ_TYPE_LEVEL_HIGH>,
+					<0 205 IRQ_TYPE_LEVEL_HIGH>,
+					<0 206 IRQ_TYPE_LEVEL_HIGH>,
+					<0 207 IRQ_TYPE_LEVEL_HIGH>,
+					<0 208 IRQ_TYPE_LEVEL_HIGH>,
+					<0 209 IRQ_TYPE_LEVEL_HIGH>,
+					<0 210 IRQ_TYPE_LEVEL_HIGH>,
+					<0 211 IRQ_TYPE_LEVEL_HIGH>,
+					<0 212 IRQ_TYPE_LEVEL_HIGH>,
+					<0 213 IRQ_TYPE_LEVEL_HIGH>,
+					<0 214 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14";
+		};
+
+		sysdma1: dmac@e6720000 {
+			compatible = "renesas,dma-r8a7790";
+			clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
+			dma-channels = <15>;
+			reg = <0 0xe6720020 0 0xffc0>;
+			status = "disabled";
+
+			interrupt-parent = <&gic>;
+			interrupts =  <0 220 IRQ_TYPE_LEVEL_HIGH>,
+					<0 216 IRQ_TYPE_LEVEL_HIGH>,
+					<0 217 IRQ_TYPE_LEVEL_HIGH>,
+					<0 218 IRQ_TYPE_LEVEL_HIGH>,
+					<0 219 IRQ_TYPE_LEVEL_HIGH>,
+					<0 308 IRQ_TYPE_LEVEL_HIGH>,
+					<0 309 IRQ_TYPE_LEVEL_HIGH>,
+					<0 310 IRQ_TYPE_LEVEL_HIGH>,
+					<0 311 IRQ_TYPE_LEVEL_HIGH>,
+					<0 312 IRQ_TYPE_LEVEL_HIGH>,
+					<0 313 IRQ_TYPE_LEVEL_HIGH>,
+					<0 314 IRQ_TYPE_LEVEL_HIGH>,
+					<0 315 IRQ_TYPE_LEVEL_HIGH>,
+					<0 316 IRQ_TYPE_LEVEL_HIGH>,
+					<0 317 IRQ_TYPE_LEVEL_HIGH>,
+					<0 318 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "error",
+					"ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14", "ch15";
+		};
+	};
+
 	gic: interrupt-controller@f1001000 {
 		compatible = "arm,cortex-a15-gic";
 		#interrupt-cells = <3>;
-- 
1.8.5.3

Re: [PATCH 2/5] ARM: shmobile: r8a7790: add dmac0 dmac1 nodes

[Geert Uytterhoeven]

On Wed, Feb 12, 2014 at 6:59 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
> +               sysdma1: dmac@e6720000 {
> +                       compatible = "renesas,dma-r8a7790";
> +                       clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
> +                       dma-channels = <15>;

15 channels

> +                       reg = <0 0xe6720020 0 0xffc0>;
> +                       status = "disabled";
> +
> +                       interrupt-parent = <&gic>;
> +                       interrupts =  <0 220 IRQ_TYPE_LEVEL_HIGH>,

error

> +                                       <0 216 IRQ_TYPE_LEVEL_HIGH>,
> +                                       <0 217 IRQ_TYPE_LEVEL_HIGH>,
> +                                       <0 218 IRQ_TYPE_LEVEL_HIGH>,
> +                                       <0 219 IRQ_TYPE_LEVEL_HIGH>,
> +                                       <0 308 IRQ_TYPE_LEVEL_HIGH>,
> +                                       <0 309 IRQ_TYPE_LEVEL_HIGH>,
> +                                       <0 310 IRQ_TYPE_LEVEL_HIGH>,
> +                                       <0 311 IRQ_TYPE_LEVEL_HIGH>,
> +                                       <0 312 IRQ_TYPE_LEVEL_HIGH>,
> +                                       <0 313 IRQ_TYPE_LEVEL_HIGH>,
> +                                       <0 314 IRQ_TYPE_LEVEL_HIGH>,
> +                                       <0 315 IRQ_TYPE_LEVEL_HIGH>,
> +                                       <0 316 IRQ_TYPE_LEVEL_HIGH>,
> +                                       <0 317 IRQ_TYPE_LEVEL_HIGH>,
> +                                       <0 318 IRQ_TYPE_LEVEL_HIGH>;

ch0 - ch14

> +                       interrupt-names = "error",
> +                                       "ch0", "ch1", "ch2", "ch3",
> +                                       "ch4", "ch5", "ch6", "ch7",
> +                                       "ch8", "ch9", "ch10", "ch11",
> +                                       "ch12", "ch13", "ch14", "ch15";

Oops, ch15 is the 16th entry?

> +               };

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/5] ARM: shmobile: r8a7790: add dmac0 dmac1 nodes

[Sergei Shtylyov]

On 02/12/2014 08:59 PM, Ben Dooks wrote:

    No signoff but that's again intentional?

> ---
>   arch/arm/boot/dts/r8a7790.dtsi | 89 ++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 89 insertions(+)

> diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
> index 700e0a1..ae65270 100644
> --- a/arch/arm/boot/dts/r8a7790.dtsi
> +++ b/arch/arm/boot/dts/r8a7790.dtsi
[...]
> @@ -79,6 +80,94 @@
>   		};
>   	};
>
> +#define CHCR_RX_32BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_32BIT)
> +#define CHCR_TX_32BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_32BIT)
> +#define CHCR_RX_256BIT	SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_256BIT)
> +#define CHCR_TX_256BIT	SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_256BIT)
> +
> +	dma0: dma-mux@0 {
> +		compatible = "renesas,shdma-mux";
> +		#dma-cells = <1>;
> +		dma-channels = <20>;
> +                dma-requests = <256>;
> +                #address-cells = <2>;
> +                #size-cells = <2>;
> +                ranges;

    The above 4 lines are indented with spaces instead of tabs.

WBR, Sergei

Re: [PATCH 2/5] ARM: shmobile: r8a7790: add dmac0 dmac1 nodes

[Ben Dooks]

On 12/02/14 19:18, Geert Uytterhoeven wrote:
> On Wed, Feb 12, 2014 at 6:59 PM, Ben Dooks <ben.dooks@codethink.co.uk> wrote:
>> +               sysdma1: dmac@e6720000 {
>> +                       compatible = "renesas,dma-r8a7790";
>> +                       clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
>> +                       dma-channels = <15>;
>
> 15 channels
>
>> +                       reg = <0 0xe6720020 0 0xffc0>;
>> +                       status = "disabled";
>> +
>> +                       interrupt-parent = <&gic>;
>> +                       interrupts =  <0 220 IRQ_TYPE_LEVEL_HIGH>,
>
> error
>
>> +                                       <0 216 IRQ_TYPE_LEVEL_HIGH>,
>> +                                       <0 217 IRQ_TYPE_LEVEL_HIGH>,
>> +                                       <0 218 IRQ_TYPE_LEVEL_HIGH>,
>> +                                       <0 219 IRQ_TYPE_LEVEL_HIGH>,
>> +                                       <0 308 IRQ_TYPE_LEVEL_HIGH>,
>> +                                       <0 309 IRQ_TYPE_LEVEL_HIGH>,
>> +                                       <0 310 IRQ_TYPE_LEVEL_HIGH>,
>> +                                       <0 311 IRQ_TYPE_LEVEL_HIGH>,
>> +                                       <0 312 IRQ_TYPE_LEVEL_HIGH>,
>> +                                       <0 313 IRQ_TYPE_LEVEL_HIGH>,
>> +                                       <0 314 IRQ_TYPE_LEVEL_HIGH>,
>> +                                       <0 315 IRQ_TYPE_LEVEL_HIGH>,
>> +                                       <0 316 IRQ_TYPE_LEVEL_HIGH>,
>> +                                       <0 317 IRQ_TYPE_LEVEL_HIGH>,
>> +                                       <0 318 IRQ_TYPE_LEVEL_HIGH>;
>
> ch0 - ch14
>
>> +                       interrupt-names = "error",
>> +                                       "ch0", "ch1", "ch2", "ch3",
>> +                                       "ch4", "ch5", "ch6", "ch7",
>> +                                       "ch8", "ch9", "ch10", "ch11",
>> +                                       "ch12", "ch13", "ch14", "ch15";
>
> Oops, ch15 is the 16th entry?

Thanks, will fix it.


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

Re: [PATCH 2/5] ARM: shmobile: r8a7790: add dmac0 dmac1 nodes

[Ben Dooks]

On 12/02/14 20:55, Sergei Shtylyov wrote:
> On 02/12/2014 08:59 PM, Ben Dooks wrote:
>
>     No signoff but that's again intentional?
>
>> ---
>>   arch/arm/boot/dts/r8a7790.dtsi | 89
>> ++++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 89 insertions(+)
>
>> diff --git a/arch/arm/boot/dts/r8a7790.dtsi
>> b/arch/arm/boot/dts/r8a7790.dtsi
>> index 700e0a1..ae65270 100644
>> --- a/arch/arm/boot/dts/r8a7790.dtsi
>> +++ b/arch/arm/boot/dts/r8a7790.dtsi
> [...]
>> @@ -79,6 +80,94 @@
>>           };
>>       };
>>
>> +#define CHCR_RX_32BIT    SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_32BIT)
>> +#define CHCR_TX_32BIT    SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_32BIT)
>> +#define CHCR_RX_256BIT    SHDMA_ARM_CHCR_RX(SHDMA_ARM_SZ_256BIT)
>> +#define CHCR_TX_256BIT    SHDMA_ARM_CHCR_TX(SHDMA_ARM_SZ_256BIT)
>> +
>> +    dma0: dma-mux@0 {
>> +        compatible = "renesas,shdma-mux";
>> +        #dma-cells = <1>;
>> +        dma-channels = <20>;
>> +                dma-requests = <256>;
>> +                #address-cells = <2>;
>> +                #size-cells = <2>;
>> +                ranges;
>
>     The above 4 lines are indented with spaces instead of tabs.
>
> WBR, Sergei

Missed indentation, will fix thanks.


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius