From: Ulrich Hecht <ulrich.hecht@gmail.com>
To: linux-sh@vger.kernel.org
Subject: [PATCH 6/6] clk: shmobile: Add r8a7740, sh73a0 SoCs to MSTP bindings
Date: Tue, 06 May 2014 14:23:53 +0000 [thread overview]
Message-ID: <1399386233-11928-7-git-send-email-ulrich.hecht+renesas@gmail.com> (raw)
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
---
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index 5992dce..8514088 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -10,8 +10,10 @@ index in the group, from 0 to 31.
Required Properties:
- compatible: Must be one of the following
+ - "renesas,r8a7740-mstp-clocks" for R8A7740 MSTP gate clocks
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
+ - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
- "renesas,cpg-mstp-clock" for generic MSTP gate clocks
- reg: Base address and length of the I/O mapped registers used by the MSTP
clocks. The first register is the clock control register and is mandatory.
--
1.8.4.5
next prev reply other threads:[~2014-05-06 14:23 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-06 14:23 [PATCH 0/6] sh73a0 common clock framework implementation Ulrich Hecht
2014-05-06 14:23 ` [PATCH 3/6] clk: shmobile: div6: support selectable-input clocks Ulrich Hecht
2014-05-07 9:01 ` Geert Uytterhoeven
2014-05-06 14:23 ` Ulrich Hecht [this message]
2014-05-07 14:59 ` [PATCH 6/6] clk: shmobile: Add r8a7740, sh73a0 SoCs to MSTP bindings Geert Uytterhoeven
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