* [PATCH] - Fix dreamcast irq.c formatting
@ 2008-11-18 15:28 Kristoffer Ericson
2008-11-18 15:49 ` Paul Mundt
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Kristoffer Ericson @ 2008-11-18 15:28 UTC (permalink / raw)
To: linux-sh
[-- Attachment #1.1: Type: text/plain, Size: 7349 bytes --]
This patch cleans the bad formatting
found in mach-dreamcast/irq.c file.
Signed-off-by: Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
diff --git a/arch/sh/boards/mach-dreamcast/irq.c b/arch/sh/boards/mach-dreamcast/irq.c
index 67bdc33..482a382 100644
--- a/arch/sh/boards/mach-dreamcast/irq.c
+++ b/arch/sh/boards/mach-dreamcast/irq.c
@@ -16,27 +16,27 @@
/* Dreamcast System ASIC Hardware Events -
- The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving
- hardware events from system peripherals and triggering an SH7750 IRQ.
- Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are
- set in the Event Mask Registers (EMRs). When a hardware event is
- triggered, it's corresponding bit in the Event Status Registers (ESRs)
- is set, and that bit should be rewritten to the ESR to acknowledge that
- event.
-
- There are three 32-bit ESRs located at 0xa05f8900 - 0xa05f6908. Event
- types can be found in include/asm-sh/dreamcast/sysasic.h. There are three
- groups of EMRs that parallel the ESRs. Each EMR group corresponds to an
- IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13, 0xa05f6920 - 0xa05f6928
- triggers IRQ 11, and 0xa05f6930 - 0xa05f6938 triggers IRQ 9.
-
- In the kernel, these events are mapped to virtual IRQs so that drivers can
- respond to them as they would a normal interrupt. In order to keep this
- mapping simple, the events are mapped as:
-
- 6900/6910 - Events 0-31, IRQ 13
- 6904/6924 - Events 32-63, IRQ 11
- 6908/6938 - Events 64-95, IRQ 9
+ The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving
+ hardware events from system peripherals and triggering an SH7750 IRQ.
+ Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are
+ set in the Event Mask Registers (EMRs). When a hardware event is
+ triggered, it's corresponding bit in the Event Status Registers (ESRs)
+ is set, and that bit should be rewritten to the ESR to acknowledge that
+ event.
+
+ There are three 32-bit ESRs located at 0xa05f8900 - 0xa05f6908. Event
+ types can be found in include/asm-sh/dreamcast/sysasic.h. There are three
+ groups of EMRs that parallel the ESRs. Each EMR group corresponds to an
+ IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13, 0xa05f6920 - 0xa05f6928
+ triggers IRQ 11, and 0xa05f6930 - 0xa05f6938 triggers IRQ 9.
+
+ In the kernel, these events are mapped to virtual IRQs so that drivers can
+ respond to them as they would a normal interrupt. In order to keep this
+ mapping simple, the events are mapped as:
+
+ 6900/6910 - Events 0-31, IRQ 13
+ 6904/6924 - Events 32-63, IRQ 11
+ 6908/6938 - Events 64-95, IRQ 9
*/
@@ -56,60 +56,60 @@
/* Disable the hardware event by masking its bit in its EMR */
static inline void disable_systemasic_irq(unsigned int irq)
{
- __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
- __u32 mask;
+ __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
+ __u32 mask;
- mask = inl(emr);
- mask &= ~(1 << EVENT_BIT(irq));
- outl(mask, emr);
+ mask = inl(emr);
+ mask &= ~(1 << EVENT_BIT(irq));
+ outl(mask, emr);
}
/* Enable the hardware event by setting its bit in its EMR */
static inline void enable_systemasic_irq(unsigned int irq)
{
- __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
- __u32 mask;
+ __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
+ __u32 mask;
- mask = inl(emr);
- mask |= (1 << EVENT_BIT(irq));
- outl(mask, emr);
+ mask = inl(emr);
+ mask |= (1 << EVENT_BIT(irq));
+ outl(mask, emr);
}
/* Acknowledge a hardware event by writing its bit back to its ESR */
static void ack_systemasic_irq(unsigned int irq)
{
- __u32 esr = ESR_BASE + (LEVEL(irq) << 2);
- disable_systemasic_irq(irq);
- outl((1 << EVENT_BIT(irq)), esr);
+ __u32 esr = ESR_BASE + (LEVEL(irq) << 2);
+ disable_systemasic_irq(irq);
+ outl((1 << EVENT_BIT(irq)), esr);
}
/* After a IRQ has been ack'd and responded to, it needs to be renabled */
static void end_systemasic_irq(unsigned int irq)
{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
- enable_systemasic_irq(irq);
+ if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+ enable_systemasic_irq(irq);
}
static unsigned int startup_systemasic_irq(unsigned int irq)
{
- enable_systemasic_irq(irq);
+ enable_systemasic_irq(irq);
- return 0;
+ return 0;
}
static void shutdown_systemasic_irq(unsigned int irq)
{
- disable_systemasic_irq(irq);
+ disable_systemasic_irq(irq);
}
struct hw_interrupt_type systemasic_int = {
- .typename = "System ASIC",
- .startup = startup_systemasic_irq,
- .shutdown = shutdown_systemasic_irq,
- .enable = enable_systemasic_irq,
- .disable = disable_systemasic_irq,
- .ack = ack_systemasic_irq,
- .end = end_systemasic_irq,
+ .typename = "System ASIC",
+ .startup = startup_systemasic_irq,
+ .shutdown = shutdown_systemasic_irq,
+ .enable = enable_systemasic_irq,
+ .disable = disable_systemasic_irq,
+ .ack = ack_systemasic_irq,
+ .end = end_systemasic_irq,
};
/*
@@ -117,37 +117,37 @@ struct hw_interrupt_type systemasic_int = {
*/
int systemasic_irq_demux(int irq)
{
- __u32 emr, esr, status, level;
- __u32 j, bit;
-
- switch (irq) {
- case 13:
- level = 0;
- break;
- case 11:
- level = 1;
- break;
- case 9:
- level = 2;
- break;
- default:
- return irq;
- }
- emr = EMR_BASE + (level << 4) + (level << 2);
- esr = ESR_BASE + (level << 2);
-
- /* Mask the ESR to filter any spurious, unwanted interrupts */
- status = inl(esr);
- status &= inl(emr);
-
- /* Now scan and find the first set bit as the event to map */
- for (bit = 1, j = 0; j < 32; bit <<= 1, j++) {
- if (status & bit) {
- irq = HW_EVENT_IRQ_BASE + j + (level << 5);
- return irq;
- }
- }
-
- /* Not reached */
- return irq;
+ __u32 emr, esr, status, level;
+ __u32 j, bit;
+
+ switch (irq) {
+ case 13:
+ level = 0;
+ break;
+ case 11:
+ level = 1;
+ break;
+ case 9:
+ level = 2;
+ break;
+ default:
+ return irq;
+ }
+ emr = EMR_BASE + (level << 4) + (level << 2);
+ esr = ESR_BASE + (level << 2);
+
+ /* Mask the ESR to filter any spurious, unwanted interrupts */
+ status = inl(esr);
+ status &= inl(emr);
+
+ /* Now scan and find the first set bit as the event to map */
+ for (bit = 1, j = 0; j < 32; bit <<= 1, j++) {
+ if (status & bit) {
+ irq = HW_EVENT_IRQ_BASE + j + (level << 5);
+ return irq;
+ }
+ }
+
+ /* Not reached */
+ return irq;
}
--
Kristoffer Ericson <kristoffer.ericson@gmail.com>
[-- Attachment #1.2: fix-dreamcast-irq-formatting.patch --]
[-- Type: application/octet-stream, Size: 6936 bytes --]
diff --git a/arch/sh/boards/mach-dreamcast/irq.c b/arch/sh/boards/mach-dreamcast/irq.c
index 67bdc33..482a382 100644
--- a/arch/sh/boards/mach-dreamcast/irq.c
+++ b/arch/sh/boards/mach-dreamcast/irq.c
@@ -16,27 +16,27 @@
/* Dreamcast System ASIC Hardware Events -
- The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving
- hardware events from system peripherals and triggering an SH7750 IRQ.
- Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are
- set in the Event Mask Registers (EMRs). When a hardware event is
- triggered, it's corresponding bit in the Event Status Registers (ESRs)
- is set, and that bit should be rewritten to the ESR to acknowledge that
- event.
-
- There are three 32-bit ESRs located at 0xa05f8900 - 0xa05f6908. Event
- types can be found in include/asm-sh/dreamcast/sysasic.h. There are three
- groups of EMRs that parallel the ESRs. Each EMR group corresponds to an
- IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13, 0xa05f6920 - 0xa05f6928
- triggers IRQ 11, and 0xa05f6930 - 0xa05f6938 triggers IRQ 9.
-
- In the kernel, these events are mapped to virtual IRQs so that drivers can
- respond to them as they would a normal interrupt. In order to keep this
- mapping simple, the events are mapped as:
-
- 6900/6910 - Events 0-31, IRQ 13
- 6904/6924 - Events 32-63, IRQ 11
- 6908/6938 - Events 64-95, IRQ 9
+ The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving
+ hardware events from system peripherals and triggering an SH7750 IRQ.
+ Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are
+ set in the Event Mask Registers (EMRs). When a hardware event is
+ triggered, it's corresponding bit in the Event Status Registers (ESRs)
+ is set, and that bit should be rewritten to the ESR to acknowledge that
+ event.
+
+ There are three 32-bit ESRs located at 0xa05f8900 - 0xa05f6908. Event
+ types can be found in include/asm-sh/dreamcast/sysasic.h. There are three
+ groups of EMRs that parallel the ESRs. Each EMR group corresponds to an
+ IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13, 0xa05f6920 - 0xa05f6928
+ triggers IRQ 11, and 0xa05f6930 - 0xa05f6938 triggers IRQ 9.
+
+ In the kernel, these events are mapped to virtual IRQs so that drivers can
+ respond to them as they would a normal interrupt. In order to keep this
+ mapping simple, the events are mapped as:
+
+ 6900/6910 - Events 0-31, IRQ 13
+ 6904/6924 - Events 32-63, IRQ 11
+ 6908/6938 - Events 64-95, IRQ 9
*/
@@ -56,60 +56,60 @@
/* Disable the hardware event by masking its bit in its EMR */
static inline void disable_systemasic_irq(unsigned int irq)
{
- __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
- __u32 mask;
+ __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
+ __u32 mask;
- mask = inl(emr);
- mask &= ~(1 << EVENT_BIT(irq));
- outl(mask, emr);
+ mask = inl(emr);
+ mask &= ~(1 << EVENT_BIT(irq));
+ outl(mask, emr);
}
/* Enable the hardware event by setting its bit in its EMR */
static inline void enable_systemasic_irq(unsigned int irq)
{
- __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
- __u32 mask;
+ __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
+ __u32 mask;
- mask = inl(emr);
- mask |= (1 << EVENT_BIT(irq));
- outl(mask, emr);
+ mask = inl(emr);
+ mask |= (1 << EVENT_BIT(irq));
+ outl(mask, emr);
}
/* Acknowledge a hardware event by writing its bit back to its ESR */
static void ack_systemasic_irq(unsigned int irq)
{
- __u32 esr = ESR_BASE + (LEVEL(irq) << 2);
- disable_systemasic_irq(irq);
- outl((1 << EVENT_BIT(irq)), esr);
+ __u32 esr = ESR_BASE + (LEVEL(irq) << 2);
+ disable_systemasic_irq(irq);
+ outl((1 << EVENT_BIT(irq)), esr);
}
/* After a IRQ has been ack'd and responded to, it needs to be renabled */
static void end_systemasic_irq(unsigned int irq)
{
- if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
- enable_systemasic_irq(irq);
+ if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+ enable_systemasic_irq(irq);
}
static unsigned int startup_systemasic_irq(unsigned int irq)
{
- enable_systemasic_irq(irq);
+ enable_systemasic_irq(irq);
- return 0;
+ return 0;
}
static void shutdown_systemasic_irq(unsigned int irq)
{
- disable_systemasic_irq(irq);
+ disable_systemasic_irq(irq);
}
struct hw_interrupt_type systemasic_int = {
- .typename = "System ASIC",
- .startup = startup_systemasic_irq,
- .shutdown = shutdown_systemasic_irq,
- .enable = enable_systemasic_irq,
- .disable = disable_systemasic_irq,
- .ack = ack_systemasic_irq,
- .end = end_systemasic_irq,
+ .typename = "System ASIC",
+ .startup = startup_systemasic_irq,
+ .shutdown = shutdown_systemasic_irq,
+ .enable = enable_systemasic_irq,
+ .disable = disable_systemasic_irq,
+ .ack = ack_systemasic_irq,
+ .end = end_systemasic_irq,
};
/*
@@ -117,37 +117,37 @@ struct hw_interrupt_type systemasic_int = {
*/
int systemasic_irq_demux(int irq)
{
- __u32 emr, esr, status, level;
- __u32 j, bit;
-
- switch (irq) {
- case 13:
- level = 0;
- break;
- case 11:
- level = 1;
- break;
- case 9:
- level = 2;
- break;
- default:
- return irq;
- }
- emr = EMR_BASE + (level << 4) + (level << 2);
- esr = ESR_BASE + (level << 2);
-
- /* Mask the ESR to filter any spurious, unwanted interrupts */
- status = inl(esr);
- status &= inl(emr);
-
- /* Now scan and find the first set bit as the event to map */
- for (bit = 1, j = 0; j < 32; bit <<= 1, j++) {
- if (status & bit) {
- irq = HW_EVENT_IRQ_BASE + j + (level << 5);
- return irq;
- }
- }
-
- /* Not reached */
- return irq;
+ __u32 emr, esr, status, level;
+ __u32 j, bit;
+
+ switch (irq) {
+ case 13:
+ level = 0;
+ break;
+ case 11:
+ level = 1;
+ break;
+ case 9:
+ level = 2;
+ break;
+ default:
+ return irq;
+ }
+ emr = EMR_BASE + (level << 4) + (level << 2);
+ esr = ESR_BASE + (level << 2);
+
+ /* Mask the ESR to filter any spurious, unwanted interrupts */
+ status = inl(esr);
+ status &= inl(emr);
+
+ /* Now scan and find the first set bit as the event to map */
+ for (bit = 1, j = 0; j < 32; bit <<= 1, j++) {
+ if (status & bit) {
+ irq = HW_EVENT_IRQ_BASE + j + (level << 5);
+ return irq;
+ }
+ }
+
+ /* Not reached */
+ return irq;
}
[-- Attachment #2: Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] - Fix dreamcast irq.c formatting
2008-11-18 15:28 [PATCH] - Fix dreamcast irq.c formatting Kristoffer Ericson
@ 2008-11-18 15:49 ` Paul Mundt
2008-11-18 15:53 ` Kristoffer Ericson
2008-11-18 15:57 ` Paul Mundt
2 siblings, 0 replies; 4+ messages in thread
From: Paul Mundt @ 2008-11-18 15:49 UTC (permalink / raw)
To: linux-sh
On Tue, Nov 18, 2008 at 05:28:47PM +0100, Kristoffer Ericson wrote:
> This patch cleans the bad formatting
> found in mach-dreamcast/irq.c file.
>
Why even bother? There are more useful things you can be doing with this
file, like fixing up the comment to deal with the fact there have been
path changes, converting to the new IRQ model (this is one of the last
ones left on hw_interrupt_type), etc. Once those sorts of things are out
of the way, the rest is fairly trivial to tidy, and you can fix up the
formatting as you go along with regards to new code.
Whitespace changes have a high risk of causing merge conflicts and
provide precisely zero benefit. If you don't plan to be making any
constructive changes to this file, then simply leave it alone.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] - Fix dreamcast irq.c formatting
2008-11-18 15:28 [PATCH] - Fix dreamcast irq.c formatting Kristoffer Ericson
2008-11-18 15:49 ` Paul Mundt
@ 2008-11-18 15:53 ` Kristoffer Ericson
2008-11-18 15:57 ` Paul Mundt
2 siblings, 0 replies; 4+ messages in thread
From: Kristoffer Ericson @ 2008-11-18 15:53 UTC (permalink / raw)
To: linux-sh
[-- Attachment #1: Type: text/plain, Size: 1099 bytes --]
On Wed, 19 Nov 2008 00:49:51 +0900
Paul Mundt <lethal@linux-sh.org> wrote:
> On Tue, Nov 18, 2008 at 05:28:47PM +0100, Kristoffer Ericson wrote:
> > This patch cleans the bad formatting
> > found in mach-dreamcast/irq.c file.
> >
> Why even bother? There are more useful things you can be doing with this
> file, like fixing up the comment to deal with the fact there have been
> path changes, converting to the new IRQ model (this is one of the last
> ones left on hw_interrupt_type), etc. Once those sorts of things are out
> of the way, the rest is fairly trivial to tidy, and you can fix up the
> formatting as you go along with regards to new code.
Oki point taken. Ive got no dreamcast to fiddle with
so I'll just leave it alone. Just decided to drop a patch
when I accidently saw the mess it was in.
>
> Whitespace changes have a high risk of causing merge conflicts and
> provide precisely zero benefit. If you don't plan to be making any
> constructive changes to this file, then simply leave it alone.
--
Kristoffer Ericson <kristoffer.ericson@gmail.com>
[-- Attachment #2: Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] - Fix dreamcast irq.c formatting
2008-11-18 15:28 [PATCH] - Fix dreamcast irq.c formatting Kristoffer Ericson
2008-11-18 15:49 ` Paul Mundt
2008-11-18 15:53 ` Kristoffer Ericson
@ 2008-11-18 15:57 ` Paul Mundt
2 siblings, 0 replies; 4+ messages in thread
From: Paul Mundt @ 2008-11-18 15:57 UTC (permalink / raw)
To: linux-sh
On Tue, Nov 18, 2008 at 05:54:24PM +0100, Kristoffer Ericson wrote:
> On Wed, 19 Nov 2008 00:49:51 +0900
> Paul Mundt <lethal@linux-sh.org> wrote:
>
> > On Tue, Nov 18, 2008 at 05:28:47PM +0100, Kristoffer Ericson wrote:
> > > This patch cleans the bad formatting
> > > found in mach-dreamcast/irq.c file.
> > >
> > Why even bother? There are more useful things you can be doing with this
> > file, like fixing up the comment to deal with the fact there have been
> > path changes, converting to the new IRQ model (this is one of the last
> > ones left on hw_interrupt_type), etc. Once those sorts of things are out
> > of the way, the rest is fairly trivial to tidy, and you can fix up the
> > formatting as you go along with regards to new code.
>
> Oki point taken. Ive got no dreamcast to fiddle with
> so I'll just leave it alone. Just decided to drop a patch
> when I accidently saw the mess it was in.
>
Note that there is nothing wrong with fixing up whitespace damage as you
encounter it, I do so all the time (usually cleaning up after the emacs
people that can't work out what the hell a tab is), but you don't want
that sort of stuff to be the focus of your work. If you are interested in
cleaning up some of the dreamcast code, you are best off making a small
incremental patch series and posting it to the list to try and get people
with hardware to some testing for you.
There are plenty of useful things to be done in terms of low-hanging
fruit at least, whitespace formatting isn't one of them ;-)
^ permalink raw reply [flat|nested] 4+ messages in thread
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2008-11-18 15:28 [PATCH] - Fix dreamcast irq.c formatting Kristoffer Ericson
2008-11-18 15:49 ` Paul Mundt
2008-11-18 15:53 ` Kristoffer Ericson
2008-11-18 15:57 ` Paul Mundt
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