From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kristoffer Ericson Date: Tue, 18 Nov 2008 15:49:03 +0000 Subject: [PATCH - UPDATED] - Fix dreamcast irq.c formatting Message-Id: <20081118174927.803cbfd6.kristoffer.ericson@gmail.com> MIME-Version: 1 Content-Type: multipart/mixed; boundary="Signature=_Tue__18_Nov_2008_17_49_27_+0100_zdCEftDb.gKHeAe7" List-Id: To: linux-sh@vger.kernel.org --Signature=_Tue__18_Nov_2008_17_49_27_+0100_zdCEftDb.gKHeAe7 Content-Type: multipart/mixed; boundary="Multipart=_Tue__18_Nov_2008_17_49_27_+0100_DNHtcQ1DYJ2ktUX9" --Multipart=_Tue__18_Nov_2008_17_49_27_+0100_DNHtcQ1DYJ2ktUX9 Content-Type: text/plain; charset=US-ASCII Content-Disposition: inline Content-Transfer-Encoding: quoted-printable This patch cleans the bad formatting found in mach-dreamcast/irq.c file. Signed-off-by: Kristoffer Ericson diff --git a/arch/sh/boards/mach-dreamcast/irq.c b/arch/sh/boards/mach-drea= mcast/irq.c index 67bdc33..36a8a08 100644 --- a/arch/sh/boards/mach-dreamcast/irq.c +++ b/arch/sh/boards/mach-dreamcast/irq.c @@ -14,31 +14,32 @@ #include #include =20 -/* Dreamcast System ASIC Hardware Events - - - The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving - hardware events from system peripherals and triggering an SH7750 IRQ. - Hardware events can trigger IRQs 13, 11, or 9 depending on which bits a= re - set in the Event Mask Registers (EMRs). When a hardware event is - triggered, it's corresponding bit in the Event Status Registers (ESRs) - is set, and that bit should be rewritten to the ESR to acknowledge that - event. - - There are three 32-bit ESRs located at 0xa05f8900 - 0xa05f6908. Event - types can be found in include/asm-sh/dreamcast/sysasic.h. There are thr= ee - groups of EMRs that parallel the ESRs. Each EMR group corresponds to an - IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13, 0xa05f6920 - 0xa05f6928 - triggers IRQ 11, and 0xa05f6930 - 0xa05f6938 triggers IRQ 9. - - In the kernel, these events are mapped to virtual IRQs so that drivers = can - respond to them as they would a normal interrupt. In order to keep this - mapping simple, the events are mapped as: - - 6900/6910 - Events 0-31, IRQ 13 - 6904/6924 - Events 32-63, IRQ 11 - 6908/6938 - Events 64-95, IRQ 9 - -*/ +/* + * Dreamcast System ASIC Hardware Events + * + * The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving + * hardware events from system peripherals and triggering an SH7750 IRQ. + * Hardware events can trigger IRQs 13, 11, or 9 depending on which bits a= re + * set in the Event Mask Registers (EMRs). When a hardware event is + * triggered, it's corresponding bit in the Event Status Registers (ESRs) + * is set, and that bit should be rewritten to the ESR to acknowledge that + * event. + * + * There are three 32-bit ESRs located at 0xa05f8900 - 0xa05f6908. Event + * types can be found in include/asm-sh/dreamcast/sysasic.h. There are thr= ee + * groups of EMRs that parallel the ESRs. Each EMR group corresponds to an + * IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13, 0xa05f6920 - 0xa05f6928 + * triggers IRQ 11, and 0xa05f6930 - 0xa05f6938 triggers IRQ 9. + * + * In the kernel, these events are mapped to virtual IRQs so that drivers = can + * respond to them as they would a normal interrupt. In order to keep this + * mapping simple, the events are mapped as: + * + * 6900/6910 - Events 0-31, IRQ 13 + * 6904/6924 - Events 32-63, IRQ 11 + * 6908/6938 - Events 64-95, IRQ 9 + * + */ =20 #define ESR_BASE 0x005f6900 /* Base event status register */ #define EMR_BASE 0x005f6910 /* Base event mask register */ @@ -56,60 +57,60 @@ /* Disable the hardware event by masking its bit in its EMR */ static inline void disable_systemasic_irq(unsigned int irq) { - __u32 emr =3D EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); - __u32 mask; + __u32 emr =3D EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); + __u32 mask; =20 - mask =3D inl(emr); - mask &=3D ~(1 << EVENT_BIT(irq)); - outl(mask, emr); + mask =3D inl(emr); + mask &=3D ~(1 << EVENT_BIT(irq)); + outl(mask, emr); } =20 /* Enable the hardware event by setting its bit in its EMR */ static inline void enable_systemasic_irq(unsigned int irq) { - __u32 emr =3D EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); - __u32 mask; + __u32 emr =3D EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2); + __u32 mask; =20 - mask =3D inl(emr); - mask |=3D (1 << EVENT_BIT(irq)); - outl(mask, emr); + mask =3D inl(emr); + mask |=3D (1 << EVENT_BIT(irq)); + outl(mask, emr); } =20 /* Acknowledge a hardware event by writing its bit back to its ESR */ static void ack_systemasic_irq(unsigned int irq) { - __u32 esr =3D ESR_BASE + (LEVEL(irq) << 2); - disable_systemasic_irq(irq); - outl((1 << EVENT_BIT(irq)), esr); + __u32 esr =3D ESR_BASE + (LEVEL(irq) << 2); + disable_systemasic_irq(irq); + outl((1 << EVENT_BIT(irq)), esr); } =20 /* After a IRQ has been ack'd and responded to, it needs to be renabled */ static void end_systemasic_irq(unsigned int irq) { - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) - enable_systemasic_irq(irq); + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_systemasic_irq(irq); } =20 static unsigned int startup_systemasic_irq(unsigned int irq) { - enable_systemasic_irq(irq); + enable_systemasic_irq(irq); =20 - return 0; + return 0; } =20 static void shutdown_systemasic_irq(unsigned int irq) { - disable_systemasic_irq(irq); + disable_systemasic_irq(irq); } =20 struct hw_interrupt_type systemasic_int =3D { - .typename =3D "System ASIC", - .startup =3D startup_systemasic_irq, - .shutdown =3D shutdown_systemasic_irq, - .enable =3D enable_systemasic_irq, - .disable =3D disable_systemasic_irq, - .ack =3D ack_systemasic_irq, - .end =3D end_systemasic_irq, + .typename =3D "System ASIC", + .startup =3D startup_systemasic_irq, + .shutdown =3D shutdown_systemasic_irq, + .enable =3D enable_systemasic_irq, + .disable =3D disable_systemasic_irq, + .ack =3D ack_systemasic_irq, + .end =3D end_systemasic_irq, }; =20 /* @@ -117,37 +118,37 @@ struct hw_interrupt_type systemasic_int =3D { */ int systemasic_irq_demux(int irq) { - __u32 emr, esr, status, level; - __u32 j, bit; - - switch (irq) { - case 13: - level =3D 0; - break; - case 11: - level =3D 1; - break; - case 9: - level =3D 2; - break; - default: - return irq; - } - emr =3D EMR_BASE + (level << 4) + (level << 2); - esr =3D ESR_BASE + (level << 2); - - /* Mask the ESR to filter any spurious, unwanted interrupts */ - status =3D inl(esr); - status &=3D inl(emr); - - /* Now scan and find the first set bit as the event to map */ - for (bit =3D 1, j =3D 0; j < 32; bit <<=3D 1, j++) { - if (status & bit) { - irq =3D HW_EVENT_IRQ_BASE + j + (level << 5); - return irq; - } - } - - /* Not reached */ - return irq; + __u32 emr, esr, status, level; + __u32 j, bit; + + switch (irq) { + case 13: + level =3D 0; + break; + case 11: + level =3D 1; + break; + case 9: + level =3D 2; + break; + default: + return irq; + } + emr =3D EMR_BASE + (level << 4) + (level << 2); + esr =3D ESR_BASE + (level << 2); + + /* Mask the ESR to filter any spurious, unwanted interrupts */ + status =3D inl(esr); + status &=3D inl(emr); + + /* Now scan and find the first set bit as the event to map */ + for (bit =3D 1, j =3D 0; j < 32; bit <<=3D 1, j++) { + if (status & bit) { + irq =3D HW_EVENT_IRQ_BASE + j + (level << 5); + return irq; + } + } + + /* Not reached */ + return irq; } --=20 Kristoffer Ericson --Multipart=_Tue__18_Nov_2008_17_49_27_+0100_DNHtcQ1DYJ2ktUX9 Content-Type: application/octet-stream; name="fix-dreamcast-irq-formatting.patch" Content-Disposition: attachment; filename="fix-dreamcast-irq-formatting.patch" Content-Transfer-Encoding: base64 ZGlmZiAtLWdpdCBhL2FyY2gvc2gvYm9hcmRzL21hY2gtZHJlYW1jYXN0L2lycS5jIGIvYXJjaC9z aC9ib2FyZHMvbWFjaC1kcmVhbWNhc3QvaXJxLmMKaW5kZXggNjdiZGMzMy4uMzZhOGEwOCAxMDA2 NDQKLS0tIGEvYXJjaC9zaC9ib2FyZHMvbWFjaC1kcmVhbWNhc3QvaXJxLmMKKysrIGIvYXJjaC9z aC9ib2FyZHMvbWFjaC1kcmVhbWNhc3QvaXJxLmMKQEAgLTE0LDMxICsxNCwzMiBAQAogI2luY2x1 ZGUgPGFzbS9pcnEuaD4KICNpbmNsdWRlIDxtYWNoL3N5c2FzaWMuaD4KIAotLyogRHJlYW1jYXN0 IFN5c3RlbSBBU0lDIEhhcmR3YXJlIEV2ZW50cyAtCi0KLSAgIFRoZSBEcmVhbWNhc3QncyBTeXN0 ZW0gQVNJQyAoYS5rLmEuIEhvbGx5KSBpcyByZXNwb25zaWJsZSBmb3IgcmVjZWl2aW5nCi0gICBo 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