[PATCH] sh: boot word / mode pin support

[PATCH] sh: boot word / mode pin support

[Magnus Damm]

From: Magnus Damm <damm@igel.co.jp>

Add mode pin support for the SuperH architecture.

Processor and board specific code can with this patch
use set_mode_pin() to set mode pin configuration. Use
test_mode_pin() to test already set mode pin values.

The code warns if a pin is tested but not configured.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
---

 arch/sh/include/asm/processor.h |    4 ++++
 arch/sh/kernel/setup.c          |   28 ++++++++++++++++++++++++++++
 2 files changed, 32 insertions(+)

--- 0001/arch/sh/include/asm/processor.h
+++ work/arch/sh/include/asm/processor.h	2009-05-21 15:57:36.000000000 +0900
@@ -94,6 +94,10 @@ extern struct pt_regs fake_swapper_regs;
 const char *get_cpu_subtype(struct sh_cpuinfo *c);
 extern const struct seq_operations cpuinfo_op;
 
+#define SH_MODE_PINS_NR 16
+void set_mode_pin(int pin, int on);
+int test_mode_pin(int pin);
+
 #ifdef CONFIG_VSYSCALL
 int vsyscall_init(void);
 #else
--- 0001/arch/sh/kernel/setup.c
+++ work/arch/sh/kernel/setup.c	2009-05-21 16:08:18.000000000 +0900
@@ -420,6 +420,34 @@ void __init setup_arch(char **cmdline_p)
 #endif
 }
 
+/* processor boot mode configuration */
+static DECLARE_BITMAP(mode_pins, SH_MODE_PINS_NR * 2);
+
+void set_mode_pin(int pin, int on)
+{
+	BUG_ON(pin >= SH_MODE_PINS_NR);
+
+	/* mark pin as configured */
+	set_bit(pin + SH_MODE_PINS_NR, mode_pins);
+
+	/* remember pin value */
+	if (on)
+		set_bit(pin, mode_pins);
+	else
+		clear_bit(pin, mode_pins);
+}
+
+int test_mode_pin(int pin)
+{
+	BUG_ON(pin >= SH_MODE_PINS_NR);
+
+	/* warn if not configured */
+	if (!test_bit(pin + SH_MODE_PINS_NR, mode_pins))
+		pr_warning("test_mode_pin(): pin %d not configured\n", pin);
+
+	return test_bit(pin, mode_pins);
+}
+
 static const char *cpu_name[] = {
 	[CPU_SH7201]	= "SH7201",
 	[CPU_SH7203]	= "SH7203",	[CPU_SH7263]	= "SH7263",

[PATCH] sh: boot word / mode pin support V2

[Magnus Damm]

From: Magnus Damm <damm@igel.co.jp>

Add mode pin support for the SuperH architecture V2.

With this patch applied the board code can add their
own function to export the cpu mode pin configuration.
In most cases this will be a constant bitmap, but
boards that allow reading this from a register can
instead read out the pin state from hardware.

The code warns if a pin is tested but no board specific
mode pin function has been provided.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
---

 arch/sh/include/asm/machvec.h   |    1 +
 arch/sh/include/asm/processor.h |    4 ++++
 arch/sh/kernel/machvec.c        |    1 +
 arch/sh/kernel/setup.c          |   12 ++++++++++++
 4 files changed, 18 insertions(+)

--- 0001/arch/sh/include/asm/machvec.h
+++ work/arch/sh/include/asm/machvec.h	2009-05-28 15:55:02.000000000 +0900
@@ -48,6 +48,7 @@ struct sh_machine_vector {
 	void (*mv_ioport_unmap)(void __iomem *);
 
 	int (*mv_clk_init)(void);
+	int (*mv_mode_pins)(void);
 };
 
 extern struct sh_machine_vector sh_mv;
--- 0001/arch/sh/include/asm/processor.h
+++ work/arch/sh/include/asm/processor.h	2009-05-28 16:00:33.000000000 +0900
@@ -94,6 +94,10 @@ extern struct pt_regs fake_swapper_regs;
 const char *get_cpu_subtype(struct sh_cpuinfo *c);
 extern const struct seq_operations cpuinfo_op;
 
+/* processor boot mode configuration */
+int generic_mode_pins(void);
+int test_mode_pin(int pin);
+
 #ifdef CONFIG_VSYSCALL
 int vsyscall_init(void);
 #else
--- 0001/arch/sh/kernel/machvec.c
+++ work/arch/sh/kernel/machvec.c	2009-05-28 15:55:02.000000000 +0900
@@ -129,6 +129,7 @@ void __init sh_mv_setup(void)
 	mv_set(ioport_map);
 	mv_set(ioport_unmap);
 	mv_set(irq_demux);
+	mv_set(mode_pins);
 
 	if (!sh_mv.mv_nr_irqs)
 		sh_mv.mv_nr_irqs = NR_IRQS;
--- 0001/arch/sh/kernel/setup.c
+++ work/arch/sh/kernel/setup.c	2009-05-28 16:00:35.000000000 +0900
@@ -420,6 +420,18 @@ void __init setup_arch(char **cmdline_p)
 #endif
 }
 
+/* processor boot mode configuration */
+int generic_mode_pins(void)
+{
+	pr_warning("generic_mode_pins(): missing mode pin configuration\n");
+	return 0;
+}
+
+int test_mode_pin(int pin)
+{
+	return sh_mv.mv_mode_pins() & (1 << pin);
+}
+
 static const char *cpu_name[] = {
 	[CPU_SH7201]	= "SH7201",
 	[CPU_SH7203]	= "SH7203",	[CPU_SH7263]	= "SH7263",

Re: [PATCH] sh: boot word / mode pin support V2

[Paul Mundt]

On Thu, May 28, 2009 at 08:51:51PM +0900, Magnus Damm wrote:
> Add mode pin support for the SuperH architecture V2.
> 
> With this patch applied the board code can add their
> own function to export the cpu mode pin configuration.
> In most cases this will be a constant bitmap, but
> boards that allow reading this from a register can
> instead read out the pin state from hardware.
> 
> The code warns if a pin is tested but no board specific
> mode pin function has been provided.
> 

On Thu, May 28, 2009 at 08:56:21PM +0900, Magnus Damm wrote:
> This patch adds sh7785 mode pin definitions. Mode pins and
> pin function controller comments are added as well.
> 
[snip]

> --- 0001/arch/sh/include/cpu-sh4/cpu/sh7785.h
> +++ work/arch/sh/include/cpu-sh4/cpu/sh7785.h	2009-05-28 20:42:21.000000000 +0900
> @@ -1,6 +1,28 @@
>  #ifndef __ASM_SH7785_H__
>  #define __ASM_SH7785_H__
>  
> +/* Boot Mode Pins, more information in sh7785 manual Rev.1.00, page 1628 */
> +#define MODE_PIN_MODE0 0 /* CPG - Initial Pck/Bck Frequency [FRQMR1] */
> +#define MODE_PIN_MODE1 1 /* CPG - Initial Uck/SHck/DDRck Frequency [FRQMR1] */
> +#define MODE_PIN_MODE2 2 /* CPG - Reserved (L: Normal operation) */
> +#define MODE_PIN_MODE3 3 /* CPG - Reserved (L: Normal operation) */
> +#define MODE_PIN_MODE4 4 /* CPG - Initial PLL setting (72x/36x) */
> +#define MODE_PIN_MODE5 5 /* LBSC - Area0 Memory Type / Bus Width [CS0BCR.8] */
> +#define MODE_PIN_MODE6 6 /* LBSC - Area0 Memory Type / Bus Width [CS0BCR.9] */
> +#define MODE_PIN_MODE7 7 /* LBSC - Area0 Memory Type / Bus Width [CS0BCR.3] */
> +#define MODE_PIN_MODE8 8 /* LBSC - Endian Mode (L: Big, H: Little) [BCR.31] */
> +#define MODE_PIN_MODE9 9 /* LBSC - Master/Slave Mode (L: Slave) [BCR.30] */
> +#define MODE_PIN_MODE10 10 /* CPG - Clock Input (L: Ext Clk, H: Crystal) */
> +#define MODE_PIN_MODE11 11 /* PCI - Pin Mode (LL: PCI host, LH: PCI slave) */
> +#define MODE_PIN_MODE12 12 /* PCI - Pin Mode (HL: Local bus, HH: DU) */
> +#define MODE_PIN_MODE13 13 /* Boot Address Mode (L: 29-bit, H: 32-bit) */
> +#define MODE_PIN_MODE14 14 /* Reserved (H: Normal operation) */
> +#define MODE_PIN_MPMD 15 /* Emulation Mode (L: Emulation mode, H: LSI mode) */
> +
I've changed this to an enum so it appears less visually offensive.

On Thu, May 28, 2009 at 09:00:25PM +0900, Magnus Damm wrote:
> This patch adds mode pin support to the sh7785lcr board.
> 
> The harware allows the user to control the mode pins using
> dip switches S1 and S2, but from the software the pins are
> fixed to the factory default since we have no way to reading
> out this configuration from software.

On Thu, May 28, 2009 at 09:06:17PM +0900, Magnus Damm wrote:
> This patch modifies the sh7785 clock code to use the MODE4
> value to switch between 72x and 36x PLL multiplication.

All applied, thanks.