sh2a 7203 LCDC memory access

sh2a 7203 LCDC memory access

[Fabio Giovagnini]

Hi All,
I'd likt to keep you informed about my last discovering about LCDC of sh2a 
7203.
If I build the kernel with cache off, the image is clean and stable but the 
performances are very very poor;
if I build with cache write back the performaces are very good but the image 
is stable but sometimes dirty; fi I build with cache write through the 
performances seems to be a little bit less than write back but the image is 
stiil clean and stable.
Does this make sense?
How can I explain this behaviour?

Thanks in advance

-- 
Ing. Fabio Giovagnini

Aurion s.r.l.
P.I e C.F.
00885711200
skype: aurion.giovagnini
Tel. +39.051.594.78.24
Fax. +39.051.082.14.49
Cell. +39.335.83.50.919
www.aurion-tech.com

Re: sh2a 7203 LCDC memory access

[Magnus Damm]

Hi Fabio,

On Tue, Mar 22, 2011 at 4:53 PM, Fabio Giovagnini
<fabio.giovagnini@aurion-tech.com> wrote:
> Hi All,
> I'd likt to keep you informed about my last discovering about LCDC of sh2a
> 7203.
> If I build the kernel with cache off, the image is clean and stable but the
> performances are very very poor;
> if I build with cache write back the performaces are very good but the image
> is stable but sometimes dirty; fi I build with cache write through the
> performances seems to be a little bit less than write back but the image is
> stiil clean and stable.
> Does this make sense?

Yes.

> How can I explain this behaviour?

The LCDC is an output device looking from the CPU point of view.

The write-though cache setting is OK for output even though you are
not flushing the cache. It behaves the same as cache off for writing
because the data is always written _through_ the cache directly to the
memory that is read by the LCDC.

If you use copy-back (write-back) but picture is not OK then this
means the data is left in the cache and has not been written out to
memory. The copy-back cache is only writing to memory when running our
of cache space or your are flushing the data to memory by software
control.

You need to make sure your frame buffer is flushed after writing. Or
use an uncached memory area for the frame buffer - that's even easier.

Good luck!

/ magnus

Re: sh2a 7203 LCDC memory access

[Fabio Giovagnini]

Many thanks Magnus.
Very clear


On Tuesday 22 March 2011 13:21:48 Magnus Damm wrote:
> Hi Fabio,
> 
> On Tue, Mar 22, 2011 at 4:53 PM, Fabio Giovagnini
> 
> <fabio.giovagnini@aurion-tech.com> wrote:
> > Hi All,
> > I'd likt to keep you informed about my last discovering about LCDC of
> > sh2a 7203.
> > If I build the kernel with cache off, the image is clean and stable but
> > the performances are very very poor;
> > if I build with cache write back the performaces are very good but the
> > image is stable but sometimes dirty; fi I build with cache write through
> > the performances seems to be a little bit less than write back but the
> > image is stiil clean and stable.
> > Does this make sense?
> 
> Yes.
> 
> > How can I explain this behaviour?
> 
> The LCDC is an output device looking from the CPU point of view.
> 
> The write-though cache setting is OK for output even though you are
> not flushing the cache. It behaves the same as cache off for writing
> because the data is always written _through_ the cache directly to the
> memory that is read by the LCDC.
> 
> If you use copy-back (write-back) but picture is not OK then this
> means the data is left in the cache and has not been written out to
> memory. The copy-back cache is only writing to memory when running our
> of cache space or your are flushing the data to memory by software
> control.
> 
> You need to make sure your frame buffer is flushed after writing. Or
> use an uncached memory area for the frame buffer - that's even easier.
> 
> Good luck!
> 
> / magnus

-- 
Ing. Fabio Giovagnini

Aurion s.r.l.
P.I e C.F.
00885711200
skype: aurion.giovagnini
Tel. +39.051.594.78.24
Fax. +39.051.082.14.49
Cell. +39.335.83.50.919
www.aurion-tech.com

Re: sh2a 7203 LCDC memory access

[Paul Mundt]

On Tue, Mar 22, 2011 at 09:21:48PM +0900, Magnus Damm wrote:
> Hi Fabio,
> 
> On Tue, Mar 22, 2011 at 4:53 PM, Fabio Giovagnini
> <fabio.giovagnini@aurion-tech.com> wrote:
> > Hi All,
> > I'd likt to keep you informed about my last discovering about LCDC of sh2a
> > 7203.
> > If I build the kernel with cache off, the image is clean and stable but the
> > performances are very very poor;
> > if I build with cache write back the performaces are very good but the image
> > is stable but sometimes dirty; fi I build with cache write through the
> > performances seems to be a little bit less than write back but the image is
> > stiil clean and stable.
> > Does this make sense?
> 
> Yes.
> 
> > How can I explain this behaviour?
> 
> The LCDC is an output device looking from the CPU point of view.
> 
> The write-though cache setting is OK for output even though you are
> not flushing the cache. It behaves the same as cache off for writing
> because the data is always written _through_ the cache directly to the
> memory that is read by the LCDC.
> 
> If you use copy-back (write-back) but picture is not OK then this
> means the data is left in the cache and has not been written out to
> memory. The copy-back cache is only writing to memory when running our
> of cache space or your are flushing the data to memory by software
> control.
> 
> You need to make sure your frame buffer is flushed after writing. Or
> use an uncached memory area for the frame buffer - that's even easier.
> 
Note that the vast majority of SH-2/SH-2A development was done on
write-through caches, so it's quite possible that there are still some
outstanding issues with write-back mode.

That being said, the LCDC fb driver at least gets its DMA buffer
management right as we know from other CPU subtypes, so we already get
the cache management logic for free by virtue of the DMA mapping
interface.

Re: sh2a 7203 LCDC memory access

[Fabio Giovagnini]

I have compared the hw manual of sh4 7760 and sh2a 7203.
I saw that the 7760 has a DMA channel able to manage the LCDC, but sh2a has no 
fatures to manage the connected to DMA.
Is it true?


On Tuesday 22 March 2011 15:36:45 Paul Mundt wrote:
> On Tue, Mar 22, 2011 at 09:21:48PM +0900, Magnus Damm wrote:
> > Hi Fabio,
> > 
> > On Tue, Mar 22, 2011 at 4:53 PM, Fabio Giovagnini
> > 
> > <fabio.giovagnini@aurion-tech.com> wrote:
> > > Hi All,
> > > I'd likt to keep you informed about my last discovering about LCDC of
> > > sh2a 7203.
> > > If I build the kernel with cache off, the image is clean and stable but
> > > the performances are very very poor;
> > > if I build with cache write back the performaces are very good but the
> > > image is stable but sometimes dirty; fi I build with cache write
> > > through the performances seems to be a little bit less than write back
> > > but the image is stiil clean and stable.
> > > Does this make sense?
> > 
> > Yes.
> > 
> > > How can I explain this behaviour?
> > 
> > The LCDC is an output device looking from the CPU point of view.
> > 
> > The write-though cache setting is OK for output even though you are
> > not flushing the cache. It behaves the same as cache off for writing
> > because the data is always written _through_ the cache directly to the
> > memory that is read by the LCDC.
> > 
> > If you use copy-back (write-back) but picture is not OK then this
> > means the data is left in the cache and has not been written out to
> > memory. The copy-back cache is only writing to memory when running our
> > of cache space or your are flushing the data to memory by software
> > control.
> > 
> > You need to make sure your frame buffer is flushed after writing. Or
> > use an uncached memory area for the frame buffer - that's even easier.
> 
> Note that the vast majority of SH-2/SH-2A development was done on
> write-through caches, so it's quite possible that there are still some
> outstanding issues with write-back mode.
> 
> That being said, the LCDC fb driver at least gets its DMA buffer
> management right as we know from other CPU subtypes, so we already get
> the cache management logic for free by virtue of the DMA mapping
> interface.

-- 
Ing. Fabio Giovagnini

Aurion s.r.l.
P.I e C.F.
00885711200
skype: aurion.giovagnini
Tel. +39.051.594.78.24
Fax. +39.051.082.14.49
Cell. +39.335.83.50.919
www.aurion-tech.com

Re: sh2a 7203 LCDC memory access

[Paul Mundt]

On Tue, Mar 22, 2011 at 04:03:15PM +0100, Fabio Giovagnini wrote:
> I have compared the hw manual of sh4 7760 and sh2a 7203.
> I saw that the 7760 has a DMA channel able to manage the LCDC, but sh2a has no 
> fatures to manage the connected to DMA.
> Is it true?
> 
If that's what the manual says, I guess. Are you seriously expecting
someone to read the manuals for you and verify your interpretation of
them?

Re: sh2a 7203 LCDC memory access

[Fabio Giovagnini]

No, Paul
I do not expect this.
I only ask if any of the list had problem like mine.
Furthermore on the list there are many @renesas.com address.
They should be the GURU's like you and I expect that being payed by renesas 
are interested to help renesas customer (like me) to use better renesas 
products.
If I'm wrong tell me.

Ciao




On Tuesday 22 March 2011 16:28:59 Paul Mundt wrote:
> On Tue, Mar 22, 2011 at 04:03:15PM +0100, Fabio Giovagnini wrote:
> > I have compared the hw manual of sh4 7760 and sh2a 7203.
> > I saw that the 7760 has a DMA channel able to manage the LCDC, but sh2a
> > has no fatures to manage the connected to DMA.
> > Is it true?
> 
> If that's what the manual says, I guess. Are you seriously expecting
> someone to read the manuals for you and verify your interpretation of
> them?

-- 
Ing. Fabio Giovagnini

Aurion s.r.l.
P.I e C.F.
00885711200
skype: aurion.giovagnini
Tel. +39.051.594.78.24
Fax. +39.051.082.14.49
Cell. +39.335.83.50.919
www.aurion-tech.com

Re: sh2a 7203 LCDC memory access

[Paul Mundt]

On Tue, Mar 22, 2011 at 05:02:02PM +0100, Fabio Giovagnini wrote:
> No, Paul
> I do not expect this.
> I only ask if any of the list had problem like mine.
> Furthermore on the list there are many @renesas.com address.
> They should be the GURU's like you and I expect that being payed by renesas 
> are interested to help renesas customer (like me) to use better renesas 
> products.
> If I'm wrong tell me.
> 
This is not a sales, marketing, or customer support venue. There are many
SH-2A CPUs with different feature sets, if you are looking for something
in particular then you have appropriate channels for searching for parts
that meet your requirements as well as people that can assist you with
remedial problems.

You have the same documentation to work with as the rest of us, so unless
you're working on a prototype or unreleased CPU there's unlikely to be
anything anyone can tell you that isn't documented in public
specifications. Also keep in mind that we are talking about hundreds of
different CPUs, while I can keep track of some of the differences on
quite a number of them, I certainly couldn't tell you off the top of my
head what CPU subtype has DMA auto-request modes for the LCDC block
without looking at the same manuals you have.

At the end of the day this is a technical forum. If you have general
questions about given products or are looking for support outside of a
technical kernel development level you have a number of venues open to
you, including http://oss.renesas.com and whoever you locally source your
components from.

Re: sh2a 7203 LCDC memory access

[Fabio Giovagnini]

You are right about other available information's sources; but I could never 
have meaningfull answers rather than the list linux-sh.
This is why I write also stuff not exactly proper for the list.
Anyway I have only to sey THANKS to you and others answering to me.
At the end of the day this list is the sole place where I can learn more than 
I already know, and the sole place where I get answer that are not trivial.

Thanks and see you next


On Tuesday 22 March 2011 17:13:49 Paul Mundt wrote:
> On Tue, Mar 22, 2011 at 05:02:02PM +0100, Fabio Giovagnini wrote:
> > No, Paul
> > I do not expect this.
> > I only ask if any of the list had problem like mine.
> > Furthermore on the list there are many @renesas.com address.
> > They should be the GURU's like you and I expect that being payed by
> > renesas are interested to help renesas customer (like me) to use better
> > renesas products.
> > If I'm wrong tell me.
> 
> This is not a sales, marketing, or customer support venue. There are many
> SH-2A CPUs with different feature sets, if you are looking for something
> in particular then you have appropriate channels for searching for parts
> that meet your requirements as well as people that can assist you with
> remedial problems.
> 
> You have the same documentation to work with as the rest of us, so unless
> you're working on a prototype or unreleased CPU there's unlikely to be
> anything anyone can tell you that isn't documented in public
> specifications. Also keep in mind that we are talking about hundreds of
> different CPUs, while I can keep track of some of the differences on
> quite a number of them, I certainly couldn't tell you off the top of my
> head what CPU subtype has DMA auto-request modes for the LCDC block
> without looking at the same manuals you have.
> 
> At the end of the day this is a technical forum. If you have general
> questions about given products or are looking for support outside of a
> technical kernel development level you have a number of venues open to
> you, including http://oss.renesas.com and whoever you locally source your
> components from.

-- 
Ing. Fabio Giovagnini

Aurion s.r.l.
P.I e C.F.
00885711200
skype: aurion.giovagnini
Tel. +39.051.594.78.24
Fax. +39.051.082.14.49
Cell. +39.335.83.50.919
www.aurion-tech.com