From: Russell King - ARM Linux <linux@arm.linux.org.uk>
To: linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 2/2] arm: Add ARM ERRATA 782773 workaround
Date: Thu, 13 Sep 2012 17:20:57 +0000 [thread overview]
Message-ID: <20120913172057.GB13739@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <20120913010041.GD7622@verge.net.au>
On Thu, Sep 13, 2012 at 10:00:42AM +0900, Simon Horman wrote:
> +config ARM_ERRATA_782773
> + bool "ARM errata: Updating a translation entry might cause an unexpected translation fault"
> + depends on CPU_V7
> + help
> + This option enables the workaround for the 782773 Cortex-A9 (all r0,
> + r2 and r3 revisions) erratum. It might cause MMU exception in case
> + page table walk happens just after updating the existing
> + with setting page table in L1 data cache.
What if we're running on a SMP system where the L1 caches are mandated
to be in write-allocate mode? This write will immediately cause the
cache line to be brought back into the cache.
This sounds like a broken work-around to me.
next prev parent reply other threads:[~2012-09-13 17:20 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-12 7:14 [PATCH 0/2] ARM ERRATA 775420 and 782773 workarounds Simon Horman
2012-09-12 7:14 ` [PATCH 1/2] arm: Add ARM ERRATA 775420 workaround Simon Horman
2012-09-20 9:58 ` Catalin Marinas
2012-09-21 1:04 ` Simon Horman
2012-09-21 8:29 ` Catalin Marinas
2012-09-12 7:14 ` [PATCH 2/2] arm: Add ARM ERRATA 782773 workaround Simon Horman
2012-09-12 17:59 ` Stephen Boyd
2012-09-13 1:00 ` Simon Horman
2012-09-13 17:20 ` Russell King - ARM Linux [this message]
2012-09-20 9:32 ` Catalin Marinas
2012-09-20 9:35 ` Catalin Marinas
2012-09-21 1:00 ` Simon Horman
2012-09-28 1:02 ` Simon Horman
2012-09-28 8:38 ` Catalin Marinas
2012-10-03 2:19 ` Simon Horman
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