From mboxrd@z Thu Jan 1 00:00:00 1970 From: Will Deacon Date: Thu, 13 Dec 2012 10:51:09 +0000 Subject: Re: [RFC PATCH v2 3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations Message-Id: <20121213105109.GB26540@mudshark.cambridge.arm.com> List-Id: References: <20120919134658.GA2111@linaro.org> <20120920102514.GD4588@e102568-lin.cambridge.arm.com> <20120920110439.GB2117@linaro.org> <20121211163313.GG16759@mudshark.cambridge.arm.com> <20121211163843.GH16759@mudshark.cambridge.arm.com> <50C7C16B.7050106@codeaurora.org> <20121212103338.GB23022@e102568-lin.cambridge.arm.com> <20121212133650.GJ6195@mudshark.cambridge.arm.com> In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: linux-arm-kernel@lists.infradead.org On Thu, Dec 13, 2012 at 08:09:33AM +0000, Guennadi Liakhovetski wrote: > On Wed, 12 Dec 2012, Will Deacon wrote: > > Back to the case in hand.... Lorenzo just pointed out to me that the > > finished in question (sh7372_do_idle_sysc) calls v7_flush_dcache_all, so > > the louis stuff should be irrelevant. The problem may actually be that the > > finisher disables the L2 cache prior to cleaning/invalidating it, which is > > the opposite order to that described by the A8 TRM. > > > > Guennadi -- can you try moving the kernel_flush call before the L2 disable > > in sh7372_do_idle_sysc please? > > Yes, this works too. That's good to know. Please can you send a patch for that? The sequence currently being used by the finisher *is* buggy, and should be fixed independently of the louis stuff. Cheers, Will