From: Simon Horman <horms@verge.net.au>
To: linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] ARM: shmobile: r8a7779: Correct TMU clock support again
Date: Thu, 14 Feb 2013 04:16:52 +0000 [thread overview]
Message-ID: <20130214041651.GB6036@verge.net.au> (raw)
In-Reply-To: <CANqRtoQtROi1cD3MmykhKLqY+1Y2=f+1Qkmw2bjAaP6yZRPW=Q@mail.gmail.com>
On Thu, Feb 14, 2013 at 01:04:35PM +0900, Magnus Damm wrote:
> On Thu, Feb 14, 2013 at 1:03 PM, Kuninori Morimoto
> <kuninori.morimoto.gx@renesas.com> wrote:
> >
> > Hi Simon
> >
> >> This partially reverts 58079fa7d54a0929d304054ee759187a2ccd3cdf
> >> (ARM: shmobile: r8a7779: Correct TMU clock support) and fixes
> >> a regression introduced by that patch.
> >>
> >> Although the documentation I have indicates that the patch above is
> >> correct it appears that the change causes the Marzen board to fail to boot
> >> as follows.
> > (snip)
> >> --- a/arch/arm/mach-shmobile/clock-r8a7779.c
> >> +++ b/arch/arm/mach-shmobile/clock-r8a7779.c
> >> @@ -161,7 +161,7 @@ static struct clk_lookup lookups[] = {
> >> CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
> >> CLKDEV_DEV_ID("ohci-platform.0", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
> >> CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
> >> - CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
> >> + CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
> >> CLKDEV_DEV_ID("sh_tmu.2", &mstp_clks[MSTP014]), /* TMU02 */
> >> CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
> >> CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
> >
> > Really ???
I am surprised too!
> > Is MSTP value of TMU01 same as TMU00 ?
With the patch above the board appears to boot.
Without the patch, it doesn't.
> Usually, the TMU channels are bundled together. So TMU00 may be for
> channel 0->3 and TMU01 for 4->6.
Ok, so in that case the correct value for "sh_tmu.2" might actually
be MSTP016 or MSTP015 depending on the bundle size. I am unsure how to test
sh_tmu.2.
However, the documentation I have seems to talk about channels
being TMU0..TMU2 and control of them being via MSTP016..MSTP014.
I.e. what the code currently is but not what seems to work for
TMU1 in practice.
next prev parent reply other threads:[~2013-02-14 4:16 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-05 3:28 [PATCH] ARM: shmobile: r8a7779: Correct TMU clock support Simon Horman
2013-02-05 3:30 ` Magnus Damm
2013-02-14 3:43 ` [PATCH] ARM: shmobile: r8a7779: Correct TMU clock support again Simon Horman
2013-02-14 4:03 ` Kuninori Morimoto
2013-02-14 4:04 ` Magnus Damm
2013-02-14 4:12 ` Kuninori Morimoto
2013-02-14 4:14 ` Kuninori Morimoto
2013-02-14 4:20 ` Simon Horman
2013-02-14 4:25 ` Kuninori Morimoto
2013-02-14 4:36 ` Simon Horman
2013-02-14 4:42 ` Simon Horman
2013-02-14 5:20 ` Magnus Damm
2013-02-14 8:34 ` Simon Horman
2013-02-14 4:16 ` Simon Horman [this message]
2013-02-14 9:10 ` Paul Mundt
2013-02-14 16:08 ` Simon Horman
2013-02-14 16:18 ` Paul Mundt
2013-02-15 13:53 ` Simon Horman
2013-02-18 0:52 ` Simon Horman
2013-02-15 13:35 ` Simon Horman
-- strict thread matches above, loose matches on Subject: below --
2013-02-19 3:49 [GIT PULL] Renesas ARM-based SoC for v3.9 #5 Simon Horman
2013-02-19 3:49 ` [PATCH] ARM: shmobile: r8a7779: Correct TMU clock support again Simon Horman
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