* [PATCH 0/2] R8A7779/Marzen: HPB-DMAC support for SDHI0 @ 2013-08-08 21:40 Sergei Shtylyov 2013-08-08 21:42 ` [PATCH 1/2] ARM: shmobile: r8a7779: add HPB-DMAC support Sergei Shtylyov 2013-08-08 21:44 ` [PATCH 2/2] ARM: shmobile: Marzen: enable DMA for SDHI0 Sergei Shtylyov 0 siblings, 2 replies; 8+ messages in thread From: Sergei Shtylyov @ 2013-08-08 21:40 UTC (permalink / raw) To: linux-arm-kernel Hello. Here's the set of 2 patches against the Simon Horman's 'renesas.git' repo, 'renesas-devel-20130807' tag. Here we add the HPB-DMAC platform code working on R8A7779 and enable DMA for SDHI0 on Marzen. The patchset depends on the R-Car HPB-DMAC driver patch posted earlier (we are still working on it). It has been actually tested on top of the 'renesas.git' unlike the R8A7778/BOCK-W patchset (which, unfortunately, doesn't work). [1/2] ARM: shmobile: r8a7779: add HPB-DMAC support [2/2] ARM: shmobile: Marzen: enable DMA for SDHI0 WBR, Sergei ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] ARM: shmobile: r8a7779: add HPB-DMAC support 2013-08-08 21:40 [PATCH 0/2] R8A7779/Marzen: HPB-DMAC support for SDHI0 Sergei Shtylyov @ 2013-08-08 21:42 ` Sergei Shtylyov 2013-08-09 1:33 ` Kuninori Morimoto 2013-08-08 21:44 ` [PATCH 2/2] ARM: shmobile: Marzen: enable DMA for SDHI0 Sergei Shtylyov 1 sibling, 1 reply; 8+ messages in thread From: Sergei Shtylyov @ 2013-08-08 21:42 UTC (permalink / raw) To: linux-arm-kernel From: Max Filippov <max.filippov@cogentembedded.com> Add HPB-DMAC platform device on R8A7779 SoC along with its slave and channel configurations. Signed-off-by: Max Filippov <max.filippov@cogentembedded.com> [Sergei: moved *enum* declaring HPB-DMAC slave IDs from now removed <mach/dma.h> to <mach/r8a7779.h>, removed #include <mach/dma.h> from setup-r8a7779.c, removed SSI-related *enum* values and SSI-related data from hpb_dmae_slaves[] and hpb_dmae_channels[], added ASYNCMDR.ASBTMD20 and ASYNCMDR.ASMD20 fields/values, fixed comments to ASYNCMDR.ASBTMD2[123] and ASYNCMDR.ASMD2[123] fields/values, moved comments after the element initializers of hpb_dmae_channels[].] Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- arch/arm/mach-shmobile/include/mach/r8a7779.h | 7 + arch/arm/mach-shmobile/setup-r8a7779.c | 132 ++++++++++++++++++++++++++ 2 files changed, 139 insertions(+) Index: renesas/arch/arm/mach-shmobile/include/mach/r8a7779.h =================================--- renesas.orig/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ renesas/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -5,6 +5,13 @@ #include <linux/pm_domain.h> #include <linux/sh_eth.h> +/* HPB-DMA slave IDs */ +enum { + HPBDMA_SLAVE_DUMMY, + HPBDMA_SLAVE_SDHI0_TX, + HPBDMA_SLAVE_SDHI0_RX, +}; + struct platform_device; struct r8a7779_pm_ch { Index: renesas/arch/arm/mach-shmobile/setup-r8a7779.c =================================--- renesas.orig/arch/arm/mach-shmobile/setup-r8a7779.c +++ renesas/arch/arm/mach-shmobile/setup-r8a7779.c @@ -25,6 +25,7 @@ #include <linux/irqchip.h> #include <linux/irqchip/arm-gic.h> #include <linux/of_platform.h> +#include <linux/platform_data/dma-rcar-hpbdma.h> #include <linux/platform_data/gpio-rcar.h> #include <linux/platform_data/irq-renesas-intc-irqpin.h> #include <linux/platform_device.h> @@ -605,6 +606,136 @@ static struct resource ether_resources[] }, }; +/* HPB-DMA */ + +/* Asynchronous mode register bits */ +#define ASYNCMDR_ASMD41_MASK BIT(19) /* SDHI3 */ +#define ASYNCMDR_ASMD41_SINGLE BIT(19) /* SDHI3 */ +#define ASYNCMDR_ASMD41_MULTI 0 /* SDHI3 */ +#define ASYNCMDR_ASBTMD41_MASK BIT(18) /* SDHI3 */ +#define ASYNCMDR_ASBTMD41_BURST BIT(18) /* SDHI3 */ +#define ASYNCMDR_ASBTMD41_NBURST 0 /* SDHI3 */ +#define ASYNCMDR_ASMD40_MASK BIT(17) /* SDHI3 */ +#define ASYNCMDR_ASMD40_SINGLE BIT(17) /* SDHI3 */ +#define ASYNCMDR_ASMD40_MULTI 0 /* SDHI3 */ +#define ASYNCMDR_ASBTMD40_MASK BIT(16) /* SDHI3 */ +#define ASYNCMDR_ASBTMD40_BURST BIT(16) /* SDHI3 */ +#define ASYNCMDR_ASBTMD40_NBURST 0 /* SDHI3 */ +#define ASYNCMDR_ASMD39_MASK BIT(15) /* SDHI3 */ +#define ASYNCMDR_ASMD39_SINGLE BIT(15) /* SDHI3 */ +#define ASYNCMDR_ASMD39_MULTI 0 /* SDHI3 */ +#define ASYNCMDR_ASBTMD39_MASK BIT(14) /* SDHI3 */ +#define ASYNCMDR_ASBTMD39_BURST BIT(14) /* SDHI3 */ +#define ASYNCMDR_ASBTMD39_NBURST 0 /* SDHI3 */ +#define ASYNCMDR_ASMD27_MASK BIT(13) /* SDHI2 */ +#define ASYNCMDR_ASMD27_SINGLE BIT(13) /* SDHI2 */ +#define ASYNCMDR_ASMD27_MULTI 0 /* SDHI2 */ +#define ASYNCMDR_ASBTMD27_MASK BIT(12) /* SDHI2 */ +#define ASYNCMDR_ASBTMD27_BURST BIT(12) /* SDHI2 */ +#define ASYNCMDR_ASBTMD27_NBURST 0 /* SDHI2 */ +#define ASYNCMDR_ASMD26_MASK BIT(11) /* SDHI2 */ +#define ASYNCMDR_ASMD26_SINGLE BIT(11) /* SDHI2 */ +#define ASYNCMDR_ASMD26_MULTI 0 /* SDHI2 */ +#define ASYNCMDR_ASBTMD26_MASK BIT(10) /* SDHI2 */ +#define ASYNCMDR_ASBTMD26_BURST BIT(10) /* SDHI2 */ +#define ASYNCMDR_ASBTMD26_NBURST 0 /* SDHI2 */ +#define ASYNCMDR_ASMD25_MASK BIT(9) /* SDHI2 */ +#define ASYNCMDR_ASMD25_SINGLE BIT(9) /* SDHI2 */ +#define ASYNCMDR_ASMD25_MULTI 0 /* SDHI2 */ +#define ASYNCMDR_ASBTMD25_MASK BIT(8) /* SDHI2 */ +#define ASYNCMDR_ASBTMD25_BURST BIT(8) /* SDHI2 */ +#define ASYNCMDR_ASBTMD25_NBURST 0 /* SDHI2 */ +#define ASYNCMDR_ASMD23_MASK BIT(7) /* SDHI0 */ +#define ASYNCMDR_ASMD23_SINGLE BIT(7) /* SDHI0 */ +#define ASYNCMDR_ASMD23_MULTI 0 /* SDHI0 */ +#define ASYNCMDR_ASBTMD23_MASK BIT(6) /* SDHI0 */ +#define ASYNCMDR_ASBTMD23_BURST BIT(6) /* SDHI0 */ +#define ASYNCMDR_ASBTMD23_NBURST 0 /* SDHI0 */ +#define ASYNCMDR_ASMD22_MASK BIT(5) /* SDHI0 */ +#define ASYNCMDR_ASMD22_SINGLE BIT(5) /* SDHI0 */ +#define ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */ +#define ASYNCMDR_ASBTMD22_MASK BIT(4) /* SDHI0 */ +#define ASYNCMDR_ASBTMD22_BURST BIT(4) /* SDHI0 */ +#define ASYNCMDR_ASBTMD22_NBURST 0 /* SDHI0 */ +#define ASYNCMDR_ASMD21_MASK BIT(3) /* SDHI0 */ +#define ASYNCMDR_ASMD21_SINGLE BIT(3) /* SDHI0 */ +#define ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ +#define ASYNCMDR_ASBTMD21_MASK BIT(2) /* SDHI0 */ +#define ASYNCMDR_ASBTMD21_BURST BIT(2) /* SDHI0 */ +#define ASYNCMDR_ASBTMD21_NBURST 0 /* SDHI0 */ +#define ASYNCMDR_ASMD20_MASK BIT(1) /* SDHI1 */ +#define ASYNCMDR_ASMD20_SINGLE BIT(1) /* SDHI1 */ +#define ASYNCMDR_ASMD20_MULTI 0 /* SDHI1 */ +#define ASYNCMDR_ASBTMD20_MASK BIT(0) /* SDHI1 */ +#define ASYNCMDR_ASBTMD20_BURST BIT(0) /* SDHI1 */ +#define ASYNCMDR_ASBTMD20_NBURST 0 /* SDHI1 */ + +static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { + { + .id = HPBDMA_SLAVE_SDHI0_TX, + .addr = 0xffe4c000 + 0x30, + .dcr = DCR_SPDS_16BIT | DCR_DMDL | DCR_DPDS_16BIT, + .rstr = ASYNCRSTR_ASRST21 | ASYNCRSTR_ASRST22 | + ASYNCRSTR_ASRST23, + .mdr = ASYNCMDR_ASMD21_SINGLE | ASYNCMDR_ASBTMD21_NBURST, + .mdm = ASYNCMDR_ASMD21_MASK | ASYNCMDR_ASBTMD21_MASK, + .port = 0x0D0C, + .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, + .dma_ch = 21, + }, { + .id = HPBDMA_SLAVE_SDHI0_RX, + .addr = 0xffe4c000 + 0x30, + .dcr = DCR_SMDL | DCR_SPDS_16BIT | DCR_DPDS_16BIT, + .rstr = ASYNCRSTR_ASRST21 | ASYNCRSTR_ASRST22 | + ASYNCRSTR_ASRST23, + .mdr = ASYNCMDR_ASMD22_SINGLE | ASYNCMDR_ASBTMD22_NBURST, + .mdm = ASYNCMDR_ASMD22_MASK | ASYNCMDR_ASBTMD22_MASK, + .port = 0x0D0C, + .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, + .dma_ch = 22, + }, +}; + +static const struct hpb_dmae_channel hpb_dmae_channels[] = { + HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ + HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ +}; + +static struct hpb_dmae_pdata dma_platform_data __initdata = { + .slaves = hpb_dmae_slaves, + .num_slaves = ARRAY_SIZE(hpb_dmae_slaves), + .channels = hpb_dmae_channels, + .num_channels = ARRAY_SIZE(hpb_dmae_channels), + .ts_shift = { + [XMIT_SZ_8BIT] = 0, + [XMIT_SZ_16BIT] = 1, + [XMIT_SZ_32BIT] = 2, + }, + .num_hw_channels = 44, +}; + +static struct resource hpb_dmae_resources[] __initdata = { + /* Channel registers */ + DEFINE_RES_MEM(0xffc08000, 0x1000), + /* Common registers */ + DEFINE_RES_MEM(0xffc09000, 0x170), + /* Asynchronous reset registers */ + DEFINE_RES_MEM(0xffc00300, 4), + /* Asynchronous mode registers */ + DEFINE_RES_MEM(0xffc00400, 4), + /* IRQ for DMA channels */ + DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ), +}; + +static void __init r8a7779_register_hpb_dmae(void) +{ + platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1, + hpb_dmae_resources, + ARRAY_SIZE(hpb_dmae_resources), + &dma_platform_data, + sizeof(dma_platform_data)); +} + static struct platform_device *r8a7779_devices_dt[] __initdata = { &scif0_device, &scif1_device, @@ -638,6 +769,7 @@ void __init r8a7779_add_standard_devices ARRAY_SIZE(r8a7779_devices_dt)); platform_add_devices(r8a7779_standard_devices, ARRAY_SIZE(r8a7779_standard_devices)); + r8a7779_register_hpb_dmae(); } void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata) ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] ARM: shmobile: r8a7779: add HPB-DMAC support 2013-08-08 21:42 ` [PATCH 1/2] ARM: shmobile: r8a7779: add HPB-DMAC support Sergei Shtylyov @ 2013-08-09 1:33 ` Kuninori Morimoto 0 siblings, 0 replies; 8+ messages in thread From: Kuninori Morimoto @ 2013-08-09 1:33 UTC (permalink / raw) To: linux-arm-kernel Hi > From: Max Filippov <max.filippov@cogentembedded.com> > > Add HPB-DMAC platform device on R8A7779 SoC along with its slave and channel > configurations. > > Signed-off-by: Max Filippov <max.filippov@cogentembedded.com> > [Sergei: moved *enum* declaring HPB-DMAC slave IDs from now removed <mach/dma.h> > to <mach/r8a7779.h>, removed #include <mach/dma.h> from setup-r8a7779.c, removed > SSI-related *enum* values and SSI-related data from hpb_dmae_slaves[] and > hpb_dmae_channels[], added ASYNCMDR.ASBTMD20 and ASYNCMDR.ASMD20 fields/values, > fixed comments to ASYNCMDR.ASBTMD2[123] and ASYNCMDR.ASMD2[123] fields/values, > moved comments after the element initializers of hpb_dmae_channels[].] > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> (snip) > +/* HPB-DMA */ > + > +/* Asynchronous mode register bits */ > +#define ASYNCMDR_ASMD41_MASK BIT(19) /* SDHI3 */ > +#define ASYNCMDR_ASMD41_SINGLE BIT(19) /* SDHI3 */ > +#define ASYNCMDR_ASMD41_MULTI 0 /* SDHI3 */ > +#define ASYNCMDR_ASBTMD41_MASK BIT(18) /* SDHI3 */ > +#define ASYNCMDR_ASBTMD41_BURST BIT(18) /* SDHI3 */ > +#define ASYNCMDR_ASBTMD41_NBURST 0 /* SDHI3 */ > +#define ASYNCMDR_ASMD40_MASK BIT(17) /* SDHI3 */ > +#define ASYNCMDR_ASMD40_SINGLE BIT(17) /* SDHI3 */ > +#define ASYNCMDR_ASMD40_MULTI 0 /* SDHI3 */ > +#define ASYNCMDR_ASBTMD40_MASK BIT(16) /* SDHI3 */ > +#define ASYNCMDR_ASBTMD40_BURST BIT(16) /* SDHI3 */ > +#define ASYNCMDR_ASBTMD40_NBURST 0 /* SDHI3 */ > +#define ASYNCMDR_ASMD39_MASK BIT(15) /* SDHI3 */ > +#define ASYNCMDR_ASMD39_SINGLE BIT(15) /* SDHI3 */ > +#define ASYNCMDR_ASMD39_MULTI 0 /* SDHI3 */ > +#define ASYNCMDR_ASBTMD39_MASK BIT(14) /* SDHI3 */ > +#define ASYNCMDR_ASBTMD39_BURST BIT(14) /* SDHI3 */ > +#define ASYNCMDR_ASBTMD39_NBURST 0 /* SDHI3 */ > +#define ASYNCMDR_ASMD27_MASK BIT(13) /* SDHI2 */ > +#define ASYNCMDR_ASMD27_SINGLE BIT(13) /* SDHI2 */ > +#define ASYNCMDR_ASMD27_MULTI 0 /* SDHI2 */ > +#define ASYNCMDR_ASBTMD27_MASK BIT(12) /* SDHI2 */ > +#define ASYNCMDR_ASBTMD27_BURST BIT(12) /* SDHI2 */ > +#define ASYNCMDR_ASBTMD27_NBURST 0 /* SDHI2 */ > +#define ASYNCMDR_ASMD26_MASK BIT(11) /* SDHI2 */ > +#define ASYNCMDR_ASMD26_SINGLE BIT(11) /* SDHI2 */ > +#define ASYNCMDR_ASMD26_MULTI 0 /* SDHI2 */ > +#define ASYNCMDR_ASBTMD26_MASK BIT(10) /* SDHI2 */ > +#define ASYNCMDR_ASBTMD26_BURST BIT(10) /* SDHI2 */ > +#define ASYNCMDR_ASBTMD26_NBURST 0 /* SDHI2 */ > +#define ASYNCMDR_ASMD25_MASK BIT(9) /* SDHI2 */ > +#define ASYNCMDR_ASMD25_SINGLE BIT(9) /* SDHI2 */ > +#define ASYNCMDR_ASMD25_MULTI 0 /* SDHI2 */ > +#define ASYNCMDR_ASBTMD25_MASK BIT(8) /* SDHI2 */ > +#define ASYNCMDR_ASBTMD25_BURST BIT(8) /* SDHI2 */ > +#define ASYNCMDR_ASBTMD25_NBURST 0 /* SDHI2 */ > +#define ASYNCMDR_ASMD23_MASK BIT(7) /* SDHI0 */ > +#define ASYNCMDR_ASMD23_SINGLE BIT(7) /* SDHI0 */ > +#define ASYNCMDR_ASMD23_MULTI 0 /* SDHI0 */ > +#define ASYNCMDR_ASBTMD23_MASK BIT(6) /* SDHI0 */ > +#define ASYNCMDR_ASBTMD23_BURST BIT(6) /* SDHI0 */ > +#define ASYNCMDR_ASBTMD23_NBURST 0 /* SDHI0 */ > +#define ASYNCMDR_ASMD22_MASK BIT(5) /* SDHI0 */ > +#define ASYNCMDR_ASMD22_SINGLE BIT(5) /* SDHI0 */ > +#define ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */ > +#define ASYNCMDR_ASBTMD22_MASK BIT(4) /* SDHI0 */ > +#define ASYNCMDR_ASBTMD22_BURST BIT(4) /* SDHI0 */ > +#define ASYNCMDR_ASBTMD22_NBURST 0 /* SDHI0 */ > +#define ASYNCMDR_ASMD21_MASK BIT(3) /* SDHI0 */ > +#define ASYNCMDR_ASMD21_SINGLE BIT(3) /* SDHI0 */ > +#define ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ > +#define ASYNCMDR_ASBTMD21_MASK BIT(2) /* SDHI0 */ > +#define ASYNCMDR_ASBTMD21_BURST BIT(2) /* SDHI0 */ > +#define ASYNCMDR_ASBTMD21_NBURST 0 /* SDHI0 */ > +#define ASYNCMDR_ASMD20_MASK BIT(1) /* SDHI1 */ > +#define ASYNCMDR_ASMD20_SINGLE BIT(1) /* SDHI1 */ > +#define ASYNCMDR_ASMD20_MULTI 0 /* SDHI1 */ > +#define ASYNCMDR_ASBTMD20_MASK BIT(0) /* SDHI1 */ > +#define ASYNCMDR_ASBTMD20_BURST BIT(0) /* SDHI1 */ > +#define ASYNCMDR_ASBTMD20_NBURST 0 /* SDHI1 */ Your "r8a7778"'s HPB-DMAC patch had "used" ASYNCMDR_xxx only, and here, r8a7779 seems have "all" ASYNCMDR_xxx. I don't care about it, but, above "all" settings seems doesn't have channel 43 (= 23/22 bit) and channel 24 (= 21/20 bit). Best regards --- Kuninori Morimoto ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/2] ARM: shmobile: Marzen: enable DMA for SDHI0 2013-08-08 21:40 [PATCH 0/2] R8A7779/Marzen: HPB-DMAC support for SDHI0 Sergei Shtylyov 2013-08-08 21:42 ` [PATCH 1/2] ARM: shmobile: r8a7779: add HPB-DMAC support Sergei Shtylyov @ 2013-08-08 21:44 ` Sergei Shtylyov 2013-09-28 20:12 ` [PATCH 2/2] ARM: shmobile: marzen: enable HPB-DMAC in defconfig Sergei Shtylyov ` (2 more replies) 1 sibling, 3 replies; 8+ messages in thread From: Sergei Shtylyov @ 2013-08-08 21:44 UTC (permalink / raw) To: linux-arm-kernel From: Max Filippov <max.filippov@cogentembedded.com> Pass HPB-DMA slave IDs in the SDHI0 platform data to enable DMA in the SDHI driver. Signed-off-by: Max Filippov <max.filippov@cogentembedded.com> [Sergei: removed #include <mach/dma.h>] Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- arch/arm/mach-shmobile/board-marzen.c | 2 ++ 1 file changed, 2 insertions(+) Index: renesas/arch/arm/mach-shmobile/board-marzen.c =================================--- renesas.orig/arch/arm/mach-shmobile/board-marzen.c +++ renesas/arch/arm/mach-shmobile/board-marzen.c @@ -122,6 +122,8 @@ static struct resource sdhi0_resources[] }; static struct sh_mobile_sdhi_info sdhi0_platform_data = { + .dma_slave_tx = HPBDMA_SLAVE_SDHI0_TX, + .dma_slave_rx = HPBDMA_SLAVE_SDHI0_RX, .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT, .tmio_caps = MMC_CAP_SD_HIGHSPEED, }; ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/2] ARM: shmobile: marzen: enable HPB-DMAC in defconfig 2013-08-08 21:44 ` [PATCH 2/2] ARM: shmobile: Marzen: enable DMA for SDHI0 Sergei Shtylyov @ 2013-09-28 20:12 ` Sergei Shtylyov 2013-09-30 0:49 ` Simon Horman 2013-10-02 6:20 ` [PATCH 2/2] ARM: shmobile: marzen: enable INTC IRQ and fixup SMSC IRQ number Kuninori Morimoto 2013-10-02 8:06 ` Simon Horman 2 siblings, 1 reply; 8+ messages in thread From: Sergei Shtylyov @ 2013-09-28 20:12 UTC (permalink / raw) To: linux-arm-kernel Enable HPB-DMAC driver in 'marzen_defconfig'. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- The patch is against 'renesas-devel-20130927v2' tag of the 'renesas.git' repo. arch/arm/configs/marzen_defconfig | 2 ++ 1 file changed, 2 insertions(+) Index: renesas/arch/arm/configs/marzen_defconfig =================================--- renesas.orig/arch/arm/configs/marzen_defconfig +++ renesas/arch/arm/configs/marzen_defconfig @@ -106,6 +106,8 @@ CONFIG_USB_STORAGE=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y +CONFIG_DMADEVICES=y +CONFIG_RCAR_HPB_DMAE=y CONFIG_UIO=y CONFIG_UIO_PDRV_GENIRQ=y # CONFIG_IOMMU_SUPPORT is not set ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] ARM: shmobile: marzen: enable HPB-DMAC in defconfig 2013-09-28 20:12 ` [PATCH 2/2] ARM: shmobile: marzen: enable HPB-DMAC in defconfig Sergei Shtylyov @ 2013-09-30 0:49 ` Simon Horman 0 siblings, 0 replies; 8+ messages in thread From: Simon Horman @ 2013-09-30 0:49 UTC (permalink / raw) To: linux-arm-kernel On Sun, Sep 29, 2013 at 12:12:33AM +0400, Sergei Shtylyov wrote: > Enable HPB-DMAC driver in 'marzen_defconfig'. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Thanks, I will queue this up for v3.13. ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/2] ARM: shmobile: marzen: enable INTC IRQ and fixup SMSC IRQ number 2013-08-08 21:44 ` [PATCH 2/2] ARM: shmobile: Marzen: enable DMA for SDHI0 Sergei Shtylyov 2013-09-28 20:12 ` [PATCH 2/2] ARM: shmobile: marzen: enable HPB-DMAC in defconfig Sergei Shtylyov @ 2013-10-02 6:20 ` Kuninori Morimoto 2013-10-02 8:06 ` Simon Horman 2 siblings, 0 replies; 8+ messages in thread From: Kuninori Morimoto @ 2013-10-02 6:20 UTC (permalink / raw) To: linux-sh This patch adds missing INTC IRQ settings, and fixup miss-setting of SMSC IRQ number. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> --- arch/arm/boot/dts/r8a7779-marzen-reference.dts | 8 ++++++-- arch/arm/mach-shmobile/board-marzen-reference.c | 1 + 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts index 6d55083..ab4110a 100644 --- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts +++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts @@ -42,8 +42,8 @@ pinctrl-names = "default"; phy-mode = "mii"; - interrupt-parent = <&gic>; - interrupts = <0 28 0x4>; + interrupt-parent = <&irqpin0>; + interrupts = <1 0>; /* IRQ1: hwirq 1 on irqpin0 */ reg-io-width = <4>; vddvario-supply = <&fixedregulator3v3>; vdd33a-supply = <&fixedregulator3v3>; @@ -63,6 +63,10 @@ }; }; +&irqpin0 { + status = "okay"; +}; + &pfc { pinctrl-0 = <&scif2_pins &scif4_pins &sdhi0_pins>; pinctrl-names = "default"; diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c index 3f4250a..2773936 100644 --- a/arch/arm/mach-shmobile/board-marzen-reference.c +++ b/arch/arm/mach-shmobile/board-marzen-reference.c @@ -28,6 +28,7 @@ static void __init marzen_init(void) { r8a7779_add_standard_devices_dt(); + r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */ } static const char *marzen_boards_compat_dt[] __initdata = { -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] ARM: shmobile: marzen: enable INTC IRQ and fixup SMSC IRQ number 2013-08-08 21:44 ` [PATCH 2/2] ARM: shmobile: Marzen: enable DMA for SDHI0 Sergei Shtylyov 2013-09-28 20:12 ` [PATCH 2/2] ARM: shmobile: marzen: enable HPB-DMAC in defconfig Sergei Shtylyov 2013-10-02 6:20 ` [PATCH 2/2] ARM: shmobile: marzen: enable INTC IRQ and fixup SMSC IRQ number Kuninori Morimoto @ 2013-10-02 8:06 ` Simon Horman 2 siblings, 0 replies; 8+ messages in thread From: Simon Horman @ 2013-10-02 8:06 UTC (permalink / raw) To: linux-sh On Tue, Oct 01, 2013 at 11:20:01PM -0700, Kuninori Morimoto wrote: > This patch adds missing INTC IRQ settings, > and fixup miss-setting of SMSC IRQ number. > > Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Please split this into two patches. 1. A DT patch that modifies r8a7779-marzen-reference.dts 2. A board patch that modifies board-marzen-reference.c > --- > arch/arm/boot/dts/r8a7779-marzen-reference.dts | 8 ++++++-- > arch/arm/mach-shmobile/board-marzen-reference.c | 1 + > 2 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts > index 6d55083..ab4110a 100644 > --- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts > +++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts > @@ -42,8 +42,8 @@ > pinctrl-names = "default"; > > phy-mode = "mii"; > - interrupt-parent = <&gic>; > - interrupts = <0 28 0x4>; > + interrupt-parent = <&irqpin0>; > + interrupts = <1 0>; /* IRQ1: hwirq 1 on irqpin0 */ > reg-io-width = <4>; > vddvario-supply = <&fixedregulator3v3>; > vdd33a-supply = <&fixedregulator3v3>; > @@ -63,6 +63,10 @@ > }; > }; > > +&irqpin0 { > + status = "okay"; > +}; > + > &pfc { > pinctrl-0 = <&scif2_pins &scif4_pins &sdhi0_pins>; > pinctrl-names = "default"; > diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c > index 3f4250a..2773936 100644 > --- a/arch/arm/mach-shmobile/board-marzen-reference.c > +++ b/arch/arm/mach-shmobile/board-marzen-reference.c > @@ -28,6 +28,7 @@ > static void __init marzen_init(void) > { > r8a7779_add_standard_devices_dt(); > + r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */ > } > > static const char *marzen_boards_compat_dt[] __initdata = { > -- > 1.7.9.5 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-sh" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2013-10-02 8:06 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-08-08 21:40 [PATCH 0/2] R8A7779/Marzen: HPB-DMAC support for SDHI0 Sergei Shtylyov 2013-08-08 21:42 ` [PATCH 1/2] ARM: shmobile: r8a7779: add HPB-DMAC support Sergei Shtylyov 2013-08-09 1:33 ` Kuninori Morimoto 2013-08-08 21:44 ` [PATCH 2/2] ARM: shmobile: Marzen: enable DMA for SDHI0 Sergei Shtylyov 2013-09-28 20:12 ` [PATCH 2/2] ARM: shmobile: marzen: enable HPB-DMAC in defconfig Sergei Shtylyov 2013-09-30 0:49 ` Simon Horman 2013-10-02 6:20 ` [PATCH 2/2] ARM: shmobile: marzen: enable INTC IRQ and fixup SMSC IRQ number Kuninori Morimoto 2013-10-02 8:06 ` Simon Horman
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