[PATCH 0/2] Add Ether support for R8A7791/Koelsch board

[PATCH 0/2] Add Ether support for R8A7791/Koelsch board

[Sergei Shtylyov]

Hello.

   Here's the set of 2 patches against Simon Horman's 'renesas.git' repo,
'renesas-devel-v3.12-rc7-20131030' tag. Here we add the Ether support to the
R8A7791/Koelsch board. The patchset requires the R8A7791 PFC support posted
earlier in order to work.

[1/2] ARM: shmobile: r8a7791: add Ether clock
[2/2] ARM: shmobile: Koelsch: add Ether support

WBR, Sergei

[PATCH 1/2] ARM: shmobile: r8a7791: add Ether clock

[Sergei Shtylyov]

Add support for R8A7791 Ether clock.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
 arch/arm/mach-shmobile/clock-r8a7791.c |    3 +++
 1 file changed, 3 insertions(+)

Index: renesas/arch/arm/mach-shmobile/clock-r8a7791.c
=================================--- renesas.orig/arch/arm/mach-shmobile/clock-r8a7791.c
+++ renesas/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -120,6 +120,7 @@ static struct clk *main_clks[] = {
 
 /* MSTP */
 enum {
+	MSTP813,
 	MSTP721, MSTP720,
 	MSTP719, MSTP718, MSTP715, MSTP714,
 	MSTP216, MSTP207, MSTP206,
@@ -129,6 +130,7 @@ enum {
 };
 
 static struct clk mstp_clks[MSTP_NR] = {
+	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
 	[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
 	[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
 	[MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */
@@ -180,6 +182,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
 	CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
 	CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
+	CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]), /* Ether */
 };
 
 #define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31)		\

Re: [PATCH 1/2] ARM: shmobile: r8a7791: add Ether clock

[Simon Horman]

On Thu, Oct 31, 2013 at 02:18:37AM +0300, Sergei Shtylyov wrote:
> Add support for R8A7791 Ether clock.
> 
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Thanks, I have queued this up.

> 
> ---
>  arch/arm/mach-shmobile/clock-r8a7791.c |    3 +++
>  1 file changed, 3 insertions(+)
> 
> Index: renesas/arch/arm/mach-shmobile/clock-r8a7791.c
> =================================> --- renesas.orig/arch/arm/mach-shmobile/clock-r8a7791.c
> +++ renesas/arch/arm/mach-shmobile/clock-r8a7791.c
> @@ -120,6 +120,7 @@ static struct clk *main_clks[] = {
>  
>  /* MSTP */
>  enum {
> +	MSTP813,
>  	MSTP721, MSTP720,
>  	MSTP719, MSTP718, MSTP715, MSTP714,
>  	MSTP216, MSTP207, MSTP206,
> @@ -129,6 +130,7 @@ enum {
>  };
>  
>  static struct clk mstp_clks[MSTP_NR] = {
> +	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
>  	[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
>  	[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
>  	[MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */
> @@ -180,6 +182,7 @@ static struct clk_lookup lookups[] = {
>  	CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
>  	CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
>  	CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
> +	CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]), /* Ether */
>  };
>  
>  #define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31)		\
> 

Re: [PATCH 1/2] ARM: shmobile: r8a7791: add Ether clock

[Sergei Shtylyov]

Hello.

On 10/31/2013 09:06 AM, Simon Horman wrote:

>> Add support for R8A7791 Ether clock.

>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

> Thanks, I have queued this up.

    Perhaps you were too quick, taking into account Magnus' mail about the 
device name...

WBR, Sergei

Re: [PATCH 1/2] ARM: shmobile: r8a7791: add Ether clock

[Simon Horman]

On Fri, Nov 01, 2013 at 12:50:46AM +0300, Sergei Shtylyov wrote:
> Hello.
> 
> On 10/31/2013 09:06 AM, Simon Horman wrote:
> 
> >>Add support for R8A7791 Ether clock.
> 
> >>Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> 
> >Thanks, I have queued this up.
> 
>    Perhaps you were too quick, taking into account Magnus' mail
> about the device name...

Yes I was. I will drop this patch.

[PATCH 1/2] arm: shmobile: r8a7791: Add SATA clocks

[Valentine Barshak]

This adds SATA 0/1 clock support. External 100MHz SATA 0/1
reference clock is supposed to be applied to the following pins:
  CICREFP0_SATA/CICREFP1_SATA;
  CICREFN0_SATA/CICREFN1_SATA.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
---
 arch/arm/mach-shmobile/clock-r8a7791.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index f546126..01a0314 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -78,6 +78,18 @@ static struct clk extal_clk = {
 	.mapping	= &cpg_mapping,
 };
 
+/* External SATA0 reference clock: 100MHz fixed */
+static struct clk sata0_clk = {
+	.rate		= 100000000,
+	.mapping	= &cpg_mapping,
+};
+
+/* External SATA1 reference clock: 100MHz fixed */
+static struct clk sata1_clk = {
+	.rate		= 100000000,
+	.mapping	= &cpg_mapping,
+};
+
 static struct sh_clk_ops followparent_clk_ops = {
 	.recalc	= followparent_recalc,
 };
@@ -118,10 +130,13 @@ static struct clk *main_clks[] = {
 	&mp_clk,
 	&cp_clk,
 	&zx_clk,
+	&sata0_clk,
+	&sata1_clk,
 };
 
 /* MSTP */
 enum {
+	MSTP815, MSTP814,
 	MSTP813,
 	MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
 	MSTP719, MSTP718, MSTP715, MSTP714,
@@ -133,6 +148,8 @@ enum {
 };
 
 static struct clk mstp_clks[MSTP_NR] = {
+	[MSTP815] = SH_CLK_MSTP32(&sata0_clk, SMSTPCR8, 15, 0), /* SATA0 */
+	[MSTP814] = SH_CLK_MSTP32(&sata1_clk, SMSTPCR8, 14, 0),	/* SATA1 */
 	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
 	[MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
 	[MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
@@ -195,6 +212,8 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
 	CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
 	CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */
+	CLKDEV_DEV_ID("sata-r8a7791.0", &mstp_clks[MSTP815]),
+	CLKDEV_DEV_ID("sata-r8a7791.1", &mstp_clks[MSTP814]),
 };
 
 #define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31)		\
-- 
1.8.3.1

Re: [PATCH 1/2] arm: shmobile: r8a7791: Add SATA clocks

[Simon Horman]

On Thu, Dec 19, 2013 at 09:59:04PM +0400, Valentine Barshak wrote:
> This adds SATA 0/1 clock support. External 100MHz SATA 0/1
> reference clock is supposed to be applied to the following pins:
>   CICREFP0_SATA/CICREFP1_SATA;
>   CICREFN0_SATA/CICREFN1_SATA.
> 
> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>

Unfortunately this patch conflicts with "ARM: shmobile: r8a7791: Wait for
status on all MSTP clocks" which I merged earlier today. Could you please
rebase this patch on top of the latest devel tag in the renesas tree,
currently renesas-devel-v3.13-rc7-20140109?

Please repost the entire two patch series.
Please include Magnus's Ack for each patch of the series.

Thanks

> ---
>  arch/arm/mach-shmobile/clock-r8a7791.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
> index f546126..01a0314 100644
> --- a/arch/arm/mach-shmobile/clock-r8a7791.c
> +++ b/arch/arm/mach-shmobile/clock-r8a7791.c
> @@ -78,6 +78,18 @@ static struct clk extal_clk = {
>  	.mapping	= &cpg_mapping,
>  };
>  
> +/* External SATA0 reference clock: 100MHz fixed */
> +static struct clk sata0_clk = {
> +	.rate		= 100000000,
> +	.mapping	= &cpg_mapping,
> +};
> +
> +/* External SATA1 reference clock: 100MHz fixed */
> +static struct clk sata1_clk = {
> +	.rate		= 100000000,
> +	.mapping	= &cpg_mapping,
> +};
> +
>  static struct sh_clk_ops followparent_clk_ops = {
>  	.recalc	= followparent_recalc,
>  };
> @@ -118,10 +130,13 @@ static struct clk *main_clks[] = {
>  	&mp_clk,
>  	&cp_clk,
>  	&zx_clk,
> +	&sata0_clk,
> +	&sata1_clk,
>  };
>  
>  /* MSTP */
>  enum {
> +	MSTP815, MSTP814,
>  	MSTP813,
>  	MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
>  	MSTP719, MSTP718, MSTP715, MSTP714,
> @@ -133,6 +148,8 @@ enum {
>  };
>  
>  static struct clk mstp_clks[MSTP_NR] = {
> +	[MSTP815] = SH_CLK_MSTP32(&sata0_clk, SMSTPCR8, 15, 0), /* SATA0 */
> +	[MSTP814] = SH_CLK_MSTP32(&sata1_clk, SMSTPCR8, 14, 0),	/* SATA1 */
>  	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
>  	[MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
>  	[MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
> @@ -195,6 +212,8 @@ static struct clk_lookup lookups[] = {
>  	CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
>  	CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
>  	CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */
> +	CLKDEV_DEV_ID("sata-r8a7791.0", &mstp_clks[MSTP815]),
> +	CLKDEV_DEV_ID("sata-r8a7791.1", &mstp_clks[MSTP814]),
>  };
>  
>  #define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31)		\
> -- 
> 1.8.3.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

[PATCH 1/2] ARM: shmobile: r8a7791: add Ether DT support

[Sergei Shtylyov]

Define the generic R8A7791 part of the Ether device node. 

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
 arch/arm/boot/dts/r8a7791.dtsi |   15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

Index: renesas/arch/arm/boot/dts/r8a7791.dtsi
=================================--- renesas.orig/arch/arm/boot/dts/r8a7791.dtsi
+++ renesas/arch/arm/boot/dts/r8a7791.dtsi
@@ -2,7 +2,8 @@
  * Device Tree Source for the r8a7791 SoC
  *
  * Copyright (C) 2013 Renesas Electronics Corporation
- * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013-2014 Renesas Solutions Corp.
+ * Copyright (C) 2014 Cogent Embedded Inc.
  *
  * This file is licensed under the terms of the GNU General Public License
  * version 2.  This program is licensed "as is" without any warranty of any
@@ -366,6 +367,18 @@
 		status = "disabled";
 	};
 
+	ether: ethernet@ee700000 {
+		compatible = "renesas,ether-r8a7791";
+		reg = <0 0xee700000 0 0x400>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
+		phy-mode = "rmii";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	sata0: sata@ee300000 {
 		compatible = "renesas,sata-r8a7791";
 		reg = <0 0xee300000 0 0x2000>;

Re: [PATCH 1/2] ARM: shmobile: r8a7791: add Ether DT support

[Ben Dooks]

On 06/02/14 22:12, Sergei Shtylyov wrote:
> Define the generic R8A7791 part of the Ether device node.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
>   arch/arm/boot/dts/r8a7791.dtsi |   15 ++++++++++++++-
>   1 file changed, 14 insertions(+), 1 deletion(-)
>
> Index: renesas/arch/arm/boot/dts/r8a7791.dtsi
> =================================> --- renesas.orig/arch/arm/boot/dts/r8a7791.dtsi
> +++ renesas/arch/arm/boot/dts/r8a7791.dtsi
> @@ -2,7 +2,8 @@
>    * Device Tree Source for the r8a7791 SoC
>    *
>    * Copyright (C) 2013 Renesas Electronics Corporation
> - * Copyright (C) 2013 Renesas Solutions Corp.
> + * Copyright (C) 2013-2014 Renesas Solutions Corp.
> + * Copyright (C) 2014 Cogent Embedded Inc.
>    *
>    * This file is licensed under the terms of the GNU General Public License
>    * version 2.  This program is licensed "as is" without any warranty of any
> @@ -366,6 +367,18 @@
>   		status = "disabled";
>   	};
>
> +	ether: ethernet@ee700000 {
> +		compatible = "renesas,ether-r8a7791";
> +		reg = <0 0xee700000 0 0x400>;
> +		interrupt-parent = <&gic>;
> +		interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
> +		phy-mode = "rmii";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};

Is the device only capable of doing RMII?


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

Re: [PATCH 1/2] ARM: shmobile: r8a7791: add Ether DT support

[Sergei Shtylyov]

Hello.

On 10-02-2014 16:54, Ben Dooks wrote:

>> Define the generic R8A7791 part of the Ether device node.

>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

>> ---
>>   arch/arm/boot/dts/r8a7791.dtsi |   15 ++++++++++++++-
>>   1 file changed, 14 insertions(+), 1 deletion(-)

>> Index: renesas/arch/arm/boot/dts/r8a7791.dtsi
>> =================================>> --- renesas.orig/arch/arm/boot/dts/r8a7791.dtsi
>> +++ renesas/arch/arm/boot/dts/r8a7791.dtsi
>> @@ -2,7 +2,8 @@
>>    * Device Tree Source for the r8a7791 SoC
>>    *
>>    * Copyright (C) 2013 Renesas Electronics Corporation
>> - * Copyright (C) 2013 Renesas Solutions Corp.
>> + * Copyright (C) 2013-2014 Renesas Solutions Corp.
>> + * Copyright (C) 2014 Cogent Embedded Inc.
>>    *
>>    * This file is licensed under the terms of the GNU General Public License
>>    * version 2.  This program is licensed "as is" without any warranty of any
>> @@ -366,6 +367,18 @@
>>           status = "disabled";
>>       };
>>
>> +    ether: ethernet@ee700000 {
>> +        compatible = "renesas,ether-r8a7791";
>> +        reg = <0 0xee700000 0 0x400>;
>> +        interrupt-parent = <&gic>;
>> +        interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
>> +        clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
>> +        phy-mode = "rmii";
>> +        #address-cells = <1>;
>> +        #size-cells = <0>;
>> +        status = "disabled";
>> +    };

> Is the device only capable of doing RMII?

    Yes.

WBR, Sergei

[PATCH 1/2] arm: shmobile: r8a7791: add USB3.0 clocks to device tree

[Yoshihiro Shimoda]

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 arch/arm/boot/dts/r8a7791.dtsi |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index ede8b7f..c2b5b38 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -784,15 +784,15 @@
 			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 			clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
-				 <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>;
+				 <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
 			#clock-cells = <1>;
 			renesas,clock-indices = <
 				R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
-				R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_CMT1
+				R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
 			>;
 			clock-output-names  				"tpu0", "sdhi2", "sdhi1", "sdhi0",
-				"mmcif0", "i2c7", "i2c8", "cmt1";
+				"mmcif0", "i2c7", "i2c8", "ssusb", "cmt1";
 		};
 		mstp5_clks: mstp5_clks@e6150144 {
 			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
-- 
1.7.9.5

[PATCH 2/2] ARM: shmobile: Koelsch: add Ether support

[Sergei Shtylyov]

Register Ether platform device and pin data on  the  Koelsch board. 
Register platform fixup for Micrel KSZ8041 PHY, just like on the Lager board.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
 arch/arm/mach-shmobile/board-koelsch.c |   61 ++++++++++++++++++++++++++++++++-
 1 file changed, 60 insertions(+), 1 deletion(-)

Index: renesas/arch/arm/mach-shmobile/board-koelsch.c
=================================--- renesas.orig/arch/arm/mach-shmobile/board-koelsch.c
+++ renesas/arch/arm/mach-shmobile/board-koelsch.c
@@ -24,14 +24,31 @@
 #include <linux/input.h>
 #include <linux/kernel.h>
 #include <linux/leds.h>
+#include <linux/phy.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_device.h>
+#include <linux/sh_eth.h>
 #include <mach/common.h>
+#include <mach/irqs.h>
 #include <mach/r8a7791.h>
 #include <mach/rcar-gen2.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+/* Ether */
+static const struct sh_eth_plat_data ether_pdata __initconst = {
+	.phy			= 0x1,
+	.edmac_endian		= EDMAC_LITTLE_ENDIAN,
+	.phy_interface		= PHY_INTERFACE_MODE_RMII,
+	.ether_link_active_low	= 1,
+};
+
+static const struct resource ether_resources[] __initconst = {
+	DEFINE_RES_MEM(0xee700000, 0x400),
+	DEFINE_RES_IRQ(gic_spi(162)),
+};
+
 /* LEDS */
 static struct gpio_led koelsch_leds[] = {
 	{
@@ -70,11 +87,29 @@ static const struct gpio_keys_platform_d
 	.nbuttons	= ARRAY_SIZE(gpio_buttons),
 };
 
+static const struct pinctrl_map koelsch_pinctrl_map[] = {
+	/* Ether */
+	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7791",
+				  "eth_link", "eth"),
+	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7791",
+				  "eth_mdio", "eth"),
+	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7791",
+				  "eth_rmii", "eth"),
+};
+
 static void __init koelsch_add_standard_devices(void)
 {
 	r8a7791_clock_init();
+
+	pinctrl_register_mappings(koelsch_pinctrl_map,
+				  ARRAY_SIZE(koelsch_pinctrl_map));
 	r8a7791_pinmux_init();
+
 	r8a7791_add_standard_devices();
+	platform_device_register_resndata(&platform_bus, "r8a7790-ether", -1,
+					  ether_resources,
+					  ARRAY_SIZE(ether_resources),
+					  &ether_pdata, sizeof(ether_pdata));
 	platform_device_register_data(&platform_bus, "leds-gpio", -1,
 				      &koelsch_leds_pdata,
 				      sizeof(koelsch_leds_pdata));
@@ -83,6 +118,30 @@ static void __init koelsch_add_standard_
 				      sizeof(koelsch_keys_pdata));
 }
 
+/*
+ * Ether LEDs on the Koelsch board are named LINK and ACTIVE which corresponds
+ * to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits
+ * 14-15. We have to set them back to 01 from the default 00 value each time
+ * the PHY is reset. It's also important because the PHY's LED0 signal is
+ * connected to SoC's ETH_LINK signal and in the PHY's default mode it will
+ * bounce on and off after each packet, which we apparently want to avoid.
+ */
+static int koelsch_ksz8041_fixup(struct phy_device *phydev)
+{
+	u16 phyctrl1 = phy_read(phydev, 0x1e);
+
+	phyctrl1 &= ~0xc000;
+	phyctrl1 |= 0x4000;
+	return phy_write(phydev, 0x1e, phyctrl1);
+}
+
+static void __init koelsch_init(void)
+{
+	koelsch_add_standard_devices();
+
+	phy_register_fixup_for_id("r8a7790-ether-ff:01", koelsch_ksz8041_fixup);
+}
+
 static const char * const koelsch_boards_compat_dt[] __initconst = {
 	"renesas,koelsch",
 	NULL,
@@ -91,7 +150,7 @@ static const char * const koelsch_boards
 DT_MACHINE_START(KOELSCH_DT, "koelsch")
 	.smp		= smp_ops(r8a7791_smp_ops),
 	.init_early	= r8a7791_init_early,
-	.init_machine	= koelsch_add_standard_devices,
+	.init_machine	= koelsch_init,
 	.init_time	= rcar_gen2_timer_init,
 	.dt_compat	= koelsch_boards_compat_dt,
 MACHINE_END

Re: [PATCH 2/2] ARM: shmobile: Koelsch: add Ether support

[Simon Horman]

On Thu, Oct 31, 2013 at 02:19:58AM +0300, Sergei Shtylyov wrote:
> Register Ether platform device and pin data on  the  Koelsch board. 
> Register platform fixup for Micrel KSZ8041 PHY, just like on the Lager board.
> 
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Thanks, I have been able to use this to successfully boot a Koelsch board
using nfsroot.  However, I believe there is a minor build problem which I
have commented on below.

> ---
>  arch/arm/mach-shmobile/board-koelsch.c |   61 ++++++++++++++++++++++++++++++++-
>  1 file changed, 60 insertions(+), 1 deletion(-)
> 
> Index: renesas/arch/arm/mach-shmobile/board-koelsch.c
> =================================> --- renesas.orig/arch/arm/mach-shmobile/board-koelsch.c
> +++ renesas/arch/arm/mach-shmobile/board-koelsch.c
> @@ -24,14 +24,31 @@
>  #include <linux/input.h>
>  #include <linux/kernel.h>
>  #include <linux/leds.h>
> +#include <linux/phy.h>
> +#include <linux/pinctrl/machine.h>
>  #include <linux/platform_data/gpio-rcar.h>
>  #include <linux/platform_device.h>
> +#include <linux/sh_eth.h>
>  #include <mach/common.h>
> +#include <mach/irqs.h>
>  #include <mach/r8a7791.h>
>  #include <mach/rcar-gen2.h>
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
>  
> +/* Ether */
> +static const struct sh_eth_plat_data ether_pdata __initconst = {
> +	.phy			= 0x1,
> +	.edmac_endian		= EDMAC_LITTLE_ENDIAN,
> +	.phy_interface		= PHY_INTERFACE_MODE_RMII,
> +	.ether_link_active_low	= 1,
> +};
> +
> +static const struct resource ether_resources[] __initconst = {
> +	DEFINE_RES_MEM(0xee700000, 0x400),
> +	DEFINE_RES_IRQ(gic_spi(162)),
> +};
> +
>  /* LEDS */
>  static struct gpio_led koelsch_leds[] = {
>  	{
> @@ -70,11 +87,29 @@ static const struct gpio_keys_platform_d
>  	.nbuttons	= ARRAY_SIZE(gpio_buttons),
>  };
>  
> +static const struct pinctrl_map koelsch_pinctrl_map[] = {
> +	/* Ether */
> +	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7791",
> +				  "eth_link", "eth"),
> +	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7791",
> +				  "eth_mdio", "eth"),
> +	PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7791",
> +				  "eth_rmii", "eth"),
> +};
> +
>  static void __init koelsch_add_standard_devices(void)
>  {
>  	r8a7791_clock_init();
> +
> +	pinctrl_register_mappings(koelsch_pinctrl_map,
> +				  ARRAY_SIZE(koelsch_pinctrl_map));
>  	r8a7791_pinmux_init();
> +
>  	r8a7791_add_standard_devices();
> +	platform_device_register_resndata(&platform_bus, "r8a7790-ether", -1,
> +					  ether_resources,
> +					  ARRAY_SIZE(ether_resources),
> +					  &ether_pdata, sizeof(ether_pdata));
>  	platform_device_register_data(&platform_bus, "leds-gpio", -1,
>  				      &koelsch_leds_pdata,
>  				      sizeof(koelsch_leds_pdata));
> @@ -83,6 +118,30 @@ static void __init koelsch_add_standard_
>  				      sizeof(koelsch_keys_pdata));
>  }
>  
> +/*
> + * Ether LEDs on the Koelsch board are named LINK and ACTIVE which corresponds
> + * to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits
> + * 14-15. We have to set them back to 01 from the default 00 value each time
> + * the PHY is reset. It's also important because the PHY's LED0 signal is
> + * connected to SoC's ETH_LINK signal and in the PHY's default mode it will
> + * bounce on and off after each packet, which we apparently want to avoid.
> + */
> +static int koelsch_ksz8041_fixup(struct phy_device *phydev)
> +{
> +	u16 phyctrl1 = phy_read(phydev, 0x1e);
> +
> +	phyctrl1 &= ~0xc000;
> +	phyctrl1 |= 0x4000;
> +	return phy_write(phydev, 0x1e, phyctrl1);
> +}
> +
> +static void __init koelsch_init(void)
> +{
> +	koelsch_add_standard_devices();
> +
> +	phy_register_fixup_for_id("r8a7790-ether-ff:01", koelsch_ksz8041_fixup);

It seems to me that this code requires CONFIG_PHYLIB in order to compile.
So I propose the following enhancement to this patch which replaces
the line immediately above.

	if (IS_ENABLED(CONFIG_PHYLIB))
		phy_register_fixup_for_id("r8a7790-ether-ff:01",
					  koelsch_ksz8041_fixup);

I believe a similar enhancement is also needed for board-lager.c
which I just realised does not compile if CONFIG_PHYLIB is not set.

> +}
> +
>  static const char * const koelsch_boards_compat_dt[] __initconst = {
>  	"renesas,koelsch",
>  	NULL,
> @@ -91,7 +150,7 @@ static const char * const koelsch_boards
>  DT_MACHINE_START(KOELSCH_DT, "koelsch")
>  	.smp		= smp_ops(r8a7791_smp_ops),
>  	.init_early	= r8a7791_init_early,
> -	.init_machine	= koelsch_add_standard_devices,
> +	.init_machine	= koelsch_init,
>  	.init_time	= rcar_gen2_timer_init,
>  	.dt_compat	= koelsch_boards_compat_dt,
>  MACHINE_END
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

Re: [PATCH 2/2] ARM: shmobile: Koelsch: add Ether support

[Sergei Shtylyov]

Hello.

On 10/31/2013 08:02 AM, Simon Horman wrote:

>> Register Ether platform device and pin data on  the  Koelsch board.
>> Register platform fixup for Micrel KSZ8041 PHY, just like on the Lager board.

>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

> Thanks, I have been able to use this to successfully boot a Koelsch board
> using nfsroot.  However, I believe there is a minor build problem which I
> have commented on below.

    Yes, there is. Unfortunately, I haven't tested the build with 
koelsch_defconfig...

>> ---
>>   arch/arm/mach-shmobile/board-koelsch.c |   61 ++++++++++++++++++++++++++++++++-
>>   1 file changed, 60 insertions(+), 1 deletion(-)

>> Index: renesas/arch/arm/mach-shmobile/board-koelsch.c
>> =================================>> --- renesas.orig/arch/arm/mach-shmobile/board-koelsch.c
>> +++ renesas/arch/arm/mach-shmobile/board-koelsch.c
[...]
>> @@ -83,6 +118,30 @@ static void __init koelsch_add_standard_
>>   				      sizeof(koelsch_keys_pdata));
>>   }
>>
>> +/*
>> + * Ether LEDs on the Koelsch board are named LINK and ACTIVE which corresponds
>> + * to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits
>> + * 14-15. We have to set them back to 01 from the default 00 value each time
>> + * the PHY is reset. It's also important because the PHY's LED0 signal is
>> + * connected to SoC's ETH_LINK signal and in the PHY's default mode it will
>> + * bounce on and off after each packet, which we apparently want to avoid.
>> + */
>> +static int koelsch_ksz8041_fixup(struct phy_device *phydev)
>> +{
>> +	u16 phyctrl1 = phy_read(phydev, 0x1e);
>> +
>> +	phyctrl1 &= ~0xc000;
>> +	phyctrl1 |= 0x4000;
>> +	return phy_write(phydev, 0x1e, phyctrl1);
>> +}
>> +
>> +static void __init koelsch_init(void)
>> +{
>> +	koelsch_add_standard_devices();
>> +
>> +	phy_register_fixup_for_id("r8a7790-ether-ff:01", koelsch_ksz8041_fixup);

> It seems to me that this code requires CONFIG_PHYLIB in order to compile.

    Not really -- only in order to link.

> So I propose the following enhancement to this patch which replaces
> the line immediately above.

> 	if (IS_ENABLED(CONFIG_PHYLIB))
> 		phy_register_fixup_for_id("r8a7790-ether-ff:01",
> 					  koelsch_ksz8041_fixup);

    Strictly speaking, this is not enough. I'm getting:

arch/arm/mach-shmobile/built-in.o: In function `koelsch_ksz8041_fixup':
platsmp-apmu.c:(.text+0xb8): undefined reference to `mdiobus_read'
platsmp-apmu.c:(.text+0xd0): undefined reference to `mdiobus_write'
arch/arm/mach-shmobile/built-in.o: In function `koelsch_init':
platsmp-apmu.c:(.init.text+0xa90): undefined reference to 
`phy_register_fixup_for_id'

So I guess the fixup function should be enclosed into #ifdef CONFIG_PHYLIB 
too. However, in practice this change seems enough (gcc probably drops unused 
static functions?)...

> I believe a similar enhancement is also needed for board-lager.c
> which I just realised does not compile if CONFIG_PHYLIB is not set.

    I believe you meant to say it doesn't link too.

WBR, Sergei

Re: [PATCH 2/2] ARM: shmobile: Koelsch: add Ether support

[Magnus Damm]

Hi Sergei,

On Thu, Oct 31, 2013 at 8:19 AM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Register Ether platform device and pin data on  the  Koelsch board.
> Register platform fixup for Micrel KSZ8041 PHY, just like on the Lager board.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Thanks for your patch. Just like on the Lager board we also need to
tie in the PHY IRQ pin. Polling is not good enough when the hardware
can do better. Can you please share your PHY IRQ plans with us?

Best,

/ magnus

Re: [PATCH 2/2] ARM: shmobile: Koelsch: add Ether support

[Sergei Shtylyov]

Hello.

On 10/31/2013 11:06 AM, Magnus Damm wrote:

>> Register Ether platform device and pin data on  the  Koelsch board.
>> Register platform fixup for Micrel KSZ8041 PHY, just like on the Lager board.

>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

> Thanks for your patch. Just like on the Lager board we also need to
> tie in the PHY IRQ pin.

    Not only on the Lager board, BOCK-W also I think.

> Polling is not good enough when the hardware
> can do better. Can you please share your PHY IRQ plans with us?

    It's on my agenda now -- will start after I do away with the CAN driver 
and the current Koelsch Ether support.

> Best,

> / magnus

WBR, Sergei

Re: [PATCH 2/2] ARM: shmobile: Koelsch: add Ether support

[Sergei Shtylyov]

Hello.

On 10/31/2013 10:03 PM, I wrote:

>>> Register Ether platform device and pin data on  the  Koelsch board.
>>> Register platform fixup for Micrel KSZ8041 PHY, just like on the Lager board.

>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

>> Thanks for your patch. Just like on the Lager board we also need to
>> tie in the PHY IRQ pin.

>     Not only on the Lager board, BOCK-W also I think.

>> Polling is not good enough when the hardware
>> can do better. Can you please share your PHY IRQ plans with us?

>     It's on my agenda now -- will start after I do away with the CAN driver
> and the current Koelsch Ether support.

    I have now implemented PHY IRQ support for BOCK-W, Lager, and Koelsch 
boards (had to extend the Micrel PHY driver to recognize undocumented 
KSZ8041RNLI PHY ID for that) but I must say that the PHY interrupt doesn't get 
generated on either of the board and I don't know why yet (I can't rule out 
the INTC driver issue); that's bad news. Good news is that even this doesn't 
prevent phylib from working properly as it still polls the PHY once a second.

>> Best,

>> / magnus

WBR, Sergei

Re: [PATCH 2/2] ARM: shmobile: Koelsch: add Ether support

[Sergei Shtylyov]

On 12/09/2013 10:57 PM, Sergei Shtylyov wrote:

>>>> Register Ether platform device and pin data on  the  Koelsch board.
>>>> Register platform fixup for Micrel KSZ8041 PHY, just like on the Lager board.

>>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

>>> Thanks for your patch. Just like on the Lager board we also need to
>>> tie in the PHY IRQ pin.

>>     Not only on the Lager board, BOCK-W also I think.

>>> Polling is not good enough when the hardware
>>> can do better. Can you please share your PHY IRQ plans with us?

>>     It's on my agenda now -- will start after I do away with the CAN driver
>> and the current Koelsch Ether support.

>     I have now implemented PHY IRQ support for BOCK-W, Lager, and Koelsch
> boards (had to extend the Micrel PHY driver to recognize undocumented
> KSZ8041RNLI PHY ID for that) but I must say that the PHY interrupt doesn't get
> generated on either of the board and I don't know why yet (I can't rule out
> the INTC driver issue); that's bad news. Good news is that even this doesn't
> prevent phylib from working properly as it still polls the PHY once a second.

    Forgot to note that using PHY IRQ on Lager/Koelsch seems quite pointless 
to me as we're using ETH_LINK signal on these boards and Ether core generates 
interrupts on the change of this signal using which the driver actually 
controls packet Rx/Tx; Micrel PHY driver also only enables interrupts on link 
up/down -- so it seems only useful on BOCK-W where we ignore ETH_LINK and so 
the driver controls packet Rx/Tx from the phylib's adjust_link() callback.

>>> Best,

>>> / magnus

WBR, Sergei

Re: [PATCH 2/2] ARM: shmobile: Koelsch: add Ether support

[Sergei Shtylyov]

Hello.

On 12/09/2013 10:57 PM, Sergei Shtylyov wrote:

>>>> Register Ether platform device and pin data on  the  Koelsch board.
>>>> Register platform fixup for Micrel KSZ8041 PHY, just like on the Lager board.

>>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

>>> Thanks for your patch. Just like on the Lager board we also need to
>>> tie in the PHY IRQ pin.

>>     Not only on the Lager board, BOCK-W also I think.

>>> Polling is not good enough when the hardware
>>> can do better. Can you please share your PHY IRQ plans with us?

>>     It's on my agenda now -- will start after I do away with the CAN driver
>> and the current Koelsch Ether support.

>     I have now implemented PHY IRQ support for BOCK-W, Lager, and Koelsch
> boards (had to extend the Micrel PHY driver to recognize undocumented
> KSZ8041RNLI PHY ID for that) but I must say that the PHY interrupt doesn't get
> generated on either of the board and I don't know why yet (I can't rule out
> the INTC driver issue); that's bad news. Good news is that even this doesn't
> prevent phylib from working properly as it still polls the PHY once a second.

    Oh yes, it does: phylib fails to recognize link down/up after you 
disconnect/reconnect the cable since it relies solely on IRQ for the link 
changes if it's specified.
    Now for the really good news: I was able to get the PHY IRQs on Koelsch 
board when I set the trigger mode to falling-edge; that seemed strange as the 
PHY interrupts are level-sensitive, according to the documentation. And only 
after we commented out the wild PHY reset done by the 'sh_eth' driver on each 
open, I was able to get the IRQs in the low-level trigger mode.
    So, I'm expecting to be able to finally resolve this issue on top of the 
net-next tree which now contains 2 patchsets that should enable me to finally 
remove that wild PHY reset for good:

http://marc.info/?l=linux-netdev&m\x138636384109141
http://marc.info/?l=linux-netdev&m\x138692649110301

>>> Best,

>>> / magnus

WBR, Sergei

Re: [PATCH 2/2] ARM: shmobile: Koelsch: add Ether support

[Magnus Damm]

Hi Sergei,

On Thu, Oct 31, 2013 at 8:19 AM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Register Ether platform device and pin data on  the  Koelsch board.
> Register platform fixup for Micrel KSZ8041 PHY, just like on the Lager board.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
>  arch/arm/mach-shmobile/board-koelsch.c |   61 ++++++++++++++++++++++++++++++++-
>  1 file changed, 60 insertions(+), 1 deletion(-)
>
> Index: renesas/arch/arm/mach-shmobile/board-koelsch.c
> =================================> --- renesas.orig/arch/arm/mach-shmobile/board-koelsch.c
> +++ renesas/arch/arm/mach-shmobile/board-koelsch.c

> @@ -70,11 +87,29 @@ static const struct gpio_keys_platform_d
>         .nbuttons       = ARRAY_SIZE(gpio_buttons),
>  };
>
> +static const struct pinctrl_map koelsch_pinctrl_map[] = {
> +       /* Ether */
> +       PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7791",
> +                                 "eth_link", "eth"),
> +       PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7791",
> +                                 "eth_mdio", "eth"),
> +       PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7791",
> +                                 "eth_rmii", "eth"),
> +};

Once again we seem to be using r8a7790 when the actual SoC is r8a7791.
If you're going to go down the route of using the SoC name then please
use the correct one at least.

Cheers,

/ magnus

Re: [PATCH 2/2] ARM: shmobile: Koelsch: add Ether support

[Sergei Shtylyov]

Hello.

On 10/31/2013 11:10 AM, Magnus Damm wrote:

>> Register Ether platform device and pin data on  the  Koelsch board.
>> Register platform fixup for Micrel KSZ8041 PHY, just like on the Lager board.

>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

>> ---
>>   arch/arm/mach-shmobile/board-koelsch.c |   61 ++++++++++++++++++++++++++++++++-
>>   1 file changed, 60 insertions(+), 1 deletion(-)
>>
>> Index: renesas/arch/arm/mach-shmobile/board-koelsch.c
>> =================================>> --- renesas.orig/arch/arm/mach-shmobile/board-koelsch.c
>> +++ renesas/arch/arm/mach-shmobile/board-koelsch.c

>> @@ -70,11 +87,29 @@ static const struct gpio_keys_platform_d
>>          .nbuttons       = ARRAY_SIZE(gpio_buttons),
>>   };
>>
>> +static const struct pinctrl_map koelsch_pinctrl_map[] = {
>> +       /* Ether */
>> +       PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7791",
>> +                                 "eth_link", "eth"),
>> +       PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7791",
>> +                                 "eth_mdio", "eth"),
>> +       PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7791",
>> +                                 "eth_rmii", "eth"),
>> +};

> Once again we seem to be using r8a7790 when the actual SoC is r8a7791.

    Note that the last time it was in the DT context which is not quite the 
same as platfrom device context.

> If you're going to go down the route of using the SoC name then please

    I don't have much choice here. Though we could have used used R-Car 
gen1/gen2 terminology (at least in the hindsight)...

> use the correct one at least.

    It wasn't me who used "r8a7790-ether" name in the first place, it was 
Simon. And as these 2 SoCs are indistinguishable at least from the 'sh_eth' 
driver's point of view, I wouldn't want to introduce another platform device 
ID, especially as it hasn't been done for R8A777[89] SoCs. What I can offer is 
renaming "r8a7790-ether" to "r8a779x-ether" if you really want.

> Cheers,

> / magnus

WBR, Sergei

[PATCH 2/2] arm: shmobile: koelsch: Add SATA support

[Valentine Barshak]

This adds SATA support to Koelsch board. Only SATA0 port is available.

Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
---
 arch/arm/mach-shmobile/board-koelsch.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c
index de7cc64..2ab5c75 100644
--- a/arch/arm/mach-shmobile/board-koelsch.c
+++ b/arch/arm/mach-shmobile/board-koelsch.c
@@ -148,6 +148,21 @@ static const struct gpio_keys_platform_data koelsch_keys_pdata __initconst = {
 	.nbuttons	= ARRAY_SIZE(gpio_buttons),
 };
 
+/* SATA0 */
+static const struct resource sata0_resources[] __initconst = {
+	DEFINE_RES_MEM(0xee300000, 0x2000),
+	DEFINE_RES_IRQ(gic_spi(105)),
+};
+
+static const struct platform_device_info sata0_info __initconst = {
+	.parent		= &platform_bus,
+	.name		= "sata-r8a7791",
+	.id		= 0,
+	.res		= sata0_resources,
+	.num_res	= ARRAY_SIZE(sata0_resources),
+	.dma_mask	= DMA_BIT_MASK(32),
+};
+
 static const struct pinctrl_map koelsch_pinctrl_map[] = {
 	/* DU */
 	PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791",
@@ -192,6 +207,8 @@ static void __init koelsch_add_standard_devices(void)
 				      sizeof(koelsch_keys_pdata));
 
 	koelsch_add_du_device();
+
+	platform_device_register_full(&sata0_info);
 }
 
 /*
-- 
1.8.3.1

[PATCH 2/2] ARM: shmobile: koelsch: add Volume Ramp usage on comment

[Kuninori Morimoto]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
 arch/arm/boot/dts/r8a7791-koelsch.dts |    9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 0551f13..5675444 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -27,6 +27,15 @@
  *
  *	amixer set "DVC Out Mute" on
  *	amixer set "DVC In Mute" on
+ *
+ * You can use Volume Ramp
+ *
+ *	amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
+ *	amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
+ *	amixer set "DVC Out Ramp" on
+ *	aplay xxx.wav &
+ *	amixer set "DVC Out"  80%  // Volume Down
+ *	amixer set "DVC Out" 100%  // Volume Up
  */
 
 /dts-v1/;
-- 
1.7.9.5