From: Simon Horman <horms@verge.net.au>
To: linux-sh@vger.kernel.org
Subject: Re: [PATCH] irqchip: renesas-intc-irqpin: Fix register bitfield shift calculation
Date: Tue, 12 Nov 2013 05:08:40 +0000 [thread overview]
Message-ID: <20131112050840.GA28649@verge.net.au> (raw)
In-Reply-To: <1383999481-2742-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
On Sat, Nov 09, 2013 at 01:18:01PM +0100, Laurent Pinchart wrote:
> The SENSE register bitfield position is incorrectly computed for SoCs
> that use 2-bit IRQ sense fields. Fix it.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Hi Laurent,
your change seems correct to me but I am wondering if it should
be considered as a bug-fix?
> ---
> drivers/irqchip/irq-renesas-intc-irqpin.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c
> index 82cec63..3ee78f0 100644
> --- a/drivers/irqchip/irq-renesas-intc-irqpin.c
> +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c
> @@ -149,8 +149,9 @@ static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
> static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
> int irq, int do_mask)
> {
> - int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */
> - int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */
> + /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
> + int bitfield_width = 4;
> + int shift = 32 - (irq + 1) * bitfield_width;
>
> intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
> shift, bitfield_width,
> @@ -159,8 +160,9 @@ static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
>
> static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
> {
> + /* The SENSE register is assumed to be 32-bit. */
> int bitfield_width = p->config.sense_bitfield_width;
> - int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */
> + int shift = 32 - (irq + 1) * bitfield_width;
>
> dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
>
> --
> Regards,
>
> Laurent Pinchart
>
> --
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>
next prev parent reply other threads:[~2013-11-12 5:08 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-09 12:18 [PATCH] irqchip: renesas-intc-irqpin: Fix register bitfield shift calculation Laurent Pinchart
2013-11-12 5:08 ` Simon Horman [this message]
2013-11-12 5:44 ` Magnus Damm
2013-11-12 13:22 ` Laurent Pinchart
2013-11-12 13:24 ` Laurent Pinchart
2013-11-13 0:54 ` Simon Horman
2013-11-13 4:14 ` Magnus Damm
2013-11-13 5:32 ` Magnus Damm
2013-11-13 6:22 ` Simon Horman
2013-11-13 11:29 ` Laurent Pinchart
2013-11-14 5:35 ` Simon Horman
2013-11-14 13:21 ` Laurent Pinchart
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