[PATCH 00/05 v2] pinctrl: sh-pfc: r7s72100 support V2

[PATCH 00/05 v2] pinctrl: sh-pfc: r7s72100 support V2

[Magnus Damm]

pinctrl: sh-pfc: r7s72100 support V2

[PATCH 01/05 v2] pinctrl: sh-pfc: Rework _GP_GPIO, introduce _GP_GPIO32
[PATCH 02/05 v2] pinctrl: sh-pfc: r7s72100 base support
[PATCH 03/05 v2] pinctrl: sh-pfc: r7s72100 single pin macros
[PATCH 04/05 v2] pinctrl: sh-pfc: r7s72100 SCIF support
[PATCH 05/05 v2] pinctrl: sh-pfc: r8a7791 and r7s72100 binding docs

This is V2 of r7s72100 PFC support. Included this time is:
- Some slight rework of shared sh-pfc macros
- Complete r7s72100 SCIF support
- Binding documentation

If you prefer me to adjust this code somehow then please let me know.

Signed-off-by: Magnus Damm <damm@opensource.se>
---

 Written against renesas.git tag renesas-devel-v3.13-rc3-20131214v2

 Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt |    2 
 drivers/pinctrl/sh-pfc/Kconfig                                    |    5 
 drivers/pinctrl/sh-pfc/Makefile                                   |    1 
 drivers/pinctrl/sh-pfc/core.c                                     |    9 
 drivers/pinctrl/sh-pfc/core.h                                     |    1 
 drivers/pinctrl/sh-pfc/pfc-r7s72100.c                             |  340 ++++++++++
 drivers/pinctrl/sh-pfc/sh_pfc.h                                   |    9 
 7 files changed, 363 insertions(+), 4 deletions(-)

[PATCH 01/05 v2] pinctrl: sh-pfc: Rework _GP_GPIO, introduce _GP_GPIO32

[Magnus Damm]

From: Magnus Damm <damm@opensource.se>

Rework _GP_GPIO to take banksize as argument, introduce
_GP_GPIO32 for SoCs with 32-bit GPIO banks.

Signed-off-by: Magnus Damm <damm@opensource.se>
---

 Developed on top of renesas git tag renesas-devel-v3.13-rc3-20131214v2

 drivers/pinctrl/sh-pfc/sh_pfc.h |    9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

--- 0001/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ work/drivers/pinctrl/sh-pfc/sh_pfc.h	2013-12-16 19:35:12.000000000 +0900
@@ -214,13 +214,14 @@ struct sh_pfc_soc_info {
 #define GP_ALL(str)			CPU_ALL_PORT(_GP_ALL, str)
 
 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
-#define _GP_GPIO(bank, _pin, _name, sfx)				\
-	[(bank * 32) + _pin] = {					\
-		.pin = (bank * 32) + _pin,				\
+#define _GP_GPIO(banksize, bank, _pin, _name, sfx)			\
+	[(bank * banksize) + _pin] = {					\
+		.pin = (bank * banksize) + _pin,			\
 		.name = __stringify(_name),				\
 		.enum_id = _name##_DATA,				\
 	}
-#define PINMUX_GPIO_GP_ALL()		CPU_ALL_PORT(_GP_GPIO, unused)
+#define _GP_GPIO32(bank, _pin, _name, sfx) _GP_GPIO(32, bank, _pin, _name, sfx)
+#define PINMUX_GPIO_GP_ALL()		CPU_ALL_PORT(_GP_GPIO32, unused)
 
 /* PINMUX_DATA_GP_ALL -  Expand to a list of name_DATA, name_FN marks */
 #define _GP_DATA(bank, pin, name, sfx)	PINMUX_DATA(name##_DATA, name##_FN)

[PATCH 02/05 v2] pinctrl: sh-pfc: r7s72100 base support

[Magnus Damm]

From: Magnus Damm <damm@opensource.se>

Add r7s72100 PINCTRL support via sh-pfc V2. At this point the code
provides enough support to allow use together with the gpio-rz
driver. Incremental per-device patches will in the future be
submitted on top of this base patch to allow PINCTRL enablement
for each individual device.

Signed-off-by: Magnus Damm <damm@opensource.se>
---

 Changes since V1:
 - Moved RZ_PORT_PIN() macro
 - Make use of _GP_GPIO() for 16-bit bank support
 - Updated _P_DATA() and _P_FN() to control PIPC

 Thanks to Laurent for the review.

 drivers/pinctrl/sh-pfc/Kconfig        |    5 +
 drivers/pinctrl/sh-pfc/Makefile       |    1 
 drivers/pinctrl/sh-pfc/core.c         |    9 +
 drivers/pinctrl/sh-pfc/core.h         |    1 
 drivers/pinctrl/sh-pfc/pfc-r7s72100.c |  161 +++++++++++++++++++++++++++++++++
 5 files changed, 177 insertions(+)

--- 0001/drivers/pinctrl/sh-pfc/Kconfig
+++ work/drivers/pinctrl/sh-pfc/Kconfig	2013-12-17 01:31:14.000000000 +0900
@@ -20,6 +20,11 @@ config GPIO_SH_PFC
 	  This enables support for GPIOs within the SoC's pin function
 	  controller.
 
+config PINCTRL_PFC_R7S72100
+	def_bool y
+	depends on ARCH_R7S72100
+	select PINCTRL_SH_PFC
+
 config PINCTRL_PFC_R8A73A4
 	def_bool y
 	depends on ARCH_R8A73A4
--- 0001/drivers/pinctrl/sh-pfc/Makefile
+++ work/drivers/pinctrl/sh-pfc/Makefile	2013-12-17 01:31:14.000000000 +0900
@@ -3,6 +3,7 @@ ifeq ($(CONFIG_GPIO_SH_PFC),y)
 sh-pfc-objs			+= gpio.o
 endif
 obj-$(CONFIG_PINCTRL_SH_PFC)	+= sh-pfc.o
+obj-$(CONFIG_PINCTRL_PFC_R7S72100)	+= pfc-r7s72100.o
 obj-$(CONFIG_PINCTRL_PFC_R8A73A4)	+= pfc-r8a73a4.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7740)	+= pfc-r8a7740.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7778)	+= pfc-r8a7778.o
--- 0001/drivers/pinctrl/sh-pfc/core.c
+++ work/drivers/pinctrl/sh-pfc/core.c	2013-12-17 01:31:14.000000000 +0900
@@ -401,6 +401,12 @@ static int sh_pfc_init_ranges(struct sh_
 
 #ifdef CONFIG_OF
 static const struct of_device_id sh_pfc_of_table[] = {
+#ifdef CONFIG_PINCTRL_PFC_R7S72100
+	{
+		.compatible = "renesas,pfc-r7s72100",
+		.data = &r7s72100_pinmux_info,
+	},
+#endif
 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
 	{
 		.compatible = "renesas,pfc-r8a73a4",
@@ -549,6 +555,9 @@ static int sh_pfc_remove(struct platform
 }
 
 static const struct platform_device_id sh_pfc_id_table[] = {
+#ifdef CONFIG_PINCTRL_PFC_R7S72100
+	{ "pfc-r7s72100", (kernel_ulong_t)&r7s72100_pinmux_info },
+#endif
 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
 	{ "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
 #endif
--- 0001/drivers/pinctrl/sh-pfc/core.h
+++ work/drivers/pinctrl/sh-pfc/core.h	2013-12-17 01:31:14.000000000 +0900
@@ -64,6 +64,7 @@ void sh_pfc_write_raw_reg(void __iomem *
 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
 
+extern const struct sh_pfc_soc_info r7s72100_pinmux_info;
 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
--- /dev/null
+++ work/drivers/pinctrl/sh-pfc/pfc-r7s72100.c	2013-12-17 10:47:26.000000000 +0900
@@ -0,0 +1,161 @@
+/*
+ * R7S72100 processor support
+ *
+ * Copyright (C) 2013  Renesas Electronics Corporation
+ * Copyright (C) 2013  Magnus Damm
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ */
+
+#include <linux/kernel.h>
+
+#include "core.h"
+#include "sh_pfc.h"
+
+#define PORT_P_1(bank, pin, fn, sfx) fn(bank, pin, P_##bank##_##pin, sfx)
+
+#define PORT_P_16(bank, fn, sfx)					\
+	PORT_P_1(bank, 0,  fn, sfx), PORT_P_1(bank, 1,  fn, sfx),	\
+	PORT_P_1(bank, 2,  fn, sfx), PORT_P_1(bank, 3,  fn, sfx),	\
+	PORT_P_1(bank, 4,  fn, sfx), PORT_P_1(bank, 5,  fn, sfx),	\
+	PORT_P_1(bank, 6,  fn, sfx), PORT_P_1(bank, 7,  fn, sfx),	\
+	PORT_P_1(bank, 8,  fn, sfx), PORT_P_1(bank, 9,  fn, sfx),	\
+	PORT_P_1(bank, 10, fn, sfx), PORT_P_1(bank, 11, fn, sfx),	\
+	PORT_P_1(bank, 12, fn, sfx), PORT_P_1(bank, 13, fn, sfx),	\
+	PORT_P_1(bank, 14, fn, sfx), PORT_P_1(bank, 15, fn, sfx)
+
+#define CPU_ALL_PORT(fn, sfx)						\
+	PORT_P_16(0, fn, sfx), PORT_P_16(1, fn, sfx),			\
+	PORT_P_16(2, fn, sfx), PORT_P_16(3, fn, sfx),			\
+	PORT_P_16(4, fn, sfx), PORT_P_16(5, fn, sfx),			\
+	PORT_P_16(6, fn, sfx), PORT_P_16(7, fn, sfx),			\
+	PORT_P_16(8, fn, sfx), PORT_P_16(9, fn, sfx),			\
+	PORT_P_16(10, fn, sfx), PORT_P_16(11, fn, sfx),			\
+	PORT_P_16(12, fn, sfx)
+
+#define P_ALL(n) GP_ALL(n)
+
+enum {
+	PINMUX_RESERVED = 0,
+
+	PINMUX_DATA_BEGIN,
+	P_ALL(DATA),
+	PINMUX_DATA_END,
+
+	PINMUX_FUNCTION_BEGIN,
+	P_ALL(PMC_0), P_ALL(PMC_1),
+	P_ALL(PFC_0), P_ALL(PFC_1),
+	P_ALL(PFCE_0), P_ALL(PFCE_1),
+	P_ALL(PFCAE_0), P_ALL(PFCAE_1),
+	P_ALL(PIBC_0), P_ALL(PIBC_1),
+	P_ALL(PBDC_0), P_ALL(PBDC_1),
+	P_ALL(PIPC_0), P_ALL(PIPC_1),
+	PINMUX_FUNCTION_END,
+
+	PINMUX_MARK_BEGIN,
+	P_ALL(MARK_FN1), P_ALL(MARK_FN2), P_ALL(MARK_FN3), P_ALL(MARK_FN4),
+	P_ALL(MARK_FN5), P_ALL(MARK_FN6), P_ALL(MARK_FN7), P_ALL(MARK_FN8),
+	PINMUX_MARK_END,
+};
+
+#define _P_ALL(n) CPU_ALL_PORT(n, unused)
+
+#define _P_GPIO(bank, _pin, _name, sfx) _GP_GPIO(16, bank, _pin, _name, sfx)
+
+#define _P_DATA(bank, pin, name, sfx)					\
+	PINMUX_DATA(name##_DATA, name##_PMC_0, name##_PIPC_0,		\
+		    name##_PIBC_1, name##_PBDC_1)
+
+#define _P_FN(n, fn, pfcae, pfce, pfc)					\
+	PINMUX_DATA(n##_MARK_FN##fn, n##_PMC_1,	n##_PIPC_1,		\
+		    n##_PFCAE_##pfcae, n##_PFCE_##pfce, n##_PFC_##pfc)
+
+#define _P_MARK_FN1(bank, pin, name, sfx) _P_FN(name, 1, 0, 0, 0)
+#define _P_MARK_FN2(bank, pin, name, sfx) _P_FN(name, 2, 0, 0, 1)
+#define _P_MARK_FN3(bank, pin, name, sfx) _P_FN(name, 3, 0, 1, 0)
+#define _P_MARK_FN4(bank, pin, name, sfx) _P_FN(name, 4, 0, 1, 1)
+#define _P_MARK_FN5(bank, pin, name, sfx) _P_FN(name, 5, 1, 0, 0)
+#define _P_MARK_FN6(bank, pin, name, sfx) _P_FN(name, 6, 1, 0, 1)
+#define _P_MARK_FN7(bank, pin, name, sfx) _P_FN(name, 7, 1, 1, 0)
+#define _P_MARK_FN8(bank, pin, name, sfx) _P_FN(name, 8, 1, 1, 1)
+
+static const u16 pinmux_data[] = {
+	_P_ALL(_P_DATA), /* PINMUX_DATA(P_M_N_DATA, P_M_N_PMC_0)... */
+	_P_ALL(_P_MARK_FN1), _P_ALL(_P_MARK_FN2),
+	_P_ALL(_P_MARK_FN3), _P_ALL(_P_MARK_FN4),
+	_P_ALL(_P_MARK_FN5), _P_ALL(_P_MARK_FN6),
+	_P_ALL(_P_MARK_FN7), _P_ALL(_P_MARK_FN8),
+};
+
+static struct sh_pfc_pin pinmux_pins[] = {
+	_P_ALL(_P_GPIO),
+};
+
+#define RZ_PORT_PIN(bank, pin) (((bank) * 16) + (pin))
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+};
+
+#define PFC_REG(idx, name, reg)						\
+	{ PINMUX_CFG_REG(__stringify(name), reg, 16, 1) {		\
+		P_##idx##_15_##name##_0, P_##idx##_15_##name##_1,	\
+		P_##idx##_14_##name##_0, P_##idx##_14_##name##_1,	\
+		P_##idx##_13_##name##_0, P_##idx##_13_##name##_1,	\
+		P_##idx##_12_##name##_0, P_##idx##_12_##name##_1,	\
+		P_##idx##_11_##name##_0, P_##idx##_11_##name##_1,	\
+		P_##idx##_10_##name##_0, P_##idx##_10_##name##_1,	\
+		P_##idx##_9_##name##_0, P_##idx##_9_##name##_1,		\
+		P_##idx##_8_##name##_0, P_##idx##_8_##name##_1,		\
+		P_##idx##_7_##name##_0, P_##idx##_7_##name##_1,		\
+		P_##idx##_6_##name##_0, P_##idx##_6_##name##_1,		\
+		P_##idx##_5_##name##_0, P_##idx##_5_##name##_1,		\
+		P_##idx##_4_##name##_0, P_##idx##_4_##name##_1,		\
+		P_##idx##_3_##name##_0, P_##idx##_3_##name##_1,		\
+		P_##idx##_2_##name##_0, P_##idx##_2_##name##_1,		\
+		P_##idx##_1_##name##_0, P_##idx##_1_##name##_1,		\
+		P_##idx##_0_##name##_0, P_##idx##_0_##name##_1 }	\
+	}
+
+#define PFC_REGS(idx)						\
+	PFC_REG(idx, PMC, (0xfcfe3400 + (idx * 4))),		\
+	PFC_REG(idx, PFC, (0xfcfe3500 + (idx * 4))),		\
+	PFC_REG(idx, PFCE, (0xfcfe3600 + (idx * 4))),		\
+	PFC_REG(idx, PFCAE, (0xfcfe3a00 + (idx * 4))),		\
+	PFC_REG(idx, PIBC, (0xfcfe7000 + (idx * 4))),		\
+	PFC_REG(idx, PBDC, (0xfcfe7100 + (idx * 4))),		\
+	PFC_REG(idx, PIPC, (0xfcfe7200 + (idx * 4)))
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+	PFC_REGS(0), PFC_REGS(1), PFC_REGS(2), PFC_REGS(3),
+	PFC_REGS(4), PFC_REGS(5), PFC_REGS(6), PFC_REGS(7),
+	PFC_REGS(8), PFC_REGS(9), PFC_REGS(10), PFC_REGS(11),
+	PFC_REG(12, PMC, 0xfcfe7b40),
+	PFC_REG(12, PIBC, 0xfcfe7f00),
+	{ },
+};
+
+const struct sh_pfc_soc_info r7s72100_pinmux_info = {
+	.name = "r7s72100_pfc",
+
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.pins = pinmux_pins,
+	.nr_pins = ARRAY_SIZE(pinmux_pins),
+	.groups = pinmux_groups,
+	.nr_groups = ARRAY_SIZE(pinmux_groups),
+	.functions = pinmux_functions,
+	.nr_functions = ARRAY_SIZE(pinmux_functions),
+
+	.cfg_regs = pinmux_config_regs,
+
+	.gpio_data = pinmux_data,
+	.gpio_data_size = ARRAY_SIZE(pinmux_data),
+};

[PATCH 03/05 v2] pinctrl: sh-pfc: r7s72100 single pin macros

[Magnus Damm]

From: Magnus Damm <damm@opensource.se>

Introduce macros that allow description of one pin per line.
Compared to the other ways of doing this, using this style
we can compresses the description of each pin from 9 to 1 line.

Signed-off-by: Magnus Damm <damm@opensource.se>
---

 This patch uses RZ_PMX_GROUP and RZ_GROUPS, thanks Laurent!

 drivers/pinctrl/sh-pfc/pfc-r7s72100.c |   21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

--- 0003/drivers/pinctrl/sh-pfc/pfc-r7s72100.c
+++ work/drivers/pinctrl/sh-pfc/pfc-r7s72100.c	2013-12-16 19:14:30.000000000 +0900
@@ -98,9 +98,30 @@ static struct sh_pfc_pin pinmux_pins[]  
 #define RZ_PORT_PIN(bank, pin) (((bank) * 16) + (pin))
 
+#define __RZ_STR(pfx, hw, bank, pin, sfx)		\
+	pfx##_##hw##_p##bank##_##pin####sfx
+
+#define RZ_PIN_AND_MUX(pfx, hw, bank, pin, fn)				\
+static const unsigned int __RZ_STR(pfx, hw, bank, pin, _pins)[] = {	\
+	RZ_PORT_PIN(bank, pin),						\
+};									\
+static const unsigned int __RZ_STR(pfx, hw, bank, pin, _mux)[] = {	\
+	P_##bank##_##pin##_MARK_FN##fn,					\
+};
+
+#define RZ_PMX_GROUP(pfx, hw, bank, pin, fn) \
+	SH_PFC_PIN_GROUP(pfx##_##hw##_p##bank##_##pin),
+
+#define __RZ_GROUPS(x) #x
+
+#define RZ_GROUPS(pfx, hw, bank, pin, fn) \
+	__RZ_GROUPS(pfx##_##hw##_p##bank##_##pin),
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 };
 
+static const char * const scif2_groups[] = {
+};
 static const struct sh_pfc_function pinmux_functions[] = {
 };
 

[PATCH 04/05 v2] pinctrl: sh-pfc: r7s72100 SCIF support

[Magnus Damm]

From: Magnus Damm <damm@opensource.se>

Add support for SCIF functions SCK, TXD, RXD, CTS and RTS to the
r7s72100 PINCTRL code. There are two possible pins that can be used
for TXD (Port 3 Pin 0 Function 6 and Port 3 Pin 1 Function 4) and
because of that are pins broken out into separate functions.

Signed-off-by: Magnus Damm <damm@opensource.se>
---

 drivers/pinctrl/sh-pfc/pfc-r7s72100.c |  158 +++++++++++++++++++++++++++++++++
 1 file changed, 158 insertions(+)

--- 0006/drivers/pinctrl/sh-pfc/pfc-r7s72100.c
+++ work/drivers/pinctrl/sh-pfc/pfc-r7s72100.c	2013-12-17 01:09:20.000000000 +0900
@@ -117,12 +117,170 @@ static const unsigned int __RZ_STR(pfx,
 #define RZ_GROUPS(pfx, hw, bank, pin, fn) \
 	__RZ_GROUPS(pfx##_##hw##_p##bank##_##pin),
 
+#define SCIF0(fn)			\
+	fn(scif0, clk, 2, 13, 6)	\
+	fn(scif0, txd, 2, 14, 6)	\
+	fn(scif0, rxd, 2, 15, 6)	\
+	fn(scif0, clk, 4, 8, 7)		\
+	fn(scif0, txd, 4, 9, 7)		\
+	fn(scif0, rxd, 4, 10, 7)	\
+	fn(scif0, clk, 6, 8, 5)		\
+	fn(scif0, txd, 6, 9, 5)		\
+	fn(scif0, rxd, 6, 10, 5)
+
+#define SCIF1(fn)			\
+	fn(scif1, cts, 2, 3, 6)		\
+	fn(scif1, clk, 2, 4, 6)		\
+	fn(scif1, txd, 2, 5, 6)		\
+	fn(scif1, rxd, 2, 6, 6)		\
+	fn(scif1, rts, 2, 7, 6)		\
+	fn(scif1, clk, 4, 11, 7)	\
+	fn(scif1, txd, 4, 12, 7)	\
+	fn(scif1, rxd, 4, 13, 7)	\
+	fn(scif1, clk, 6, 11, 5)	\
+	fn(scif1, txd, 6, 12, 5)	\
+	fn(scif1, rxd, 6, 13, 5)	\
+	fn(scif1, clk, 9, 2, 4)		\
+	fn(scif1, txd, 9, 3, 4)		\
+	fn(scif1, rxd, 9, 4, 4)		\
+	fn(scif1, cts, 9, 5, 4)		\
+	fn(scif1, rts, 9, 6, 4)
+
+#define SCIF2(fn)			\
+	fn(scif2, clk, 3, 0, 4)		\
+	fn(scif2, txd, 3, 1, 4)		\
+	fn(scif2, rxd, 3, 2, 4)		\
+	fn(scif2, txd, 3, 0, 6)		\
+	fn(scif2, clk, 4, 1, 5)		\
+	fn(scif2, txd, 4, 2, 5)		\
+	fn(scif2, rxd, 4, 3, 5)		\
+	fn(scif2, txd, 4, 14, 7)	\
+	fn(scif2, rxd, 4, 15, 7)	\
+	fn(scif2, txd, 6, 2, 7)		\
+	fn(scif2, rxd, 6, 3, 7)		\
+	fn(scif2, clk, 8, 3, 7)		\
+	fn(scif2, rxd, 8, 4, 7)		\
+	fn(scif2, txd, 8, 6, 7)
+
+#define SCIF3(fn)			\
+	fn(scif3, clk, 3, 4, 7)		\
+	fn(scif3, txd, 3, 5, 7)		\
+	fn(scif3, rxd, 3, 6, 7)		\
+	fn(scif3, clk, 5, 2, 5)		\
+	fn(scif3, txd, 5, 3, 5)		\
+	fn(scif3, rxd, 5, 4, 5)		\
+	fn(scif3, rxd, 6, 0, 7)		\
+	fn(scif3, txd, 6, 1, 7)		\
+	fn(scif3, txd, 8, 8, 7)		\
+	fn(scif3, rxd, 8, 9, 7)
+
+#define SCIF4(fn)			\
+	fn(scif4, txd, 5, 0, 5)		\
+	fn(scif4, rxd, 5, 1, 5)		\
+	fn(scif4, clk, 7, 0, 4)		\
+	fn(scif4, txd, 7, 1, 4)		\
+	fn(scif4, rxd, 7, 2, 4)		\
+	fn(scif4, txd, 8, 14, 7)	\
+	fn(scif4, rxd, 8, 15, 7)
+
+#define SCIF5(fn)			\
+	fn(scif5, cts, 6, 3, 5)		\
+	fn(scif5, rts, 6, 4, 5)		\
+	fn(scif5, clk, 6, 5, 5)		\
+	fn(scif5, txd, 6, 6, 5)		\
+	fn(scif5, rxd, 6, 7, 5)		\
+	fn(scif5, cts, 7, 15, 4)	\
+	fn(scif5, clk, 8, 0, 4)		\
+	fn(scif5, txd, 8, 1, 4)		\
+	fn(scif5, rxd, 8, 2, 4)		\
+	fn(scif5, rts, 8, 3, 4)		\
+	fn(scif5, rxd, 8, 11, 5)	\
+	fn(scif5, clk, 8, 12, 5)	\
+	fn(scif5, txd, 8, 13, 5)	\
+	fn(scif5, cts, 11, 7, 3)	\
+	fn(scif5, rts, 11, 8, 3)	\
+	fn(scif5, clk, 11, 9, 3)	\
+	fn(scif5, txd, 11, 10, 3)	\
+	fn(scif5, rxd, 11, 11, 3)
+
+#define SCIF6(fn)			\
+	fn(scif6, txd, 5, 6, 5)		\
+	fn(scif6, rxd, 5, 7, 5)		\
+	fn(scif6, clk, 6, 13, 4)	\
+	fn(scif6, txd, 6, 14, 4)	\
+	fn(scif6, rxd, 6, 15, 4)	\
+	fn(scif6, clk, 11, 0, 4)	\
+	fn(scif6, txd, 11, 1, 4)	\
+	fn(scif6, rxd, 11, 2, 4)
+
+#define SCIF7(fn)			\
+	fn(scif7, clk, 7, 3, 4)		\
+	fn(scif7, txd, 7, 4, 4)		\
+	fn(scif7, rxd, 7, 5, 4)		\
+	fn(scif7, cts, 7, 6, 4)		\
+	fn(scif7, rts, 7, 7, 4)
+
+SCIF0(RZ_PIN_AND_MUX)
+SCIF1(RZ_PIN_AND_MUX)
+SCIF2(RZ_PIN_AND_MUX)
+SCIF3(RZ_PIN_AND_MUX)
+SCIF4(RZ_PIN_AND_MUX)
+SCIF5(RZ_PIN_AND_MUX)
+SCIF6(RZ_PIN_AND_MUX)
+SCIF7(RZ_PIN_AND_MUX)
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SCIF0(RZ_PMX_GROUP)
+	SCIF1(RZ_PMX_GROUP)
+	SCIF2(RZ_PMX_GROUP)
+	SCIF3(RZ_PMX_GROUP)
+	SCIF4(RZ_PMX_GROUP)
+	SCIF5(RZ_PMX_GROUP)
+	SCIF6(RZ_PMX_GROUP)
+	SCIF7(RZ_PMX_GROUP)
+};
+
+static const char * const scif0_groups[] = {
+	SCIF0(RZ_GROUPS)
+};
+
+static const char * const scif1_groups[] = {
+	SCIF1(RZ_GROUPS)
 };
 
 static const char * const scif2_groups[] = {
+	SCIF2(RZ_GROUPS)
+};
+
+static const char * const scif3_groups[] = {
+	SCIF3(RZ_GROUPS)
+};
+
+static const char * const scif4_groups[] = {
+	SCIF4(RZ_GROUPS)
+};
+
+static const char * const scif5_groups[] = {
+	SCIF5(RZ_GROUPS)
+};
+
+static const char * const scif6_groups[] = {
+	SCIF6(RZ_GROUPS)
 };
+
+static const char * const scif7_groups[] = {
+	SCIF7(RZ_GROUPS)
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(scif0),
+	SH_PFC_FUNCTION(scif1),
+	SH_PFC_FUNCTION(scif2),
+	SH_PFC_FUNCTION(scif3),
+	SH_PFC_FUNCTION(scif4),
+	SH_PFC_FUNCTION(scif5),
+	SH_PFC_FUNCTION(scif6),
+	SH_PFC_FUNCTION(scif7),
 };
 
 #define PFC_REG(idx, name, reg)						\

[PATCH 05/05 v2] pinctrl: sh-pfc: r8a7791 and r7s72100 binding docs

[Magnus Damm]

From: Magnus Damm <damm@opensource.se>

Add compatible strings for r7s72100 and r8a7791.

Signed-off-by: Magnus Damm <damm@opensource.se>
---

 Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt |    2 ++
 1 file changed, 2 insertions(+)

--- 0001/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ work/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt	2013-12-16 19:55:12.000000000 +0900
@@ -10,11 +10,13 @@ Pin Control
 Required Properties:
 
   - compatible: should be one of the following.
+    - "renesas,pfc-r7s72100": for R7S72100 (RZ/A1H) compatible pin-controller.
     - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
     - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
     - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
     - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
     - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
+    - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2) compatible pin-controller.
     - "renesas,pfc-sh7372": for SH7372 (SH-Mobile AP4) compatible pin-controller.
     - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
 

Re: [PATCH 03/05 v2] pinctrl: sh-pfc: r7s72100 single pin macros

[Laurent Pinchart]

Hi Magnus,

Thank you for the patches.

On Tuesday 17 December 2013 11:38:14 Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
> 
> Introduce macros that allow description of one pin per line.
> Compared to the other ways of doing this, using this style
> we can compresses the description of each pin from 9 to 1 line.
> 
> Signed-off-by: Magnus Damm <damm@opensource.se>
> ---
> 
>  This patch uses RZ_PMX_GROUP and RZ_GROUPS, thanks Laurent!
> 
>  drivers/pinctrl/sh-pfc/pfc-r7s72100.c |   21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> --- 0003/drivers/pinctrl/sh-pfc/pfc-r7s72100.c
> +++ work/drivers/pinctrl/sh-pfc/pfc-r7s72100.c	2013-12-16 
19:14:30.000000000
> +0900 @@ -98,9 +98,30 @@ static struct sh_pfc_pin pinmux_pins[] > 
>  #define RZ_PORT_PIN(bank, pin) (((bank) * 16) + (pin))
> 
> +#define __RZ_STR(pfx, hw, bank, pin, sfx)		\
> +	pfx##_##hw##_p##bank##_##pin####sfx

Do you mean s/####sfx/##sfx/ ?

> +
> +#define RZ_PIN_AND_MUX(pfx, hw, bank, pin, fn)				\
> +static const unsigned int __RZ_STR(pfx, hw, bank, pin, _pins)[] = {	\
> +	RZ_PORT_PIN(bank, pin),						\
> +};									\
> +static const unsigned int __RZ_STR(pfx, hw, bank, pin, _mux)[] = {	\
> +	P_##bank##_##pin##_MARK_FN##fn,					\
> +};

I would have preferred keeping the trailing semicolon (and comma in the 
RZ_GROUPS macro) out of the macro, but that won't be possible as the 
RZ_PIN_AND_MUX and RZ_GROUPS macros are used as arguments to the SCIF macros 
in the next patch.

> +
> +#define RZ_PMX_GROUP(pfx, hw, bank, pin, fn) \
> +	SH_PFC_PIN_GROUP(pfx##_##hw##_p##bank##_##pin),
> +
> +#define __RZ_GROUPS(x) #x

Can't you replace __RZ_GROUPS() by __stringify() ?

> +#define RZ_GROUPS(pfx, hw, bank, pin, fn) \
> +	__RZ_GROUPS(pfx##_##hw##_p##bank##_##pin),
> +
>  static const struct sh_pfc_pin_group pinmux_groups[] = {
>  };
> 
> +static const char * const scif2_groups[] = {
> +};

I think this should be part of patch 04/05.

>  static const struct sh_pfc_function pinmux_functions[] = {
>  };

-- 
Regards,

Laurent Pinchart

Re: [PATCH 04/05 v2] pinctrl: sh-pfc: r7s72100 SCIF support

[Laurent Pinchart]

Hi Magnus,

Thank you for the patch.

On Tuesday 17 December 2013 11:38:23 Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
> 
> Add support for SCIF functions SCK, TXD, RXD, CTS and RTS to the
> r7s72100 PINCTRL code. There are two possible pins that can be used
> for TXD (Port 3 Pin 0 Function 6 and Port 3 Pin 1 Function 4) and
> because of that are pins broken out into separate functions.
> 
> Signed-off-by: Magnus Damm <damm@opensource.se>
> ---
> 
>  drivers/pinctrl/sh-pfc/pfc-r7s72100.c |  158 ++++++++++++++++++++++++++++++
>  1 file changed, 158 insertions(+)
> 
> --- 0006/drivers/pinctrl/sh-pfc/pfc-r7s72100.c
> +++ work/drivers/pinctrl/sh-pfc/pfc-r7s72100.c	2013-12-17 
01:09:20.000000000
> +0900 @@ -117,12 +117,170 @@ static const unsigned int __RZ_STR(pfx,
>  #define RZ_GROUPS(pfx, hw, bank, pin, fn) \
>  	__RZ_GROUPS(pfx##_##hw##_p##bank##_##pin),
> 
> +#define SCIF0(fn)			\
> +	fn(scif0, clk, 2, 13, 6)	\
> +	fn(scif0, txd, 2, 14, 6)	\
> +	fn(scif0, rxd, 2, 15, 6)	\
> +	fn(scif0, clk, 4, 8, 7)		\
> +	fn(scif0, txd, 4, 9, 7)		\
> +	fn(scif0, rxd, 4, 10, 7)	\
> +	fn(scif0, clk, 6, 8, 5)		\
> +	fn(scif0, txd, 6, 9, 5)		\
> +	fn(scif0, rxd, 6, 10, 5)

The SCIF0 SCK, TXD and RXD pins are grouped together with three options to 
choose from. Unlike the PFC devices we support so far, the driver allows 
picking pins individually. This allows greater flexibility, at the cost of a 
more verbose PFC DT node.

I assume that this is correct, but could you please confirm that the SoC 
really allows picking pins individually (for instance using P2.14 as SCIF0 TXD 
together with P6.10 as SCIF0 RXD) ?

I also wonder whether other currently supported SoCs wouldn't happen to also 
support picking pins from different groups, even though they name the groups 
differently.

> +
> +#define SCIF1(fn)			\
> +	fn(scif1, cts, 2, 3, 6)		\
> +	fn(scif1, clk, 2, 4, 6)		\
> +	fn(scif1, txd, 2, 5, 6)		\
> +	fn(scif1, rxd, 2, 6, 6)		\
> +	fn(scif1, rts, 2, 7, 6)		\
> +	fn(scif1, clk, 4, 11, 7)	\
> +	fn(scif1, txd, 4, 12, 7)	\
> +	fn(scif1, rxd, 4, 13, 7)	\
> +	fn(scif1, clk, 6, 11, 5)	\
> +	fn(scif1, txd, 6, 12, 5)	\
> +	fn(scif1, rxd, 6, 13, 5)	\
> +	fn(scif1, clk, 9, 2, 4)		\
> +	fn(scif1, txd, 9, 3, 4)		\
> +	fn(scif1, rxd, 9, 4, 4)		\
> +	fn(scif1, cts, 9, 5, 4)		\
> +	fn(scif1, rts, 9, 6, 4)
> +
> +#define SCIF2(fn)			\
> +	fn(scif2, clk, 3, 0, 4)		\
> +	fn(scif2, txd, 3, 1, 4)		\
> +	fn(scif2, rxd, 3, 2, 4)		\
> +	fn(scif2, txd, 3, 0, 6)		\
> +	fn(scif2, clk, 4, 1, 5)		\
> +	fn(scif2, txd, 4, 2, 5)		\
> +	fn(scif2, rxd, 4, 3, 5)		\
> +	fn(scif2, txd, 4, 14, 7)	\
> +	fn(scif2, rxd, 4, 15, 7)	\
> +	fn(scif2, txd, 6, 2, 7)		\
> +	fn(scif2, rxd, 6, 3, 7)		\
> +	fn(scif2, clk, 8, 3, 7)		\
> +	fn(scif2, rxd, 8, 4, 7)		\
> +	fn(scif2, txd, 8, 6, 7)
> +
> +#define SCIF3(fn)			\
> +	fn(scif3, clk, 3, 4, 7)		\
> +	fn(scif3, txd, 3, 5, 7)		\
> +	fn(scif3, rxd, 3, 6, 7)		\
> +	fn(scif3, clk, 5, 2, 5)		\
> +	fn(scif3, txd, 5, 3, 5)		\
> +	fn(scif3, rxd, 5, 4, 5)		\
> +	fn(scif3, rxd, 6, 0, 7)		\
> +	fn(scif3, txd, 6, 1, 7)		\
> +	fn(scif3, txd, 8, 8, 7)		\
> +	fn(scif3, rxd, 8, 9, 7)
> +
> +#define SCIF4(fn)			\
> +	fn(scif4, txd, 5, 0, 5)		\
> +	fn(scif4, rxd, 5, 1, 5)		\
> +	fn(scif4, clk, 7, 0, 4)		\
> +	fn(scif4, txd, 7, 1, 4)		\
> +	fn(scif4, rxd, 7, 2, 4)		\
> +	fn(scif4, txd, 8, 14, 7)	\
> +	fn(scif4, rxd, 8, 15, 7)
> +
> +#define SCIF5(fn)			\
> +	fn(scif5, cts, 6, 3, 5)		\
> +	fn(scif5, rts, 6, 4, 5)		\
> +	fn(scif5, clk, 6, 5, 5)		\
> +	fn(scif5, txd, 6, 6, 5)		\
> +	fn(scif5, rxd, 6, 7, 5)		\
> +	fn(scif5, cts, 7, 15, 4)	\
> +	fn(scif5, clk, 8, 0, 4)		\
> +	fn(scif5, txd, 8, 1, 4)		\
> +	fn(scif5, rxd, 8, 2, 4)		\
> +	fn(scif5, rts, 8, 3, 4)		\
> +	fn(scif5, rxd, 8, 11, 5)	\
> +	fn(scif5, clk, 8, 12, 5)	\
> +	fn(scif5, txd, 8, 13, 5)	\
> +	fn(scif5, cts, 11, 7, 3)	\
> +	fn(scif5, rts, 11, 8, 3)	\
> +	fn(scif5, clk, 11, 9, 3)	\
> +	fn(scif5, txd, 11, 10, 3)	\
> +	fn(scif5, rxd, 11, 11, 3)
> +
> +#define SCIF6(fn)			\
> +	fn(scif6, txd, 5, 6, 5)		\
> +	fn(scif6, rxd, 5, 7, 5)		\
> +	fn(scif6, clk, 6, 13, 4)	\
> +	fn(scif6, txd, 6, 14, 4)	\
> +	fn(scif6, rxd, 6, 15, 4)	\
> +	fn(scif6, clk, 11, 0, 4)	\
> +	fn(scif6, txd, 11, 1, 4)	\
> +	fn(scif6, rxd, 11, 2, 4)
> +
> +#define SCIF7(fn)			\
> +	fn(scif7, clk, 7, 3, 4)		\
> +	fn(scif7, txd, 7, 4, 4)		\
> +	fn(scif7, rxd, 7, 5, 4)		\
> +	fn(scif7, cts, 7, 6, 4)		\
> +	fn(scif7, rts, 7, 7, 4)
> +
> +SCIF0(RZ_PIN_AND_MUX)
> +SCIF1(RZ_PIN_AND_MUX)
> +SCIF2(RZ_PIN_AND_MUX)
> +SCIF3(RZ_PIN_AND_MUX)
> +SCIF4(RZ_PIN_AND_MUX)
> +SCIF5(RZ_PIN_AND_MUX)
> +SCIF6(RZ_PIN_AND_MUX)
> +SCIF7(RZ_PIN_AND_MUX)
> +
>  static const struct sh_pfc_pin_group pinmux_groups[] = {
> +	SCIF0(RZ_PMX_GROUP)
> +	SCIF1(RZ_PMX_GROUP)
> +	SCIF2(RZ_PMX_GROUP)
> +	SCIF3(RZ_PMX_GROUP)
> +	SCIF4(RZ_PMX_GROUP)
> +	SCIF5(RZ_PMX_GROUP)
> +	SCIF6(RZ_PMX_GROUP)
> +	SCIF7(RZ_PMX_GROUP)
> +};
> +
> +static const char * const scif0_groups[] = {
> +	SCIF0(RZ_GROUPS)
> +};
> +
> +static const char * const scif1_groups[] = {
> +	SCIF1(RZ_GROUPS)
>  };
> 
>  static const char * const scif2_groups[] = {
> +	SCIF2(RZ_GROUPS)
> +};
> +
> +static const char * const scif3_groups[] = {
> +	SCIF3(RZ_GROUPS)
> +};
> +
> +static const char * const scif4_groups[] = {
> +	SCIF4(RZ_GROUPS)
> +};
> +
> +static const char * const scif5_groups[] = {
> +	SCIF5(RZ_GROUPS)
> +};
> +
> +static const char * const scif6_groups[] = {
> +	SCIF6(RZ_GROUPS)
>  };
> +
> +static const char * const scif7_groups[] = {
> +	SCIF7(RZ_GROUPS)
> +};
> +
>  static const struct sh_pfc_function pinmux_functions[] = {
> +	SH_PFC_FUNCTION(scif0),
> +	SH_PFC_FUNCTION(scif1),
> +	SH_PFC_FUNCTION(scif2),
> +	SH_PFC_FUNCTION(scif3),
> +	SH_PFC_FUNCTION(scif4),
> +	SH_PFC_FUNCTION(scif5),
> +	SH_PFC_FUNCTION(scif6),
> +	SH_PFC_FUNCTION(scif7),
>  };
> 
>  #define PFC_REG(idx, name, reg)						\
-- 
Regards,

Laurent Pinchart

Re: [PATCH 02/05 v2] pinctrl: sh-pfc: r7s72100 base support

[Laurent Pinchart]

Hi Magnus,

Thank you for the patch.

On Tuesday 17 December 2013 11:38:04 Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
> 
> Add r7s72100 PINCTRL support via sh-pfc V2. At this point the code
> provides enough support to allow use together with the gpio-rz
> driver. Incremental per-device patches will in the future be
> submitted on top of this base patch to allow PINCTRL enablement
> for each individual device.
> 
> Signed-off-by: Magnus Damm <damm@opensource.se>
> ---
> 
>  Changes since V1:
>  - Moved RZ_PORT_PIN() macro
>  - Make use of _GP_GPIO() for 16-bit bank support
>  - Updated _P_DATA() and _P_FN() to control PIPC
> 
>  Thanks to Laurent for the review.
> 
>  drivers/pinctrl/sh-pfc/Kconfig        |    5 +
>  drivers/pinctrl/sh-pfc/Makefile       |    1
>  drivers/pinctrl/sh-pfc/core.c         |    9 +
>  drivers/pinctrl/sh-pfc/core.h         |    1
>  drivers/pinctrl/sh-pfc/pfc-r7s72100.c |  161 ++++++++++++++++++++++++++++++
>  5 files changed, 177 insertions(+)

[snip]

> --- /dev/null
> +++ work/drivers/pinctrl/sh-pfc/pfc-r7s72100.c	2013-12-17
> 10:47:26.000000000 +0900
> @@ -0,0 +1,161 @@

[snip]

> +#define RZ_PORT_PIN(bank, pin) (((bank) * 16) + (pin))

Could you please move this macro to the next patch where it gets use d?

> +static const struct sh_pfc_pin_group pinmux_groups[] = {
> +};
> +
> +static const struct sh_pfc_function pinmux_functions[] = {
> +};
> +
> +#define PFC_REG(idx, name, reg)						\
> +	{ PINMUX_CFG_REG(__stringify(name), reg, 16, 1) {		\
> +		P_##idx##_15_##name##_0, P_##idx##_15_##name##_1,	\
> +		P_##idx##_14_##name##_0, P_##idx##_14_##name##_1,	\
> +		P_##idx##_13_##name##_0, P_##idx##_13_##name##_1,	\
> +		P_##idx##_12_##name##_0, P_##idx##_12_##name##_1,	\
> +		P_##idx##_11_##name##_0, P_##idx##_11_##name##_1,	\
> +		P_##idx##_10_##name##_0, P_##idx##_10_##name##_1,	\
> +		P_##idx##_9_##name##_0, P_##idx##_9_##name##_1,		\
> +		P_##idx##_8_##name##_0, P_##idx##_8_##name##_1,		\
> +		P_##idx##_7_##name##_0, P_##idx##_7_##name##_1,		\
> +		P_##idx##_6_##name##_0, P_##idx##_6_##name##_1,		\
> +		P_##idx##_5_##name##_0, P_##idx##_5_##name##_1,		\
> +		P_##idx##_4_##name##_0, P_##idx##_4_##name##_1,		\
> +		P_##idx##_3_##name##_0, P_##idx##_3_##name##_1,		\
> +		P_##idx##_2_##name##_0, P_##idx##_2_##name##_1,		\
> +		P_##idx##_1_##name##_0, P_##idx##_1_##name##_1,		\
> +		P_##idx##_0_##name##_0, P_##idx##_0_##name##_1 }	\
> +	}
> +
> +#define PFC_REGS(idx)						\
> +	PFC_REG(idx, PMC, (0xfcfe3400 + (idx * 4))),		\
> +	PFC_REG(idx, PFC, (0xfcfe3500 + (idx * 4))),		\
> +	PFC_REG(idx, PFCE, (0xfcfe3600 + (idx * 4))),		\
> +	PFC_REG(idx, PFCAE, (0xfcfe3a00 + (idx * 4))),		\
> +	PFC_REG(idx, PIBC, (0xfcfe7000 + (idx * 4))),		\
> +	PFC_REG(idx, PBDC, (0xfcfe7100 + (idx * 4))),		\
> +	PFC_REG(idx, PIPC, (0xfcfe7200 + (idx * 4)))
> +
> +static struct pinmux_cfg_reg pinmux_config_regs[] = {
> +	PFC_REGS(0), PFC_REGS(1), PFC_REGS(2), PFC_REGS(3),
> +	PFC_REGS(4), PFC_REGS(5), PFC_REGS(6), PFC_REGS(7),
> +	PFC_REGS(8), PFC_REGS(9), PFC_REGS(10), PFC_REGS(11),
> +	PFC_REG(12, PMC, 0xfcfe7b40),
> +	PFC_REG(12, PIBC, 0xfcfe7f00),
> +	{ },
> +};
> +
> +const struct sh_pfc_soc_info r7s72100_pinmux_info = {
> +	.name = "r7s72100_pfc",
> +
> +	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
> +
> +	.pins = pinmux_pins,
> +	.nr_pins = ARRAY_SIZE(pinmux_pins),
> +	.groups = pinmux_groups,
> +	.nr_groups = ARRAY_SIZE(pinmux_groups),
> +	.functions = pinmux_functions,
> +	.nr_functions = ARRAY_SIZE(pinmux_functions),
> +
> +	.cfg_regs = pinmux_config_regs,
> +
> +	.gpio_data = pinmux_data,
> +	.gpio_data_size = ARRAY_SIZE(pinmux_data),
> +};

-- 
Regards,

Laurent Pinchart

Re: [PATCH 02/05 v2] pinctrl: sh-pfc: r7s72100 base support

[Wolfram Sang]

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Hi,

> +#define _P_DATA(bank, pin, name, sfx)					\
> +	PINMUX_DATA(name##_DATA, name##_PMC_0, name##_PIPC_0,		\
> +		    name##_PIBC_1, name##_PBDC_1)
> +
> +#define _P_FN(n, fn, pfcae, pfce, pfc)					\
> +	PINMUX_DATA(n##_MARK_FN##fn, n##_PMC_1,	n##_PIPC_1,		\
> +		    n##_PFCAE_##pfcae, n##_PFCE_##pfce, n##_PFC_##pfc)

I need to apply this patch, otherwise my i2c pinmuxing fails?

diff --git a/drivers/pinctrl/sh-pfc/pfc-r7s72100.c b/drivers/pinctrl/sh-pfc/pfc-r7s72100.c
index 4acdaae..2b716d1 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r7s72100.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r7s72100.c
@@ -68,11 +68,11 @@ enum {
 #define _P_GPIO(bank, _pin, _name, sfx) _GP_GPIO(16, bank, _pin, _name, sfx)
 
 #define _P_DATA(bank, pin, name, sfx)					\
-	PINMUX_DATA(name##_DATA, name##_PMC_0, name##_PIPC_0,		\
+	PINMUX_DATA(name##_DATA, name##_PMC_0,		\
 		    name##_PIBC_1, name##_PBDC_1)
 
 #define _P_FN(n, fn, pfcae, pfce, pfc)					\
-	PINMUX_DATA(n##_MARK_FN##fn, n##_PMC_1,	n##_PIPC_1,		\
+	PINMUX_DATA(n##_MARK_FN##fn, n##_PMC_1,		\
 		    n##_PFCAE_##pfcae, n##_PFCE_##pfce, n##_PFC_##pfc)
 
 #define _P_MARK_FN1(bank, pin, name, sfx) _P_FN(name, 1, 0, 0, 0)


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Re: [PATCH 04/05 v2] pinctrl: sh-pfc: r7s72100 SCIF support

[Magnus Damm]

Hi Laurent,

On Wed, Dec 18, 2013 at 1:08 AM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> Hi Magnus,
>
> Thank you for the patch.
>
> On Tuesday 17 December 2013 11:38:23 Magnus Damm wrote:
>> From: Magnus Damm <damm@opensource.se>
>>
>> Add support for SCIF functions SCK, TXD, RXD, CTS and RTS to the
>> r7s72100 PINCTRL code. There are two possible pins that can be used
>> for TXD (Port 3 Pin 0 Function 6 and Port 3 Pin 1 Function 4) and
>> because of that are pins broken out into separate functions.
>>
>> Signed-off-by: Magnus Damm <damm@opensource.se>
>> ---
>>
>>  drivers/pinctrl/sh-pfc/pfc-r7s72100.c |  158 ++++++++++++++++++++++++++++++
>>  1 file changed, 158 insertions(+)
>>
>> --- 0006/drivers/pinctrl/sh-pfc/pfc-r7s72100.c
>> +++ work/drivers/pinctrl/sh-pfc/pfc-r7s72100.c        2013-12-17
> 01:09:20.000000000
>> +0900 @@ -117,12 +117,170 @@ static const unsigned int __RZ_STR(pfx,
>>  #define RZ_GROUPS(pfx, hw, bank, pin, fn) \
>>       __RZ_GROUPS(pfx##_##hw##_p##bank##_##pin),
>>
>> +#define SCIF0(fn)                    \
>> +     fn(scif0, clk, 2, 13, 6)        \
>> +     fn(scif0, txd, 2, 14, 6)        \
>> +     fn(scif0, rxd, 2, 15, 6)        \
>> +     fn(scif0, clk, 4, 8, 7)         \
>> +     fn(scif0, txd, 4, 9, 7)         \
>> +     fn(scif0, rxd, 4, 10, 7)        \
>> +     fn(scif0, clk, 6, 8, 5)         \
>> +     fn(scif0, txd, 6, 9, 5)         \
>> +     fn(scif0, rxd, 6, 10, 5)
>
> The SCIF0 SCK, TXD and RXD pins are grouped together with three options to
> choose from. Unlike the PFC devices we support so far, the driver allows
> picking pins individually. This allows greater flexibility, at the cost of a
> more verbose PFC DT node.

You need more detailed PFC data, yes, but I'm not sure if "Unlike the
PFC devices we support so far" is a correct statement. =)

> I assume that this is correct, but could you please confirm that the SoC
> really allows picking pins individually (for instance using P2.14 as SCIF0 TXD
> together with P6.10 as SCIF0 RXD) ?

Your example would work just fine, yes. I don't have any hardware to
test that though. I suspect the same would be fine on all of our SoCs
actually, unless

> I also wonder whether other currently supported SoCs wouldn't happen to also
> support picking pins from different groups, even though they name the groups
> differently.

It seems to me that in general the hardware has much more flexibility
than what the PINCTRL groups actually expose today. In the end it
depends on the actual hardware, so its a case by case thing:

A) RZ series: Individual per-pin settings always available

B) R-Mobile series (PORTnCR + MSELnCR): Individual per-pin settings
usually available

C) R-Car series (IPSRnn + MOD_SEL): Shared to some degree, but often
still allows individual control.

So with the current PINCTRL interface it looks like we have introduced
some artificial limitation based on software grouping even though the
actual hardware often can handle per-pin settings.

Cheers,

/ magnus

Re: [PATCH 02/05 v2] pinctrl: sh-pfc: r7s72100 base support

[Magnus Damm]

Hi Wolfram,

On Wed, Dec 18, 2013 at 6:04 AM, Wolfram Sang <wsa@the-dreams.de> wrote:
> Hi,
>
>> +#define _P_DATA(bank, pin, name, sfx)                                        \
>> +     PINMUX_DATA(name##_DATA, name##_PMC_0, name##_PIPC_0,           \
>> +                 name##_PIBC_1, name##_PBDC_1)
>> +
>> +#define _P_FN(n, fn, pfcae, pfce, pfc)                                       \
>> +     PINMUX_DATA(n##_MARK_FN##fn, n##_PMC_1, n##_PIPC_1,             \
>> +                 n##_PFCAE_##pfcae, n##_PFCE_##pfce, n##_PFC_##pfc)
>
> I need to apply this patch, otherwise my i2c pinmuxing fails?

Thanks. It looks to me like the _P_FN() bits would be mainly needed.
Can you try to omit the _P_DATA() portion and check if it is still
behaving as expected?

Cheers,

/ magnus

Re: [PATCH 03/05 v2] pinctrl: sh-pfc: r7s72100 single pin macros

[Magnus Damm]

Hi Laurent,

Thanks for your feedback.

On Wed, Dec 18, 2013 at 1:01 AM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> Hi Magnus,
>
> Thank you for the patches.
>
> On Tuesday 17 December 2013 11:38:14 Magnus Damm wrote:
>> From: Magnus Damm <damm@opensource.se>
>>
>> Introduce macros that allow description of one pin per line.
>> Compared to the other ways of doing this, using this style
>> we can compresses the description of each pin from 9 to 1 line.
>>
>> Signed-off-by: Magnus Damm <damm@opensource.se>
>> ---
>>
>>  This patch uses RZ_PMX_GROUP and RZ_GROUPS, thanks Laurent!
>>
>>  drivers/pinctrl/sh-pfc/pfc-r7s72100.c |   21 +++++++++++++++++++++
>>  1 file changed, 21 insertions(+)
>>
>> --- 0003/drivers/pinctrl/sh-pfc/pfc-r7s72100.c
>> +++ work/drivers/pinctrl/sh-pfc/pfc-r7s72100.c        2013-12-16
> 19:14:30.000000000
>> +0900 @@ -98,9 +98,30 @@ static struct sh_pfc_pin pinmux_pins[] >>
>>  #define RZ_PORT_PIN(bank, pin) (((bank) * 16) + (pin))
>>
>> +#define __RZ_STR(pfx, hw, bank, pin, sfx)            \
>> +     pfx##_##hw##_p##bank##_##pin####sfx
>
> Do you mean s/####sfx/##sfx/ ?

Yes, thanks for catching that.

>> +
>> +#define RZ_PIN_AND_MUX(pfx, hw, bank, pin, fn)                               \
>> +static const unsigned int __RZ_STR(pfx, hw, bank, pin, _pins)[] = {  \
>> +     RZ_PORT_PIN(bank, pin),                                         \
>> +};                                                                   \
>> +static const unsigned int __RZ_STR(pfx, hw, bank, pin, _mux)[] = {   \
>> +     P_##bank##_##pin##_MARK_FN##fn,                                 \
>> +};
>
> I would have preferred keeping the trailing semicolon (and comma in the
> RZ_GROUPS macro) out of the macro, but that won't be possible as the
> RZ_PIN_AND_MUX and RZ_GROUPS macros are used as arguments to the SCIF macros
> in the next patch.

That's correct. As much as I like semicolons, having a
single-line-per-pin must be better than duplicating stuff and use
semicolons.

>> +
>> +#define RZ_PMX_GROUP(pfx, hw, bank, pin, fn) \
>> +     SH_PFC_PIN_GROUP(pfx##_##hw##_p##bank##_##pin),
>> +
>> +#define __RZ_GROUPS(x) #x
>
> Can't you replace __RZ_GROUPS() by __stringify() ?

I'll try!

>> +#define RZ_GROUPS(pfx, hw, bank, pin, fn) \
>> +     __RZ_GROUPS(pfx##_##hw##_p##bank##_##pin),
>> +
>>  static const struct sh_pfc_pin_group pinmux_groups[] = {
>>  };
>>
>> +static const char * const scif2_groups[] = {
>> +};
>
> I think this should be part of patch 04/05.

Yes, so it seems.

Thanks,

/ magnus

Re: [PATCH 02/05 v2] pinctrl: sh-pfc: r7s72100 base support

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 735 bytes --]


> >> +#define _P_DATA(bank, pin, name, sfx)                                        \
> >> +     PINMUX_DATA(name##_DATA, name##_PMC_0, name##_PIPC_0,           \
> >> +                 name##_PIBC_1, name##_PBDC_1)
> >> +
> >> +#define _P_FN(n, fn, pfcae, pfce, pfc)                                       \
> >> +     PINMUX_DATA(n##_MARK_FN##fn, n##_PMC_1, n##_PIPC_1,             \
> >> +                 n##_PFCAE_##pfcae, n##_PFCE_##pfce, n##_PFC_##pfc)
> >
> > I need to apply this patch, otherwise my i2c pinmuxing fails?
> 
> Thanks. It looks to me like the _P_FN() bits would be mainly needed.
> Can you try to omit the _P_DATA() portion and check if it is still
> behaving as expected?

Nope, doesn't work.


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Re: [PATCH 02/05 v2] pinctrl: sh-pfc: r7s72100 base support

[Magnus Damm]

On Wed, Dec 18, 2013 at 7:05 PM, Wolfram Sang <wsa@the-dreams.de> wrote:
>
>> >> +#define _P_DATA(bank, pin, name, sfx)                                        \
>> >> +     PINMUX_DATA(name##_DATA, name##_PMC_0, name##_PIPC_0,           \
>> >> +                 name##_PIBC_1, name##_PBDC_1)
>> >> +
>> >> +#define _P_FN(n, fn, pfcae, pfce, pfc)                                       \
>> >> +     PINMUX_DATA(n##_MARK_FN##fn, n##_PMC_1, n##_PIPC_1,             \
>> >> +                 n##_PFCAE_##pfcae, n##_PFCE_##pfce, n##_PFC_##pfc)
>> >
>> > I need to apply this patch, otherwise my i2c pinmuxing fails?
>>
>> Thanks. It looks to me like the _P_FN() bits would be mainly needed.
>> Can you try to omit the _P_DATA() portion and check if it is still
>> behaving as expected?
>
> Nope, doesn't work.

Ok, thanks for checking!

/ magnus

Re: [PATCH 00/05 v2] pinctrl: sh-pfc: r7s72100 support V2

[Laurent Pinchart]

Hi Magnus,

I have pending PFC patches for v3.14. Do you plan to resubmit this series with 
the problem pointed out by Wolfram fixed for v3.14, or will you push it back 
to v3.15 ?

On Tuesday 17 December 2013 11:37:45 Magnus Damm wrote:
> pinctrl: sh-pfc: r7s72100 support V2
> 
> [PATCH 01/05 v2] pinctrl: sh-pfc: Rework _GP_GPIO, introduce _GP_GPIO32
> [PATCH 02/05 v2] pinctrl: sh-pfc: r7s72100 base support
> [PATCH 03/05 v2] pinctrl: sh-pfc: r7s72100 single pin macros
> [PATCH 04/05 v2] pinctrl: sh-pfc: r7s72100 SCIF support
> [PATCH 05/05 v2] pinctrl: sh-pfc: r8a7791 and r7s72100 binding docs
> 
> This is V2 of r7s72100 PFC support. Included this time is:
> - Some slight rework of shared sh-pfc macros
> - Complete r7s72100 SCIF support
> - Binding documentation
> 
> If you prefer me to adjust this code somehow then please let me know.
> 
> Signed-off-by: Magnus Damm <damm@opensource.se>
> ---
> 
>  Written against renesas.git tag renesas-devel-v3.13-rc3-20131214v2
> 
>  Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt |    2
>  drivers/pinctrl/sh-pfc/Kconfig                                    |    5
>  drivers/pinctrl/sh-pfc/Makefile                                   |    1
>  drivers/pinctrl/sh-pfc/core.c                                     |    9
>  drivers/pinctrl/sh-pfc/core.h                                     |    1
>  drivers/pinctrl/sh-pfc/pfc-r7s72100.c                             |  340 ++
>  drivers/pinctrl/sh-pfc/sh_pfc.h                                   |    9
>  7 files changed, 363 insertions(+), 4 deletions(-)

-- 
Regards,

Laurent Pinchart

Re: [PATCH 04/05 v2] pinctrl: sh-pfc: r7s72100 SCIF support

[Laurent Pinchart]

Hi Magnus,

On Wednesday 18 December 2013 07:26:15 Magnus Damm wrote:
> On Wed, Dec 18, 2013 at 1:08 AM, Laurent Pinchart wrote:
> > On Tuesday 17 December 2013 11:38:23 Magnus Damm wrote:
> >> From: Magnus Damm <damm@opensource.se>
> >> 
> >> Add support for SCIF functions SCK, TXD, RXD, CTS and RTS to the
> >> r7s72100 PINCTRL code. There are two possible pins that can be used
> >> for TXD (Port 3 Pin 0 Function 6 and Port 3 Pin 1 Function 4) and
> >> because of that are pins broken out into separate functions.
> >> 
> >> Signed-off-by: Magnus Damm <damm@opensource.se>
> >> ---
> >> 
> >>  drivers/pinctrl/sh-pfc/pfc-r7s72100.c |  158 +++++++++++++++++++++++++++
> >>  1 file changed, 158 insertions(+)
> >> 
> >> --- 0006/drivers/pinctrl/sh-pfc/pfc-r7s72100.c
> >> +++ work/drivers/pinctrl/sh-pfc/pfc-r7s72100.c        2013-12-17
> > 
> > 01:09:20.000000000
> > 
> >> +0900 @@ -117,12 +117,170 @@ static const unsigned int __RZ_STR(pfx,
> >> 
> >>  #define RZ_GROUPS(pfx, hw, bank, pin, fn) \
> >>       __RZ_GROUPS(pfx##_##hw##_p##bank##_##pin),
> >> 
> >> +#define SCIF0(fn)                    \
> >> +     fn(scif0, clk, 2, 13, 6)        \
> >> +     fn(scif0, txd, 2, 14, 6)        \
> >> +     fn(scif0, rxd, 2, 15, 6)        \
> >> +     fn(scif0, clk, 4, 8, 7)         \
> >> +     fn(scif0, txd, 4, 9, 7)         \
> >> +     fn(scif0, rxd, 4, 10, 7)        \
> >> +     fn(scif0, clk, 6, 8, 5)         \
> >> +     fn(scif0, txd, 6, 9, 5)         \
> >> +     fn(scif0, rxd, 6, 10, 5)
> > 
> > The SCIF0 SCK, TXD and RXD pins are grouped together with three options to
> > choose from. Unlike the PFC devices we support so far, the driver allows
> > picking pins individually. This allows greater flexibility, at the cost of
> > a more verbose PFC DT node.
> 
> You need more detailed PFC data, yes, but I'm not sure if "Unlike the
> PFC devices we support so far" is a correct statement. =)
> 
> > I assume that this is correct, but could you please confirm that the SoC
> > really allows picking pins individually (for instance using P2.14 as SCIF0
> > TXD together with P6.10 as SCIF0 RXD) ?
> 
> Your example would work just fine, yes. I don't have any hardware to
> test that though. I suspect the same would be fine on all of our SoCs
> actually, unless
> 
> > I also wonder whether other currently supported SoCs wouldn't happen to
> > also support picking pins from different groups, even though they name
> > the groups differently.
> 
> It seems to me that in general the hardware has much more flexibility
> than what the PINCTRL groups actually expose today. In the end it
> depends on the actual hardware, so its a case by case thing:
> 
> A) RZ series: Individual per-pin settings always available
> 
> B) R-Mobile series (PORTnCR + MSELnCR): Individual per-pin settings
> usually available
> 
> C) R-Car series (IPSRnn + MOD_SEL): Shared to some degree, but often
> still allows individual control.
> 
> So with the current PINCTRL interface it looks like we have introduced
> some artificial limitation based on software grouping even though the
> actual hardware often can handle per-pin settings.

That's probably true for some devices, yes. We've started by limiting the 
possibilities on R-Car either rightfully (when IPSR would allow individidual 
control but MODSEL would forbid it) or incorrectly, and have probably carried 
that on to new SoCs. We should carefully review the pin groups in the future.

-- 
Regards,

Laurent Pinchart