* [PATCH] ARM: shmobile: r8a7791: Wait for status on all MSTP clocks
@ 2014-01-08 7:54 Laurent Pinchart
2014-01-08 8:13 ` Magnus Damm
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Laurent Pinchart @ 2014-01-08 7:54 UTC (permalink / raw)
To: linux-sh
From: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
When enabling a module clock by clearing its bit in the MSTP control
register, the CPG requires waiting for the status register to signal
that the clock has started. Failure to do so will result in returning
from the clk_enable() call with the clock potentially still disabled,
leading to various race conditions and difficult to debug errors.
Enable status wait for all MSTP clocks on the r8a7791.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
arch/arm/mach-shmobile/clock-r8a7791.c | 68 +++++++++++++++++++---------------
1 file changed, 38 insertions(+), 30 deletions(-)
Simon,
This patch is a follow-up on the "[PATCH v4 0/3] ARM: shmobile: r8a7779/90:
Poll MSTP clocks status" series. Could you please queue it up for v3.14 as
well ?
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index 191ad60..1074ba4 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -59,6 +59,14 @@
#define SMSTPCR10 0xE6150998
#define SMSTPCR11 0xE615099C
+#define MSTPSR1 IOMEM(0xe6150038)
+#define MSTPSR2 IOMEM(0xe6150040)
+#define MSTPSR5 IOMEM(0xe615003c)
+#define MSTPSR7 IOMEM(0xe61501c4)
+#define MSTPSR8 IOMEM(0xe61509a0)
+#define MSTPSR9 IOMEM(0xe61509a4)
+#define MSTPSR11 IOMEM(0xe61509ac)
+
#define MODEMR 0xE6160060
#define SDCKCR 0xE6150074
#define SD2CKCR 0xE6150078
@@ -137,36 +145,36 @@ enum {
};
static struct clk mstp_clks[MSTP_NR] = {
- [MSTP931] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 31, 0), /* I2C0 */
- [MSTP930] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 30, 0), /* I2C1 */
- [MSTP929] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 29, 0), /* I2C2 */
- [MSTP928] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 28, 0), /* I2C3 */
- [MSTP927] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 27, 0), /* I2C4 */
- [MSTP925] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 25, 0), /* I2C5 */
- [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
- [MSTP811] = SH_CLK_MSTP32(&zg_clk, SMSTPCR8, 11, 0), /* VIN0 */
- [MSTP810] = SH_CLK_MSTP32(&zg_clk, SMSTPCR8, 10, 0), /* VIN1 */
- [MSTP809] = SH_CLK_MSTP32(&zg_clk, SMSTPCR8, 9, 0), /* VIN2 */
- [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
- [MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
- [MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */
- [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
- [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
- [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */
- [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */
- [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */
- [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */
- [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
- [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
- [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
- [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
- [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
- [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
- [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
- [MSTP1105] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 5, 0), /* SCIFA3 */
- [MSTP1106] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 6, 0), /* SCIFA4 */
- [MSTP1107] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 7, 0), /* SCIFA5 */
- [MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */
+ [MSTP931] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
+ [MSTP930] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
+ [MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
+ [MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
+ [MSTP927] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */
+ [MSTP925] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */
+ [MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
+ [MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
+ [MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
+ [MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 9, MSTPSR8, 0), /* VIN2 */
+ [MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
+ [MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
+ [MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */
+ [MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */
+ [MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */
+ [MSTP719] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 19, MSTPSR7, 0), /* SCIF2 */
+ [MSTP718] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 18, MSTPSR7, 0), /* SCIF3 */
+ [MSTP715] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 15, MSTPSR7, 0), /* SCIF4 */
+ [MSTP714] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 14, MSTPSR7, 0), /* SCIF5 */
+ [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
+ [MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
+ [MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
+ [MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
+ [MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */
+ [MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */
+ [MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */
+ [MSTP1105] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 5, MSTPSR11, 0), /* SCIFA3 */
+ [MSTP1106] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 6, MSTPSR11, 0), /* SCIFA4 */
+ [MSTP1107] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 7, MSTPSR11, 0), /* SCIFA5 */
+ [MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */
};
static struct clk_lookup lookups[] = {
--
Regards,
Laurent Pinchart
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] ARM: shmobile: r8a7791: Wait for status on all MSTP clocks
2014-01-08 7:54 [PATCH] ARM: shmobile: r8a7791: Wait for status on all MSTP clocks Laurent Pinchart
@ 2014-01-08 8:13 ` Magnus Damm
2014-01-08 8:14 ` Magnus Damm
2014-01-09 5:08 ` Simon Horman
2 siblings, 0 replies; 4+ messages in thread
From: Magnus Damm @ 2014-01-08 8:13 UTC (permalink / raw)
To: linux-sh
On Wed, Jan 8, 2014 at 4:54 PM, Laurent Pinchart
<laurent.pinchart+renesas@ideasonboard.com> wrote:
> From: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
>
> When enabling a module clock by clearing its bit in the MSTP control
> register, the CPG requires waiting for the status register to signal
> that the clock has started. Failure to do so will result in returning
> from the clk_enable() call with the clock potentially still disabled,
> leading to various race conditions and difficult to debug errors.
>
> Enable status wait for all MSTP clocks on the r8a7791.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Looking good, thanks for your help!
/ magnus
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] ARM: shmobile: r8a7791: Wait for status on all MSTP clocks
2014-01-08 7:54 [PATCH] ARM: shmobile: r8a7791: Wait for status on all MSTP clocks Laurent Pinchart
2014-01-08 8:13 ` Magnus Damm
@ 2014-01-08 8:14 ` Magnus Damm
2014-01-09 5:08 ` Simon Horman
2 siblings, 0 replies; 4+ messages in thread
From: Magnus Damm @ 2014-01-08 8:14 UTC (permalink / raw)
To: linux-sh
On Wed, Jan 8, 2014 at 5:13 PM, Magnus Damm <magnus.damm@gmail.com> wrote:
> On Wed, Jan 8, 2014 at 4:54 PM, Laurent Pinchart
> <laurent.pinchart+renesas@ideasonboard.com> wrote:
>> From: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
>>
>> When enabling a module clock by clearing its bit in the MSTP control
>> register, the CPG requires waiting for the status register to signal
>> that the clock has started. Failure to do so will result in returning
>> from the clk_enable() call with the clock potentially still disabled,
>> leading to various race conditions and difficult to debug errors.
>>
>> Enable status wait for all MSTP clocks on the r8a7791.
>>
>> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
>
> Looking good, thanks for your help!
And yes, I'm too trigger happy as usual so I forgot:
Acked-by: Magnus Damm <damm@opensource.se>
Cheers,
/ magnus
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] ARM: shmobile: r8a7791: Wait for status on all MSTP clocks
2014-01-08 7:54 [PATCH] ARM: shmobile: r8a7791: Wait for status on all MSTP clocks Laurent Pinchart
2014-01-08 8:13 ` Magnus Damm
2014-01-08 8:14 ` Magnus Damm
@ 2014-01-09 5:08 ` Simon Horman
2 siblings, 0 replies; 4+ messages in thread
From: Simon Horman @ 2014-01-09 5:08 UTC (permalink / raw)
To: linux-sh
On Wed, Jan 08, 2014 at 05:14:07PM +0900, Magnus Damm wrote:
> On Wed, Jan 8, 2014 at 5:13 PM, Magnus Damm <magnus.damm@gmail.com> wrote:
> > On Wed, Jan 8, 2014 at 4:54 PM, Laurent Pinchart
> > <laurent.pinchart+renesas@ideasonboard.com> wrote:
> >> From: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
> >>
> >> When enabling a module clock by clearing its bit in the MSTP control
> >> register, the CPG requires waiting for the status register to signal
> >> that the clock has started. Failure to do so will result in returning
> >> from the clk_enable() call with the clock potentially still disabled,
> >> leading to various race conditions and difficult to debug errors.
> >>
> >> Enable status wait for all MSTP clocks on the r8a7791.
> >>
> >> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> >
> > Looking good, thanks for your help!
>
> And yes, I'm too trigger happy as usual so I forgot:
>
> Acked-by: Magnus Damm <damm@opensource.se>
Thanks, I will queue this up.
^ permalink raw reply [flat|nested] 4+ messages in thread
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2014-01-08 7:54 [PATCH] ARM: shmobile: r8a7791: Wait for status on all MSTP clocks Laurent Pinchart
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