[GIT PULL] Renesas ARM Based SoC Clock Fixes For v3.17

[GIT PULL] Renesas ARM Based SoC Clock Fixes For v3.17

[Simon Horman]

Hi Olof, Hi Kevin, Hi Arnd,

Please consider these Renesas ARM based SoC clock fixes for v3.17.

This pull request is based on third round of Renesas ARM based SoC
lock updates for v3.17, tagged as renesas-clock3-for-v3.17,
which you have previously pulled.

I would like the first to patches considered for -stable.


The following changes since commit a0f7e7496d56ac2da7c684e2035815318c17973a:

  ARM: shmobile: sh73a0: add CMT1 clock support for DT (2014-07-15 13:34:17 +0900)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-clock-fixes-for-v3.17

for you to fetch changes up to 58b80ad6472c0fa12926dfa1f9103d3a326bdf18:

  ARM: shmobile: r8a7791: add missing 0x0100 for SDCKCR (2014-08-22 09:59:54 +0900)

----------------------------------------------------------------
Renesas ARM Based SoC Clock Fixes For v3.17

* ARM: shmobile: r8a7791: add missing 0x0100 for SDCKCR

  This resolves a problem introduced by 4bfb358b1d6cdeff
  ("ARM: shmobile: Add r8a7791 legacy SDHI clocks")
  which was included in v3.15.

  This fix does not have any run-time affect at this time.

* ARM: shmobile: r8a7790: add missing 0x0100 for SDCKCR

  This resolves a problem introduced by 9f13ee6f83c52065
  ("ARM: shmobile: r8a7790: add div4 clocks")
  which was included in v3.11.

  This fix does not have any run-time affect at this time.

* ARM: shmobile: sh73a0: Remove spurious 0x from SCIFB clock name

  This resolves a problem introduced by a0f7e7496d56ac2d
  ("ARM: shmobile: sh73a0: add CMT1 clock support for DT")
  which was included in v3.17-rc1.

  This fix does not have any run-time affect at this time as the clock in
  question is used by a SCIF device that is not enabled by default.

----------------------------------------------------------------
Kuninori Morimoto (2):
      ARM: shmobile: r8a7790: add missing 0x0100 for SDCKCR
      ARM: shmobile: r8a7791: add missing 0x0100 for SDCKCR

Simon Horman (1):
      ARM: shmobile: sh73a0: Remove spurious 0x from SCIFB clock name

 arch/arm/mach-shmobile/clock-r8a7790.c | 4 ++--
 arch/arm/mach-shmobile/clock-r8a7791.c | 2 +-
 arch/arm/mach-shmobile/clock-sh73a0.c  | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

[PATCH 1/3] ARM: shmobile: sh73a0: Remove spurious 0x from SCIFB clock name

[Simon Horman]

A stray '0x' crept into a0f7e7496d56ac2d ("ARM: shmobile: sh73a0: add CMT1
clock support for DT"). This  patch removes it.

This change should not have any run-time affect at this time as
the clock in question is used by a SCIF device that is not enabled by
default.

Reported-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/clock-sh73a0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 0d77f65..b0993a5 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -644,7 +644,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
 	CLKDEV_DEV_ID("e6cb0000.serial", &mstp_clks[MSTP207]), /* SCIFA5 */
 	CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
-	CLKDEV_DEV_ID("0xe6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */
+	CLKDEV_DEV_ID("e6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */
 	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
 	CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]), /* SCIFA0 */
 	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
-- 
2.0.1

[PATCH 2/3] ARM: shmobile: r8a7790: add missing 0x0100 for SDCKCR

[Simon Horman]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

9f13ee6f83c52065112d3e396e42e3780911ef53
(ARM: shmobile: r8a7790: add div4 clocks)
added r8a7790 DIV4 clock support.

But, it is missing
"0x0100: x 1/8" division ratio.
This patch fixes hidden bug.
It is based on R-Car H2 v0.7, R-Car M2 v0.9.

Reported-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7790.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 296a057..c62bfe7 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -181,8 +181,8 @@ enum {
 
 static struct clk div4_clks[DIV4_NR] = {
 	[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
-	[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
-	[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
+	[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
+	[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1df0, CLK_ENABLE_ON_INIT),
 };
 
 /* DIV6 clocks */
-- 
2.0.1

[PATCH 3/3] ARM: shmobile: r8a7791: add missing 0x0100 for SDCKCR

[Simon Horman]

From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

4bfb358b1d6cdeff8c6a13677f01ed78e9696b98
(ARM: shmobile: Add r8a7791 legacy SDHI clocks)
added r8a7791 SDHI clock support.

But, it is missing
"0x0100: x 1/8" division ratio.
This patch fixes hidden bug.
It is based on R-Car H2 v0.7, R-Car M2 v0.9.

Reported-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7791.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index e2fdfcc..53161c4 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -152,7 +152,7 @@ enum {
 
 static struct clk div4_clks[DIV4_NR] = {
 	[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
-	[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
+	[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
 };
 
 /* DIV6 clocks */
-- 
2.0.1

Re: [GIT PULL] Renesas ARM Based SoC Clock Fixes For v3.17

[Simon Horman]

On Mon, Aug 25, 2014 at 10:09:47AM +0900, Simon Horman wrote:
> Hi Olof, Hi Kevin, Hi Arnd,
> 
> Please consider these Renesas ARM based SoC clock fixes for v3.17.
> 
> This pull request is based on third round of Renesas ARM based SoC
> lock updates for v3.17, tagged as renesas-clock3-for-v3.17,
> which you have previously pulled.
> 
> I would like the first to patches considered for -stable.

On reflection as these fixes do not fix any run-time problems
I would like to withdraw my request for them to considered for -stable.
I would, however, still like them considered for v3.17.

Thanks

> The following changes since commit a0f7e7496d56ac2da7c684e2035815318c17973a:
> 
>   ARM: shmobile: sh73a0: add CMT1 clock support for DT (2014-07-15 13:34:17 +0900)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-clock-fixes-for-v3.17
> 
> for you to fetch changes up to 58b80ad6472c0fa12926dfa1f9103d3a326bdf18:
> 
>   ARM: shmobile: r8a7791: add missing 0x0100 for SDCKCR (2014-08-22 09:59:54 +0900)
> 
> ----------------------------------------------------------------
> Renesas ARM Based SoC Clock Fixes For v3.17
> 
> * ARM: shmobile: r8a7791: add missing 0x0100 for SDCKCR
> 
>   This resolves a problem introduced by 4bfb358b1d6cdeff
>   ("ARM: shmobile: Add r8a7791 legacy SDHI clocks")
>   which was included in v3.15.
> 
>   This fix does not have any run-time affect at this time.
> 
> * ARM: shmobile: r8a7790: add missing 0x0100 for SDCKCR
> 
>   This resolves a problem introduced by 9f13ee6f83c52065
>   ("ARM: shmobile: r8a7790: add div4 clocks")
>   which was included in v3.11.
> 
>   This fix does not have any run-time affect at this time.
> 
> * ARM: shmobile: sh73a0: Remove spurious 0x from SCIFB clock name
> 
>   This resolves a problem introduced by a0f7e7496d56ac2d
>   ("ARM: shmobile: sh73a0: add CMT1 clock support for DT")
>   which was included in v3.17-rc1.
> 
>   This fix does not have any run-time affect at this time as the clock in
>   question is used by a SCIF device that is not enabled by default.
> 
> ----------------------------------------------------------------
> Kuninori Morimoto (2):
>       ARM: shmobile: r8a7790: add missing 0x0100 for SDCKCR
>       ARM: shmobile: r8a7791: add missing 0x0100 for SDCKCR
> 
> Simon Horman (1):
>       ARM: shmobile: sh73a0: Remove spurious 0x from SCIFB clock name
> 
>  arch/arm/mach-shmobile/clock-r8a7790.c | 4 ++--
>  arch/arm/mach-shmobile/clock-r8a7791.c | 2 +-
>  arch/arm/mach-shmobile/clock-sh73a0.c  | 2 +-
>  3 files changed, 4 insertions(+), 4 deletions(-)
> 

Re: [GIT PULL] Renesas ARM Based SoC Clock Fixes For v3.17

[Olof Johansson]

On Mon, Aug 25, 2014 at 10:09:47AM +0900, Simon Horman wrote:
> Hi Olof, Hi Kevin, Hi Arnd,
> 
> Please consider these Renesas ARM based SoC clock fixes for v3.17.
> 
> This pull request is based on third round of Renesas ARM based SoC
> lock updates for v3.17, tagged as renesas-clock3-for-v3.17,
> which you have previously pulled.
> 
> I would like the first to patches considered for -stable.
> 
> 
> The following changes since commit a0f7e7496d56ac2da7c684e2035815318c17973a:
> 
>   ARM: shmobile: sh73a0: add CMT1 clock support for DT (2014-07-15 13:34:17 +0900)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-clock-fixes-for-v3.17

Merged.


-Olof

[GIT PULL] Renesas ARM Based SoC Clock Fixes for v3.18

[Simon Horman]

Hi Olof, Hi Kevin, Hi Arnd,

Please consider these Renesas ARM based SoC clock fixes for v3.18.
Or alternatively for v3.19 if you feel they are too late for v3.18.


* ARM: shmobile: r8a7740 legacy: Add missing INTCA clock for irqpin module

  This problem appears to have been introduced when the r8a7740 started
  using the irqpin driver, a change made by 0b7d7820226016205 ("ARM:
  shmobile: r8a7740: Migrate from INTC to GIC") in v3.9.
  It may well have existed in a different form before then.

  It is my understanding that the problem problem only manifests if
  uboot does not start the clock: in practice it does.

* ARM: shmobile: r8a7740 legacy: Correct IIC0 parent clock

  This problem appears to have been introduced when IIC0 support was
  added to the r8a7740 by commit 6c01ba445cecb2d8 ("ARM: mach-shmobile:
  R-Mobile A1 support.") in v3.3.

  I am not aware of any run-time effect of this problem.

* ARM: shmobile: r8a7790: Fix SD3CKCR address

  This problem was introduced when div6 clock support was added to the
  r8a7790 by 46632512c4b6ed9d5 ("ARM: shmobile: r8a7790: add div6 clocks")
  in v3.10.

  As there is no SD card slot for SDHI3 on the lager board there is no
  run-time effect of this problem on boards supported in mainline.


The following changes since commit f114040e3ea6e07372334ade75d1ee0775c355e1:

  Linux 3.18-rc1 (2014-10-19 18:08:38 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-clock-fixes-for-v3.18

for you to fetch changes up to 4f37828d4d69a46830e0525a065da9847fc7a819:

  ARM: shmobile: r8a7740 legacy: Correct IIC0 parent clock (2014-11-10 09:54:12 +0900)

----------------------------------------------------------------
Renesas ARM Based SoC Clock Fixes for v3.18

* Correct IIC0 parent clock for r8a7740
* Add missing INTCA clock for irqpin module for r8a7740
* Correct SD3CKCR address on r8a7790

----------------------------------------------------------------
Geert Uytterhoeven (2):
      ARM: shmobile: r8a7740 legacy: Add missing INTCA clock for irqpin module
      ARM: shmobile: r8a7740 legacy: Correct IIC0 parent clock

Shinobu Uehara (1):
      ARM: shmobile: r8a7790: Fix SD3CKCR address

 arch/arm/mach-shmobile/clock-r8a7740.c | 9 +++++++--
 arch/arm/mach-shmobile/clock-r8a7790.c | 2 +-
 2 files changed, 8 insertions(+), 3 deletions(-)

[PATCH 1/3] ARM: shmobile: r8a7790: Fix SD3CKCR address

[Simon Horman]

From: Shinobu Uehara <shinobu.uehara.xc@renesas.com>

Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7790.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 126ddaf..f622652 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -68,7 +68,7 @@
 
 #define SDCKCR		0xE6150074
 #define SD2CKCR		0xE6150078
-#define SD3CKCR		0xE615007C
+#define SD3CKCR		0xE615026C
 #define MMC0CKCR	0xE6150240
 #define MMC1CKCR	0xE6150244
 #define SSPCKCR		0xE6150248
-- 
2.1.1

[PATCH 2/3] ARM: shmobile: r8a7740 legacy: Add missing INTCA clock for irqpin module

[Simon Horman]

From: Geert Uytterhoeven <geert+renesas@glider.be>

This clock drives the irqpin controller modules.
Before, it was assumed enabled by the bootloader or reset state.
By making it available to the driver, we make sure it gets enabled when
needed, and allow it to be managed by system or runtime PM.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7740.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 0794f04..16a6b7c 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -455,7 +455,7 @@ enum {
 	MSTP128, MSTP127, MSTP125,
 	MSTP116, MSTP111, MSTP100, MSTP117,
 
-	MSTP230,
+	MSTP230, MSTP229,
 	MSTP222,
 	MSTP218, MSTP217, MSTP216, MSTP214,
 	MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
@@ -479,6 +479,7 @@ static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B],	SMSTPCR1,  0, 0), /* LCDC0 */
 
 	[MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB],	SMSTPCR2, 30, 0), /* SCIFA6 */
+	[MSTP229] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],	SMSTPCR2, 29, 0), /* INTCA */
 	[MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB],	SMSTPCR2, 22, 0), /* SCIFA7 */
 	[MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR2, 18, 0), /* DMAC1 */
 	[MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR2, 17, 0), /* DMAC2 */
@@ -575,6 +576,10 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh-dma-engine.0",	&mstp_clks[MSTP218]),
 	CLKDEV_DEV_ID("sh-sci.7",		&mstp_clks[MSTP222]),
 	CLKDEV_DEV_ID("e6cd0000.serial",	&mstp_clks[MSTP222]),
+	CLKDEV_DEV_ID("renesas_intc_irqpin.0",	&mstp_clks[MSTP229]),
+	CLKDEV_DEV_ID("renesas_intc_irqpin.1",	&mstp_clks[MSTP229]),
+	CLKDEV_DEV_ID("renesas_intc_irqpin.2",	&mstp_clks[MSTP229]),
+	CLKDEV_DEV_ID("renesas_intc_irqpin.3",	&mstp_clks[MSTP229]),
 	CLKDEV_DEV_ID("sh-sci.6",		&mstp_clks[MSTP230]),
 	CLKDEV_DEV_ID("e6cc0000.serial",	&mstp_clks[MSTP230]),
 
-- 
2.1.1

[PATCH 3/3] ARM: shmobile: r8a7740 legacy: Correct IIC0 parent clock

[Simon Horman]

From: Geert Uytterhoeven <geert+renesas@glider.be>

According to the datasheet, the operating clock for IIC0 is the HPP
(RT Peri) clock, not the SUB (Peri) clock. Both clocks run at the same
speed (50 Mhz).

This is consistent with IIC0 being located in the A4R PM domain, and
IIC1 in the A3SP PM domain.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/mach-shmobile/clock-r8a7740.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 16a6b7c..19df9cb 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -474,7 +474,7 @@ static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_S],	SMSTPCR1, 27, 0), /* CEU20 */
 	[MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB],	SMSTPCR1, 25, 0), /* TMU0 */
 	[MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B],	SMSTPCR1, 17, 0), /* LCDC1 */
-	[MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB],	SMSTPCR1, 16, 0), /* IIC0 */
+	[MSTP116] = SH_CLK_MSTP32(&div4_clks[DIV4_HPP],	SMSTPCR1, 16, 0), /* IIC0 */
 	[MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB],	SMSTPCR1, 11, 0), /* TMU1 */
 	[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B],	SMSTPCR1,  0, 0), /* LCDC0 */
 
-- 
2.1.1

Re: [GIT PULL] Renesas ARM Based SoC Clock Fixes for v3.18

[Arnd Bergmann]

On Thursday 13 November 2014, Simon Horman wrote:
> Hi Olof, Hi Kevin, Hi Arnd,
> 
> Please consider these Renesas ARM based SoC clock fixes for v3.18.
> Or alternatively for v3.19 if you feel they are too late for v3.18.
> 

I've merged all three 'fixes' pull requests you had into the fixes
branch:

Renesas ARM Based SoC Clock Fixes for v3.18
Renesas ARM Based SoC DT Fixes for v3.18
Renesas ARM Based SoC Fixes for v3.18

I'm still waiting for a reply from Olof, since he seems to have
skipped them last week when he sent the fixes pull request to Linus.
If he had already decided to postpone the branches for 3.19, I'll
just undo the merge here and put it into next/fixes-non-critical
instead, I'm fine with it either way.

	Arnd

Re: [GIT PULL] Renesas ARM Based SoC Clock Fixes for v3.18

[Simon Horman]

On Wed, Nov 19, 2014 at 10:20:20PM +0100, Arnd Bergmann wrote:
> On Thursday 13 November 2014, Simon Horman wrote:
> > Hi Olof, Hi Kevin, Hi Arnd,
> > 
> > Please consider these Renesas ARM based SoC clock fixes for v3.18.
> > Or alternatively for v3.19 if you feel they are too late for v3.18.
> > 
> 
> I've merged all three 'fixes' pull requests you had into the fixes
> branch:
> 
> Renesas ARM Based SoC Clock Fixes for v3.18
> Renesas ARM Based SoC DT Fixes for v3.18
> Renesas ARM Based SoC Fixes for v3.18
> 
> I'm still waiting for a reply from Olof, since he seems to have
> skipped them last week when he sent the fixes pull request to Linus.
> If he had already decided to postpone the branches for 3.19, I'll
> just undo the merge here and put it into next/fixes-non-critical
> instead, I'm fine with it either way.

Thanks, I am also fine with it either way.

Re: [GIT PULL] Renesas ARM Based SoC Clock Fixes for v3.18

[Geert Uytterhoeven]

Hi Arnd,

On Wed, Nov 19, 2014 at 10:20 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Thursday 13 November 2014, Simon Horman wrote:
>> Please consider these Renesas ARM based SoC clock fixes for v3.18.
>> Or alternatively for v3.19 if you feel they are too late for v3.18.
>
> I've merged all three 'fixes' pull requests you had into the fixes
> branch:
>
> Renesas ARM Based SoC Clock Fixes for v3.18
> Renesas ARM Based SoC DT Fixes for v3.18
> Renesas ARM Based SoC Fixes for v3.18
>
> I'm still waiting for a reply from Olof, since he seems to have
> skipped them last week when he sent the fixes pull request to Linus.
> If he had already decided to postpone the branches for 3.19, I'll
> just undo the merge here and put it into next/fixes-non-critical
> instead, I'm fine with it either way.

I agree the first two are non-critical.

The third, "Renesas ARM Based SoC Fixes for v3.18" may fix a regression
introduced in v3.16. While the original problem with the i2c timings was
indeed present in v2.6.37, the i2c bys most probably "just worked" (albeit with
wrong timings), until the i2c-sh_mobile driver got more picky in commit
7663ebefca8079ef ("i2c: sh_mobile: check timing parameters for valid range").

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds