From: Thierry Reding <thierry.reding@gmail.com>
To: linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] ARM: v7 setup function should invalidate L1 cache
Date: Thu, 21 May 2015 08:30:47 +0000 [thread overview]
Message-ID: <20150521083046.GA30323@ulmo.nvidia.com> (raw)
In-Reply-To: <E1Yuk8W-0001tC-IK@rmk-PC.arm.linux.org.uk>
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On Tue, May 19, 2015 at 05:12:56PM +0100, Russell King wrote:
> All ARMv5 and older CPUs invalidate their caches in the early assembly
> setup function, prior to enabling the MMU. This is because the L1
> cache should not contain any data relevant to the execution of the
> kernel at this point; all data should have been flushed out to memory.
>
> This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed,
> these typically do not search their caches when caching is disabled (as
> it needs to be when the MMU is disabled) so this change should be safe.
>
> ARMv7 allows there to be CPUs which search their caches while caching is
> disabled, and it's permitted that the cache is uninitialised at boot;
> for these, the architecture reference manual requires that an
> implementation specific code sequence is used immediately after reset
> to ensure that the cache is placed into a sane state. Such
> functionality is definitely outside the remit of the Linux kernel, and
> must be done by the SoC's firmware before _any_ CPU gets to the Linux
> kernel.
>
> Changing the data cache clean+invalidate to a mere invalidate allows us
> to get rid of a lot of platform specific hacks around this issue for
> their secondary CPU bringup paths - some of which were buggy.
>
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
[...]
> arch/arm/mach-tegra/Makefile | 2 +-
> arch/arm/mach-tegra/headsmp.S | 12 ------------
> arch/arm/mach-tegra/reset.c | 2 +-
> arch/arm/mach-tegra/reset.h | 1 -
[...]
Russell,
I saw a couple of conflicts trying to apply this to v4.1-rc1..v4.1-rc4
or any of recent linux-next versions. I ended up applying this on top of
your for-next branch and tested using that. The conflicts seem very
minor and a test merge of Tegra's for-next branch resolved this fine. A
test merge of next-20150520 shows one conflict in mach-socfpga/core.h,
but it's a trivial one to resolve.
Anyway, the patch seems to work fine on TrimSlice (Tegra20), Beaver
(Tegra30), Dalmore (Tegra114) and Jetson TK1 (Tegra124). Tested on
Paul's boot farm:
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Paul, thanks for setting up the boot test infrastructure, this saved me
a lot of time.
Thierry
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next prev parent reply other threads:[~2015-05-21 8:30 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <E1Yuk8W-0001tC-IK@rmk-PC.arm.linux.org.uk>
2015-05-19 21:44 ` [PATCH] ARM: v7 setup function should invalidate L1 cache Heiko Stuebner
2015-05-19 21:55 ` Arnd Bergmann
2015-05-19 22:07 ` Russell King - ARM Linux
2015-05-19 22:18 ` Arnd Bergmann
2015-05-19 22:32 ` Russell King - ARM Linux
2015-05-19 22:01 ` Florian Fainelli
2015-05-20 18:54 ` Dinh Nguyen
2015-05-20 22:48 ` Sebastian Hesselbarth
2015-05-21 2:08 ` Shawn Guo
2015-05-21 8:30 ` Thierry Reding [this message]
2015-05-22 7:36 ` Geert Uytterhoeven
2015-06-01 10:41 ` Geert Uytterhoeven
2015-06-01 10:53 ` Russell King - ARM Linux
2015-06-01 11:50 ` Geert Uytterhoeven
2015-06-17 20:35 ` Dinh Nguyen
2015-06-17 21:30 ` Russell King - ARM Linux
2015-06-17 22:12 ` Dinh Nguyen
2015-06-17 22:31 ` Dinh Nguyen
2015-06-17 22:51 ` Russell King - ARM Linux
2015-05-22 10:45 ` Michal Simek
2015-06-01 10:21 ` Wei Xu
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