* Re: [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support
2015-06-15 4:54 [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support Kuninori Morimoto
@ 2015-06-15 7:46 ` Magnus Damm
2015-06-15 8:11 ` Geert Uytterhoeven
` (9 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Magnus Damm @ 2015-06-15 7:46 UTC (permalink / raw)
To: linux-sh
Hi Morimoto-san,
On Mon, Jun 15, 2015 at 1:54 PM, Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Gaku Inami <gaku.inami.xw@bp.renesas.com>
>
> Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> ---
> arch/arm64/boot/dts/renesas/Makefile | 5 ++
> arch/arm64/boot/dts/renesas/r8a7795.dtsi | 90 +++++++++++++++++++++++++++++++
> include/dt-bindings/clock/r8a7795-clock.h | 31 +++++++++++
> 3 files changed, 126 insertions(+)
> create mode 100644 arch/arm64/boot/dts/renesas/Makefile
> create mode 100644 arch/arm64/boot/dts/renesas/r8a7795.dtsi
> create mode 100644 include/dt-bindings/clock/r8a7795-clock.h
>
> diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
> new file mode 100644
> index 0000000..970627c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/Makefile
> @@ -0,0 +1,5 @@
> +dtb-$(CONFIG_ARCH_RCAR_GEN3) +> +
> +always := $(dtb-y)
> +subdir-y := $(dts-dirs)
> +clean-files := *.dtb
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> new file mode 100644
> index 0000000..13c7d8d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -0,0 +1,90 @@
> +/*
> + * Device Tree Source for the r8a7795 SoC
> + *
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This file is licensed under the terms of the GNU General Public License
> + * version 2. This program is licensed "as is" without any warranty of any
> + * kind, whether express or implied.
> + */
> +/dts-v1/;
> +
> +#include <dt-bindings/clock/r8a7795-clock.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + compatible = "renesas,r8a7795";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* 1core only at this point */
> + a53_0: cpu@100 {
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x100>;
> + device_type = "cpu";
> + };
> + };
> +
> + gic: interrupt-controller@0xf1010000 {
> + compatible = "arm,gic-400", "arm,cortex-a15-gic";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0x0 0xf1010000 0 0x1000>,
> + <0x0 0xf1020000 0 0x2000>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
Thanks for your efforts. On ARM v8, is ARM v7 compat string
"arm,cortex-a15-gic" really correct?
Cheers,
/ magus
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support
2015-06-15 4:54 [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support Kuninori Morimoto
2015-06-15 7:46 ` Magnus Damm
@ 2015-06-15 8:11 ` Geert Uytterhoeven
2015-06-15 8:23 ` Kuninori Morimoto
` (8 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2015-06-15 8:11 UTC (permalink / raw)
To: linux-sh
Hi Morimoto-san, Inami-san,
On Mon, Jun 15, 2015 at 6:54 AM, Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Thanks for your patch!
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -0,0 +1,90 @@
> +/*
> + * Device Tree Source for the r8a7795 SoC
> + *
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This file is licensed under the terms of the GNU General Public License
> + * version 2. This program is licensed "as is" without any warranty of any
> + * kind, whether express or implied.
> + */
> +/dts-v1/;
> +
> +#include <dt-bindings/clock/r8a7795-clock.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + compatible = "renesas,r8a7795";
ideally, this compatible value should be documented before it's being used.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support
2015-06-15 4:54 [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support Kuninori Morimoto
2015-06-15 7:46 ` Magnus Damm
2015-06-15 8:11 ` Geert Uytterhoeven
@ 2015-06-15 8:23 ` Kuninori Morimoto
2015-06-15 8:30 ` Kuninori Morimoto
` (7 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Kuninori Morimoto @ 2015-06-15 8:23 UTC (permalink / raw)
To: linux-sh
Hi Geert
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> > @@ -0,0 +1,90 @@
> > +/*
> > + * Device Tree Source for the r8a7795 SoC
> > + *
> > + * Copyright (C) 2015 Renesas Electronics Corp.
> > + *
> > + * This file is licensed under the terms of the GNU General Public License
> > + * version 2. This program is licensed "as is" without any warranty of any
> > + * kind, whether express or implied.
> > + */
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/clock/r8a7795-clock.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > + compatible = "renesas,r8a7795";
>
> ideally, this compatible value should be documented before it's being used.
Ahh.. yes indeed
Best regards
---
Kuninori Morimoto
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support
2015-06-15 4:54 [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support Kuninori Morimoto
` (2 preceding siblings ...)
2015-06-15 8:23 ` Kuninori Morimoto
@ 2015-06-15 8:30 ` Kuninori Morimoto
2015-06-15 8:41 ` Gaku Inami
` (6 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Kuninori Morimoto @ 2015-06-15 8:30 UTC (permalink / raw)
To: linux-sh
Hi Magnus, Inami-san
> > + gic: interrupt-controller@0xf1010000 {
> > + compatible = "arm,gic-400", "arm,cortex-a15-gic";
> > + #interrupt-cells = <3>;
> > + #address-cells = <0>;
> > + interrupt-controller;
> > + reg = <0x0 0xf1010000 0 0x1000>,
> > + <0x0 0xf1020000 0 0x2000>;
> > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
> > + };
>
> Thanks for your efforts. On ARM v8, is ARM v7 compat string
> "arm,cortex-a15-gic" really correct?
I don't know detail of this.
but, I guess current Inami-san's status is "create working something".
Maybe he don't care small detail at this point.
Do you think "arm,gic-400" is very enough ?
If so, I can drop it in v2
Best regards
---
Kuninori Morimoto
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support
2015-06-15 4:54 [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support Kuninori Morimoto
` (3 preceding siblings ...)
2015-06-15 8:30 ` Kuninori Morimoto
@ 2015-06-15 8:41 ` Gaku Inami
2015-06-15 8:44 ` Geert Uytterhoeven
` (5 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Gaku Inami @ 2015-06-15 8:41 UTC (permalink / raw)
To: linux-sh
Hi Morimoto-san, Magnus-san,
On 2015/06/15 17:30, Kuninori Morimoto wrote:
> Hi Magnus, Inami-san
>
>>> + gic: interrupt-controller@0xf1010000 {
>>> + compatible = "arm,gic-400", "arm,cortex-a15-gic";
>>> + #interrupt-cells = <3>;
>>> + #address-cells = <0>;
>>> + interrupt-controller;
>>> + reg = <0x0 0xf1010000 0 0x1000>,
>>> + <0x0 0xf1020000 0 0x2000>;
>>> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
>>> + };
>> Thanks for your efforts. On ARM v8, is ARM v7 compat string
>> "arm,cortex-a15-gic" really correct?
> I don't know detail of this.
> but, I guess current Inami-san's status is "create working something".
> Maybe he don't care small detail at this point.
> Do you think "arm,gic-400" is very enough ?
> If so, I can drop it in v2
This is based on arch/arm64/boot/dts/arm/juno.dts.
Since "arm,cortex-a15-gic" is not required, please drop this.
Regards,
Inami
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support
2015-06-15 4:54 [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support Kuninori Morimoto
` (4 preceding siblings ...)
2015-06-15 8:41 ` Gaku Inami
@ 2015-06-15 8:44 ` Geert Uytterhoeven
2015-06-15 12:22 ` Khiem Nguyen
` (4 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2015-06-15 8:44 UTC (permalink / raw)
To: linux-sh
Hi Morimoto-san,
On Mon, Jun 15, 2015 at 10:30 AM, Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
>> > + gic: interrupt-controller@0xf1010000 {
>> > + compatible = "arm,gic-400", "arm,cortex-a15-gic";
>> > + #interrupt-cells = <3>;
>> > + #address-cells = <0>;
>> > + interrupt-controller;
>> > + reg = <0x0 0xf1010000 0 0x1000>,
>> > + <0x0 0xf1020000 0 0x2000>;
>> > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
>> > + };
>>
>> Thanks for your efforts. On ARM v8, is ARM v7 compat string
>> "arm,cortex-a15-gic" really correct?
>
> I don't know detail of this.
> but, I guess current Inami-san's status is "create working something".
> Maybe he don't care small detail at this point.
> Do you think "arm,gic-400" is very enough ?
> If so, I can drop it in v2
Both are (currently) handled identically by drivers/irqchip/irq-gic.c.
As the datasheet documents it as "GIC-400", we should use "arm,gic-400".
BTW, we should do the same for APE6 and R-Car Gen2, cfr.
https://lkml.org/lkml/2015/4/29/315
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support
2015-06-15 4:54 [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support Kuninori Morimoto
` (5 preceding siblings ...)
2015-06-15 8:44 ` Geert Uytterhoeven
@ 2015-06-15 12:22 ` Khiem Nguyen
2015-06-15 12:40 ` Geert Uytterhoeven
` (3 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Khiem Nguyen @ 2015-06-15 12:22 UTC (permalink / raw)
To: linux-sh
On 6/15/2015 11:54 AM, Kuninori Morimoto wrote:
> From: Gaku Inami <gaku.inami.xw@bp.renesas.com>
>
> Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> ---
> arch/arm64/boot/dts/renesas/Makefile | 5 ++
> arch/arm64/boot/dts/renesas/r8a7795.dtsi | 90 +++++++++++++++++++++++++++++++
> include/dt-bindings/clock/r8a7795-clock.h | 31 +++++++++++
> 3 files changed, 126 insertions(+)
> create mode 100644 arch/arm64/boot/dts/renesas/Makefile
> create mode 100644 arch/arm64/boot/dts/renesas/r8a7795.dtsi
> create mode 100644 include/dt-bindings/clock/r8a7795-clock.h
>
> diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
> new file mode 100644
> index 0000000..970627c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/Makefile
> @@ -0,0 +1,5 @@
> +dtb-$(CONFIG_ARCH_RCAR_GEN3) +> +
> +always := $(dtb-y)
> +subdir-y := $(dts-dirs)
> +clean-files := *.dtb
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> new file mode 100644
> index 0000000..13c7d8d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -0,0 +1,90 @@
> +/*
> + * Device Tree Source for the r8a7795 SoC
> + *
> + * Copyright (C) 2015 Renesas Electronics Corp.
> + *
> + * This file is licensed under the terms of the GNU General Public License
> + * version 2. This program is licensed "as is" without any warranty of any
> + * kind, whether express or implied.
> + */
> +/dts-v1/;
> +
> +#include <dt-bindings/clock/r8a7795-clock.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + compatible = "renesas,r8a7795";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* 1core only at this point */
> + a53_0: cpu@100 {
> + compatible = "arm,cortex-a53","arm,armv8";
> + reg = <0x100>;
> + device_type = "cpu";
> + };
> + };
> +
> + gic: interrupt-controller@0xf1010000 {
> + compatible = "arm,gic-400", "arm,cortex-a15-gic";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0x0 0xf1010000 0 0x1000>,
> + <0x0 0xf1020000 0 0x2000>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
Since there's only 1 CPU in this DTS, I guess the value should be 1,
instead of 6.
I remembered that Geert has a discussion thread about this matter. Geert ?
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
Same here.
> + };
> +
> + clocks {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + extal_clk: extal_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <0>;
> + clock-output-names = "extal";
> + };
> + cpg_clocks: cpg_clocks@e6150000 {
> + compatible = "renesas,r8a7795-cpg-clocks",
> + "renesas,rcar-gen3-cpg-clocks";
> + reg = <0 0xe6150000 0 0x1000>;
> + clocks = <&extal_clk>;
> + #clock-cells = <1>;
> + clock-output-names = "main", "pll0", "pll1","pll2",
> + "pll3", "pll4";
> + };
> + p_clk: p_clk {
> + compatible = "fixed-factor-clock";
> + clocks = <&cpg_clocks RCAR_GEN3_CLK_PLL1>;
> + #clock-cells = <0>;
> + clock-div = <24>;
> + clock-mult = <1>;
> + clock-output-names = "p";
> + };
> + mstp3_clks: mstp3_clks@e615013c {
> + compatible = "renesas,r8a7795-mstp-clocks",
> + "renesas,cpg-mstp-clocks";
> + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>,
> + <0 0xe6150900 0 4>;
> + clocks = <&p_clk>;
> + #clock-cells = <1>;
> + renesas,clock-indices = <RCAR_GEN3_CLK_IRDA>;
> + clock-output-names = "irda";
> + };
> + };
> +};
> diff --git a/include/dt-bindings/clock/r8a7795-clock.h b/include/dt-bindings/clock/r8a7795-clock.h
> new file mode 100644
> index 0000000..fc1c4da
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a7795-clock.h
> @@ -0,0 +1,31 @@
> +#ifndef __DT_BINDINGS_CLOCK_RCAR_GEN3_H__
> +#define __DT_BINDINGS_CLOCK_RCAR_GEN3_H__
> +
> +/* CPG */
> +#define RCAR_GEN3_CLK_MAIN 0
> +#define RCAR_GEN3_CLK_PLL0 1
> +#define RCAR_GEN3_CLK_PLL1 2
> +#define RCAR_GEN3_CLK_PLL2 3
> +#define RCAR_GEN3_CLK_PLL3 4
> +#define RCAR_GEN3_CLK_PLL4 5
> +
> +/* MSTP0 */
> +
> +/* MSTP1 */
> +
> +/* MSTP2 */
> +
> +/* MSTP3 */
> +#define RCAR_GEN3_CLK_IRDA 10
> +
> +/* MSTP5 */
> +
> +/* MSTP7 */
> +
> +/* MSTP8 */
> +
> +/* MSTP9 */
> +
> +/* MSTP10 */
> +
> +#endif /* __DT_BINDINGS_CLOCK_RCAR_GEN3_H__ */
>
--
Best regards,
KHIEM Nguyen
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support
2015-06-15 4:54 [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support Kuninori Morimoto
` (6 preceding siblings ...)
2015-06-15 12:22 ` Khiem Nguyen
@ 2015-06-15 12:40 ` Geert Uytterhoeven
2015-06-17 1:05 ` Simon Horman
` (2 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2015-06-15 12:40 UTC (permalink / raw)
To: linux-sh
On Mon, Jun 15, 2015 at 2:22 PM, Khiem Nguyen
<khiem.nguyen.xt@rvc.renesas.com> wrote:
>> + /* 1core only at this point */
>> + a53_0: cpu@100 {
>> + compatible = "arm,cortex-a53","arm,armv8";
>> + reg = <0x100>;
>> + device_type = "cpu";
>> + };
>> + };
>> + gic: interrupt-controller@0xf1010000 {
>> + compatible = "arm,gic-400", "arm,cortex-a15-gic";
>> + #interrupt-cells = <3>;
>> + #address-cells = <0>;
>> + interrupt-controller;
>> + reg = <0x0 0xf1010000 0 0x1000>,
>> + <0x0 0xf1020000 0 0x2000>;
>> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) |
>> IRQ_TYPE_LEVEL_HIGH)>;
>
>
> Since there's only 1 CPU in this DTS, I guess the value should be 1, instead
> of 6.
> I remembered that Geert has a discussion thread about this matter. Geert ?
That's correct, cfr.
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/313194.html
which suggests the above was just copied from juno.dts.
However, as the single CPU in the dtsi is vpu@100, not cpu@0, I'm not sure
"GIC_CPU_MASK_SIMPLE(1)" is the right value anyway...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support
2015-06-15 4:54 [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support Kuninori Morimoto
` (7 preceding siblings ...)
2015-06-15 12:40 ` Geert Uytterhoeven
@ 2015-06-17 1:05 ` Simon Horman
2015-06-17 7:22 ` Geert Uytterhoeven
2015-06-17 8:38 ` Simon Horman
10 siblings, 0 replies; 12+ messages in thread
From: Simon Horman @ 2015-06-17 1:05 UTC (permalink / raw)
To: linux-sh
On Mon, Jun 15, 2015 at 10:44:33AM +0200, Geert Uytterhoeven wrote:
> Hi Morimoto-san,
>
> On Mon, Jun 15, 2015 at 10:30 AM, Kuninori Morimoto
> <kuninori.morimoto.gx@renesas.com> wrote:
> >> > + gic: interrupt-controller@0xf1010000 {
> >> > + compatible = "arm,gic-400", "arm,cortex-a15-gic";
> >> > + #interrupt-cells = <3>;
> >> > + #address-cells = <0>;
> >> > + interrupt-controller;
> >> > + reg = <0x0 0xf1010000 0 0x1000>,
> >> > + <0x0 0xf1020000 0 0x2000>;
> >> > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
> >> > + };
> >>
> >> Thanks for your efforts. On ARM v8, is ARM v7 compat string
> >> "arm,cortex-a15-gic" really correct?
> >
> > I don't know detail of this.
> > but, I guess current Inami-san's status is "create working something".
> > Maybe he don't care small detail at this point.
> > Do you think "arm,gic-400" is very enough ?
> > If so, I can drop it in v2
>
> Both are (currently) handled identically by drivers/irqchip/irq-gic.c.
>
> As the datasheet documents it as "GIC-400", we should use "arm,gic-400".
> BTW, we should do the same for APE6 and R-Car Gen2, cfr.
> https://lkml.org/lkml/2015/4/29/315
Although it seems low priority I am interested in cleaning up the GIC nodes
for the you mention above. Can I confirm that their desired compat string
usage is:
compatible = "arm,gic-400";
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support
2015-06-15 4:54 [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support Kuninori Morimoto
` (8 preceding siblings ...)
2015-06-17 1:05 ` Simon Horman
@ 2015-06-17 7:22 ` Geert Uytterhoeven
2015-06-17 8:38 ` Simon Horman
10 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2015-06-17 7:22 UTC (permalink / raw)
To: linux-sh
Hi Simon,
On Wed, Jun 17, 2015 at 3:05 AM, Simon Horman <horms@verge.net.au> wrote:
> On Mon, Jun 15, 2015 at 10:44:33AM +0200, Geert Uytterhoeven wrote:
>> On Mon, Jun 15, 2015 at 10:30 AM, Kuninori Morimoto
>> <kuninori.morimoto.gx@renesas.com> wrote:
>> >> > + gic: interrupt-controller@0xf1010000 {
>> >> > + compatible = "arm,gic-400", "arm,cortex-a15-gic";
>> >> > + #interrupt-cells = <3>;
>> >> > + #address-cells = <0>;
>> >> > + interrupt-controller;
>> >> > + reg = <0x0 0xf1010000 0 0x1000>,
>> >> > + <0x0 0xf1020000 0 0x2000>;
>> >> > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
>> >> > + };
>> >>
>> >> Thanks for your efforts. On ARM v8, is ARM v7 compat string
>> >> "arm,cortex-a15-gic" really correct?
>> >
>> > I don't know detail of this.
>> > but, I guess current Inami-san's status is "create working something".
>> > Maybe he don't care small detail at this point.
>> > Do you think "arm,gic-400" is very enough ?
>> > If so, I can drop it in v2
>>
>> Both are (currently) handled identically by drivers/irqchip/irq-gic.c.
>>
>> As the datasheet documents it as "GIC-400", we should use "arm,gic-400".
>> BTW, we should do the same for APE6 and R-Car Gen2, cfr.
>> https://lkml.org/lkml/2015/4/29/315
>
> Although it seems low priority I am interested in cleaning up the GIC nodes
> for the you mention above. Can I confirm that their desired compat string
> usage is:
>
> compatible = "arm,gic-400";
That's correct.
But please don't start working on it, as I already made the changes locally.
I haven't send out the patches yet, though. Will do.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support
2015-06-15 4:54 [PATCH 5/6][RFC] arm64: renesas: Add r8a7795 SoC support Kuninori Morimoto
` (9 preceding siblings ...)
2015-06-17 7:22 ` Geert Uytterhoeven
@ 2015-06-17 8:38 ` Simon Horman
10 siblings, 0 replies; 12+ messages in thread
From: Simon Horman @ 2015-06-17 8:38 UTC (permalink / raw)
To: linux-sh
On Wed, Jun 17, 2015 at 09:22:00AM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Wed, Jun 17, 2015 at 3:05 AM, Simon Horman <horms@verge.net.au> wrote:
> > On Mon, Jun 15, 2015 at 10:44:33AM +0200, Geert Uytterhoeven wrote:
> >> On Mon, Jun 15, 2015 at 10:30 AM, Kuninori Morimoto
> >> <kuninori.morimoto.gx@renesas.com> wrote:
> >> >> > + gic: interrupt-controller@0xf1010000 {
> >> >> > + compatible = "arm,gic-400", "arm,cortex-a15-gic";
> >> >> > + #interrupt-cells = <3>;
> >> >> > + #address-cells = <0>;
> >> >> > + interrupt-controller;
> >> >> > + reg = <0x0 0xf1010000 0 0x1000>,
> >> >> > + <0x0 0xf1020000 0 0x2000>;
> >> >> > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
> >> >> > + };
> >> >>
> >> >> Thanks for your efforts. On ARM v8, is ARM v7 compat string
> >> >> "arm,cortex-a15-gic" really correct?
> >> >
> >> > I don't know detail of this.
> >> > but, I guess current Inami-san's status is "create working something".
> >> > Maybe he don't care small detail at this point.
> >> > Do you think "arm,gic-400" is very enough ?
> >> > If so, I can drop it in v2
> >>
> >> Both are (currently) handled identically by drivers/irqchip/irq-gic.c.
> >>
> >> As the datasheet documents it as "GIC-400", we should use "arm,gic-400".
> >> BTW, we should do the same for APE6 and R-Car Gen2, cfr.
> >> https://lkml.org/lkml/2015/4/29/315
> >
> > Although it seems low priority I am interested in cleaning up the GIC nodes
> > for the you mention above. Can I confirm that their desired compat string
> > usage is:
> >
> > compatible = "arm,gic-400";
>
> That's correct.
>
> But please don't start working on it, as I already made the changes locally.
> I haven't send out the patches yet, though. Will do.
No problem, I am quite happy to wait.
^ permalink raw reply [flat|nested] 12+ messages in thread